Semiconductor device

Abstract

To manufacture an oxide semiconductor suitable for the use in a semiconductor device, and provide a manufacturing method for a semiconductor device using the same, and the semiconductor device.SOLUTION: In a manufacturing method for forming an oxide semiconductor layer by a sputtering method using an oxide semiconductor target containing In, Ga, and Zn, the oxide semiconductor layer contains less Ga than Ga in the target, and the oxide semiconductor layer contains less Zn than Zn in the target. In the oxide semiconductor layer containing In, Ga, and Zn, the content of Zn is less than the content of Ga, the content of Zn is less than the content of In, and an amorphous structure is 90 vol% or less.SELECTED DRAWING: None

Description

Technical Field

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

Background Art

[0002] Field effect transistors are currently the most widely used semiconductor elements. The materials used for field effect transistors vary depending on their applications. In particular, semiconductor materials containing silicon are widely used.

[0003] The field effect transistors using the above-mentioned silicon satisfy the characteristics required for many applications. For example, single crystal silicon is used for applications such as integrated circuits that require high-speed operation, and the requirements are satisfied. Also, for large-area applications such as display devices, amorphous silicon is used to satisfy the requirements.

[0004] As described above, silicon has high versatility and can be used for various applications. However, in recent years, there has been a tendency to demand further performance along with versatility for semiconductor materials. For example, from the viewpoint of high performance of large-area display devices, in order to realize high-speed operation of switching elements, a semiconductor material that is easy to form into a large area and has performance exceeding that of amorphous silicon is required.

[0005] Under such circumstances, technologies related to field effect transistors (also referred to as FETs) using oxide semiconductors have attracted attention. For example, in Patent Document 1, a homologue compound InM O 3 (ZnO) m (M = In, Fe, Ga, or Al, m is an integer of 1 or more and less than 50) is used. There is disclosed a transparent thin film field effect transistor.

[0006] Further, Patent Document 2 discloses a field effect transistor using an amorphous oxide semiconductor containing In, Ga, and Zn and having an electron carrier concentration of less than 10 18 / cm 3 . In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn = 1:1:m (m < 6).

[0007] Furthermore, Patent Document 3 discloses a field effect transistor having an amorphous oxide semiconductor containing microcrystals as an active layer.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] In Patent Document 3, there is a disclosure that the composition in the crystalline state is InGaO 3 (ZnO) m (m is an integer less than 6 ). Further, in Example 1 of Patent Document 3, the case of InGaO 3 (ZnO) 4 is disclosed. However, the fact is that even when using such an oxide semiconductor, sufficient characteristics have not been obtained.

[0010] In view of the above problems, an object of the present invention is to provide an oxide semiconductor suitable for use in semiconductor devices. Another object is to provide a semiconductor device using the same. [Means for solving the problem]

[0011] In the disclosed invention, InGaO 3 (ZnO) m In the amorphous structure represented by (m>0) InGaO 3 (ZnO) m A semiconductor device is fabricated by incorporating crystal grains represented by (m=1). More specifically, it is as follows:

[0012] One of the disclosed inventions is a method for manufacturing a transistor having an In-Ga-Zn-O-based oxide semiconductor layer. In the semiconductor device used in the formation region, the In-Ga-Zn-O-based oxide semiconductor layer is GaO 3 (ZnO) m In the amorphous structure represented by (m>0), InGaO 3 (ZnO) m It is characterized by having a structure containing crystal grains represented by (m=1).

[0013] In the above, the content (atomic %) of Zn in the In-Ga-Zn-O based oxide semiconductor layer is It is preferable that the content is less than the In content (atomic %) and less than the Ga content (atomic %). In addition, the oxide semiconductor layer has a Zn content (atomic %) that is equal to or less than the In content (atomic %) and a Ga content (atomic %) that is equal to or less than the In content (atomic %). It is formed by the sputtering method using a target with a content (atomic percent) of In the above, it is preferable that the crystal grains are formed only of the structure related to m=1. However, in a situation where the structure relating to m=1 occupies 80% or more by volume of the crystal grains, It is possible to obtain certain properties.

[0014] Another aspect of the present invention is to deposit amorphous In on a substrate by sputtering. By forming a -Ga-Zn-O-based oxide semiconductor layer and subjecting the oxide semiconductor layer to a heat treatment, nGaO 3 (ZnO) m In the amorphous structure represented by (m>0), InGaO 3 (ZnO) m (m=1) is formed, and the oxide semiconductor layer including the crystal grains is US20100232633A1 - Fabrication of a semiconductor device using a semiconductor layer as a channel forming region of a transistor - Google Patents This is the method.

[0015] In the above, the content of Zn in the In-Ga-Zn-O-based oxide semiconductor layer having an amorphous structure is The content (atomic %) is less than the In content (atomic %) and less than the Ga content (atomic %). It is preferable that the In-Ga-Zn-O oxide having an amorphous structure is formed as follows. The compound semiconductor layer has a Zn content (atomic %) that is equal to or less than the In content (atomic %) and a Ga content (atomic %) that is equal to or less than the In content (atomic %). It is preferable that the film is formed by a sputtering method using a target having a content (atomic %) of 0.1 or less. Moreover, the heat treatment is preferably carried out at a temperature of 350° C. or higher.

[0016] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to display devices, semiconductor circuits, and electronic devices, all of which are included in the category of semiconductor devices. Effect of the Invention

[0017] InGaO 3 (ZnO) m In the amorphous structure represented by (m>0), InGaO 3 (ZnO ) mBy including crystal grains represented by (m = 1), the electrical characteristics of the oxide semiconductor can be improved. In addition, by using the oxide semiconductor, an excellent semiconductor device can be provided.

Brief Description of Drawings

[0018]

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[0019] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the described embodiment, and various changes in form and details are possible without departing from the spirit of the invention. It is obvious to those skilled in the art that the configurations according to the different embodiments can be combined as appropriate. In the configuration of the invention described below, the same parts or In the following, the same reference numerals are used for parts having similar functions, and repeated explanations thereof will be omitted.

[0020] (Embodiment 1) In this embodiment, InGaO 3 (ZnO) m In the amorphous structure represented by (m>0), I nGaO 3 (ZnO) m The oxide semiconductor layer (In-Ga A method for producing a Zn-O-based oxide semiconductor layer will be described with reference to the drawings.

[0021] First, an In-Ga-Zn-O non-single crystal semiconductor is formed on the surface to be formed (here, on the substrate 100). A conductor layer 102 is formed (see FIG. 1(a)). For example, indium (In), gallium ( The non-metallic compound was fabricated by sputtering using an oxide semiconductor target containing Ga and zinc (Zn). A single crystal semiconductor layer 102 can be formed. The sputtering conditions are, for example, The distance between the target and the oxide semiconductor was set to 30 mm to 500 mm, and the pressure was set to 0.1 Pa to 2.0 Pa. Pa, a DC power supply of 0.2 kW to 5.0 kW (when using an 8-inch diameter target) , the atmosphere may be an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen .

[0022] Here, the composition ratio of the oxide semiconductor target is In 2 O 3 :Ga 2 O 3 :ZnO = 1:1 :1, the distance between the substrate 100 and the oxide semiconductor target is 170 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, the flow rate of argon gas is 10 sccm, and the flow rate of oxygen gas is 5 sccm, and the polycrystalline semiconductor layer 102 was formed under these conditions.

[0023] Thereafter, for the sample prepared by the above method, inductively coupled plasma mass spectrometry (Induct ively Coupled Plasma Mass Spectrometry: I CP-MS analysis) was used for composition analysis. The composition of the polycrystalline semiconductor layer 102 obtained under the condition that the flow rate of argon gas is 10 sccm and the flow rate of oxygen gas is 5 sccm is InGa 0.94 Zn 0.40 O 3.31 . Combining with the above analysis results, the analysis of the polycrystalline semiconductor layer prepared under the condition that the flow rate of argon gas is 40 sccm and the flow rate of oxygen gas is 0 sccm results are shown in Figure 2.

[0024] In addition, the results when Rutherford Backscattering Spectrometry (RBS analysis) is used as the analysis method are shown in Figure 3.

[0025] ​From FIGS. 2 and 3, it can be seen that in the non-single crystal semiconductor layer, the contents of Ga and Zn tend to be smaller compared to the composition of the target. Also, depending on the production conditions, analysis methods, etc., the analysis results of the non-single crystal semiconductor layer are different.

[0026] Next, the above non-single crystal semiconductor layer is heat-treated at 350°C to 800°C (preferably 500 to 750 °C) for about 10 minutes to 200 minutes. As a result, an oxide semiconductor layer 106 containing crystal grains 10 4 is obtained (see FIG. 1(b)). The electrical characteristics of the thin film transistor fabricated using the above oxide semiconductor layer 10 6 are good, with an on-off ratio of 10 or more and a mobility of 10 cm 9 / Vs or more at a gate voltage of ±20V. Here, the heat treatment is performed under the conditions of 700°C for 1 hour. 2

[0027] After the above heat treatment, the structure of the oxide semiconductor layer 106 was analyzed. Specifically, STEM (scanning transmission electron m icroscope) images of the cross-section of the above sample were observed.

[0028] FIG. 4 shows the Bright-field-STEM image of the above sample. FIG. 4(a) is the STEM image of the sample fabricated using a target of In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 (In:Ga:Zn = 1:1:0.5) (hereinafter referred to as target A), and FIG. 4(b) is the STEM image of the target only of In O 2 :Ga 3 O 2 :ZnO = 1:1 3 for comparison with the above sample. ​​​​:2 (In:Ga:Zn = 1:1:1) (hereinafter referred to as target B) and the sample prepared by changing it is the STEM image of

[0029] From FIG. 4, it can be seen that the oxide semiconductor layer 106 prepared by the above method has a structure including crystal grains 104 in an amorphous structure

[0030] In addition, as can be seen from the comparison between FIGS. 4(a) and 4(b), when the content of Zn in the target is low, the crystal growth rate is slower than that when the content of Zn in the target is high By utilizing this, the controllability of crystal growth can be improved . For example, if the content (atomic %) of Zn in the non-single crystal semiconductor layer 102 is less than the content (atomic %) of In and less than the content (atomic %) of Ga, a good oxide semiconductor layer 106 can be formed with good controllability On the other hand, when emphasizing the crystal growth rate, the content of zinc in the non-single crystal semiconductor layer 102 can be increased

[0031] Next, STEM image observation of a finer region was performed. FIG. 5 shows the STEM image of the sample prepared using target A . FIG. 5(a) is a Bright-field-STEM image, and FIG. 5 (b) is a HAADF (high-angle annular dark field) -STEM image. A regular structure can be read from FIG. 5(a), but it is difficult to specify the positions of each atom, and the crystal orientation cannot be discriminated. On the other hand, in FIG. 5(b), the positions of the white dots corresponding to each atom can be clearly discriminated . Also, it can be seen that an amorphous structure remains in the lower right region in FIG. 5(b)

[0032] ​​​​​​In the HAADF-STEM image, a contrast proportional to the square of the atomic number is obtained. Therefore, brighter points indicate heavier atoms. In Fig. 5(b), the bright points are In, and the dark points are Ga or Zn.

[0033] Next, referring to Fig. 6, the above crystal structure will be discussed. Here, the left figure (photo graph) in Fig. 6 is an enlarged view (enlarged photograph) of Fig. 5(b). Also, the right figure in Fig. 6 is a model diagram of the crystal 4 structure of InGaO 3 (ZnO) m corresponding to m = 1 (viewed from the

[0100] direction). By comparing the left and right figures in Fig. 6, it can be seen that the crystal grains in the sample prepared using target A have the crystal structure of InGaO (ZnO) 3 (ZnO) 1 . Note that in the In-Ga-Zn-O-based oxide semiconductor, since In and Ga are considered to contribute to electrical conduction, in order to maintain good electrical properties, a crystal structure with a high ratio of In and Ga, that is, a crystal structure with m = 1 in InGaO (ZnO) 3 (ZnO) m , the higher the ratio of the crystal structure is, the more preferable it is.

[0034] Fig. 7 shows the HAADF-STEM image of the sample prepared using target B. It can be seen that the bright points are regularly arranged and form a linear shape. The distance between the lines formed by the bright points is about 0.9 nm, about 1.15 nm, and about 1.4 nm. These correspond to the indium intervals in the crystal structures of m = 1, m = 2, and m = 3, respectively. That is, in the sample prepared using target B, at least a plurality of sets from m = 1 to m = 3 It can be said that it has a crystalline structure.

[0035] As described above, in the In-Ga-Zn-O-based oxide semiconductor, In and Ga contribute to electrical conduction. Therefore, in a situation where the ratios of In and Ga are low (i.e., a situation where m is large), its electrical characteristics deteriorate. Thus, by increasing the proportion of the structure related to m = 1, it is possible to maintain good electrical characteristics. Specifically, it is preferable that the crystal structure with m = 1 occupies 80% by volume or more of the entire crystal structure. More preferably, it is 90% by volume or more. One method of increasing the proportion of the crystal structure with m = 1 is to form the non-single crystal semiconductor layer 102 with a low Zn content using a target with a low Zn content. For example,

[0036] the Zn content (atomic %) in the non-single crystal semiconductor layer 102 may be made less than the In content (atomic %) and less than the Ga content (atomic %). In this way, by reducing the Zn content in the non-single crystal semiconductor layer 102, it is possible to obtain a crystal structure with good electrical characteristics.

[0037] The electronic state of the In-Ga-Zn-O-based oxide semiconductor has not been fully elucidated, and it is considered that the elucidation of this electronic state leads to an understanding of the electrical characteristics of the oxide semiconductor. Therefore, the calculation results and discussions of the first-principles calculation performed on the In-Ga-Zn-O-based oxide semiconductor are shown below. The following calculation results are based on the crystal structure, but can be understood in the same way for a structure containing crystal grains in the amorphous structure.

[0038] In FIG. 8, the calculated In-Ga-Zn-O-based oxide semiconductor (InGaZnO 4 ​​​​​​​​​Crystal structure of is shown. InGaZnO 4 The unit cell of the crystal structure is composed of 21 atoms, but here, in order to examine the arrangement of Ga, the calculation was performed by expanding to a unit (2×2×1) composed of 84 atoms.

[0039] The calculation is carried out using CASTEP. CASTEP is a first-principles calculation program based on density functional theory (DFT) and the plane-wave pseudopotential method. Here, as the exchange-correlation functional, GGA (generalized-gradient approximation) and PBE (Perdew-Burke-Ernzer hof) were selected. Also, the cut-off energy was set to 500 eV and the k-point was set to 3×3×1.

[0040] From Figure 8, it can be seen that the unit cell is composed of two (Ga, Zn)O 2 layers and one InO 2 layer. For simplicity, here, a crystal structure formed by repeating a unit cell with a predetermined atomic arrangement is assumed.

[0041] Figure 9 shows the arrangement of Ga and Zn in the two (Ga, Zn)O 2 layers in the unit cell. In Figure 9, a structure obtained by expanding the unit cell by 2×2 times is shown. Also, the thick lines in the figure indicate the unit cell. Figure 9(a) shows the case where two Ga are arranged in the upper layer and the lower layer respectively, and Figure 9(b) shows the case where one Ga is arranged in the upper layer and three Ga are arranged in the lower layer. ​​​

[0042] In the case shown in Fig. 9(a), the arrangement of Ga in each layer is striped. That is, within each layer, Ga takes a linear arrangement parallel to each other.

[0043] Also, considering the combination of the upper layer and the lower layer, the arrangement of Ga can be divided into two patterns: parallel arrangement and cross arrangement. The parallel arrangement refers to the case where the lines formed by Ga in the upper layer and the lower layer are parallel to each other, and the cross arrangement refers to the case where the lines formed by Ga in the upper layer and the lower layer cross each other. In the case of the parallel arrangement, for example, two combinations such as U1+L 1 and U1+L4 can be considered. On the other hand, in the case of the cross arrangement, since it has rotational symmetry, there is only one combination such as U1+L2 at most. That is, in the case shown in Fig. 9(a), there are a total of three combinations.

[0044] In the case shown in Fig. 9(b), as combinations of the upper layer and the lower layer, for example, two combinations such as U7 +L7 and U7+L10 can be considered. Note that when all Ga enters either the upper layer or the lower layer, there is only one combination (U11+L 11: not shown in the figure). Therefore, a total of six combinations should be considered for the arrangement of Ga.

[0045] Next, the comparison results of the energies for the above six arrangements are shown in Fig. 10. The lowest energy of InGaZn O 4 appears when two Ga are arranged in the upper layer and the lower layer respectively. More specifically, it is a structure such as U1+L1.

[0046] More detailed calculations were performed on the electronic state related to this structure (the structure with the lowest energy). Figure 11 shows the calculation results of the DOS (density of state) and PDOS (projected density of state) of electrons in the above structure. It can be seen from Figure 11 that Ga is the most dominant, followed by In with a large influence.

[0047] Next, the probability of electron existence |Ψ| at the bottom of the conduction band was calculated from the orbital function Ψ at the bottom of the conduction band. 2 Calculated The distribution diagram is shown in Figure 12. Here, Figure 12(a) represents the probability of electron existence in the In plane (in the InO 2 layer), and Figure 12(b) represents the probability of electron existence in the (Ga, Zn)O 2 layer. The fact that the orbits of In are separated is interesting.

[0048] From Figure 12(b), it can be seen that the probability of electron existence is high around Ga and low around Zn. Also, the electrical conduction path seems to exist not only in the In plane but also in the (Ga, Zn )O layer. From this, it is considered that Ga contributes greatly to the electrical conduction of InGaZnO 2 . The orbit of Ga acts on the orbit of In and also seems to contribute to the electrical conduction related to the (Ga, Zn)O 4 layer. One of the characteristics of InGaZnO is the high tolerance of electrical conductivity. This is thought to be due to 2 the generation probability of oxygen vacancies (defects). This is because the electrical conductivity varies variously depending on the amount of oxygen added in the process. Therefore, this mechanism was elucidated

[0049] InGaZnO 4 As one of the characteristics of, the high tolerance of electrical conductivity can be mentioned. This is considered to be due to the generation probability of oxygen vacancies (defects). This is because the electrical conductivity varies variously depending on the amount of oxygen added in the process. Therefore, this mechanism was elucidated due to the fact that the electrical conductivity varies variously depending on the amount of oxygen added in the process. Therefore, this mechanism was elucidated Accordingly, the formation energy of oxygen vacancies was calculated.

[0050] In calculations based on density functional theory (DFT), the energy level of oxygen vacancy defects is still a subject of discussion. For example, the band gaps obtained by functions such as LDA (Local Density Approximation) and GGA tend to be smaller than the measured values. Thus, since there is still discussion about the scaling method, here we simply used the GGA function without the scaling method. This is considered to remove artificial phenomena and enable the grasping of the essence of the phenomenon. functions such as GGA are smaller than the measured values. Thus, since there is still discussion about the scaling method, here we simply used the GGA function without the scaling method. This is considered to remove artificial phenomena and enable the grasping of the essence of the phenomenon. Since there is still discussion about the scaling method, here we simply used the GGA function without the scaling method. This is considered to remove artificial phenomena and enable the grasping of the essence of the phenomenon.

[0051] The energy of the oxygen vacancy (E VO ) is defined as follows. E VO = E(A m O n―1 ) + E(O) - E(A m O n ) Here, E VO is 1 / 2 of the energy of an oxygen molecule, and E(A m O n―1 ) represents the energy of A with an oxygen vacancy. m O n―1 A represents any element.

[0052] Figure 13 shows the calculation results of the geometric optimum value of E VO in the structure with oxygen vacancies. Here, the lattice constant of an ideal crystal was used. A high E means that the density of oxygen vacancies in the thermal equilibrium state is low. In Figure 13, for In VO O, ZnO, Ga O, the E n 2 O 3 , ZnO, Ga 2 O 3 of​VO is also shown together. In 2 O 3 , Zn O, Ga 2 O 3 The crystal structures of are, respectively, the bixbyte type, wurtzite (wurtzite) type, and β-Ga type.

[0053] InGaZnO 4 The E in VO varies depending on the elements around the oxygen vacancy. Specifically, the following three structural models are conceivable. Model 1 is a model in which a certain oxygen vacancy is surrounded by one Zn and three In atoms. Model 2 is a model in which a certain oxygen vacancy is surrounded by one Ga and three In atoms. Model 3 is a model in which a certain oxygen vacancy is surrounded by two Zn and two Ga atoms. From Fig. 13, it can be read that the E in In GaZnO 4 increases as the number of Ga around the oxygen vacancy increases. Also, the E of Ga VO O is the largest, and it can be said that Ga and O are strongly bonded 2 to each other. 3 The E of VO is the largest, and it can be said that Ga and O are strongly bonded to each other.

[0054] InGaZnO 4 When is in an amorphous state, in addition to the above three models, more possible structures exist. And the E in each structure is slightly different. As the proportion of Ga in InGaZ VO nO increases, the density of oxygen vacancies decreases, and as the proportion of Ga in InGaZnO 4 decreases, the density of oxygen vacancies increases. 4 As the proportion of Ga in InGaZnO decreases, the density of oxygen vacancies increases.

[0055] Thus, by increasing the proportion of Ga in the non - single - crystal semiconductor layer 102, the density of oxygen vacancies can be reduced. That is, an In - Ga - Zn - O - based oxide semiconductor with good electrical properties can be obtained. Considering the presence of In that contributes to electrical conduction, it is not preferable to reduce the proportion of In. Therefore, it is preferable to lower the proportion of Zn in the non - single - crystal semiconductor layer 102. For example, the content (atomic %) of Zn in the non - single - crystal semiconductor layer 102 may be less than the content (atomic %) of In and less than the content (atomic %) of Ga. In this way, by reducing the content of Zn in the non - single - crystal semiconductor layer 102, an oxide semiconductor layer with good electrical properties can be obtained. That is, an In - Ga - Zn - O - based oxide semiconductor with good electrical properties can be obtained. Considering the presence of In that contributes to electrical conduction, it is not preferable to reduce the proportion of In. Therefore, it is preferable to lower the proportion of Zn in the non - single - crystal semiconductor layer 102. For example, the content (atomic %) of Zn in the non - single - crystal semiconductor layer 102 may be less than the content (atomic %) of In and less than the content (atomic %) of Ga. In this way, by reducing the content of Zn in the non - single - crystal semiconductor layer 102, an oxide semiconductor layer with good electrical properties can be obtained.

[0056] According to this embodiment, a high - performance oxide semiconductor layer can be provided. Note that this embodiment can be used in appropriate combination with other embodiments. That is, an In - Ga - Zn - O - based oxide semiconductor with good electrical properties can be obtained.

[0057] (Embodiment 2) In this embodiment, the results of further consideration regarding the In - Ga - Zn - O - based oxide semiconductor layer performed in Embodiment 1 will be described with reference to the drawings. That is, an In - Ga - Zn - O - based oxide semiconductor with good electrical properties can be obtained.

[0058] In Embodiment 1, it was shown that the unit cell of the InGaZnO 4 crystal structure is composed of two (Ga, Zn) O 2 layers and one InO 2 layer. In response to this, in this embodiment, a more detailed examination of the arrangement of Ga and Zn was carried out. Specifically, as shown in FIG. 9, several combinations of the upper layer and the lower layer were considered, and the relationship between the arrangement of Ga and Zn in the two (Ga, Zn)O 2 layers and energy was studied. Then, calculations and considerations were carried out.

[0059] The specific combinations (atomic arrangements) for which calculations were performed are shown in Fig. 14. In the present embodiment these combinations were selected by focusing on the number of like atoms in the nearest neighbor relationship. For example, in Fig. the combination of Fig. 14(a) has Ga and Zn separated in the upper layer and the lower layer respectively such that the number of like atoms in the nearest neighbor relationship is zero. Also, the combination of Fig. 1 4(b) is a case where there are 2 like atoms in the nearest neighbor positions, and the combination of Fig. 14(c ) is a case where there are 1.5 like atoms in the nearest neighbor positions, and the combination of Fig. 14(d) is a case where there is 1 like atom in the nearest neighbor position. The calculation conditions were the same as those shown in Embodiment 1.

[0060] The calculation results are shown in Fig. 15. In Fig. 15, the energy of each structure is shown with the structure having the lowest energy as the origin (energy is 0 eV).

[0061] The arrangements investigated in the present embodiment are only a small part of a large number of arrangements, but from the results of Fig. 15 the tendency of the arrangement of Ga and Zn can be read. The results of Fig. 15 are considered to show that as the degree of aggregation of like elements decreases, it becomes more stable energetically . That is, in the InGaZnO 4 crystal structure, it can be concluded that Ga and Zn do not aggregate as GaO or ZnO, but rather take an arrangement in which Ga and Zn are mixed with each other. Fig. 16 shows a model diagram of the most likely arrangement (corresponding to Fig. 15(d)).

[0062] Note that the present embodiment can be used in appropriate combination with other embodiments.​

[0063] (Embodiment 3) In this embodiment, an oxide semiconductor layer formed by the method described in Embodiment 1 or the like is used. An example of a manufacturing process of the semiconductor device will be described with reference to FIG. In this embodiment, detailed description of the same contents as those in the first embodiment will be omitted.

[0064] First, a gate electrode 202 is formed on a substrate 200 having an insulating surface, and then the gate After forming a gate insulating layer 204 on the gate electrode 202, an oxide semiconductor layer 206 and an oxide semiconductor The insulating layer 207 is formed by laminating layers (see FIG. 17(a)).

[0065] The substrate 200 having an insulating surface is, for example, a visible light transmissive substrate used in a liquid crystal display device or the like. The glass substrate may be a non-alkali glass substrate. The alkali-free glass substrate is preferably an aluminosilicate glass plate. Glass materials such as quartz, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, the substrate 200 having an insulating surface may be a resin substrate, a ceramic substrate, a stone substrate, or the like. Insulating substrates made of insulators such as silicon substrates and sapphire substrates, and semiconductor substrates made of semiconductor materials such as silicon A conductive substrate whose surface is covered with an insulating material, or a conductive material made of a conductor such as metal or stainless steel The surface of the substrate can be covered with an insulating material. From the viewpoint of cost efficiency, it is particularly preferable to use a glass substrate. It is preferable that the ion exchange layer 10 has a thickness of 100 nm or less.

[0066] The gate electrode 202 is formed by forming a conductive layer on the entire surface of the substrate 200 and then forming the conductive layer by photolithography. By using the formed resist mask, the conductive layer can be selectively etched to form it. At this time, in order to improve the coverage of the gate insulating layer 204 to be formed later and prevent step breakage, it is preferable to etch the end of the gate electrode 202 so as to have a tapered shape. Note that the gate electrode 202 includes electrodes and wirings formed by the above conductive layer, such as gate wirings. The gate electrode 202 is preferably formed of a low-resistance conductive material such as aluminum (Al) or copper (Cu). When aluminum is used as the wiring and electrode, there are problems such as low heat resistance and easy corrosion in aluminum alone. Therefore, it is preferably formed in combination with a heat-resistant conductive material.

[0067] As the above heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), scandium (Sc), or an alloy containing the above elements as components, or an alloy combining the above elements, or a nitride containing the above elements as components can be used. A film made of these heat-resistant conductive materials and aluminum (or copper) can be laminated to form a wiring or an electrode. The gate insulating layer 204 can be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like.

[0068] These films can also be laminated and provided. These films can be formed with a film thickness of 20 nm or more and 250 nm or less using a sputtering method or the like. For example, as the gate insulating layer 204, from the elements selected, or an alloy containing the above-mentioned elements as components, or an alloy combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components can be used. These heat-resistant conductive materials can be laminated with aluminum (or copper) to form wirings and electrodes. The gate insulating layer 204 can be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, etc. Also, these films may be laminated and provided. These films can be formed with a film thickness of 20 nm or more and 250 nm or less using a sputtering method or the like.

[0069] The gate insulating layer 204 can be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, etc. Also, these films may be laminated and provided. These films can be formed with a film thickness of 20 nm or more and 250 nm or less using a sputtering method or the like. For example, as the gate insulating layer 204, The gate insulating layer 204 can be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, etc. A silicon oxide film is formed to a thickness of 100 nm by a sputtering method. Note that the gate insulating layer 2 04 only needs to function as the gate insulating layer of the transistor, and the manufacturing method, film thickness, etc. should not be interpreted as being limited to the above numerical ranges.

[0070] Note that before forming the oxide semiconductor layer 206 on the gate insulating layer 204, the surface of the gate insulating layer 20 4 may be subjected to plasma treatment. By performing the plasma treatment, dust adhering to the surface of the gate insulating layer 204 can be removed.

[0071] The above plasma treatment is performed by introducing an inert gas such as argon (Ar) gas into a chamber in a vacuum state, and applying a bias voltage to the object to be processed (here, the substrate 200 on which the gate insulating layer 204 is formed) to form a plasma state. In this case, electrons and Ar positive ions exist in the plasma, and Ar positive ions are accelerated in the cathode direction (substrate 200 side). When the accelerated Ar positive ions collide with the surface of the gate insulating layer 204, the surface of the gate insulating layer 204 is sputter-etched, and the surface can be modified. Note that instead of argon gas, helium gas may be used. Also, the treatment may be performed in an atmosphere in which oxygen, hydrogen, nitrogen, etc. are added to the argon atmosphere. Also, the treatment may be performed in an atmosphere in which chlorine (Cl 2 ) or carbon tetrafluoride (CF 4 ) etc. are added to the argon atmosphere. Such 2 ) or carbon tetrafluoride (CF 4 ) etc. are added to the argon atmosphere. Such a plasma treatment is sometimes referred to as "reverse sputtering".

[0072] The oxide semiconductor layer 206 can be formed of an In-Ga-Zn-O-based polycrystalline semiconductor layer. Cut. For example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) Semiconductor target (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1) is used in the sputtering method to form the oxide semiconductor layer 206. For the sputtering conditions and the like, refer to Embodiment 1 etc. for reference.

[0073] Note that when a pulsed DC power supply is used in the above sputtering, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. Also, after performing the above-described plasma treatment, without exposing to the atmosphere by forming the oxide semiconductor layer 206, it is possible to suppress the adhesion of dust and moisture to the interface between the gate insulating layer 204 and the oxide semiconductor layer 206. The film thickness of the oxide semiconductor layer 2 06 may be about 5 nm to 500 nm.

[0074] The oxide semiconductor layer 207 can be formed of an In-Ga-Zn-O-based non-single crystal semiconductor layer in the same manner as the oxide semiconductor layer 206. For example, an oxide semiconductor target containing In, Ga, and Zn (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1) is used in the sputtering method to form the oxide semiconductor layer 207 on the oxide semiconductor layer 206. At this time, it is preferable to continuously form the oxide semiconductor layer 207 without exposing the oxide semiconductor layer 206 to the atmosphere . The sputtering conditions can be, for example, a temperature of 20°C to 100°C, a pressure of 0.1 Pa to 2 .0 Pa, and a power of 250 W to 3 kW (when 8 inches in diameter). Also, it is good to introduce argon gas into the atmosphere.

[0075] It is preferable to make the film formation conditions of the oxide semiconductor layer 206 and the oxide semiconductor layer 207 different. For example, in the film formation conditions of the oxide semiconductor layer 206, compared with the film formation conditions of the oxide semiconductor layer 207 increase the ratio of the flow rate of oxygen gas to the flow rate of argon gas. Specifically, the film formation conditions of the oxide semiconductor layer 207 are in an atmosphere of a noble gas (such as argon or helium), or in an atmosphere of 10% or less of oxygen gas and 90% or more of noble gas, and the film formation conditions of the oxide semiconductor layer 206 are in an oxygen atmosphere or in an atmosphere where the flow rate ratio of oxygen gas to noble gas is 1 or more. By doing so, an oxide semiconductor layer 207 with higher electrical conductivity than the oxide semiconductor layer 206 can be formed.

[0076] As the sputtering method for forming the oxide semiconductor layer 206 or the oxide semiconductor layer 207, an RF sputtering method using a high-frequency power source for the sputtering power supply, a DC sputtering method, a pulsed DC sputtering method in which a DC bias is applied pulsatively, etc. can be used.

[0077] Also, a multi-source sputtering apparatus capable of installing a plurality of targets made of different materials may be used. In a multi-source sputtering apparatus, different films can be laminated and formed in the same chamber, or a single film can be formed by simultaneously sputtering a plurality of types of materials in the same chamber. Furthermore, a method using a magnetron sputtering apparatus equipped with a magnetic field generation mechanism inside the chamber (magnetron sputtering method), an ECR sputtering method using plasma generated using microwaves, etc. may be used. Also, a reactive sputtering method in which a chemical reaction is caused between the target substance and the sputtering gas component during film formation to form a compound thereof, a bias sputtering method in which a voltage is also applied to the substrate during film formation, etc. may be used. ​

[0078] Note that in this embodiment, when the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are stacked, However, the disclosed invention is not limited to this. A structure in which the semiconductor layer 207 is not provided (a structure in which only the oxide semiconductor layer 206 is formed) may be used. stomach.

[0079] Next, a resist mask 208 is formed over the oxide semiconductor layer 207. 08, the oxide semiconductor layer 206 and the oxide semiconductor layer 207 were selectively etched. An island-shaped oxide semiconductor layer 210 and an island-shaped oxide semiconductor layer 211 are formed (FIG. 17(b) reference).

[0080] For the above etching, it is recommended to use wet etching. For example, ITO07N (Kanto Chemical Co., Ltd.), or by wet etching using a mixture of acetic acid, nitric acid, and phosphoric acid. Then, unnecessary portions of the oxide semiconductor layer 206 and the oxide semiconductor layer 207 are removed to form island-shaped oxide semiconductor layers. The oxide semiconductor layer 210 and the island-shaped oxide semiconductor layer 211 are formed. The resist mask 208 is then removed. The material may be any material that can etch the oxide semiconductor layers 206 and 207. Of course, the above etching may be dry etching. You may use it.

[0081] Next, the conductive layer 212 is formed over the island-shaped oxide semiconductor layer 211 (see FIG. 17(c)).

[0082] The conductive layer 212 is formed by depositing aluminum (Al), copper (Cu) or the like by using a sputtering method or a vacuum deposition method. ) Metals containing elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), alloys composed of the above elements, alloys combining the above elements, or materials made of nitrides or the like containing the above elements as components. In this embodiment, after the formation of the conductive layer 212, heat treatment (for example, 350°C to 800°C (preferably 500 to 750°C)) is performed, so it is preferable to give the conductive layer 212 a predetermined heat resistance.

[0083] For example, the conductive layer 212 can be formed with a single-layer structure of a titanium film. Also, the conductive layer 212 may have a laminated structure, for example, a laminated structure of an aluminum film and a titanium film. Also, a three-layer structure of a titanium film, an aluminum (Al-Nd) film containing neodymium, and a titanium film may be used. Further, the conductive layer 212 may have a single-layer structure of an aluminum film containing silicon.

[0084] Next, resist masks 214a, 214b, and 214c are formed on the conductive layer 212, and the conductive layer 212 is selectively etched to form conductive layers 216a, conductive layer 216b, and conductive layer 218. At the same time, the island-shaped oxide semiconductor layer 211 is etched to form high-conductivity semiconductor regions 215a and 215b, and a part (a part near the surface) of the island-shaped oxide semiconductor layer 210 is removed (channel etching) (see FIG. 1 7(d)).

[0085] A part of the island-shaped oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 are removed. The recess 220 formed is located between the conductive layer 216a and the conductive layer 216b, and in the region between the high-conductivity semiconductor region 215a and the high-conductivity semiconductor region 215b. Therefore, the conductive layer 216a functions as one of the source electrode or the drain electrode of the transistor, and the conductive layer 216b functions as the other of the source electrode or the drain electrode of the transistor. As shown in FIG. 17(d), by removing a part of the oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 to form the recess 220, the insulation between the conductive layer 216a and the conductive layer 216b can be ensured. Further, the conductive layer 218 functions as a wiring for electrically connecting transistors and the like. As described above, the conductive layer 216a functions as one of the source electrode or the drain electrode of the transistor, and the conductive layer 216b functions as the other of the source electrode or the drain electrode of the transistor. As shown in FIG. 17(d), by removing a part of the oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 to form the recess 220, the insulation between the conductive layer 216a and the conductive layer 216b can be ensured. Further, the conductive layer 218 functions as a wiring for electrically connecting transistors and the like. As shown in FIG. 17(d), by removing a part of the oxide semiconductor layer 210 and a part of the island-shaped oxide semiconductor layer 211 to form the recess 220, the insulation between the conductive layer 216a and the conductive layer 216b can be ensured. Further, the conductive layer 218 functions as a wiring for electrically connecting transistors and the like. For the above etching, it is preferable to use dry etching. By using dry etching, miniaturization of the wiring structure and the like becomes possible as compared with the case of using wet etching. Further, by using dry etching, the controllability of etching is good, so that the removal of the island-shaped oxide semiconductor layer 210 (formation of the recess 220) can be performed with good controllability.

[0086] For the above etching, it is preferable to use dry etching. By using dry etching, miniaturization of the wiring structure and the like becomes possible as compared with the case of using wet etching. Further, by using dry etching, the controllability of etching is good, so that the removal of the island-shaped oxide semiconductor layer 210 (formation of the recess 220) can be performed with good controllability. For the above etching, it is preferable to use dry etching. By using dry etching, miniaturization of the wiring structure and the like becomes possible as compared with the case of using wet etching. Further, by using dry etching, the controllability of etching is good, so that the removal of the island-shaped oxide semiconductor layer 210 (formation of the recess 220) can be performed with good controllability. Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 2 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 3 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 4 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 4 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 4 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 6 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 3 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 3 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above 2 Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above Gases that can be used for dry etching include chlorine-based gases such as chlorine (Cl), boron chloride (BCl), silicon chloride (SiCl), carbon tetrachloride (CCl), and fluorine-based gases such as carbon tetrafluoride (CF), sulfur hexafluoride (SF), nitrogen trifluoride (NF), trifluoromethane (CHF), hydrogen bromide (HBr), oxygen (O), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases. Of course, the above Wet etching may be used as the etching.

[0087] Also, as the material of the conductive layer 212, it is preferable to use a material having an etching rate higher than that of the island-shaped oxide semiconductor layer 210 or the island-shaped oxide semiconductor layer 211. This is because when the conductive layer 212, the island-shaped oxide semiconductor layer 210, and the island-shaped oxide semiconductor layer 211 are etched at once, by making the etching rate of the island-shaped oxide semiconductor layer 210 or the island-shaped oxide semiconductor layer 211 smaller than the etching rate of the conductive layer 212, it is possible to suppress the excessive etching of the island-shaped oxide semiconductor layer 210. body layer 211, it is possible to suppress the excessive etching of the island-shaped oxide semiconductor layer 210. 12, the island-shaped oxide semiconductor layer 210, and the island-shaped oxide semiconductor layer 211 are etched at once. etching rate of the conductive layer 212, it is possible to suppress the excessive etching of the island-shaped oxide semiconductor layer 210. etching rate of the conductive layer 212, it is possible to suppress the excessive etching of the island-shaped oxide semiconductor layer 210. layer 210 can be suppressed.

[0088] After the above etching, the resist masks 214a, 214b, and 214c are removed. etching, the resist masks 214a, 214b, and 214c are removed.

[0089] Thereafter, heat treatment is performed under predetermined temperature conditions (for example, 350°C to 800°C (preferably 500 to 750°C)). When using a glass substrate as the substrate 200 having an insulating surface, it is necessary to perform heat treatment under temperature conditions below the strain point of the glass substrate. The atmosphere for the heat treatment may be an air atmosphere or a nitrogen atmosphere. By this heat treatment, crystal grains of the oxide semiconductor grow in the island-shaped oxide semiconductor layer 210, and an oxide semiconductor layer (In-Ga-Zn-O-based oxide semiconductor layer) containing crystal grains represented by InGaO (ZnO) (m>0) in the amorphous structure, and containing crystal grains represented by InGaO (ZnO) (m = 1) can be obtained. 3 (ZnO) m (m>0) in the amorphous structure, and containing crystal grains represented by InGaO (ZnO) 3 (ZnO) m (m = 1) can be obtained. body layer (In-Ga-Zn-O-based oxide semiconductor layer) can be obtained.

[0090] Note that an amorphous oxide semiconductor is easily changed to a crystalline oxide semiconductor by heat or the like. In the case of a high ratio of the amorphous structure, the reliability of the transistor tends to decrease in order to transform it. From the viewpoint of improving reliability, heat treatment is performed so that the amorphous structure is 90% by volume or less (preferably 80% by volume or less, more preferably 60% by volume or less). The heat treatment is performed so that the amorphous structure is 90% by volume or less (preferably 80% by volume or less, more preferably 60% by volume or less).

[0091] The heat treatment time can be appropriately changed according to the heat treatment temperature. For example, at a temperature of 700 ° C, it may be about 0.5 to 2 hours. In addition, since the temperature conditions suitable for the heat treatment vary depending on the composition of the target oxide semiconductor, there is no particular limitation as long as the desired oxide semiconductor layer can be obtained. The heat treatment time can be appropriately changed according to the heat treatment temperature. For example, at a temperature of 700 ° C, it may be about 0.5 to 2 hours. In addition, since the temperature conditions suitable for the heat treatment vary depending on the composition of the target oxide semiconductor, there is no particular limitation as long as the desired oxide semiconductor layer can be obtained. The heat treatment time can be appropriately changed according to the heat treatment temperature. For example, at a temperature of 700 ° C, it may be about 0.5 to 2 hours. In addition, since the temperature conditions suitable for the heat treatment vary depending on the composition of the target oxide semiconductor, there is no particular limitation as long as the desired oxide semiconductor layer can be obtained. The heat treatment time can be appropriately changed according to the heat treatment temperature. For example, at a temperature of 700 ° C, it may be about 0.5 to 2 hours. In addition, since the temperature conditions suitable for the heat treatment vary depending on the composition of the target oxide semiconductor, there is no particular limitation as long as the desired oxide semiconductor layer can be obtained.

[0092] The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used. The above heat treatment can be performed using a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Anneal) apparatus, a microwave heating apparatus, or the like. Instead of the heat treatment, light (electromagnetic wave) having a wavelength absorbed by the oxide semiconductor may be irradiated. That is, a structure including crystal grains in the amorphous structure may be realized by irradiation with light (electromagnetic wave). In this case, as the light source, a laser oscillator capable of oscillating at a short wavelength, an ultraviolet lamp, or the like may be used.

[0093] Thus, by using an oxide semiconductor layer including crystal grains represented by InGaO(ZnO)(m>0) as a channel formation region of a transistor, a high-performance semiconductor device can be provided. 3 (ZnO) m (m>0) in the amorphous structure represented by InGaO(ZnO)(m>0), InGaO(ZnO)(m = 1) O 3 (ZnO) m (m = 1) as a channel formation region of a transistor, a high-performance semiconductor device can be provided. Thus, by using an oxide semiconductor layer including crystal grains represented by InGaO(ZnO)(m>0) as a channel formation region of a transistor, a high-performance semiconductor device can be provided.

[0094] Here, in order to realize an oxide semiconductor layer having good electrical characteristics, for example, an oxide semiconductor The content of Zn in the body (atomic %) is preferably less than the content of In (atomic %) and less than the content of Ga (atomic %). By setting such a composition, an oxide semiconductor layer having good characteristics can be obtained.

[0095] In addition, for the oxide semiconductor layer in which the content of Zn (atomic %) is less than the content of In (atomic %) and less than the content of Ga as described above, it can be formed by a sputtering method using a target close to the target composition. In this case, considering FIGS. 2 and 3, compared with the composition of the target, the ratio of Zn decreasing in the formed oxide semiconductor layer is larger than that of In and Ga. Therefore, for example, to form an oxide semiconductor layer in which the content of Zn (atomic %) is less than the content of In (atomic %) and less than the content of Ga (atomic %), a target in which the content of Zn (atomic %) is equal to the content of In or Ga (atomic %) may be used. That is, as the target, one in which the content of Zn (atomic %) is less than or equal to the content of In (atomic %) and less than or equal to the content of Ga (atomic %) may be used.

[0096] Here, in the present embodiment, an example in the case where the above heat treatment is performed after the formation of the island-shaped oxide semiconductor layer 210 is shown, but the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor layer 206. Further, if a structure in which a plurality of crystal grains are included in the amorphous structure (a structure in which a plurality of crystal grains are dispersed in the amorphous structure) can be obtained at the film formation stage, the heat treatment is unnecessary.

[0097] In addition, for the concave portion 220 of the exposed island-shaped oxide semiconductor layer 210, oxygen radicals ​​​​​​Processing may be performed. By performing oxygen radical treatment, the island-shaped oxide semiconductor layer 210 can be easily made into a normally-off thin film transistor having a channel formation region. Also, by performing radical treatment, damage caused by etching of the island-shaped oxide semiconductor layer 210 can be repaired. The radical treatment is preferably performed in an atmosphere of O 2 , N 2 O, N containing oxygen 2 , He , Ar, etc. Further, it may be performed in an atmosphere in which Cl 2 , CF 4 is added. Note that the radical treatment is preferably performed without applying a bias voltage to the substrate 200 side.

[0098] Next, a protective insulating layer 222 is formed so as to cover the thin film transistor 250 including the gate electrode 202, the island-shaped oxide semiconductor layer 210, the semiconductor region 215a with high conductivity, the semiconductor region 215b with high conductivity, the conductive layer 216a, the conductive layer 216b, etc. (see Fig. 17(e)). As the protective insulating layer 222, a layer containing a material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, tantalum oxide, etc. may be formed using a sputtering method or the like.

[0099] Thereafter, the semiconductor device is completed by forming various electrodes and wirings.

[0100] According to this embodiment, a high-performance semiconductor device can be provided. Note that this embodiment can be used in appropriate combination with other embodiments.

Description of Reference Numerals

[0101] 100 Substrate 102 Non-single crystal semiconductor layer 104 crystal grains 106 oxide semiconductor layer 200 substrate 202 gate electrode 204 gate insulating layer 206 oxide semiconductor layer 207 oxide semiconductor layer 208 resist mask 210 oxide semiconductor layer 211 oxide semiconductor layer 212 conductive layer 214a resist mask 214b resist mask 214c resist mask 215a semiconductor region 215b semiconductor region 216a conductive layer 216b conductive layer 218 conductive layer 220 recess 222 protective insulating layer 250 thin film transistor

Claims

[Claim 1] A semiconductor device including an In—Ga—Zn—O-based oxide semiconductor layer in a channel formation region of a transistor, The In—Ga—Zn—O-based oxide semiconductor layer is InGaO ３ (ZnO) ｍ In the amorphous structure represented by (m>0), InGaO ３ (ZnO) ｍ A semiconductor device having a structure including crystal grains represented by (m=1).

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