Semiconductor device

Abstract

To reduce the standby power or suppress the malfunction in a logic circuit performing clock gating.SOLUTION: A logic circuit includes a transistor that is turned off in a state that a potential difference exists between a source terminal and a drain terminal in a period for which a clock signal is not supplied. A channel formation region of the transistor is formed of an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms / cm3) or less. Thus, the leakage current of the transistor can be reduced. As a result, the standby power can be reduced and the malfunction can be suppressed in the logic circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a logic circuit. In particular, it relates to a logic circuit having a transistor in which a channel formation region is formed of an oxide semiconductor. It also relates to a semiconductor device having the logic circuit. Here, in this specification, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electrical equipment are all semiconductor devices.

[0002]

Background Art

[0003] Generally, in a circuit having transistors fabricated using a Si-wafer or SOI (Silicon On Insulator), as the microfabrication progresses and the operating voltage decreases, the power consumption decreases.

[0004]

[0005]

Prior Art Documents

[0006] [Patent Document 1] JP 2008-219882 A Summary of the Invention [Problem to be solved by the invention]

[0007] Standby power is generally the power consumed by circuits that are not in operation (hereafter referred to as non-operating circuits) and the power consumed by Leakage current of a transistor (generally, the leakage current between the source and drain when the gate-source voltage is 0V) The power consumed by the load is divided into two parts: the power consumed by the load (current flowing through the load) and the power consumed by the load (current flowing through the load).

[0008] The clock gating described above can reduce dynamic power consumption, but it also has a drawback in that it It is not possible to reduce the static power consumption due to the clock current in non-operating circuits. Dynamic power consumption includes the charging and discharging of parasitic capacitance in the wiring that supplies the clock signal. Furthermore, in a circuit that performs clock gating, Therefore, the state of each element constituting the non-operating circuit is maintained. The proportion of standby power consumed by power dissipation caused by current flow will increase. The current increases the probability of logic circuits malfunctioning.

[0009] In view of the above-described problems, one embodiment of the present invention provides a logic circuit that performs clock gating. One object of the present invention is to reduce standby power consumption or suppress malfunctions caused by leakage current. do. [Means for solving the problem]

[0010] One embodiment of the present invention is to provide an oxide semiconductor having an impurity (hydrogen or is a true or substantially true semiconductor obtained by removing impurities (such as water), and is a silicon semiconductor in which a channel formation region is formed of an oxide semiconductor having an energy gap larger than that of silicon, and a transistor is applied to an N-type transistor in which a logic circuit has a transistor.

[0011] Specifically, the hydrogen contained in the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less , preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×10 17 ( atoms / cm 3 ) or less, and the hydrogen or OH group contained in the oxide semiconductor is removed , and the carrier density is 5×10 14 / cm 3 or less, preferably 5×10 12 / cm 3 or less, and a logic circuit is configured by a transistor in which a channel formation region is formed of an oxide semiconductor thus formed.

[0012] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier density is 5×10 14 / cm 3 or less, preferably 5×10 12 / cm 3 or less.

[0013] The oxide semiconductor purified in this way is used for the channel formation region of the transistor, so that even when the channel width is 10 mm, when the drain voltage is 1 V and 10 V, In the case where the gate voltage is in the range of -5V to -20V, the drain current acts so as to be 1×10 -1 3 [A] or less. That is, by applying a highly purified oxide semiconductor to the channel formation region of the transistor, the leakage current can be significantly reduced. That is, one aspect of the present invention is a logic circuit having a first period in which a clock signal is input and a second period in which the clock signal is not input, and over the second period, a source terminal and a drain terminal having a transistor that turns off in a state where a potential difference exists, and the channel formation region of the transistor has a hydrogen concentration of 5×10

[0014] It is a logic circuit characterized in that it is composed of an oxide semiconductor of (atoms / cm ) or less. 19 19 (atoms / cm 3 ) or less.

Effect of the Invention

[0015] The logic circuit according to one aspect of the present invention has a transistor that turns off in a state where a potential difference exists between the source terminal and the drain terminal over a period when the clock signal is not supplied. The channel formation region of the transistor is composed of an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 19 (atoms / cm 3 ) or less. Therefore, the leakage current of the transistor can be reduced. As a result, the standby power of the logic circuit can be reduced and malfunction can be suppressed. In particular, in a logic circuit where clock gating is performed, the state within the logic circuit remains for a long time

[0016] ​​​​It will be maintained. That is, a specific transistor will turn off for a long time while there is a potential difference between the source terminal and the drain terminal. Applying such a transistor as the transistor has a great effect.

[0017] In addition, by reducing the power consumption of the entire circuit, the load on the external circuit for operating the logic circuit according to one aspect of the present invention can be reduced. Thereby, the semiconductor device having the logic circuit and the external circuit can be functionally extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0018]

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Mode for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0020] Note that since the source terminal and drain terminal of the transistor change depending on the structure and operating conditions of the transistor, etc., it is difficult to specify which is the source terminal or drain terminal. Therefore, in this document, one of the source terminal and drain terminal is designated as the first terminal and the other of the source terminal and drain terminal is designated as the second terminal for distinction.

[0021] In addition, the size, layer thickness, or area of each component shown in the drawings and the like of each embodiment may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Also, the ordinal numbers such as "first", "second", and "third" used in this specification are added to avoid confusion of components and it is noted that they are not numerically limiting.

[0022] (Embodiment 1) In this embodiment, an example of a logic circuit in which clock gating is performed will be described. ​​​​​. Specifically, the period during which the clock signal is input and the period during which the clock signal is not input are described with reference to FIG. 1 for an example of a logic circuit that has the clock signal and performs arithmetic processing using the clock signal.

[0023] The logic circuit 10 shown in FIG. 1 has a first input terminal 11 electrically connected to a wiring (hereinafter also referred to as a pulse signal line) that supplies a pulse signal (PS), a second input terminal 12 electrically connected to a wiring (hereinafter also referred to as a data signal line) that supplies a data signal (Data), and an output terminal 13. The logic circuit 10 has a period during which a clock signal (CK) is supplied and a period during which the clock signal is not supplied via the pulse signal line. That is, the logic circuit shown in FIG. 1 is a logic circuit in which clock gating is performed. Note that the non - supply of the clock signal means that the clock signal is fixed at a high - level potential or a low - level potential, and a signal that changes from high level to low level and from low level to high level is not supplied.

[0024] Furthermore, the logic circuit 10 of the present embodiment shown in FIG. 1 has a main logic circuit section 14 and a transistor 15 that turns off in a state where there is a potential difference between the source terminal and the drain terminal over a period during which the clock signal is not supplied. The main logic circuit section 14 is composed of a plurality of elements such as transistors, capacitive elements, or resistive elements.

[0025] Also, the channel formation region of the transistor 15 has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) or less, preferably 5×10 18 (atoms / cm 3 ) or less, and more preferably​​​​​​​​​​​​ is 5×10 17 (atoms / cm 3 ) and is composed of the following oxide semiconductors. That is, transistor 15 is a transistor in which an oxide semiconductor with highly purified hydrogen, which serves as a carrier donor, reduced to an extremely low concentration, is applied to the channel formation region. Note that the hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Spectroscopy). .

[0026] The logic circuit of this embodiment is a logic circuit in which clock gating is performed, and during the period in which the clock gating is performed (that is, the period in which the clock signal is not input), it has a transistor that turns off while having a potential difference between the source terminal and the drain terminal. The transistor has a channel formation region formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 The hydrogen concentration of the oxide semiconductor is 5×10 (atoms / cm 19 ) or less, preferably 5×10 3 (atoms / cm 18 ) or less, more preferably 5×10 3 (atoms / cm 17 ) or less, and is controlled to be 5×10 3 (atoms / cm -13 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 [A] or less. That is, the leakage of charge through the transistor can be suppressed. As a result, it is possible to reduce the standby power during the period and suppress malfunction of the logic circuit during the period.

[0027] In particular, in a logic circuit in which clock gating is performed, the state within the logic circuit remains unchanged for a long time​​​ will be maintained. That is, a specific transistor will be turned off for a long time while there is a potential difference between the source terminal and the drain terminal. Applying such a transistor to the transistor has a great effect as described above.

[0028] In addition, by reducing the power consumption of the logic circuit, the load on the external circuit for operating the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be enhanced in function.

[0029] Note that the content of the present embodiment or a part of the content can be freely combined with the content of another embodiment or a part of the content, or the content of another example or a part of the content.

[0030] (Embodiment 2) In the present embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically, with reference to FIGS. 2 to 4, a logic circuit having an AND gate and a flip-flop will be described.

[0031] <Configuration Example of Logic Circuit> The logic circuit 200 of the present embodiment shown in FIG. 2(A) includes an AND gate 201 electrically connected to a wiring (hereinafter also referred to as an enable signal line) that supplies an enable signal (EN) to a first input terminal, and a second input terminal electrically connected to a wiring (hereinafter also referred to as a clock signal line) that supplies a clock signal (CK). The AND gate 201 has a flip -flop 202 whose first input terminal is electrically connected to a data signal line and whose second input terminal is electrically connected to the output terminal of the AND gate 201.

[0032] Note that the flip-flop 202 included in the logic circuit of the present embodiment utilizes a feedback operation to hold data for one bit. Also, the output signal of the flip-flop 202 becomes the output signal of the logic circuit 200.

[0033] <Operation Example of Logic Circuit> The operation of the logic circuit shown in FIG. 2(A) will be described below with reference to the timing chart shown in FIG. 2(B).

[0034] During period T1, the enable signal line functions as a wiring that supplies a high-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 becomes the clock signal (CK). That is, the clock signal (CK) is input to the second input terminal of the flip-flop 202. The flip-flop 202 operates based on the input clock signal (CK). Specifically, the flip-flop 202 captures the data signal (D0 or D1) when the clock signal (CK) changes from a low level to a high level, and outputs the data signal when the clock signal (CK) changes from a high level to a low level.

[0035] During period T2, the enable signal line functions as a wiring that supplies a low-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 becomes a low-level signal. That is, a low-level signal is input to the second input terminal of the flip-flop 202. At this time, the output signal (Out) of the logic circuit maintains the data signal (D1).

[0036] During period T3, the enable signal line again functions as a wiring that supplies a high-level signal. functions. That is, similar to the period T1, the flip-flop 202 captures the data signal (D2 or D3) when the clock signal (C K) changes from the low level to the high level, and outputs the data signal when the clock signal (CK) changes from the high level to the low level. forces.

[0037] In the logic circuit of the present embodiment, the clock signal input to the flip-flop 20 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on the flip-flop 202.

[0038] Note that the logic circuit of the present embodiment reads data when the clock signal input to the flip-flop 202 changes to the high level, and holds the read data during one clock cycle. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the period T1 or the period T3 during which the flip-flop 202 operates has elapsed.

[0039] <Circuit Configuration Examples of AND Gate and Flip-Flop> Specific circuit configuration examples of the AND gate 201 included in the logic circuit shown in FIG. 2(A) are shown in FIGS. 3 (A) and (B), and specific circuit configuration examples of the flip-flop 202 are shown in FIGS. 4(A) to ( C).

[0040] The AND gate shown in FIG. 3(A) includes transistors 211 to 216. Note that the transistors 211, 214, and 215 are P-type transistors, and the transistors 212, 213, and 216 are N-type transistors.

[0041] The transistor 211 has its gate terminal electrically connected to the enable signal line, and its first terminal​​​​​​ is electrically connected to a wiring that supplies a high power supply potential (VDD) (hereinafter also referred to as a high power supply potential line). It is supplied.

[0042] The transistor 212 has a gate terminal electrically connected to the enable signal line and the gate terminal of the transistor 211, and a first terminal electrically connected to the second terminal of the transistor 211. It is connected. It is connected.

[0043] The transistor 213 has a gate terminal electrically connected to the clock signal line, a first terminal electrically connected to the second terminal of the transistor 212, and a second terminal electrically connected to a wiring that supplies a low power supply potential (VSS) (hereinafter also referred to as a low power supply potential line). It is connected. It is connected.

[0044] The transistor 214 has a gate terminal electrically connected to the clock signal line and the gate terminal of the transistor 213, a first terminal electrically connected to the high power supply potential line, and a second terminal electrically connected to the second terminal of the transistor 211 and the first terminal of the transistor 212. It is connected. It is connected.

[0045] The transistor 215 has a gate terminal electrically connected to the second terminal of the transistor 211, the first terminal of the transistor 212, and the second terminal of the transistor 214, and a first terminal electrically connected to the high power supply potential line. It is connected. It is connected.

[0046] The transistor 216 has a gate terminal electrically connected to the second terminal of the transistor 211, the first terminal of the transistor 212, the second terminal of the transistor 214, and the gate terminal of the transistor 215, a first terminal electrically connected to the second terminal of the transistor 215, and a second terminal electrically connected to the low power supply potential line. It is connected. It is connected. It is connected.

[0047] In the AND gate, the potential of the node to which the second terminal of transistor 215 and the first terminal of transistor 216 are electrically connected is output as the output signal (AND(Out )) of the AND gate. )) of the AND gate.

[0048] Also, in this specification, the high power supply potential (VDD) and the low power supply potential (VSS) may be any potential as long as the high power supply potential (VDD) is higher than the low power supply potential (VSS) when they are compared with each other. For example, as the low power supply potential (VSS), a ground potential or 0V can be applied, and as the high power supply potential (VDD), any positive potential can be applied. Also, in this specification, the high power supply potential (VDD) and the low power supply potential (VSS) may be any potential as long as the high power supply potential (VDD) is higher than the low power supply potential (VSS) when they are compared with each other. For example, as the low power supply potential (VSS), a ground potential or 0V can be applied, and as the high power supply potential (VDD), any positive potential can be applied. Also, in this specification, the high power supply potential (VDD) and the low power supply potential (VSS) may be any potential as long as the high power supply potential (VDD) is higher than the low power supply potential (VSS) when they are compared with each other. For example, as the low power supply potential (VSS), a ground potential or 0V can be applied, and as the high power supply potential (VDD), any positive potential can be applied. Also, in this specification, the high power supply potential (VDD) and the low power supply potential (VSS) may be any potential as long as the high power supply potential (VDD) is higher than the low power supply potential (VSS) when they are compared with each other. For example, as the low power supply potential (VSS), a ground potential or 0V can be applied, and as the high power supply potential (VDD), any positive potential can be applied.

[0049] The AND gate shown in FIG. 3(B) includes transistors 221 to 225. Note that transistors 221 to 225 are N-type transistors. In addition, transistors 221 to 225 are enhancement-type transistors having a positive threshold voltage. The AND gate shown in FIG. 3(B) includes transistors 221 to 225. Note that transistors 221 to 225 are N-type transistors. In addition, transistors 221 to 225 are enhancement-type transistors having a positive threshold voltage. The AND gate shown in FIG. 3(B) includes transistors 221 to 225. Note that transistors 221 to 225 are N-type transistors. In addition, transistors 221 to 225 are enhancement-type transistors having a positive threshold voltage. The AND gate shown in FIG. 3(B) includes transistors 221 to 225. Note that transistors 221 to 225 are N-type transistors. In addition, transistors 221 to 225 are enhancement-type transistors having a positive threshold voltage.

[0050] The gate terminal and the first terminal of transistor 221 are electrically connected to the high power supply potential line. The gate terminal and the first terminal of transistor 221 are electrically connected to the high power supply potential line.

[0051] The gate terminal of transistor 222 is electrically connected to the enable signal line, and the first terminal is electrically connected to the second terminal of transistor 221. The gate terminal of transistor 222 is electrically connected to the enable signal line, and the first terminal is electrically connected to the second terminal of transistor 221.

[0052] The gate terminal of transistor 223 is electrically connected to the clock signal line, the first terminal is electrically connected to the second terminal of transistor 222, and the second terminal is electrically connected to the low power supply potential line. The gate terminal of transistor 223 is electrically connected to the clock signal line, the first terminal is electrically connected to the second terminal of transistor 222, and the second terminal is electrically connected to the low power supply potential line. The gate terminal of transistor 223 is electrically connected to the clock signal line, the first terminal is electrically connected to the second terminal of transistor 222, and the second terminal is electrically connected to the low power supply potential line.

[0053] The transistor 224 has its gate terminal and first terminal electrically connected to the high power supply potential line. .

[0054] The transistor 225 has its gate terminal electrically connected to the second terminal of the transistor 221 and the first terminal of the transistor 222, its first terminal electrically connected to the second terminal of the transistor 224, and its second terminal electrically connected to the low power supply potential line.

[0055] In this AND gate, the potential of the node where the second terminal of the transistor 224 and the first terminal of the transistor 225 are electrically connected is output as the output signal (AND(Out )) of the AND gate.

[0056] Also, the transistors 221 and 224 are enhancement-type transistors with their gate terminals and first terminals electrically connected to the high power supply potential line. Therefore, the transistors 221 and 224 maintain an on state regardless of the period. In other words, the transistors 221 and 224 are utilized as resistance elements.

[0057] Also, the first input terminal and the second input terminal of the AND gate are interchangeable. That is, the terminal defined as being electrically connected to the enable signal line in the above description is electrically connected to the clock signal line, and the terminal defined as being electrically connected to the clock signal line is electrically connected to the enable signal line, and such a configuration is possible.

[0058] The flip-flop shown in FIG. 4(A) has NAND gates 231 to NAND gate 23 4.

[0059] The NAND gate 231 has its first input terminal electrically connected to the data signal line and its second input terminal electrically connected to the output terminal of the AND gate.

[0060] The NAND gate 232 has its first input terminal electrically connected to the output terminal of the NAND gate 231, and its second terminal electrically connected to the output terminal of the AND gate and the second input terminal of the NAND gate 231.

[0061] The NAND gate 233 has its first input terminal electrically connected to the output terminal of the NAND gate 231 and the first input terminal of the NAND gate 232.

[0062] The NAND gate 234 has its first input terminal electrically connected to the output terminal of the NAND gate 233, its second input terminal electrically connected to the output terminal of the NAND gate 232, and its output terminal electrically connected to the second input terminal of the NAND gate 233.

[0063] The flip-flop shown in FIG. 4(A) is a Delay type flip-flop. Note that the flip-flop of this embodiment is a Delay type flip-flop that uses only the Q terminal as the output terminal, but it may also have a configuration with two output terminals, the Q terminal and the QB terminal (the output terminal of the NAND gate 234).

[0064] Also, the flip-flop shown in FIG. 4(A) is an example, and the flip-flop of this embodiment is not limited to this configuration. That is, the flip-flop of this embodiment may have any configuration as long as it is a circuit that can hold 1-bit data using a feedback operation.

[0065] ​​Figures 4(B) and (C) show specific examples of circuits applicable to NAND gates 231 to 234. Specific examples of applicable circuits are shown.

[0066] The NAND gate shown in Figure 4(B) has transistors 241 to 244. Note that transistors 241 and 244 are P-type transistors, and transistors 242 and 243 are N-type transistors.

[0067] The gate terminal of transistor 241 is electrically connected to the first input terminal of the NAND gate, and the first terminal is electrically connected to the high power supply potential line.

[0068] The gate terminal of transistor 242 is electrically connected to the first input terminal of the NAND gate and the gate terminal of transistor 241, and the first terminal is electrically connected to the second terminal of transistor 241.

[0069] The gate terminal of transistor 243 is electrically connected to the second input terminal of the NAND gate, the first terminal is electrically connected to the second terminal of transistor 242, and the second terminal is electrically connected to the low power supply potential line.

[0070] The gate terminal of transistor 244 is electrically connected to the second input terminal of the NAND gate and the gate terminal of transistor 243, the first terminal is electrically connected to the high power supply potential line, and the second terminal is electrically connected to the second terminal of transistor 241 and the first terminal of transistor 242.

[0071] Note that in this NAND gate, the potential of the node where the second terminal of transistor 241, the first terminal of transistor 242, and the second terminal of transistor 244 are electrically connected is NAN. ​​​​​​​​​​It is output as the output signal of the D gate.

[0072] The NAND gate shown in FIG. 4(C) includes transistors 251 to 253. Note that transistors 251 to 253 are N-type transistors. In addition, transistors 251 to 253 are enhancement-type transistors with a positive threshold voltage.

[0073] The gate terminal and the first terminal of transistor 251 are electrically connected to the high power supply potential line.

[0074] The gate terminal of transistor 252 is electrically connected to the first input terminal of the NAND gate, and the first terminal is electrically connected to the second terminal of transistor 251.

[0075] The gate terminal of transistor 253 is electrically connected to the second input terminal of the NAND gate, the first terminal is electrically connected to the second terminal of transistor 252, and the second terminal is electrically connected to the low power supply potential line.

[0076] In the NAND gate, the potential of the node where the second terminal of transistor 251 and the first terminal of transistor 252 are electrically connected is output as the output signal of the NAND gate.

[0077] Also, the first input terminal and the second input terminal of the NAND gate are interchangeable. That is, the terminal defined as being electrically connected to the first input terminal of the NAND gate in the above description is electrically connected to the second input terminal of the NAND gate, and the terminal defined as being electrically connected to the second input terminal of the NAND gate is electrically connected to the first input terminal of the NAND gate. It is possible to adopt a configuration in which it is connected to

[0078] The logic circuit of this embodiment is the one that NAND gates 231 to 234 have At least one channel formation region of transistors 242, 243, 252, and 253 is made of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (ato ms / cm 3 ) or less, preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×10 17 (atoms / cm 3 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 [A] or less. That is, -13 the leakage of charge through the transistor during the period when clock gating is performed can be suppressed. As a result, it is possible to reduce the standby power during the period and suppress the malfunction of the logic circuit during the period.

[0079] Furthermore, as the AND gate 201 included in the logic circuit of this embodiment, the AND gate shown in FIG. 3(B) is applied, and as the flip-flop 202, the Delay type flip-flop composed of the NAN D gate shown in FIG. 4(C) is applied. Thus, all of the transistors constituting the logic circuit can be N-type transistors. These N-type transistors are the above-mentioned transistors (transistors whose channel formation regions are made of an oxide semiconductor with a hydrogen concentration of 5×10 (atoms / cm 19 ) or less). 3 ) ​Thus, it is possible to reduce power consumption while being a logic circuit composed only of N-type transistors. In addition, by configuring the logic circuit with only N-type transistors, the manufacturing process can be reduced, improving the yield of the logic circuit and reducing the manufacturing cost can be achieved.

[0080] Further, by reducing the power consumption of the logic circuit, the load on the external circuit operating the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be enhanced in function.

[0081] Note that part or all of the content of the present embodiment can be freely combined with the content of another embodiment or part of the content, or the content of another example or part of the content. It is possible.

[0082] (Embodiment 3) In the present embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically with reference to FIGS. 5 and 6, a logic circuit having a NOR gate and a flip-flop will be described. will be described.

[0083] [Configuration Example of Logic Circuit] The logic circuit 500 of the present embodiment shown in FIG. 5(A) has a NOR gate 501 in which a first input terminal is electrically connected to an enable signal line, and a second input terminal is electrically connected to a wiring ([[]] hereinafter also referred to as an inverted clock signal line) that supplies an inverted clock signal (CKB), and a first input terminal is electrically connected to a data signal line, and a second input terminal is electrically connected to the output terminal of the NOR gate 501, and a flip-flop 502.

[0084] Note that the flip-flop 502 included in the logic circuit of the present embodiment utilizes a feedback operation and is a circuit that can hold data for one bit. Also, the output signal of the flip-flop 502 becomes the output signal of the logic circuit 500.

[0085] <Operation Example of Logic Circuit> The operation of the logic circuit shown in FIG. 5(A) will be described below with reference to the timing chart shown in FIG. 5(B).

[0086] During period T4, the enable signal line functions as a wiring that supplies a low-level signal. Therefore, the output signal (NOR(Out)) of the NOR gate 501 becomes the clock signal (CK). That is, the clock signal (CK) is input to the second input terminal of the flip-flop 502. The flip-flop 502 operates based on the input clock signal (CK). Specifically, the flip-flop 502 captures the data signal (D4 or D5) when the clock signal (CK) changes from low level to high level, and outputs the data signal when the clock signal (CK) changes from high level to low level.

[0087] During period T5, the enable signal line functions as a wiring that supplies a high-level signal. Therefore, the output signal (NOR(Out)) of the NOR gate 501 becomes a low-level signal. That is, a low-level signal is input to the second input terminal of the flip-flop 502. At this time, the output signal (Out) of the logic circuit maintains the data signal (D5).

[0088] During period T6, the enable signal line once again functions as a wiring that supplies a low-level signal. ​​​It functions. That is, similar to period T4, flip-flop 502 captures the data signal (D6 or D7) when the clock signal (C K) changes from a low level to a high level, and outputs the data signal when the clock signal (CK) changes from a high level to a low level. Outputs it.

[0089] In the logic circuit of this embodiment, the clock signal input to flip-flop 50 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on flip-flop 502.

[0090] Note that the logic circuit of this embodiment reads data when the clock signal input to flip-flop 502 is at a high level, and holds the read data during one clock cycle. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T4 or period T6 during which flip-flop 502 is operating.

[0091] <Circuit Configuration Example of NOR Gate and Flip-Flop> A specific circuit configuration example of NOR gate 501 included in the logic circuit shown in FIG. 5(A) is shown in FIGS. 6 (A) and (B). Note that for flip-flop 5 02 included in the logic circuit shown in FIG. 5(A), the Delay type flip-flop shown in FIG. 4(A) can be applied. Therefore, here, for the specific circuit configuration example of flip-flop 502, the above description will be incorporated by reference. Hereinafter, a specific circuit configuration example of NOR gate 501 will be described with reference to FIGS. 6(A) and (B).

[0092] The NOR gate shown in FIG. 6(A) includes transistors 511 to 514. This is the case. Note that transistors 511 and 512 are P-type transistors, and transistors 51 3 and 514 are N-type transistors.

[0093] For transistor 511, the gate terminal is electrically connected to the enable signal line, and the first terminal is electrically connected to a wiring (hereinafter also referred to as the high power supply potential line) that supplies the high power supply potential (VDD). is connected.

[0094] For transistor 512, the gate terminal is electrically connected to the inverted clock signal line, and the first terminal is electrically connected to the second terminal of transistor 511.

[0095] For transistor 513, the gate terminal is electrically connected to the inverted clock signal line and the gate terminal of transistor 512, the first terminal is electrically connected to the second terminal of transistor 512, and the second terminal is electrically connected to the low power supply potential line.

[0096] For transistor 514, the gate terminal is electrically connected to the enable signal line and the gate terminal of transistor 511, the first terminal is electrically connected to the second terminal of transistor 512 and the first terminal of transistor 513, and the second terminal is electrically connected to the low power supply potential line.

[0097] In this NOR gate, the potential of the node to which the second terminal of transistor 512, the first terminal of transistor 513, and the first terminal of transistor 514 are electrically connected is output as the output signal (NOR(Out)) of the NOR gate. The NOR gate shown in FIG. 6(B) has transistors 521 to 523. is output.

[0098] The NOR gate shown in FIG. 6(B) has transistors 521 to 523. Note that transistors 521 to 523 are N-type transistors. In addition, transistors 521 to 523 are enhancement-type transistors with a positive threshold voltage.

[0099] For transistor 521, the gate terminal and the first terminal are electrically connected to the high power supply potential line.

[0100] For transistor 522, the gate terminal is electrically connected to the inversion clock signal line, the first terminal is electrically connected to the second terminal of transistor 521, and the second terminal is electrically connected to the low power supply potential line.

[0101] For transistor 523, the gate terminal is electrically connected to the enable signal line, the first terminal is electrically connected to the second terminal of transistor 521 and the first terminal of transistor 522, and the second terminal is electrically connected to the low power supply potential line.

[0102] Note that in this NOR gate, the potential of the node to which the second terminal of transistor 521, the first terminal of transistor 522, and the first terminal of transistor 523 are electrically connected is output as the output signal (NOR(Out)) of the NOR gate.

[0103] Also, transistor 521 is an enhancement-type transistor whose gate terminal and first terminal are electrically connected to the high power supply potential line. Therefore, transistor 521 maintains an on state regardless of the period. In other words, transistor 521 is used as a resistance element.

[0104] Also, the first input terminal and the second input terminal of the NOR gate are interchangeable. That is, ​​​​​​​​​​​The terminal defined as being electrically connected to the enable signal line in the above description is connected to the inverted clock signal line, and the terminal defined as being electrically connected to the inverted clock signal line is electrically connected to the enable signal line.

[0105] The logic circuit of this embodiment has a transistor whose channel formation region is composed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less, preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 [A] or less. That is, the leakage of charge through the transistor during the period when clock gating is performed can be suppressed. -13 As a result, it is possible to reduce the standby power during that period and suppress the malfunction of the logic circuit during that period.

[0106] Furthermore, as the NOR gate 501 included in the logic circuit of this embodiment, the NOR gate shown in FIG. 6(B) is applied, and as the flip-flop 502, the Delay type flip-flop composed of the NAND gate shown in FIG. 4(C) is applied. Thus, all the transistors constituting the logic circuit can be N-type transistors. These N-type transistors are the above transistors (the channel formation region has a hydrogen concentration of 5×10 (atoms / cm 19 (atoms / cm 3)Let it be a transistor composed of the following oxide semiconductor) As a result, it is a logic circuit composed only of N-type transistors, but can reduce power consumption Moreover, by configuring the logic circuit with only N-type transistors, the manufacturing process can be reduced, the yield of the logic circuit can be improved, and the manufacturing cost can be reduced .

[0107] In addition, by reducing the power consumption of the logic circuit, the load on the external circuit that operates the logic circuit of this embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be functionally expanded

[0108] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content, or the content of other examples or a part of the content .

[0109] (Embodiment 4) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically , a logic circuit having a latch and a flip-flop will be described with reference to FIGS. 7 and 8 .

[0110] (Configuration example of logic circuit) The logic circuit 600 of this embodiment shown in FIG. 7(A) has a latch 601 whose first input terminal is electrically connected to the enable signal line and whose second input terminal is electrically connected to the inverted clock signal line, and a flip-flop 602 whose first input terminal is electrically connected to the data signal line and whose second input terminal is electrically connected to the output terminal of the latch 601 .

[0111] Note that the flip-flop 602 included in the logic circuit of the present embodiment utilizes a feedback operation and is a circuit that can hold data for one bit. Also, the output signal of the flip-flop 602 becomes the output signal of the logic circuit 600.

[0112] Also, the latch 601 of the present embodiment may have any configuration as long as it can latch data. Here, when a high-level signal is supplied to the first input terminal, a circuit that latches and outputs the inverted signal of the signal input to the second input terminal is applied to the latch 601.

[0113] <Operation Example of Logic Circuit> The operation of the logic circuit shown in FIG. 7(A) will be described below with reference to the timing chart shown in FIG. 7(B).

[0114] During period T7, the enable signal line functions as a wiring that supplies a high-level signal. At this time, the output signal (Latch(Out)) of the latch 601 becomes the clock signal (C K). That is, the clock signal (C K) is input to the second input terminal of the flip-flop 602. The flip-flop 602 operates based on the input clock signal (CK). Specifically, the flip-flop 602 captures the data signal (D8 or D9) when the clock signal (CK) changes from a low level to a high level, and outputs the data signal when the clock signal ( CK) changes from a high level to a low level.

[0115] During period T8, the enable signal line functions as a wiring that supplies a low-level signal. At this time, the output signal (Latch(Out)) of the latch 601 holds a low level. ​​​​​​That is, a low-level signal is input to the second input terminal of the flip-flop 602. At this time, the output signal (Out) of the logic circuit maintains the data signal (D9).

[0116] During the period T9, the enable signal line functions again as a wiring that supplies a high-level signal. That is, similar to the period T7, when the clock signal (CK) changes from low level to high level, the flip-flop 602 captures the data signal (D10 or D11), and outputs the data signal when the clock signal (CK) changes from high level to low level.

[0117] In the logic circuit of the present embodiment, the clock signal (CK) input to the flip-flop 602 is controlled by the enable signal (EN). That is, it is a logic circuit that performs clock gating on the flip-flop 602.

[0118] Note that the logic circuit of the present embodiment reads data when the clock signal input to the flip-flop 602 is high level, and holds the read data during one clock cycle. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the period T7 or the period T9 during which the flip-flop 602 operates has elapsed.

[0119] <Latch and Flip-Flop Circuit Configuration Example> Specific circuit configuration examples of the latch 601 included in the logic circuit shown in FIG. 7(A) are shown in FIGS. 8(A) to (C). Note that the flip-flop 602 included in the logic circuit shown in FIG. 7(A) can apply the Delay type flip-flop shown in FIG. 4(A). Therefore, here, for the specific circuit configuration example of the flip-flop 602, the description mentioned above will be incorporated by reference. The following will describe the specific circuit configuration example of the latch 601 with reference to FIGS. 8( A) to (C).

[0120] The latch shown in FIG. 8(A) has a transistor 611, an inverter 612, and an inverter 613. Note that the transistor 611 is an N-type transistor.

[0121] The gate terminal of the transistor 611 is electrically connected to the enable signal line, and the first terminal is electrically connected to the inverted clock signal line.

[0122] The input terminal of the inverter 612 is electrically connected to the second terminal of the transistor 611 .

[0123] The input terminal of the inverter 613 is electrically connected to the output terminal of the inverter 612, and the output terminal is electrically connected to the second terminal of the transistor 611 and the input terminal of the inverter 612 .

[0124] In this latch, the output signal of the inverter 612 is output as the output signal of the latch (Latch (Out)).

[0125] FIGS. 8(B) and (C) show specific examples of circuits applicable to the inverter 612 and the inverter 613. The inverter shown in FIG. 8(B) has a transistor 621 and a transistor 622

[0126] . Note that the transistor 621 is a P-type transistor, and the transistor 622 is an N-type transistor. transistor.

[0127] The transistor 621 has its gate terminal electrically connected to the input terminal of the inverter, and its first terminal is electrically connected to the high power supply potential line.

[0128] The transistor 622 has its gate terminal electrically connected to the input terminal of the inverter and the gate terminal of the transistor 621, its first terminal is electrically connected to the second terminal of the transistor 621, and its second terminal is electrically connected to the low power supply potential line.

[0129] In this inverter, the potential of the node to which the second terminal of the transistor 621 and the first terminal of the transistor 622 are electrically connected is output as the output signal.

[0130] The inverter shown in FIG. 8(C) includes transistors 631 and 632. Note that the transistors 631 and 632 are N-type transistors. Additionally, the transistors 631 and 632 are enhancement-mode transistors with a positive threshold voltage.

[0131] For the transistor 631, its gate terminal and first terminal are electrically connected to the high power supply potential line.

[0132] For the transistor 632, its gate terminal is electrically connected to the input terminal of the inverter, its first terminal is electrically connected to the second terminal of the transistor 631, and its second terminal is electrically connected to the low power supply potential line.

[0133] In this inverter, the potential of the node to which the second terminal of the transistor 631 and the first terminal of the transistor 632 are electrically connected is output as the output signal.

[0134] In the above description, the case where the transistor 611 is an N-type transistor has been described. However, the transistor 611 can also be a P-type transistor. In this case, by inverting the enable signal, it is possible to perform the same operation as the above-described operation. The logic circuit of this embodiment includes a transistor whose channel formation region is formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is controlled to be 5×10 (atoms / cm

[0135] or less, preferably 5×10 (atoms / cm 19 ) or less, and more preferably 5×1 3 0 18 (atoms / cm 3 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 [A] or less. That is, it is possible to suppress the leakage of charges through the transistor during the period when clock gating is performed. As a result, it is possible to reduce the standby power during that period and suppress the malfunction of the logic circuit during that period. 17 (atoms / cm 3 ) or less. As a result, it is possible to suppress the leakage of charges through the transistor during the period when clock gating is performed. As a result, it is possible to reduce the standby power during that period and suppress the malfunction of the logic circuit during that period. Furthermore, as the latch 601 included in the logic circuit of this embodiment, a latch constituted by the inverter shown in FIG. 8(C) is applied, and as the flip-flop 602, a Delay-type flip-flop constituted by the NAND gate shown in FIG. 4(C ) is applied. By doing so, all of the transistors constituting the logic circuit can be N-type transistors. These N-type transistors are the above-described transistors (the channel formation region has a hydrogen concentration of 5×10 ) or less, and more preferably 5×1 0 -13 (atoms / cm

[0136] ). Furthermore, as the latch 601 included in the logic circuit of this embodiment, a latch constituted by the inverter shown in FIG. 8(C) is applied, and as the flip-flop 602, a Delay-type flip-flop constituted by the NAND gate shown in FIG. 4(C ) is applied. By doing so, all of the transistors constituting the logic circuit can be N-type transistors. These N-type transistors are the above-described transistors (the channel formation region has a hydrogen concentration of 5×10 (atoms / cm ) or less, and more preferably 5×1 0 19 (atoms / cm 3)A transistor composed of the following oxide semiconductor ) is a logic circuit composed only of N-type transistors, but can reduce power consumption. In addition, by configuring the logic circuit with only N-type transistors , the manufacturing process can be reduced, the yield of the logic circuit can be improved, and the manufacturing cost can be reduced.

[0137] Also, by reducing the power consumption of the logic circuit, the load on the external circuit that operates the logic circuit of this embodiment can be reduced. As a result, the semiconductor having the logic circuit and the external circuit device can be functionally expanded.

[0138] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content or the content of other examples or a part of the content.

[0139] (Embodiment 5) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically with reference to FIG. 9, a logic circuit having an AND gate and a plurality of flip-flops will be described.

[0140] The logic circuit 800 of this embodiment shown in FIG. 9 has an AND gate 801 and a flip-flop group 805 including flip-flops 802 to 804.

[0141] The AND gate 801 has its first input terminal electrically connected to an enable signal line and its second input terminal electrically connected to a clock signal line.

[0142] The flip-flop 802 has its first input terminal electrically connected to the data signal line and its second input terminal electrically connected to the output terminal of the AND gate 801.

[0143] The flip-flop 803 has its first input terminal electrically connected to the output terminal of the flip-flop 802 and its second input terminal electrically connected to the output terminal of the AND gate 801. .

[0144] The flip-flop 804 has its first input terminal electrically connected to the output terminal of the flip-flop 803 and its second input terminal electrically connected to the output terminal of the AND gate 801. .

[0145] Note that the output signal of the flip-flop 804 becomes the output signal (Out) of the logic circuit 800. .

[0146] Also, the flip-flops 802 to 804 included in the logic circuit of this embodiment are circuits that can hold data for one bit by utilizing the feedback effect. For example, the Dela y-type flip-flop shown in FIG. 4 can be applied.

[0147] In the logic circuit of this embodiment, the clock signal input to the flip-flop group 8 05 is controlled by the enable signal (EN). That is, it is a logic circuit that performs clock gating on the flip-flop group 805.

[0148] Also, for the flip-flops after the second stage included in the flip-flop group 805, the first input terminal is electrically connected to the output terminal of the previous-stage flip-flop. That is, in the logic circuit of this embodiment, during the period when the clock signal is input, the data signal (Data ) is a shift register that sequentially shifts flip - flops.

[0149] The logic circuit of this embodiment has a transistor whose channel - forming region is composed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is controlled to be 5×10 19 (atoms / cm 3 ) or less, preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 ) or less. Therefore, the off - current of the transistor can be reduced to 1×10 [A] or less. That is, it is possible to suppress the leakage of charge through the transistor during the period when clock gating is performed. -13 As a result, it is possible to reduce the standby power during that period and suppress the malfunction of the logic circuit during that period.

[0150] Furthermore, all of the transistors constituting the AND gate 801 and the flip - flop group 805 of the logic circuit of this embodiment can be N - type transistors. By making these N - type transistors the above - mentioned transistors (transistors whose channel - forming region is composed of an oxide semiconductor with a hydrogen concentration of 5×10 1 9 (atoms / cm (atoms / cm 3 ) or less), it is possible to achieve low power consumption while being a logic circuit composed only of N - type transistors. Also, by configuring the logic circuit only with N - type transistors, the manufacturing process can be reduced, the yield of the logic circuit can be improved, and the manufacturing cost can be reduced. ​

[0151] Also, by reducing the power consumption of the logic circuit, the load on the external circuit other than the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be functionally expanded. In the present embodiment, a logic circuit having three flip-flops is shown, but the number of flip-flops included in the logic circuit of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit having the first flip-flop to the nth (n is a natural number) flip-flops. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the logic circuit has its first input terminal electrically connected to the output terminal of the (k-1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 801.

[0152] In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage. However, the configuration of the logic circuit of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input from outside the logic circuit 800 to the flip-flop may be used. Also, the first input terminal of the flip-flop may be electrically connected to the output terminal of a flip-flop other than the previous stage, such as a flip-flop two stages before. Furthermore, the first input terminal of a certain flip-flop may not be directly connected to the output terminal of another flip-flop, but may be connected via another circuit in between.

[0153]

[0154] ​​​​​​​​​​​​​​In addition, the circuit configurations of the plurality of flip-flops included in the logic circuit of the present embodiment do not have to be common, and the circuit configuration may be changed for each flip-flop according to the application or the like.

[0155] Note that the content of the present embodiment or a part of the content can be freely combined with the content of another embodiment or a part of the content, or the content of another example or a part of the content.

[0156] (Embodiment 6) In the present embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically, with reference to FIG. 10, a logic circuit having an AND gate and a plurality of flip-flops will be described.

[0157] The logic circuit 900 of the present embodiment shown in FIG. 10 includes a control unit 903 including a flip-flop 901 and an AND gate 902, and a flip-flop group 907 having flip-flops 904 to 906.

[0158] The flip-flop 901 is electrically connected to a wiring (hereinafter also referred to as a first data signal line) that supplies a first data signal (Data1) to a first input terminal, and a second input terminal is electrically connected to a clock signal line.

[0159] The AND gate 902 has a first input terminal electrically connected to an output terminal of the flip-flop 901, and a second input terminal electrically connected to an enable signal line.

[0160] The flip-flop 904 is electrically connected to a wiring (hereinafter also referred to as a second data signal line) that supplies a second data signal (Data2) to a first input terminal, and a second input terminal is electrically connected to... ​​​​​​​​It is electrically connected to the output terminal of the AND gate 902.

[0161] The flip-flop 905 has its first input terminal electrically connected to the output terminal of the flip-flop 904 and its second input terminal electrically connected to the output terminal of the AND gate 902. .

[0162] The flip-flop 906 has its first input terminal electrically connected to the output terminal of the flip-flop 905 and its second input terminal electrically connected to the output terminal of the AND gate 902. .

[0163] Note that the output signal of the flip-flop 906 becomes the output signal (Out) of the logic circuit 900. .

[0164] Also, the flip-flops 901, 904 to 906 included in the logic circuit of this embodiment are circuits that can hold one-bit data by utilizing the feedback effect. For example, the Delay type flip-flop shown in FIG. 4 can be applied.

[0165] The logic circuit of this embodiment is controlled by the output signal of the flip-flop 901 controlled by the first data signal (Data1) and the clock signal, and the clock signal input to the flip-flop group 907 is controlled by the enable signal (EN). That is, it is a logic circuit that performs clock gating on the flip-flop group 907.

[0166] Also, the flip-flops from the second stage and later included in the flip-flop group 907 have their first input terminals electrically connected to the output terminals of the previous-stage flip-flops. That is, during the period when the clock signal is input, the logic circuit of this embodiment performs operations related to the second data signal (D The shift register that sequentially shifts ata2) is a flip-flop.

[0167] The logic circuit of this embodiment includes a transistor whose channel formation region is formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is controlled to be 5×10 19 (atoms / cm 3 ) or less, preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×1 0 17 (atoms / cm 3 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 [A] or less. That is, it is possible to suppress the leakage of charges through the transistor during the clock gating period. -13 As a result, it is possible to reduce the standby power during the period and suppress the malfunction of the logic circuit during the period. Furthermore, all of the transistors constituting the control unit 903 and the flip-flop group 907 included in the logic circuit of this embodiment can be N-type transistors. By using these N-type transistors as the above-mentioned transistors (transistors whose channel formation region is formed of an oxide semiconductor with a hydrogen concentration of 5×10 19 (a

[0168] toms / cm 3 ) or less), it is possible to achieve low power consumption while being a logic circuit composed only of N-type transistors. Also, by configuring the logic circuit only with N-type transistors, the manufacturing process can be simplified, (a toms / cm 3 ) or less), it is possible to improve the yield of the logic circuit and reduce the manufacturing cost. The yield of the logic circuit can be improved and the manufacturing cost can be reduced. The power consumption can be reduced while being a logic circuit composed only of N-type transistors. By configuring the logic circuit only with N-type transistors, the manufacturing process can be simplified. The yield of the logic circuit can be improved and the manufacturing cost can be reduced.

[0169] Also, by reducing the power consumption of the logic circuit, the load on the external circuit other than the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be enhanced in function. Also, by reducing the power consumption of the logic circuit, the load on the external circuit other than the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be enhanced in function. Also, by reducing the power consumption of the logic circuit, the load on the external circuit other than the logic circuit of the present embodiment can be reduced. As a result, the semiconductor device having the logic circuit and the external circuit can be enhanced in function.

[0170] In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902. In the present embodiment, a flip-flop group 907 having three flip-flops is shown. However, the number of flip-flops included in the flip-flop group 907 of the present embodiment is not limited to three. That is, the logic circuit of the present embodiment includes a logic circuit in which the flip-flop group has flip-flops from the first flip-flop to the nth (n is a natural number) flip-flop. Note that the kth (k is a natural number less than or equal to n) flip-flop included in the flip-flop group has its first input terminal electrically connected to the output terminal of the (k - 1)th flip-flop and its second input terminal electrically connected to the output terminal of the AND gate 902.

[0171] In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. Also, a configuration in which the first input terminal of the flip-flop is electrically connected to the output terminal of the flip-flop two stages before, that is, a configuration in which the first input terminal of the flip-flop is electrically connected to the output terminal of a flip-flop other than the previous stage may be used. Further, a configuration in which the first input terminal of a certain flip-flop is electrically connected to the output terminal of another flip-flop In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. In the present embodiment, a configuration is shown in which the output signal of the previous flip-flop is input to the first input terminal of the flip-flops after the second stage of the flip-flop group 907. However, the configuration of the flip-flop group of the present embodiment is not limited to this configuration. For example, a configuration in which a signal is input to the flip-flop from outside the logic circuit 900 may be used. It may not be directly connected to the output terminal of P, and other circuits may be provided therebetween.

[0172] In addition, the circuit configurations of the plurality of flip-flops included in the logic circuit of the present embodiment do not have to be common, and the circuit configuration may be changed for each flip-flop according to the application or the like.

[0173] Note that the content of the present embodiment or a part of the content can be freely combined with the content of another embodiment or a part of the content, or the content of another example or a part of the content.

[0174] (Embodiment 7) In the present embodiment, an example of a transistor included in the logic circuit shown in Embodiments 1 to 6 will be described. Specifically, as a P-type transistor included in the logic circuit, a transistor formed using a substrate containing a semiconductor material is applied, and as an N-type transistor, an example in which a transistor formed using an oxide semiconductor is applied is shown.

[0175] <Configuration Example> The P-type transistor and N-type transistor included in the logic circuit of the present embodiment are shown in FIG. 11.

[0176] The P-type transistor 160 shown in FIG. 11 includes a channel formation region 116 provided in a substrate 100 containing a semiconductor material, a pair of impurity regions 114a and 114b provided so as to sandwich the channel formation region 116, and a pair of high-concentration impurity regions 120a and 120b (collectively referred to simply as impurity regions), a gate insulating layer 108a provided on the channel formation region 116, a gate electrode layer 110a provided on the gate insulating layer 108a, and an impurity region ​A source electrode layer 130a electrically connected to 114a and a drain electrode layer 130b electrically connected to the impurity region 114b are provided. It has.

[0177] A sidewall insulating layer 118 is provided on the side surface of the gate electrode layer 110a. In addition, in a region of the substrate 100 containing a semiconductor material that does not overlap with the sidewall insulating layer 118, There are a pair of high-concentration impurity regions 120a and 120b, and a pair of metal compound regions 124a and 124b exist on the pair of high-concentration impurity regions 120 a, 120b. Also, an element isolation insulating layer 106 is provided on the substrate 1 00 so as to surround the transistor 160, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160. Yes. The source electrode layer 130a and the drain electrode layer 130b are electrically connected to one of the pair of metal compound regions 124a and 124b through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode layer 130a is electrically connected to the high-concentration impurity region 120a and the impurity region 114a via the metal compound region 124 a, and the drain electrode layer 130b is electrically connected to the high-concentration impurity region 120b and the impurity region 114b via the metal compound region 124b. b. a and the impurity region 114a, and the drain The electrode layer 130b is electrically connected to the high-concentration impurity region 120b and the impurity region 114b via the metal compound region 124b. Yes.

[0178] Also, below the N-type transistor 164 described later, an insulating layer 108b made of the same material as the gate insulating layer 108a, an electrode layer 110b made of the same material as the gate electrode layer 110a, and An electrode layer 130c made of the same material as the source electrode layer 130a and the drain electrode layer 130b is provided. c is provided. It is.

[0179] The N-type transistor 164 shown in FIG. 11 includes a gate electrode provided on the interlayer insulating layer 128 layer 136d, a gate insulating layer 138 provided on the gate electrode layer 136d, and a gate insulating oxide semiconductor layer 140 provided on the layer 138, and a source electrode layer 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a drain electrode layer 142b.

[0180] Here, the gate electrode layer 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Also, similar to the gate electrode layer 136d, an electrode layer 136a in contact with the source electrode layer 130a and an electrode layer 1 in contact with the drain electrode layer 130b, which the P-type transistor 160 has, are formed. Also, an electrode layer 136c in contact with the electrode layer 130c is formed. 30b is formed. Also, an electrode layer 136c in contact with the electrode layer 130c is formed.

[0181] Also, a protective insulating layer 144 is provided on the transistor 164 so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144 Here, openings reaching the source electrode layer 142a and the drain electrode layer 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, an electrode layer 150d in contact with the source electrode layer 142a and an electrode layer 1 50e in contact with the drain electrode layer 142b are formed. Also, similar to the electrode layer 150d and the electrode layer 150e, through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, an electrode layer 150a in contact with the electrode layer 13 6a, an electrode layer 150b in contact with the electrode layer 136b, and an electrode layer 1 50c in contact with the electrode layer 136c are formed. 6c are formed. 6a, an electrode layer 150b in contact with the electrode layer 136b, and an electrode layer 1 6c are formed.

[0182] Here, the oxide semiconductor layer 140 has been sufficiently purified by removing impurities such as hydrogen, and is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 (atoms / cm 3 ) or less. Note that the hydrogen concentration in the oxide semiconductor layer 140 is preferably 5×10 18 (atoms / cm 3 ) or less, and more preferably 5×10 17 (atoms / cm 3 ) or less. By using the oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration and high purity, a transistor 164 with extremely excellent off-current characteristics can be obtained. For example, when the drain voltage Vd is +1V or +10V and the gate voltage Vg ranges from - 5V to -20V, the off-current is 1×10 [A] or less. In this way, -13 by applying the oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration and high purity, the off-current of the transistor 164 can be reduced. Note that the hydrogen concentration in the above-mentioned oxide semiconductor layer 1 40 is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy).

[0183] Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and electrode layers 154a, 154b, 154c, and 154d are provided so as to be embedded in the insulating layer 152. Note that the electrode layer 154a is in contact with the electrode layer 150a, and the electrode layer 154b is in contact with the electrode layer 150b. The electrode layer 154c is in contact with the electrode layers 150c and 150d, and the electrode layer 154d is in contact with the electrode layer 150e.

[0184] The source electrode layer 130a of the P-type transistor 160 shown in this embodiment is electrically connected to the electrode layer 136a, the electrode layer 150a, and the electrode layer 154a provided in the upper layer region. Therefore, the source electrode layer 130a of the P-type transistor 160 can be electrically connected to any of the electrode layers of the N-type transistor 164 provided in the upper layer region by appropriately forming these conductive layers. Similarly, the drain electrode layer 130b of the P-type transistor can also be electrically connected to any of the electrode layers of the N-type transistor 164 provided in the upper layer region. Although not shown in FIG. 11, the gate electrode layer 110a of the P-type transistor 160 can also be electrically connected to any of the electrode layers of the N-type transistor 164 through the electrode layer provided in the upper layer region.

[0185] Similarly, the source electrode layer 142a of the N-type transistor 164 shown in this embodiment is electrically connected to the electrode layer 130c and the electrode layer 110b provided in the lower layer region. Therefore, the source electrode layer 142a of the N-type transistor 164 can be electrically connected to the gate electrode layer 110a, the source electrode layer 130a, or the drain electrode layer 130b of the P-type transistor 160 provided in the lower layer region by appropriately forming these conductive layers. Although not shown in FIG. 11, the gate electrode layer 136d or the drain electrode layer 142b of the N-type transistor 164 can also be electrically connected to any of the electrode layers of the P-type transistor 160 through the electrode layer provided in the lower layer region. ​​​​​​​​​​​​​

[0186] A plurality of the above-described P-type transistors 160 and N-type transistors 164 are provided respectively, and by doing so, the logic circuits shown in Embodiments 1 to 6 can be configured. Note that, not all of the N-type transistors 164 included in the logic circuit need to be transistors formed using an oxide semiconductor, and they can be appropriately changed according to the characteristics required for each transistor. For example, as the N-type transistor for which high-speed operation is required, a transistor formed using a substrate including a semiconductor material is applied, and as the N-type transistor for which reduction of leakage current is required, a transistor formed using an oxide semiconductor is applied. This is possible.

[0187] <Example of manufacturing process> Next, an example of a method for manufacturing the P-type transistor 160 and the N-type transistor 164 will be described. Hereinafter, first, the method for manufacturing the P-type transistor 160 will be described with reference to FIG. 12, and then, the method for manufacturing the N-type transistor 164 will be described with reference to FIGS. 13 and 14.

[0188] First, a substrate 100 including a semiconductor material is prepared (see FIG. 12(A)). As the substrate 100 including a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied. Here, an example in the case of using a single crystal silicon substrate as the substrate 100 including a semiconductor material will be shown. Note that, generally, an "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface, but in this specification and the like, a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface is referred to as an SOI substrate. ​​​​​​​​​​It is used as a concept including a substrate configured with a semiconductor layer made of a material other than silicon. Next, the semiconductor layer included in the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the SOI substrate includes a configuration in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. It shall also be included.

[0189] On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see Fig. 12(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. Note that before and after this process, in order to control the threshold voltage of the semiconductor device, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, examples of the impurity imparting n-type conductivity include phosphorus and arsenic, etc. which can be used. Also, examples of the impurity imparting p-type conductivity include boron, aluminum, gallium, etc. which can be used.

[0190] Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). Thereby, a separated semiconductor region 104 is formed (see Fig. 12(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected according to the material to be etched.

[0191] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region By selectively removing the insulating layer of the region, the element isolation insulating layer 106 is formed (Fig. 12(B) reference). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As a method for removing the insulating layer, there are polishing processes such as CMP (Chemical Mechanica l Polishing) and etching processes, and any of them can be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0192] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer.

[0193] The insulating layer will become the gate insulating layer later, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide nium, tantalum oxide, etc., obtained by using the CVD method, sputtering method, etc. Alternatively, the surface of the semiconductor region 104 can be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above insulating layer. The high-density plasma treatment can be performed using, for example, a mixed gas of rare gases such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer is not particularly limited, but can be, for example, 1 nm or more and 100 nm or less.

[0194] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Alternatively, a layer containing a conductive material can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The formation method is not particularly limited, and methods such as vapor deposition, Various film formation methods such as CVD method, sputtering method, spin coating method, etc. can be used. . In this embodiment, an example of forming a layer containing a conductive material using a metal material will be shown.

[0195] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 10 8a and the gate electrode layer 110a (see Fig. 12(C)).

[0196] Next, an insulating layer 112 covering the gate electrode layer 110a is formed (see Fig. 12(C)). Then boron (B), aluminum (Al), etc. are added to the semiconductor region 104 to form a pair of impurity regions 114a, 114b with a shallow junction depth (see Fig. 12(C)). Here boron or aluminum is added to form a p-type transistor, but when forming an n-type transistor impurity elements such as phosphorus (P) and arsenic (As) may be added. Note that by forming the pair of impurity regions 114a, 114b, a channel formation region 116 is formed under the gate insulating layer 108a of the semiconductor region 104 (see Fig. 12(C) reference). Here, the concentration of the impurity to be added can be set as appropriate, but when the semiconductor device is highly miniaturized, it is desirable to increase the concentration. Also, here, the step of forming the pair of impurity regions 114a, 114b after forming the insulating layer 112 is adopted . However, the step of forming the insulating layer 112 after forming the pair of impurity regions 114a, 114b may also be used.

[0197] Next, a sidewall insulating layer 118 is formed (see Fig. 12(D)). The sidewall insulating layer 118 is formed by forming an insulating layer so as to cover the insulating layer 112, and then anisotropy is applied to the insulating layer. By applying a high etching process, it can be self-alignedly formed. Also, at this time, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode layer 110a and the upper surfaces of the pair of impurity regions 114a, 114b.

[0198] Next, an insulating layer is formed so as to cover the gate electrode layer 110a, the pair of impurity regions 114a, 114b, the sidewall insulating layer 118, etc. Then, boron (B), aluminum (Al), etc. are added to a part of the pair of impurity regions 114a, 114b to form a pair of high-concentration impurity regions 120a, 120b (see Fig. 12(E)). Here too, when forming an N-type transistor, impurity elements such as phosphorus (P) and arsenic (As) may be added. Then, the above insulating layer is removed, and a metal layer 122 is formed so as to cover the gate electrode layer 110a, the sidewall insulating layer 11 8, the pair of high-concentration impurity regions 120a, 120b, etc. (see Fig. 12(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 10 to form a low-resistance metal compound. Examples of such metal materials include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc. Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a pair of metal compound regions 124a, 124 b in contact with the pair of high-concentration impurity regions 120a, 120b are formed (see Fig. 12(F)). Note that polycrystalline silicon is used as the gate electrode layer 110a.

[0199] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a pair of metal compound regions 124a, 124 b in contact with the pair of high-concentration impurity regions 120a, 120b are formed (see Fig. 12(F)). Note that polycrystalline silicon is used as the gate electrode layer 110a. b are formed (see Fig. 12(F)). Note that polycrystalline silicon is used as the gate electrode layer 110a. ​​When using, for example, gold or the like, a metal compound region is also formed at the portion in contact with the metal layer 122 of the gate electrode layer 110a. A metal compound region will be formed.

[0200] As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method capable of realizing heat treatment for a very short time. Incidentally, the above metal compound region is formed by the reaction between the metal material and the semiconductor material, and is a region with sufficiently enhanced conductivity. By forming the metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. After forming the pair of metal compound regions 124a and 124b, the metal layer 122 is removed. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method capable of realizing heat treatment for a very short time. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method capable of realizing heat treatment for a very short time. Incidentally, the above metal compound region is formed by the reaction between the metal material and the semiconductor material, and is a region with sufficiently enhanced conductivity. By forming the metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. Incidentally, by forming the metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. After forming the pair of metal compound regions 124a and 124b, the metal layer 122 is removed.

[0201] Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each configuration formed by the above-described process (see FIG. 12(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form using an organic insulating material such as polyimide or acrylic. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is used, but the configuration of the interlayer insulating layer is not limited to this. After forming the interlayer insulating layer 128, it is desirable to planarize its surface by CMP or etching treatment or the like. Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each configuration formed by the above-described process (see FIG. 12(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form using an organic insulating material such as polyimide or acrylic. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is used, but the configuration of the interlayer insulating layer is not limited to this. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is used, but the configuration of the interlayer insulating layer is not limited to this. After forming the interlayer insulating layer 128, it is desirable to planarize its surface by CMP or etching treatment or the like.

[0202] Thereafter, openings reaching the pair of metal compound regions 124a and 124b are formed in the above interlayer insulating layer. Form a mouth, and form a source electrode layer 130a and a drain electrode layer 130b in the opening.( Refer to Fig. 12(H). The source electrode layer 130a and the drain electrode layer 130b are formed, for example, by forming a conductive layer in a region including the opening using a PVD method, a CVD method, etc., and then removing a part of the conductive layer using a method such as etching or CMP.( It can be formed by removing a part of the conductive layer using a method such as etching or CMP.(

[0203] When forming the source electrode layer 130a and the drain electrode layer 130b, it is desirable to process their surfaces to be flat. For example, when forming a tungsten film so as to embed it in the opening after thinly forming a titanium film or a titanium nitride film in a region including the opening , unnecessary tungsten, titanium, titanium nitride, etc. can be removed by subsequent CMP , and at the same time, the flatness of their surfaces can be improved. Thus, by planarizing the surfaces including the source electrode layer 130a and the drain electrode layer 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Here, only the source electrode layer 130a and the drain electrode layer 130b that are in contact with the pair of metal compound regions 124a and 124b are shown, but in this step, an electrode layer that functions as a wiring (for example, the electrode layer 130c in Fig. 11) can be formed together.

[0204] There is no particular limitation on the materials that can be used as the source electrode layer 130a and the drain electrode layer 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium can be used. There is no particular limitation on the materials that can be used as the source electrode layer 130a and the drain electrode layer 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium , etc. can be used. etc. can be used.

[0205] As described above, a P-type transistor 160 using a substrate 100 containing a semiconductor material is formed. After the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure formed by laminating an interlayer insulating layer and a conductive layer as the wiring structure, a highly integrated logic circuit can be provided. Also, an N-type transistor using a substrate 100 containing a semiconductor material can be formed by the same process as the above process. That is, in the above-described process, by changing the impurity element added to the semiconductor region to an impurity element such as phosphorus (P) or arsenic (As), an N-type transistor can be formed.

[0206] Next, a process of fabricating an N-type transistor 164 on an interlayer insulating layer 128 will be described with reference to FIGS. 13 and 14. FIGS. 13 and 14 show the fabrication processes of various electrode layers on the interlayer insulating layer 128 and the N-type transistor 164, etc., and thus the P-type transistor 160 etc. existing below the N-type transistor 164 are omitted. Note that FIGS. 13 and 14 show the fabrication processes of various electrode layers on the interlayer insulating layer 128 and the N-type transistor 164, etc., and thus the P-type transistor 160 etc. existing below the N-type transistor 164 are omitted.

[0207] First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source electrode layer 130a, the drain electrode layer 130b, and the electrode layer 1 30c (see FIG. 13(A)). The insulating layer 132 can be formed using a PVD method, a C VD method, etc. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0208] Next, with respect to the insulating layer 132, the source electrode layer 130a, the drain electrode layer 130b, and An opening is formed that reaches the electrode layer 130c. At this time, the gate electrode layer 136d is to be formed later. An opening is also formed in the area where the conductive layer 13 is to be formed. 4 is formed (see FIG. 13(B)). The opening is formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. The etching method can be either wet etching or dry etching. Either method may be used, but from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 134 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 134 include molybdenum, titanium, chromium, and tantalum. Conductive materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium Examples of such materials include conductive materials, alloys thereof, and compounds (for example, nitrides).

[0209] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and C After forming a thin titanium nitride film by the VD method, a tungsten film is deposited to fill the opening. The titanium film formed by the PVD method is The oxide film at the interface is reduced, and the lower electrode layer (here, the source electrode layer 130a and the drain electrode layer The contact resistance between the insulating layer 130 and the electrode layer 130b, the electrode layer 130c, etc. is reduced. The titanium nitride film formed in the above has a barrier function to suppress the diffusion of conductive materials. After forming a barrier film using titanium or titanium nitride, a copper film is formed by plating. Good too.

[0210] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. Remove a part of 134 to expose the insulating layer 132, and form the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode layer 136d (see Fig. 13(C)). Note that the above-mentioned conductive layer 134 is removed in part to form the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate When forming the electrode layer 136d, it is desirable to process it so that the surface becomes flat. In this way, by planarizing the surfaces of the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode layer 136d, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0211] Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode layer 136d (see Fig. 13(D)). The gate insulating layer 138 can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 138 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the gate insulating layer 138 may have a single-layer structure or a laminated structure. For example, as the raw material gas, a plasma CVD method using silane (SiH ), oxygen, and nitrogen can be used to form a gate insulating layer 138 made of silicon oxynitride. The thickness of the gate insulating layer 138 4 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less. In the case of a laminated structure, for example, it is suitable to form a laminate of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. ​

[0212] Note that an oxide semiconductor that has been i - type or substantially i - type converted by removing impurities ( high - purity oxide semiconductor) is extremely sensitive to interface levels and interface charges. Therefore, when such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the high - purity oxide semiconductor layer is required to have high quality.

[0213] For example, the high - density plasma CVD method using microwaves (2.45 GHz) is suitable in that it can form a high - quality gate insulating layer 138 that is dense and has high breakdown voltage. By closely contacting the high - purity oxide semiconductor layer and the high - quality gate insulating layer, the interface levels can be reduced and the interface characteristics can be made good. This is because

[0214] Of course, as long as a high - quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering or plasma CVD can be applied even when using a high - purity oxide semiconductor layer. Also, an insulating layer whose film quality and interface characteristics are modified by heat treatment after formation may be applied. In any case, the film quality as the gate insulating layer 138 is good, and it is only necessary to form one that can reduce the interface level density with the oxide semiconductor layer and form a good interface.

[0215] Furthermore, in a gate bias - thermal stress test (BT test) at 85 °C, 2×10 6 (V / cm), for 12 hours, when impurities are added to the oxide semiconductor, the bonds between the impurities and the main components of the oxide semiconductor are broken by a strong electric field (B: bias) and high temperature (T: temperature). ​​​​​​​This will induce the drift of the generated dangling bonds to the threshold voltage (Vth).

[0216] On the other hand, impurities in the oxide semiconductor, especially hydrogen and water, are excluded as much as possible, and as described above By improving the interface characteristics with the gate insulating layer, a stable transistor can also be obtained for the BT test is possible.

[0217] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and the oxide semiconductor layer is processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see FIG. 13(E)).

[0218] As the oxide semiconductor layer, an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In- Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Z n-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn -O-based, Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer, is preferably used In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using an In-Ga-Zn-O-based metal oxide target as the oxide semiconductor layer. Note that By adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, an acid using a target containing 2 wt% or more and 10 wt% or less of SiO The oxide semiconductor layer may be formed. 2

[0219] As a target for producing the oxide semiconductor layer by sputtering, for example, a target of a metal oxide mainly composed of zinc oxide can be used. Also, In, ​​​​A metal oxide target containing Ga and Zn (as a composition ratio, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [atom]) can also be used. Also, as a metal oxide target containing In, Ga, and Zn it is also possible to use a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom] or In:Ga:Zn = 1:1: 2 [atom]. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using a metal oxide target with a high filling rate, a dense oxide semiconductor layer can be formed formed. The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to about several ppm (desirably

[0220] to about several ppb). or about several ppb). When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, the damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using the metal oxide

[0221] as a target. To remove the residual moisture in the processing chamber temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, the damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using the metal oxide as a target. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, the damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using the metal oxide as a target. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, the damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using the metal oxide as a target. While removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using the metal oxide as a target. To remove the residual moisture in the processing chamber It is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Further, as the exhaust means, a turbo pump added with a cold trap may be used. The processing chamber evacuated using a cryopump is, for example, exhausted of compounds containing hydrogen atoms such as hydrogen 2 atoms, water (H O), etc. (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the

[0222] processing chamber can be reduced. As the formation conditions, for example, the distance between the substrate and the target is 100 mm, the pressure is 0. 6 Pa, the DC (direct current) power is 0.5 kW, and the atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere, and the like can be applied. When a pulsed DC (direct current) power supply is used, powdery substances (also referred to as particles, dust) generated during film formation can be reduced, and the film thickness distribution can also be made uniform, which is preferable. The thickness of the

[0223] oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material used. Before forming the oxide semiconductor layer by sputtering, it is preferable to A method is to apply a high-frequency voltage to the surface side to be processed under an argon atmosphere to generate plasma near the substrate. There are also methods such as using nitrogen, helium, oxygen, etc. instead of the argon atmosphere. It is also acceptable.

[0224] For the etching of the above oxide semiconductor layer, either dry etching or wet etching can be used. Of course, both can also be used in combination. Set the etching conditions (etching gas, etching solution, etching time, temperature, etc.) appropriately according to the material so that the desired shape can be etched.

[0225] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases , such as chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), etc.). Also, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CH F 3 ), etc.), hydrogen bromide (HBr), oxygen (O 2 ), and gases obtained by adding noble gases such as helium (He) or argon (Ar) to these gases can also be used.

[0226] As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. It can be etched into the desired shape. ​​​​As such, the etching conditions (the amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are set as appropriate. The amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are set as appropriate.

[0227] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) can also be used. It is also possible to use.

[0228] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be performed. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and less than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere and re-mixing of water or hydrogen is prevented. the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere and re-mixing of water or hydrogen is prevented. the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere and re-mixing of water or hydrogen is prevented. the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere and re-mixing of water or hydrogen is prevented.

[0229] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. mercury lamp. mercury lamp. It is as follows. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. As the gas, a noble gas such as argon, or an inert gas that does not react with the object to be treated by heat treatment, such as nitrogen, is used.

[0230] For example, as the first heat treatment, a substrate is introduced into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then a GRTA treatment of taking out the substrate from the inert gas may be performed. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment in a short time, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0231] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0232] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 90% or more, or 8 0% or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer containing no crystal component.

[0233] In addition, microcrystals (particle size 1 nm ​​The oxide semiconductor layer may contain oxides of 20 nm or less (typically 2 nm or more and 4 nm or less). This may be the case.

[0234] Also, by arranging microcrystals in the amorphous material, it is possible to change the electrical characteristics of the oxide semiconductor layer. For example, when forming an oxide semiconductor layer using a metal oxide target of the In-Ga-Zn-O system, the electrical anisotropy of In 2 Ga 2 ZnO 7 crystals By forming a microcrystalline portion in which the crystal grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. This is possible.

[0235] More specifically, for example, by orienting the c-axis of In 2 Ga 2 ZnO 7 to be perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be enhanced, and the insulation in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Also, such a microcrystalline portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. This function exists.

[0236] The oxide semiconductor layer having the above-described microcrystalline portion can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Also, by using a sputtering target in which the Zn content is smaller than the In or Ga content, it is possible to form it more preferably.

[0237] The first heat treatment for the oxide semiconductor layer 140 can also be performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the heating device is used. ​​​The substrate is taken out and the photolithography process is to be performed.

[0238] Note that the above heat treatment has an effect of dehydration and dehydrogenation on the oxide semiconductor layer 140 and can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such a dehydration treatment, dehydrogenation treatment can be performed at timings such as after forming the source electrode layer and the drain electrode layer on the oxide semiconductor layer 140 after forming the oxide semiconductor layer, or after forming a protective insulating layer on the source electrode layer and the drain electrode layer and the like. Further, such a dehydration treatment, dehydrogenation treatment may be performed multiple times, not limited to once.

[0239] Next, a source electrode layer 142a and a drain electrode layer 142b are formed in contact with the oxide semiconductor layer 140 (see FIG. 13(F)). The source electrode layer 142a and the drain electrode layer 142b can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer.

[0240] The conductive layer can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Further, as the material of the conductive layer, an element selected from aluminum, chromium , copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described elements as components, etc. can be used. A material selected from any one or more of manganese, magnesium, zirconium, beryllium , lithium, and thorium may also be used. Further, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium is singly or plurally combined with aluminum may also be used. The conductive The layer may have a single-layer structure or a laminated structure of two or more layers. For example, silicon a single-layer structure of an aluminum film containing, a two-layer structure in which a titanium film is laminated on the aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned.

[0241] Here, for the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or Ar F laser light.

[0242] The channel length (L) of the transistor is determined by the distance between the lower end of the source electrode layer 142a and the lower end of the drain electrode layer 142b. When performing exposure with a channel length (L) of less than 25 nm, extremely short-wavelength extreme ultraviolet (Extre me Ultraviolet) of several nm to several tens of nm is used for the exposure of mask formation. Exposure with extreme ultraviolet has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor formed later to be 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be increased .

[0243] In addition, during the etching of the conductive layer, each material and etching conditions are appropriately adjusted so that the oxide semiconductor layer 140 is not removed. Depending on the material and etching conditions , in this process, a part of the oxide semiconductor layer 140 may be etched, resulting in an oxide semiconductor layer having a groove (concave part).

[0244] Also, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode layer 142a, or between the oxide semiconductor layer 140 and the drain electrode layer 142b. The oxide conductive layer and the source The metal layer for forming the source electrode layer 142a and the drain electrode layer 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the low resistance of the source region or the drain region can be achieved, and thus the high-speed operation of the transistor can be realized.

[0245] In addition, in order to reduce the number of masks used and the number of processes, a resist mask is formed by a multi-tone mask, which is an exposure mask having multiple light intensities, and the etching process may be performed using this. The resist mask formed using the multi-tone mask has a shape (step shape) having multiple thicknesses, and the shape can be further deformed by ashing and thus can be used for a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photo lithography process can also be reduced, so that the process can be simplified. Note that after the above process, plasma treatment using a gas such as NO, N , or Ar is preferably performed. By the plasma treatment, water or the like attached to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0246] Note that after the above process, 2 O, N 2 , or Ar is preferably performed. By the plasma treatment, water or the like attached to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon. Next, without exposing to the atmosphere, a protective insulating layer 1 44 in contact with a part of the oxide semiconductor layer 140 is formed (see Fig. 13(G)).

[0247] 44 is formed (see Fig. 13(G)).

[0248] The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness should be at least 1 nm or more. Examples of materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride , silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300 °C or lower, and the atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere , or a mixed atmosphere of a rare gas (typically argon) and oxygen. If hydrogen is contained in the protective insulating layer 144, problems such as the intrusion of hydrogen into the oxide semiconductor layer 140 and the extraction of oxygen in the oxide semiconductor layer 140 by hydrogen may occur,

[0249] resulting in a decrease in the resistance of the back channel side of the oxide semiconductor layer 140 and the possible formation of a parasitic channel. Therefore, it is important that the protective insulating layer 144 contains as little hydrogen as possible and that hydrogen is not used in the formation method. Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to ensure that the oxide semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups, or moisture.

[0250] To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump . For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as an exhaust means, a turbo pump with a cold trap added is

[0251] preferred. It may be. Since the processing chamber evacuated using a cryopump has had, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H 2 2O), etc. removed, the concentration of impurities contained in the protective insulating layer 144 formed in the processing chamber can be reduced. When forming the protective insulating layer 144, as the sputtering gas used, high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or

[0252] hydrides have been removed to about several ppm (preferably about several ppb) is preferably used. Next, it is desirable to perform a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor.

[0253] Also, it may be heat-treated in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or may be repeated a plurality of times for the temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C or lower and the temperature decrease from the heating temperature to room temperature. Further, this heat treatment may be performed under reduced pressure before forming the protective insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the above-described second heat treatment, or may be performed before or after the second heat treatment. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide

[0254] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide

[0255] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, silicon oxide Materials including inorganic insulating materials such as recon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. can be used for formation. After the formation of the interlayer insulating layer 146, it is desirable to planarize its surface by methods such as CMP or etching.

[0256] Next, openings reaching the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, the source electrode layer 142a, and the drain electrode layer 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138, and a conductive layer 148 is formed so as to fill the openings (see FIG. 14(B)). The above openings can be formed by methods such as etching using a mask. The mask can be formed by methods such as exposure using a photomask. As the etching, either wet etching or dry etching can be used, but from the viewpoint of microfabrication, it is preferable to use dry etching. The formation of the conductive layer 148 can be performed using a film formation method such as PVD method or CVD method. Materials that can be used for the formation of the conductive layer 148 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., and alloys and compounds (for example, nitrides) thereof.

[0257] Specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD method in a region including the opening, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to fill the opening. Here, the titanium film formed by PVD method is the interface ​​​​​​​​​​​​​​​Reduce the oxide film and reduce the contact resistance with the lower electrodes (here, electrode layer 136a, electrode layer 136b, electrode layer 13 6c, source electrode layer 142a, drain electrode layer 142b). Also, the subsequently formed titanium nitride suppresses the diffusion of the conductive material as a barrier function. Further, after forming a barrier film made of titanium or titanium nitride, a copper film may be formed by a plating method .

[0258] After forming the conductive layer 148, a part of the conductive layer 14 8 is removed using methods such as etching or CMP to expose the interlayer insulating layer 146, and electrode layers 150a, 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e are formed (see FIG. 14(C)). Note that when removing a part of the conductive layer 148 to form the electrode layers 150a, 150b, electrode layer 150 c, electrode layer 150d, and electrode layer 150e, it is desirable to process so that the surface becomes flat . In this way, by planarizing the surfaces of the interlayer insulating layer 146, electrode layers 150a, 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0259] Furthermore, an insulating layer 152 is formed, and openings reaching the electrode layers 150a, 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e are formed in the insulating layer 152. After forming a conductive layer so as to fill the openings , a part of the conductive layer is removed using methods such as etching or CMP to expose the insulating layer 152, and electrode layers 154a, 154b, electrode layer 1 54c, and electrode layer 154d are formed (see FIG. 14(D)). This process is for the electrode layer 150a ​Since it is the same as the case of forming etc., details are omitted.

[0260] When the N-type transistor 164 is manufactured by the method as described above, the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10 19 (atoms / cm 3 ) or less, and the off-current of the N-type transistor 1 64 is 1 × 10 -13 [A] or less at room temperature. By applying such an N-type transistor 164 with excellent characteristics to the logic circuits shown in Embodiments 1 to 6, it becomes possible to reduce the standby power of the logic circuit and suppress malfunction of the logic circuit.

[0261] <Modification Example> Figs. 15 to 18 show modification examples of the configuration of the N-type transistor 164. Note that in Figs. 15 to 18, the configuration of the transistor 160 is the same as the configuration shown in Fig. 11.

[0262] Fig. 15 shows an N-type transistor 164 having a gate electrode layer 136d under the oxide semiconductor layer 140, and a source electrode layer 142a and a drain electrode layer 142b in contact with the lower surface of the oxide semiconductor layer 140.

[0263] A major difference between the configuration shown in Fig. 15 and the configuration shown in Fig. 11 is the connection position of the source electrode layer 142a and the drain electrode layer 142b to the oxide semiconductor layer 140. That is, in the configuration shown in Fig. 11, the source electrode layer 1 42a and the drain electrode layer 142b are in contact with the upper surface of the oxide semiconductor layer 140, while in the configuration shown in Fig. 15, the source electrode layer 142a and the drain electrode layer 142b are in contact with the lower surface of the oxide semiconductor layer 140. It is in contact with. And due to this difference in contact, the arrangements of other electrode layers, insulating layers, etc. are different It is like this. Note that the details of each component are the same as those in FIG. 11.

[0264] Specifically, the N-type transistor 164 shown in FIG. 15 includes a gate electrode layer 136d provided on the interlayer insulating layer 128 a gate insulating layer 138 provided on the gate electrode layer 136d, a source electrode layer 142a and a drain electrode layer 142b provided on the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. Also, a protective insulating layer 144 is provided on the N-type transistor 164 so as to cover the oxide semiconductor layer 140.

[0265] FIG. 16 shows an N-type transistor 164 having a gate electrode layer 136d on the oxide semiconductor layer 140. Here, FIG. 16(A) is a diagram showing an example of a configuration in which the source electrode layer 142a and the drain electrode layer 142b are in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140, and FIG. 16(B) is a diagram showing an example of a configuration in which the source electrode layer 142a and the drain electrode layer 142b are in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140.

[0266] A major difference between the configuration shown in FIG. 11 or FIG. 15 and the configuration shown in FIG. 16 is that there is a gate electrode layer 136d on the oxide semiconductor layer 140. Also, a major difference between the configuration shown in FIG. 16(A) and the configuration shown in FIG. 16(B) is whether the source electrode layer 142a and the drain electrode layer 142b are in contact with the lower surface or the upper surface of the oxide semiconductor layer 140. This is the point. Due to these differences, the arrangements of other electrode layers, insulating layers, etc. are different. Note that the details of each component are the same as those in FIG. 11 and the like.

[0267] Specifically, the N-type transistor 164 shown in FIG. 16(A) includes a source electrode layer 142a and a drain electrode layer 142b provided on the interlayer insulating layer 128, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. And a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate electrode layer 136d in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. 140.

[0268] Also, the N-type transistor 164 shown in FIG. 16(B) includes an oxide semiconductor layer 140 provided on the interlayer insulating layer 128, and a source electrode layer 142a and a drain electrode layer 142b provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. And a gate insulating layer 138 provided on the oxide semiconductor layer 140, the source electrode layer 142a, and the drain electrode layer 142b, and a gate electrode layer 13 provided in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. And a gate electrode layer 13 provided in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. 6d.

[0269] Note that in the configuration shown in FIG. 16, compared with the configuration shown in FIG. 11 and the like, some components may be omitted (for example, the electrode layer 150a, the electrode layer 154a, etc.). In this case, a secondary effect of simplifying the manufacturing process can also be obtained. Of course, it goes without saying that in the configuration shown in FIG. 11 and the like, non-essential components can also be omitted.

[0270] FIG. 17 shows a case where the size of the element is relatively large, and under the oxide semiconductor layer 140 An N-type transistor 164 having a gate electrode layer 136d is shown. In this case, since the requirements for surface flatness and coverage are relatively loose, it is not necessary to form wiring, electrodes, etc. by embedding them in the insulating layer. For example, after forming the conductive layer, patterning can be performed to form the gate electrode layer 136d and the like.

[0271] A major difference between the configuration shown in FIG. 17(A) and the configuration shown in FIG. 17(B) is whether the source electrode layer 1 42a and the drain electrode layer 142b are in contact with either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrode layers, insulating layers, etc. are different. Note that the details of each component are the same as those in FIG. 11 and the like.

[0272] Specifically, the N-type transistor 164 shown in FIG. 17(A) includes a gate electrode layer 136d provided on the interlayer insulating layer 128, a gate insulating layer 1 38 provided on the gate electrode layer 136d, a source electrode layer 142a and a drain electrode layer 142b provided on the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. It has.

[0273] Further, the N-type transistor 164 shown in FIG. 17(B) includes a gate electrode layer 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode layer 136d, and an oxide semiconductor layer 140 provided in a region overlapping the gate electrode layer 136d on the gate insulating layer 138, and a source electrode layer provided so as to be in contact with the upper surface of the oxide semiconductor layer 140 142a and a drain electrode layer 142b. It has. It has.

[0274] In addition, the configuration shown in FIG. 17 also has fewer components than the configuration shown in FIG. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0275] FIG. 18 shows a case where the size of the element is relatively large, and a An N-type transistor 164 is shown having a gate electrode layer 136d. The requirements for surface flatness and coverage are relatively low, so wiring, electrodes, etc. It is not necessary to form the conductive layer so as to be embedded in the insulating layer. For example, the conductive layer may be patterned after the formation of the conductive layer. By performing etching, the gate electrode layer 136d and the like can be formed.

[0276] The major difference between the configuration shown in FIG. 18(A) and the configuration shown in FIG. 18(B) is that the source electrode layer 1 42a and the drain electrode layer 142b are disposed on the lower or upper surface of the oxide semiconductor layer 140. And due to these differences, The arrangement of the electrode layers, insulating layers, etc. is different. This is similar to 11 etc.

[0277] Specifically, the N-type transistor 164 shown in FIG. 18A is provided on the interlayer insulating layer 128. The source electrode layer 142a and the drain electrode layer 142b are formed by the above-mentioned The oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142b and the drain electrode layer 142b, 42a, the drain electrode layer 142b, and the gate insulating film provided on the oxide semiconductor layer 140. the oxide semiconductor layer 140 provided over the gate insulating layer 138 and a gate electrode layer 136d.

[0278] Also, the N-type transistor 164 shown in FIG. 18(B) is provided on the interlayer insulating layer 128 with an oxide semiconductor layer 140, a source electrode layer 142a and a drain electrode layer 142b provided so as to be in contact with the upper surface of the oxide semiconductor layer 140, a gate insulating layer 138 provided on the source electrode layer 142a, the drain electrode layer 142b, and the oxide semiconductor layer 140, and a gate electrode layer 13 6d provided in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. It has.

[0279] Note that also in the configuration shown in FIG. 18, components may be omitted as compared with the configuration shown in FIG. 11 and the like. Also in this case, the effect of simplifying the manufacturing process can be obtained.

[0280] In this embodiment, an example in which the N-type transistor 164 is stacked on the P-type transistor 160 has been described. However, the configurations of the P-type transistor 160 and the N-type transistor 164 are not limited to this. For example, a P-type transistor and an N-type transistor can be formed on the same plane. Further, the P-type transistor 160 and the N-type transistor 164 may be provided so as to overlap each other. By applying the above-described N-type transistor 164 to the N-type transistor included in the logic circuits shown in Embodiments 1 to 6, it is possible to suppress charge leakage through the thin film transistor. As a result, it becomes possible to reduce the standby power of the logic circuit and suppress malfunction of the logic circuit.

[0281]

[0282] Note that part or all of the content of this embodiment may be the content of other embodiments or part of the content ​​​​​​​​​It is possible to freely combine with a part of another embodiment or the content of another embodiment or a part of the content. with.

[0283] (Embodiment 8) In this embodiment, an example of a transistor included in the logic circuit shown in Embodiments 1 to 6 will be described. Specifically, an example of a thin film transistor in which a channel formation region is formed of an oxide semiconductor will be described. A form of the thin film transistor and a method for manufacturing the same according to this embodiment will be described with reference to FIGS. 19 and 20. with reference to FIGS. 19 and 20.

[0284] An example of the planar and cross-sectional structures of the thin film transistor is shown in FIGS. 19(A) and 19(B). The thin film transistor 460 shown in FIGS. 19(A) and 19(B) is a thin film transistor having a top gate structure. is a thin film transistor having a top gate structure.

[0285] FIG. 19(A) is a plan view of the thin film transistor 460 having a top gate structure, and FIG. 19(B) is a cross-sectional view taken along line D1-D2 of FIG. 19(A). is a cross-sectional view taken along line D1-D2 of FIG. 19(A). is.

[0286] FIG. 19(A) is a plan view of the thin film transistor 460 having a top gate structure, and FIG. 19(B) is a cross-sectional view taken along line D1-D2 of FIG. 19(A).

[0287] The thin film transistor 460 includes an insulating layer 457, a source electrode layer or a drain electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, a source electrode layer or a drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate electrode layer 461 (461a, 461b) on a substrate 450 having an insulating surface. The source electrode layer or the drain electrode layer 465a (465a1, 465a2) is electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source electrode layer or the drain electrode layer 465b is also electrically connected to the wiring layer at an opening provided in the gate insulating layer 452. on a substrate 450 having an insulating surface, an insulating layer 457, a source electrode layer or a drain electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462 , a source electrode layer or a drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, a gate electrode layer 461 (461a, 461b), and the source electrode layer or the drain electrode layer 465 a (465a1, 465a2) is electrically connected to the wiring layer 464 via the wiring layer 468 is. Although not shown, the source electrode layer or the drain electrode layer 465b is also electrically connected to the wiring layer at an opening provided in the gate insulating layer 452. is electrically connected to the wiring layer at an opening provided in the gate insulating layer 452.

[0288] Hereinafter, a process of fabricating a thin film transistor 460 on a substrate 450 will be described with reference to FIGS. 20(A) to (E). The process will be described below.

[0289] First, an insulating layer 457 serving as an underlayer film is formed on a substrate 450 having an insulating surface.

[0290] In this embodiment, as the insulating layer 457, a silicon oxide layer is formed by a sputtering method. The substrate 450 is transferred into a processing chamber, and a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. Using a silicon target or quartz (preferably synthetic quartz), a silicon oxide layer is formed on the substrate 450 as the insulating layer 457. Note that as the sputtering gas, oxygen or a mixed gas of oxygen and argon can be used. For example, with a purity of 6N, using quartz (preferably synthetic quartz), a substrate temperature of 108° C., a distance between the substrate and the target (T-S distance) of 60 mm, a pressure of 0.4 Pa, a high-frequency power source of 1.5 kW, and an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1), a silicon oxide layer is formed by RF sputtering. The film thickness is set to 100 nm.

[0291] Note that instead of quartz (preferably synthetic quartz), a silicon target can be used as a target for forming a silicon oxide layer.

[0292] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber.

[0292] This is to prevent hydrogen, hydroxyl groups, or moisture from being included in the insulating layer 457. For example, a processing chamber evacuated using a cryopump contains compounds containing hydrogen atoms such as water (H 2 O). 2 Since compounds and the like containing [it] are exhausted, impurities contained in the insulating layer 457 formed in the processing chamber can have their concentration reduced.

[0293] For the insulating layer 457, the sputtering gas used during film formation is preferably a high-purity gas in which any impurities have been removed to the extent of several ppm to several ppb, such as hydrogen, water, hydroxyl groups, or hydrides. preferable.

[0294] Also, the insulating layer 457 may have a laminated structure. For example, it may have a laminated structure of nitride insulating layers such as a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, and an aluminum oxynitride layer, etc., and the oxide insulating layer.

[0295] For example, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced between the silicon oxide layer and the substrate, and a silicon nitride layer is formed using a silicon target. Even in this case, similar to the silicon oxide layer, it is preferable to form the silicon nitride layer while removing residual moisture in the processing chamber. preferable.

[0296] Next, a conductive layer is formed on the insulating layer 457, and a resist mask is formed on the conductive film by a first photolithography process. After selectively etching to form the source electrode layer or the drain electrode layers 465a1, 465a2, the resist mask is removed (see Fig. 20(A )). The source electrode layer or the drain electrode layers 465a1, 465a2 are shown as separated in the cross-sectional view, but they are continuous films. Note that if the ends of the formed source electrode layer and drain electrode layer are tapered, the coverage of the gate insulating layer laminated thereon is improved, which is preferable. preferable.

[0297] As the material of the source electrode layer or the drain electrode layer 465a1, 465a2, Al, Cr , an element selected from Cu, Ta, Ti, Mo, W, or an alloy containing the above-mentioned elements , or an alloy such as an alloy combining the above-mentioned elements can be mentioned. Further, a material selected from any one or more of manganese, magnesium , zirconium, beryllium, and thorium may be used. Further, the conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on the aluminum layer , a three-layer structure in which a Ti layer is formed, an aluminum layer is laminated on the Ti layer, and a Ti layer is further formed thereon can be mentioned. Further, a layer, an alloy layer, or a nitride layer in which an element selected from titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium) , Sc (scandium) is combined singly or in plural may be used. In the present embodiment, a titanium layer with a film thickness of 150 nm is formed as the source electrode layer or the drain electrode layer 465a1, 465a2 by sputtering.

[0298] Next, an oxide semiconductor layer having a film thickness of 2 nm or more and 200 nm or less is formed on the insulating layer 457 and the source electrode layer or the drain electrode layer 465a1, 465a2.

[0299] Next, it is processed into an island-shaped oxide semiconductor layer 462 by a second photolithography process ( see Fig. 20(B)). In the present embodiment, an oxide semiconductor layer is formed by sputtering using an In-Ga-Zn-O-based metal oxide target.

[0300]

[0301] A substrate is held in a processing chamber maintained under a reduced pressure state, and while removing residual moisture in the processing chamber, hydrogen and moisture-removed sputter gas are introduced, and an oxide semiconductor layer is formed on a substrate 450 using a metal oxide as a target. In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The processing chamber evacuated using a cryopump is, for example, exhausted of compounds containing hydrogen atoms such as water (H 2 O) (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the processing chamber can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor layer. When forming the oxide semiconductor layer, the sputter gas used is a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm to about several ppb.

[0302] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the DC (direct current) power supply is 0.5 kW, and the conditions in an atmosphere of oxygen and argon (oxygen flow rate 15 scc m: argon flow rate 30 sccm) are applied. Note that when a pulsed DC (direct current)

[0303] power supply is used, it is preferable because the powdery substances (also called particles or dust) generated during film formation are reduced and the film thickness distribution becomes uniform. The oxide semiconductor layer is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material . ​​

[0304] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 462 by a thermal etching method.

[0305] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the specimen was placed in an oxygen-free environment without exposure to air. This first heat treatment prevents water and hydrogen from re-mixing into the oxide semiconductor layer, and obtains an oxide semiconductor layer. The oxide semiconductor layer 462 can be dehydrated or dehydrogenated by this.

[0306] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment For example, the first heat treatment may be performed at a temperature of 650° C. to 7 The substrate is moved into an inert gas atmosphere heated to a high temperature of 00°C and heated for several minutes. Alternatively, GRTA can be performed by moving the container and releasing it from the inert gas heated to a high temperature. When used, high-temperature heat treatment can be performed in a short period of time.

[0307] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. Preferably, it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment apparatus , or the purity of noble gases such as helium, neon, and argon is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0308] In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline.

[0309] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor layer before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus, and a photolithography process is performed.

[0310] The heat treatment that exhibits the effect of dehydration and dehydrogenation on the oxide semiconductor layer can be performed after forming the oxide semiconductor layer, after further laminating the source electrode and the drain electrode on the oxide semiconductor layer, or after forming the gate insulating layer on the source electrode and the drain electrode.

[0311] Next, a conductive layer is formed on the insulating layer 457 and the oxide semiconductor layer 462, a resist mask is formed on the conductive layer by a third photolithography process, and selective etching is performed to form the source electrode layer or the drain electrode layer 465b and the wiring layer 468, and then the resist mask is removed (see FIG. 20(C)). The source electrode layer or the drain electrode layer 465b and the wiring layer 468 may be formed of the same materials and processes as the source electrode layers or the drain electrode layers 465a1 and 465a2.

[0312] ​​​​​​In this embodiment, a titanium layer with a thickness of 150 nm is formed as the source electrode layer or drain electrode layer 465b and the wiring layer 468 by sputtering. Since the same titanium layer is used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b in this embodiment, the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b do not have a selectivity in etching. Therefore, the wiring layer 468 is provided on the source electrode layer or drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462 so that the source electrode layer or drain electrode layer 465a1, 465a2 is not etched during the etching of the source electrode layer or drain electrode layer 465b. When different materials having a high selectivity in the etching process are used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b, the wiring layer 468 for protecting the source electrode layer or drain electrode layer 465a2 during etching is not necessarily provided. In this embodiment, a titanium layer with a thickness of 150 nm is formed as the source electrode layer or drain electrode layer 465b and the wiring layer 468 by sputtering. Since the same titanium layer is used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b in this embodiment, the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b do not have a selectivity in etching. Therefore, the source electrode layer or drain electrode layer 465a1, 465a2 is not etched during the etching of the source electrode layer or drain electrode layer 465b. So that the source electrode layer or drain electrode layer 465a1, 465a2 is not etched during the etching of the source electrode layer or drain electrode layer 465b, the wiring layer 468 is provided on the source electrode layer or drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462. In this embodiment, a titanium layer with a thickness of 150 nm is formed as the source electrode layer or drain electrode layer 465b and the wiring layer 468 by sputtering. Since the same titanium layer is used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b in this embodiment, the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b do not have a selectivity in etching. Therefore, the source electrode layer or drain electrode layer 465a1, 465a2 is not etched during the etching of the source electrode layer or drain electrode layer 465b. So that the source electrode layer or drain electrode layer 465a1, 465a2 is not etched during the etching of the source electrode layer or drain electrode layer 465b,

[0313] When different materials having a high selectivity in the etching process are used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b, the wiring layer 468 for protecting the source electrode layer or drain electrode layer 465a2 during etching is not necessarily provided.

[0314] In this embodiment, a Ti layer is used as the conductive film, an In-Ga-Zn-O based oxide semiconductor is used for the oxide semiconductor layer 462, and ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide solution) is used as the etchant. In this embodiment, a titanium layer with a thickness of 150 nm is formed as the source electrode layer or drain electrode layer 465b and the wiring layer 468 by sputtering. Since the same titanium layer is used for the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b in this embodiment,

[0315] In the third photolithography process, only a part of the oxide semiconductor layer 462 is etched. It may also become an oxide semiconductor layer having a groove portion (concave portion). Further, a resist mask for forming the source electrode layer or the drain electrode layer 465b and the wiring layer 468 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Next, a gate insulating layer 452 is formed on the insulating layer 457, the oxide semiconductor layer 462, the source electrode layer or the drain electrode layer 46

[0316] 5a1, 465a2, the source electrode layer or the drain electrode layer 465b, and the wiring 468. 5a1, 465a2, the source electrode layer or the drain electrode layer 465b, and the wiring 468. As the gate insulating layer 452, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer,

[0317] or an aluminum oxide layer formed by using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 4 52, it is preferable to form the gate insulating layer 452 by a sputtering method. When forming a silicon oxide layer by the sputtering method in this case, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 452, it is preferable to form the gate insulating layer 452 by a sputtering method. When forming a silicon oxide layer by the sputtering method in this case, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. to perform.

[0318] The gate insulating layer 452 may have a structure in which a silicon oxide layer and a silicon nitride layer are laminated from the side of the source electrode layer or the drain electrode layer 465a1, 465a2, the source electrode layer or the drain electrode layer 465b. In this embodiment, the pressure is 0.4 Pa, the high-frequency power source is 1.5 kW and an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) is used. A silicon oxide layer with a thickness of 100 nm is formed by RF sputtering in air.

[0319] Next, a resist mask is formed by a fourth photolithography process, and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 that reaches the wiring layer 468. Although not shown, when the opening 423 is formed, the source electrode layer or An opening reaching the drain electrode layer 465b may be formed. An opening for the drain electrode layer 465b is formed after laminating an interlayer insulating layer. In this example, a wiring layer for connecting to a target is formed in an opening.

[0320] Next, a conductive layer is formed on the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a lithography process. The resist mask may be formed by an ink-jet method. When the ink jet method is used, no photomask is used, which reduces manufacturing costs.

[0321] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium It is possible to apply a single layer or a multi-layer of metal materials such as aluminum or alloy materials that have these as the main components. Cut.

[0322] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are A titanium layer having a thickness of 150 nm is formed by a sputtering method.

[0323] Then, a second heat treatment (preferably It is carried out at a temperature of 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower. In this embodiment a second heat treatment is carried out at 250 °C for 1 hour in a nitrogen atmosphere. Also, the second heat treatment may be carried out after forming a protective insulating layer or a planarizing insulating layer on the thin film transistor 460.

[0324] Furthermore, a heat treatment may be carried out in the atmosphere at 100 °C or higher and 200 °C or lower for 1 hour or more and 30 hours or less This heat treatment may be carried out while maintaining a constant heating temperature, or from room temperature to 1 heating temperature increase to 100 °C or higher and 200 °C or lower, and a temperature decrease from the heating temperature to room temperature may be repeated multiple times Also, this heat treatment may be carried out under reduced pressure before forming the oxide insulating layer. When the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0325] Through the above steps, a thin film transistor 460 having an oxide semiconductor layer 4 62 with reduced concentrations of hydrogen, moisture, hydrides, and hydroxides can be formed (see Fig. 20(E)).

[0326] Also, a protective insulating layer or a planarizing insulating layer for planarization may be provided on the thin film transistor 460. Although not shown, an opening reaching the source electrode layer or the drain electrode layer 465b is formed in the gate insulating layer, the protective insulating layer, and the planarizing insulating layer, and a wiring layer electrically connected to the source electrode layer or the drain electrode layer 465b is formed in the opening. or a drain electrode layer 465b.

[0327] When forming the oxide semiconductor layer as described above, residual moisture in the reaction atmosphere is removed so that the concentrations of hydrogen and hydrides in the oxide semiconductor layer can be reduced. Thereby the stabilization of the oxide semiconductor layer can be achieved.

[0328] By applying the thin film transistor described above to the transistors included in the logic circuits shown in Embodiments 1 to 6, it is possible to suppress the leakage of electric charges through the thin film transistor. As a result, it becomes possible to reduce the power consumption (standby power) of the logic circuit and to suppress malfunction of the logic circuit.

[0329] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content, or the content of other examples or a part of the content.

[0330] (Embodiment 9) In this embodiment, an example of the transistor included in the logic circuits shown in Embodiments 1 to 6 will be described. Specifically, an example of a thin film transistor in which a channel formation region is formed of an oxide semiconductor will be described.

[0331] One mode of the thin film transistor and a method for manufacturing the same according to this embodiment will be described with reference to FIG. 21.

[0332] Examples of the cross-sectional structure of the thin film transistor are shown in FIGS. 21(A) to (E). The thin film transistor 390 shown in FIGS. 21(A) to (E) is one of bottom gate structures and is also referred to as an inverted staggered type thin film transistor.

[0333] Although the thin film transistor 390 is described using a single gate structure thin film transistor, a multi-gate structure thin film transistor having a plurality of channel formation regions can be formed as necessary.

[0334] Hereinafter, the thin film transistor 390 is manufactured on the substrate 394 with reference to FIGS. 21(A) to (E).​​​​​​​​​​​ The steps will be described.

[0335] First, after forming a conductive layer on a substrate 394 having an insulating surface, a gate electrode layer 391 is formed by a first photolithography process. If the end of the formed gate electrode layer 391 is in a tapered shape, it is preferable because the coverage of the gate insulating layer laminated thereon is improved. Note that a resist mask may be formed by an inkjet method. When a resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. There is no great limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least

[0336] it is necessary to have heat resistance to withstand subsequent heat treatment. Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used.

[0337] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. Further, for the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Generally, by containing more barium oxide (BaO) than boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B 2 O 3

[0338] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. Also, plastic substrates or the like can be appropriately used.​​​

[0339] An insulating layer serving as an underlayer film may be provided between the substrate 394 and the gate electrode layer 391. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 394, and is formed by a laminated structure of one or more films selected from a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride oxide layer. It can be formed by a laminated structure.

[0340] Further, as the gate electrode layer 391, a single layer or a laminate of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., or an alloy material mainly composed of these can be applied. It can be formed by a laminated structure.

[0341] For example, as the two-layer laminated structure of the gate electrode layer 391, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer structure in which a molybdenum layer is laminated on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated is preferable. As the three-layer laminated structure, a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated is preferable. In addition, the gate electrode layer can also be formed using a conductive layer having translucency. As the conductive layer having translucency, a translucent conductive oxide or the like can be cited as an example. a two-layer structure is preferable. As the three-layer laminated structure, a structure in which a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated is preferable. In addition, the gate electrode layer can also be formed using a conductive layer having translucency. As the conductive layer having translucency, a translucent conductive oxide or the like can be cited as an example. a translucent conductive oxide or the like can be cited as an example. a translucent conductive oxide or the like can be cited as an example. a translucent conductive oxide or the like can be cited as an example.

[0342] Next, a gate insulating layer 397 is formed on the gate electrode layer 391.

[0343] As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. The gate insulating layer 397 may have a structure in which a silicon nitride layer and a silicon oxide layer are laminated from the gate electrode layer 391 side. For example, as a first gate insulating layer, a silicon nitride layer (SiN(y>0)) having a film thickness of 50 nm or more and 200 nm or less is formed by a sputtering method, and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less is formed on the first gate insulating layer. A silicon oxide layer (SiO(x>0)) is laminated to form a gate insulating layer having a film thickness of 100 nm. Further, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the gate insulating layer 397 and the oxide semiconductor layer 393, as a pretreatment for film formation, the substrate 394 on which the gate electrode layer 391 is formed or the substrate 394 on which the gate insulating layer 397 is formed up to is preheated in a preheating chamber of a sputtering apparatus to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 394. It is preferable. The preheating temperature is preferably 100°C or higher and 400°C or lower. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0344] As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. y As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. x As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0345] As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. As the gate insulating layer 397, a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer formed using a plasma CVD method, a sputtering method, or the like can be applied. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide layer by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. is 150°C or higher and 300°C or lower. Note that the exhaust means provided in the preheating chamber is preferably a cryopump. This preheating treatment can also be omitted. Also, this preheating may be similarly performed on the substrate 394 formed before the formation of the oxide insulating layer 396, also on the source electrode layer 395a and the drain electrode layer 395b.

[0346] Next, an oxide semiconductor layer 393 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 397 (see Fig. 21(A)).

[0347] Note that before forming the oxide semiconductor layer 393 by sputtering, reverse sputtering is performed to generate plasma by introducing argon gas, and it is preferable to remove the dust adhering to the surface of the gate insulating layer 397. Reverse sputtering is a method of modifying the surface by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0348] The oxide semiconductor layer 393 is formed by sputtering. The oxide semiconductor layer 393 uses an oxide semiconductor of In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system. In this embodiment, the oxide semiconductor layer 393 is formed by sputtering using an In-Ga-Zn-O-based metal oxide target. Also, the oxide semiconductor layer 393 is formed in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or a noble gas (typically argon) and an oxygen atmosphere. It can be formed by sputtering in an argon and oxygen atmosphere. When using the sputtering method, a target of a metal oxide mainly composed of SiO 2 containing 2% by weight or more and 10% by weight or less of getter may be used for film formation.

[0349] As a target for producing the oxide semiconductor layer 393 by sputtering, a target of a metal oxide mainly composed of zinc oxide can be used. Further, as another example of the metal oxide target a metal oxide target containing In, Ga, and Zn (composition ratio as, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [mol], In:Ga:Zn = 1:1:0.5 [atom]) can be used. Further, as a metal oxide target containing In, Ga, and Zn a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom], or In :Ga:Zn = 1:1:2 [atom] can also be used . The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 9 9.9%. By using a metal oxide target with a high filling rate, the formed oxide semiconductor layer becomes a dense layer.

[0350] A substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to a temperature of room temperature or higher and lower than 400 °C. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor layer 393 is formed on the substrate 394 using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. ​It is preferable. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust means, a turbo pump with a cold trap added thereto may be used. The processing chamber evacuated using a cryopump is evacuated of compounds containing hydrogen atoms such as, for example, water (H 2 O) and the like (more preferably compounds containing carbon atoms as well), so that the concentration of impurities contained in the oxide semiconductor layer formed in the processing chamber can be reduced. Further, by performing sputter film formation while removing moisture remaining in the processing chamber by a cryopump, the substrate temperature when forming the oxide semiconductor layer 393 can be set to be equal to or higher than room temperature and lower than 400°C.

[0351] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 P a, a DC power source of 0.5 kW, and conditions in an oxygen (oxygen flow rate ratio: 100%) atmosphere are applied. Note that when a pulsed DC power source is used, it is preferable because powdery substances (also referred to as particles or dust) generated during film formation can be reduced and the film thickness distribution becomes uniform. The oxide semiconductor layer is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material.

[0352] The sputtering method includes an RF sputtering method using a high-frequency power source as a sputtering power source and a DC sputtering method, and further includes a pulsed DC sputtering method in which a bias is applied pulsatively. The RF sputtering method is mainly used when forming an insulating layer, and the DC sputtering method is mainly used when forming a metal layer.

[0353] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack different material layers in the same chamber to form a film, or can also discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0354] In addition, there is a sputtering apparatus that uses a magnetron sputtering method with a magnet mechanism inside the chamber, and an ECR sputtering apparatus that uses plasma generated by using microwaves without using glow discharge.

[0355] In addition, as a film formation method using a sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation.

[0356] Next, the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer 399 by a second photolithography process (see FIG. 21(B)). Further, a resist mask for forming the island-shaped oxide semiconductor layer 399 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0357] In addition, when forming a contact hole in the gate insulating layer 397, the process can be performed during the formation of the oxide semiconductor layer 399.

[0358] Note that the etching of the oxide semiconductor layer 393 here may be dry etching, wet etching, or both may be used.

[0359] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example for example, chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), carbon tetrachloride (C Cl 4 ), etc.) is preferable.

[0360] Also, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF 4 ), sulfur fluoride (S F 6 ), nitrogen fluoride (NF 3 ), trifluoromethane (CHF 3 ), etc.), hydrogen bromide (HB r), oxygen (O 2 ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used. As the dry etching method, a parallel plate type RIE (Reactive Ion Etc

[0361] hing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that etching can be performed to the desired processed shape. hing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that etching can be performed to the desired processed shape. ductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that etching can be performed to the desired processed shape. As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0362] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0363] After wet etching, the etching solution is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material is removed. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after etching, resources can be effectively utilized and the cost can be reduced. etc., it is possible to achieve this.

[0364] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired processed shape.

[0365] Note that it is preferable to perform reverse sputtering before forming the conductive layer in the next process to remove resist residues and the like adhering to the surfaces of the oxide semiconductor layer 399 and the gate insulating layer 397.

[0366] Next, a conductive layer is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive layer may be formed by a sputtering method or a vacuum evaporation method. As the material of the conductive layer, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W, or alloys containing the above-mentioned elements, or alloy layers or alloy layers combined with the above-mentioned elements, etc. may be mentioned. Further, materials selected from any one or more of manganese, magnesium, neodium, zirconium, beryllium, and thorium may be used. Also, the metal conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on the aluminum layer, a three-layer structure in which a Ti layer is laminated, an aluminum layer is laminated on the Ti layer, and a Ti layer is further laminated thereon, etc. may be mentioned. Further, for Al, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), layers, alloy layers, or nitride layers selected from one or a plurality of elements selected from Nd (neodymium), Sc (scandium) may be used. ​

[0367] A resist mask is formed on the conductive layer by a third photolithography process, and selective etching is performed to form a source electrode layer 395a and a drain electrode layer 395b, and then the resist mask is removed (see Fig. 21(C)). A resist mask is formed on the conductive layer by a third photolithography process, and selective etching is performed to form a source electrode layer 395a and a drain electrode layer 395b, and then the resist mask is removed (see Fig. 21(C)). A resist mask is formed on the conductive layer by a third photolithography process, and selective etching is performed to form a source electrode layer 395a and a drain electrode layer 395b, and then the resist mask is removed (see Fig. 21(C)).

[0368] For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin film transistor to be formed later is determined by the interval width between the lower ends of the adjacent source electrode layers and the lower ends of the drain electrode layers on the oxide semiconductor layer 399. When performing exposure with a channel length L of less than 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet light with a wavelength as short as several nm to several tens of nm. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor to be formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit and further achieve low power consumption because the off-current value is extremely small. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor to be formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit and further achieve low power consumption because the off-current value is extremely small. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor to be formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit and further achieve low power consumption because the off-current value is extremely small. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor to be formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit and further achieve low power consumption because the off-current value is extremely small.

[0369] When etching the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 399 is not removed. When etching the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 399 is not removed.

[0370] In this embodiment, a Ti layer is used as the conductive film, an In-Ga-Zn-O based oxide semiconductor is used for the oxide semiconductor layer 399, and ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant. In this embodiment, a Ti layer is used as the conductive film, an In-Ga-Zn-O based oxide semiconductor is used for the oxide semiconductor layer 399, and ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant. In this embodiment, a Ti layer is used as the conductive film, an In-Ga-Zn-O based oxide semiconductor is used for the oxide semiconductor layer 399, and ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant.

[0371] Note that in the third photolithography step, the oxide semiconductor layer 399 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 395a and the drain electrode layer 395b is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0372] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0373] N 2 O, N 2 or by plasma treatment with a gas such as Ar. Water adsorbed on the surface of the semiconductor layer may be removed. A plasma treatment may be performed using the gas.

[0374] When the plasma treatment is performed, the oxide semiconductor layer is not exposed to the air and the oxygen is in contact with the oxide semiconductor layer. In this embodiment, an oxide semiconductor layer is formed on the oxide semiconductor insulating layer 396 (see FIG. 21D). In a region where 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b, an oxide semiconductor layer 399 and an oxide insulating layer 396 are formed to be in contact with each other.

[0375] In this embodiment, as the oxide insulating layer 396, a substrate 394 formed up to the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, and the drain electrode layer 395b is heated to a temperature equal to or higher than room temperature and lower than 100 °C, and a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. Using a silicon target, a silicon oxide layer containing defects is formed.

[0376] For example, a silicon target with a purity of 6N and doped with boron (resistivity 0.01 Ωcm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, a pulsed DC sputtering method is used in an atmosphere of a DC power supply of 6 kW and oxygen (oxygen flow ratio 100%) to form a silicon oxide layer. The film thickness is 300 nm. Note that instead of the silicon target, quartz (preferably synthetic quartz) can be used as a target for forming the silicon oxide layer. Note that oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0377] In this case, it is preferable to form the oxide insulating layer 396 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 399 and the oxide insulating layer 396.

[0378] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. is preferred. As the exhaust means, a cold trap may be added to the turbo pump. This is also acceptable. The processing chamber evacuated using a cryopump is, for example, water (H 2 O) or a compound containing a compound containing a hydrogen atom, etc. is exhausted. Therefore, the concentration of impurities contained in the oxide insulating layer 396 formed in the processing chamber can be reduced.

[0379] Note that as the oxide insulating layer 396, instead of the silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer, etc. can also be used.

[0380] Furthermore, heat treatment may be performed at 100°C to 4 00°C with the oxide insulating layer 396 and the oxide semiconductor layer 399 in contact. Since the oxide insulating layer 396 in this embodiment contains many defects, hydrogen, moisture, hydroxyl groups, or hydrides, etc. contained in the oxide semiconductor layer 399 are diffused into the oxide insulating layer 396 by this heat treatment, and the impurities contained in the oxide semiconductor layer 399 can be further reduced.

[0381] In the above steps, a thin film transistor 390 having an oxide semiconductor layer 392 with reduced concentrations of hydrogen, moisture, hydroxyl groups, or hydrides can be formed (see Fig. 21(E)).

[0382] When forming the oxide semiconductor layer as described above, by removing residual moisture in the reaction atmosphere, the concentrations of hydrogen and hydrides in the oxide semiconductor layer can be reduced. Thereby, the oxide semiconductor layer can be stabilized.

[0383] A protective insulating layer may be provided on the oxide insulating layer. In this embodiment, the protective insulating layer 398 is It is formed on the oxide insulating layer 396. As the protective insulating layer 398, a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, an aluminum oxynitride layer, or the like is used. When forming the protective insulating layer 398, the substrate 394 formed up to the oxide insulating layer 396 is heated to a temperature of 100°C to

[0384] 400°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced, and a silicon nitride layer is formed using a silicon target. Also in this case, similar to the oxide insulating layer 396, it is preferable to form the protective insulating layer 398 while removing residual moisture in the processing chamber. When forming the protective insulating layer 398, by heating the substrate 394 to 100°C to 400°C during the film formation of the protective insulating layer 398, hydrogen or moisture contained in the oxide semiconductor layer can be diffused into the oxide insulating layer. In this case, heat treatment may not be performed after the formation of the oxide insulating layer 396. When a silicon oxide layer is formed as the oxide insulating layer 396 and a silicon nitride layer is laminated as the protective insulating layer 398, the silicon oxide layer and the silicon nitride layer can be formed using a common

[0385] silicon target in the same processing chamber. First, a sputtering gas containing oxygen is introduced, and a silicon oxide layer is formed using the silicon target mounted in the processing chamber. Next, the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. heat treatment may not be performed after the formation of the oxide insulating layer 396. When forming the protective insulating layer 398, by heating the substrate 394 to 100°C to 400°C during the film formation of the protective insulating layer 398, hydrogen or moisture contained in the oxide semiconductor layer can be diffused into the oxide insulating layer. In this case,

[0386] When a silicon oxide layer is formed as the oxide insulating layer 396 and a silicon nitride layer is laminated as the protective insulating layer 398, the silicon oxide layer and the silicon nitride layer can be formed using a common silicon target in the same processing chamber. First, a sputtering gas containing oxygen is introduced, and a silicon oxide layer is formed using the silicon target mounted in the processing chamber. Next, the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396. A silicon nitride layer is then laminated as a protective insulating layer 398, and then the oxide semiconductor layer is Heat treatment (temperature 100°C to 40°C) to diffuse hydrogen or moisture into the oxide insulating layer. 0℃).

[0387] After the protective insulation layer is formed, it is further left in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment may be performed at a constant temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times to lower the temperature to 100° C. Before the formation, the heating treatment may be performed under reduced pressure. By performing the heating treatment under reduced pressure, the heating time can be shortened. This heat treatment makes it possible to obtain a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0388] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, By removing residual moisture in the reaction atmosphere, the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. can be reduced.

[0389] The above process is applicable to LCD panels, electroluminescent display panels, and electronic ink displays. Used in the manufacture of backplanes (substrates on which thin-film transistors are formed) for display devices, etc. The above process is carried out at a temperature of 400°C or less, so the thickness is 1 mm or less. It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 400°C, making it ideal for manufacturing display panels. It is possible to consume much less energy.

[0390] By applying the thin film transistor described above to the transistors included in the logic circuits shown in Embodiments 1 to 6, it is possible to suppress charge leakage through the thin film transistor. As a result, it becomes possible to reduce the standby power of the logic circuit and suppress malfunction of the logic circuit.

[0391] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content, or the content of other examples or a part of the content.

[0392] (Embodiment 10) In this embodiment, an example of the transistors included in the logic circuits shown in Embodiments 1 to 6 will be described. Specifically, an example of a thin film transistor in which a channel formation region is formed of an oxide semiconductor will be described.

[0393] One mode of the thin film transistor and its manufacturing method according to this embodiment will be described with reference to FIG. 22.

[0394] Examples of the cross-sectional structure of the thin film transistor are shown in FIGS. 22(A) to (D). The thin film transistor 360 shown in FIG. 22(D) is one of the bottom gate structures called channel protection type (also called channel stop type), and is also called an inverse staggered type thin film transistor.

[0395] The thin film transistor 360 is described using a single gate structure thin film transistor, but a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed as necessary. ​​​​​​​​​​​

[0396] Hereinafter, a process of fabricating the thin film transistor 360 on the substrate 320 will be described with reference to FIGS. 22(A) to (D). This will be described below.

[0397] First, after forming a conductive layer on the substrate 320 having an insulating surface, a gate electrode layer 361 is formed by a first photolithography process. Note that a resist mask may be formed by an inkjet method In this case, since a photomask is not used, the manufacturing cost can be reduced.

[0398] In addition, as the gate electrode layer 361, a single layer or a laminate of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten sten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these can be applied.

[0399] Next, a gate insulating layer 322 is formed on the gate electrode layer 361.

[0400] In this embodiment, a silicon oxynitride layer having a thickness of 100 nm or less is formed by plasma CVD as the gate insulating layer 322

[0401] Next, an oxide semiconductor layer having a thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 322 and processed into an island-shaped oxide semiconductor layer by a second photolithography process. In this embodiment a In-Ga-Zn-O-based metal oxide target is used as the oxide semiconductor layer and formed by sputtering.

[0402] In this case, it is preferable to form the oxide semiconductor layer while removing residual moisture in the processing chamber This is to prevent hydrogen, hydroxyl groups or moisture from being contained in the oxide semiconductor layer.​​

[0403] In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The processing chamber evacuated using a cryopump is, for example, exhausted of compounds containing hydrogen atoms such as water (H 2 O), etc., so that the concentration of impurities contained in the oxide semiconductor layer formed in the processing chamber can be reduced.

[0404] When forming the oxide semiconductor layer, the sputtering gas used is preferably a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to the extent of several ppm to several ppb.

[0405] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably 400°C or higher and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 332 is obtained (see Fig. 22(A)). (see Fig. 22(A)).

[0406] Next, plasma treatment is performed using a gas such as N 2 O, N 2 , or Ar. This plasma treatment removes adsorbed water and the like adhering to the surface of the oxide semiconductor layer exposed by the plasma treatment. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.​​​​​​​

[0407] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. Then, a resist mask is formed by a third photolithography process, and selective etching is performed. After etching is performed to form the oxide insulating layer 366, the resist mask is removed.

[0408] In this embodiment, a silicon oxide layer having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The silicon oxide layer is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen mixture The reaction can be carried out in an atmosphere. The target is a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. The silicon oxide layer can be formed by sputtering in a nitrogen atmosphere.

[0409] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 332 and the oxide insulating layer 366. This is to ensure that it is not included.

[0410] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may be filled with water (H 2 O) etc. Since compounds containing elemental atoms and the like are exhausted, the concentration of impurities contained in the oxide insulating layer 366 formed in the processing chamber can be reduced.

[0411] When forming the oxide insulating layer 366, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrogen compounds are removed to the extent of several ppm to several ppb.

[0412] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in a state of being in contact with the oxide insulating layer 366.

[0413] In this embodiment, the oxide semiconductor layer 332 provided with the oxide insulating layer 366 and having a part exposed is heat-treated in a nitrogen, inert gas atmosphere, or under reduced pressure. When the exposed region of the oxide semiconductor layer 332 not covered by the oxide insulating layer 366 is heat-treated in a nitrogen, inert gas atmosphere, or under reduced pressure, it can be in an oxygen-deficient state and have its resistance reduced, that is, be N-type converted. For example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere.

[0414] By the heat treatment in a nitrogen atmosphere for the oxide semiconductor layer 332 provided with the oxide insulating layer 366, the exposed region of the oxide semiconductor layer 332 has its resistance reduced, and an oxide semiconductor layer 362 having regions with different resistances (indicated by the hatched region and the blank region in FIG. 22(B)) is obtained.

[0415] Next, after forming a conductive layer on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form the source electrode layer 365a and the drain electrode layer 365b, and then the resist mask is removed (see FIG. 22(C)).

[0416] As materials for the source electrode layer 365a and the drain electrode layer 365b, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W, or alloys containing the above-described elements as components, or alloy layers formed by combining the above-described elements may be mentioned. Further, the metal conductive layer may have a single-layer structure or a laminated structure of two or more layers.

[0417] Through the above steps, heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor layer after film formation, and at the same time, the oxide semiconductor layer has a lower resistance, that is, becomes N-type. Then an oxide insulating layer in contact with the oxide semiconductor layer is formed to selectively make a part of the oxide semiconductor layer in an oxygen-excessive state. As a result, the channel formation region 363 overlapping with the gate electrode layer 361 becomes of type I. At this time, at least compared with the channel formation region 363, the carrier density is high, and the high-resistance source region 364a overlapping with the source electrode layer 365a and at least compared with the channel formation region 363, the carrier density is high, and the high-resistance drain region 364b overlapping with the drain electrode layer 365b are self-alignedly formed. The thin-film transistor 3 60 is formed by the above steps.

[0418] Furthermore, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment is constant​​​​​​ It may be heated while maintaining the heating temperature, or the temperature may be increased from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and the temperature may be decreased from the heating temperature to room temperature multiple times. Further, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved.

[0419] In addition, by forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the oxide semiconductor layer that overlaps with the drain electrode layer 365b (and the source electrode layer 365a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 364b, a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 364b and the channel formation region 363. Therefore, when a wiring for supplying a high power supply potential VDD to the drain electrode layer 365b is continuously operated, even if a high electric field is applied between the gate electrode layer 361 and the drain electrode layer 365b, the high-resistance drain region serves as a buffer and local electric field concentration is less likely to occur, and a configuration can be obtained in which the breakdown voltage of the transistor is improved.

[0420] A protective insulating layer 323 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride layer (see FIG. 22(D)).

[0421] Note that an oxide insulating layer may be further formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366, and the protective insulating layer 323 may be laminated on the oxide insulating layer.

[0422] By applying the thin film transistor described above to the transistors included in the logic circuits shown in Embodiments 1 to 6, it is possible to suppress the leakage of electric charges through the thin film transistor. As a result, it becomes possible to reduce the standby power of the logic circuit and suppress malfunction of the logic circuit.

[0423] Note that the content of this embodiment or a part of the content can be freely combined with the content of other embodiments or a part of the content or the content of other examples.

[0424] (Embodiment 11) In this embodiment, an example of a semiconductor device equipped with the logic circuit obtained in the above embodiment will be described with reference to FIG. 23. Note that the logic circuit according to the above embodiment is integrated together with an external circuit or the like that operates the logic circuit and mounted on a circuit board or the like, and will be mounted inside each semiconductor device.

[0425] FIG. 23(A) is a diagram showing a notebook personal computer having the logic circuit described above, which is composed of a main body 2201, a housing 2202, a display unit 2203, a keyboard 2204, and the like.

[0426] FIG. 23(B) is a diagram showing a personal digital assistant (PDA) having the logic circuit described above. The main body 2211 includes a display unit 2213, an external interface 2215, and operation buttons 22 14 etc. are provided. Also, there is a stylus 2212 as an accessory for operation.

[0427] FIG. 23(C) shows an example of an electronic paper having the above-described logic circuit, which is an electronic book 22 20. The electronic book 2220 is composed of two housings, a housing 2221 and a housing 2223. The housing 2221 and the housing 2223 are integrated by a shaft portion 2237 and can be opened and closed about the shaft portion 2237. With such a configuration, the electronic book 2220 can be used like a paper book. A display unit 2225 is incorporated in the housing 2221, and a display unit 2227 is incorporated in the housing 2223.

[0428] The display unit 2225 and the display unit 2227 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, text can be displayed on the right display unit (display unit 2225 in FIG. 23(C)), and an image can be displayed on the left display unit (display unit 2227 in FIG. 23(C)). In FIG. 23(C), an example in which the housing 2221 is provided with an operation unit or the like is shown. For example, the housing 2221 includes a power supply 2231, operation keys 2233, a speaker 2235, etc.

[0429] By operating the operation keys 2233, pages can be turned. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit. Also, on the back or side of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a US B cable), a recording medium insertion portion, etc. may be provided. Furthermore, the electronic book 2220 may be configured to have a function as an electronic dictionary. It may also be possible.

[0430] Also, the e-book 2220 may be configured to be able to wirelessly transmit and receive information. By wireless means it is also possible to purchase and download desired book data etc. from an e-book server. It is also possible.

[0431] In addition, the electronic paper can be applied to any field as long as it can display information. For example, in addition to e-books, it can be applied to posters, in-vehicle advertisements on vehicles such as trains, displays on various cards such as credit cards, etc.

[0432] Figure 23(D) is a diagram showing a mobile phone having the above-described logic circuit. The mobile phone is composed of two housings, a housing 2240 and a housing 2241. The housing 2241 is provided with a display panel 2242, a speaker 2243, a microphone 2244, a pointing device 2246, a camera lens 2247, an external connection terminal 2248, etc. In addition, the housing 2240 is provided with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. Also, the antenna is built inside the housing 2241.

[0433] The display panel 2242 has a touch panel function, and in Figure 23(D), a plurality of operation keys 2245 displayed on the screen are shown by dotted lines. Note that the mobile phone implements a boost circuit for boosting the voltage output by the solar cell 2249 to the voltage required for each circuit. In addition to the above configuration, it is also possible to incorporate a contactless IC chip, a small recording device, etc. into the configuration.

[0434] ​The display panel 2242 can appropriately change the display direction according to the usage mode. Also, since the camera lens 2247 is provided on the same surface as the display panel 2242, video phone is possible. The speaker 2243 and the microphone 2244 can be used not only for voice calls but also for video phone calls, recording, playback, etc. Further, the housing 2240 and the housing 2241 can slide and change from the unfolded state as shown in FIG. 23(D) to the overlapping state, enabling miniaturization suitable for portability.

[0435] The external connection terminal 2248 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, a recording medium can be inserted into the external memory slot 2250 to support the storage and transfer of a larger amount of data. In addition to the above functions, it may also be equipped with an infrared communication function, a TV receiving function, etc.

[0436] FIG. 23(E) is a diagram showing a digital camera having the above-described logic circuit. The digital camera is composed of a main body 2261, a display unit (A) 2267, an eyepiece 2263, an operation switch 2 264, a display unit (B) 2265, a battery 2266, etc.

[0437] FIG. 23(F) is a diagram showing a television apparatus having the above-described logic circuit. In the television apparatus 2270, a display unit 2273 is incorporated in the housing 2271. The display unit 2 273 can display images. Here, a configuration in which the housing 2271 is supported by the stand 2275 is shown.

[0438] The operation of the television apparatus 2270 can be performed by the operation switch provided in the housing 2271 or a separate remote It can be performed by the remote control operation unit 2280. The operation keys -2279 provided in the remote control operation unit 2280 can be used to operate channels and volume, and the video displayed on the display unit 2273 can be operated. Further, the remote control operation unit 2280 may be configured to be provided with a display unit 2277 for displaying information output from the remote control operation unit 2280.

[0439] Note that the television device 2270 is preferably configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. Further, by connecting to a wired or wireless communication network via a modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between receivers) information communication can be performed.

Example

[0440] In this example, the measured value of the off-current in the evaluation element (also referred to as TEG) will be described below.

[0441] In FIG. 24, 200 thin film transistors with L / W = 3 μm / 50 μm are connected in parallel, and effectively shows the initial characteristics of a thin film transistor with L / W = 3 μm / 10000 μm. Also, the top view is shown in FIG. 25(A), and the enlarged top view of a part thereof is shown in FIG. 25(B). The region surrounded by the dotted line in FIG. 25( B) is a thin film transistor for one stage with L / W = 3 μm / 50 μm and Lov = 1.5 μm. To measure the initial characteristics of the thin film transistor, the substrate temperature is set to room temperature, the source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10 V, and the source-gate voltage (hereinafter referred to as gate voltage or Vg) is changed from -20 V to +20 V. ​​​​​The change characteristics of the source-drain current (hereinafter referred to as drain current or Id) when turned on, that is, the Vg-Id characteristics were measured. In FIG. 24, Vg is shown in the range of -20V to +5V. As shown in FIG. 24, for a thin film transistor with a channel width W of 10000 μm, the off-current is 1×10 or less at Vd of 1V and 10V, and the resolution of the measuring instrument (semiconductor

[0442] parameter analyzer, Agilent 4156C; manufactured by Agilent) is 100fA or less. -13 [A] or less. parameter analyzer, Agilent 4156C; manufactured by Agilent) is 100fA or less.

[0443] The manufacturing method of the measured thin film transistor will be described.

[0444] First, as an underlying film on a glass substrate, a silicon nitride layer was formed by CVD method, and a silicon oxynitride layer was formed on the silicon nitride layer. A tungsten layer was formed as a gate electrode layer on the silicon oxynitride layer by sputtering method. Here, the tungsten layer was selectively etched to form the gate electrode layer. electrode layer. electrode layer.

[0445] Next, a silicon oxynitride layer with a thickness of 100 nm was formed as a gate insulating layer on the gate electrode layer by CVD method. Next, a silicon oxynitride layer with a thickness of 100 nm was formed as a gate insulating layer on the gate electrode layer by CVD method.

[0446] Next, an In-Ga-Zn-O based oxide semiconductor target (in molar ratio, In O 2 :Ga 3 O 2 :ZnO = 1:1:2) was used to form an oxide semiconductor layer with a thickness of 5 3 0 nm on the gate insulating layer. Here, the oxide semiconductor layer was selectively etched to form an island-shaped oxide semiconductor layer. 0 nm on the gate insulating layer. Here, the oxide semiconductor layer was selectively etched to form an island-shaped oxide semiconductor layer. island-shaped oxide semiconductor layer.

[0447] Next, the oxide semiconductor layer was subjected to a first heat treatment at 450°C for 1 hour in a nitrogen atmosphere in a clean oven.

[0448] Next, a titanium layer (thickness 150 nm) was formed as a source electrode layer and a drain electrode layer on the oxide semiconductor layer by sputtering. Here, the source electrode layer and the drain electrode layer were selectively etched so that the channel length L of one thin-film transistor was 3 μm and the channel width W was 50 μm, and by arranging 200 in parallel, effectively L / W = 3 μm / 10000 μm was achieved.

[0449] Next, a silicon oxide layer was formed by reactive sputtering as a protective insulating layer with a film thickness of 300 nm so as to be in contact with the oxide semiconductor layer. Here, the silicon oxide layer as the protective layer was selectively etched to form openings on the gate electrode layer, the source electrode layer, and the drain electrode layer. Then, a second heat treatment was performed at 250°C for 1 hour in a nitrogen atmosphere.

[0450] And before measuring the Vg-Id characteristics, heating was performed at 150°C for 10 hours.

[0451] Through the above steps, a bottom-gate type thin-film transistor was fabricated.

[0452] As shown in FIG. 24, the fact that the thin-film transistor is about 1×10[A] is because the hydrogen concentration in the oxide semiconductor layer could be sufficiently reduced in the above fabrication process. The hydrogen concentration in the oxide semiconductor layer is 5×10 (atoms / cm) or less, preferably 5×10 (atoms / cm) or less, more preferably 5×10 -13 19 (atoms / cm 3 ) 18 (atoms / cm 3 ) 17(atoms / cm 3 ) shall be as follows. The hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy).

[0453] In addition, although an example using an In-Ga-Zn-O-based oxide semiconductor is shown, it is not particularly limited, and other oxide semiconductor materials, for example, In-Sn-Zn-O-based, Sn-Ga-Zn-O-based, A l-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, In-Sn-O-based , Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based, etc. can be used. In addition, as the oxide semiconductor material, an In-Al-Zn-O-based material mixed with 2.5 to 10 wt% of AlOx or an In-Zn-O -based material mixed with 2.5 to 10 wt% of SiOx can also be used.

[0454] In addition, the carrier density of the oxide semiconductor layer measured by a carrier measurement instrument is 5×10 14 / cm 3 or less, more preferably 5×10 12 / cm 3 or less, and more preferably equivalent to or less than the intrinsic carrier density of silicon, 1.45×10 10 / cm 3 . That is, the carrier density of the oxide semiconductor layer can be made as close to zero as possible.

[0455] In addition, it is also possible to set the channel length L of the thin film transistor to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit. Since the off-current value is extremely small, further reduction of power consumption can also be achieved.

[0456] Also, in the off state of the thin-film transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be performed.

[0457] Subsequently, the temperature characteristics of the off-current were evaluated for the thin-film transistor fabricated in this example . The temperature characteristics are important in consideration of the environmental resistance of the final product in which the thin-film transistor is used and the maintenance of performance, etc. Naturally, the smaller the change amount, the more preferable, and the degree of freedom in product design increases.

[0458] Regarding the temperature characteristics, using a thermostat, the substrate on which the thin-film transistor was formed at each temperature of -30, 0, 25, 40, 60, 80, 100, and 12 0 °C was set to a constant temperature, and the drain voltage was changed from 6 V and the gate voltage from -20 V to +20 V to obtain the Vg-Id characteristics.

[0459] Fig. 26(A) shows the Vg-Id characteristics measured at each of the above temperatures overlaid, and an enlarged view of the off-current region surrounded by the dotted line is shown in Fig. 26(B). In the figure, the rightmost curve indicated by the arrow is the curve obtained at -30 °C, and the leftmost is the curve obtained at 120 °C, and the curves obtained at other temperatures are located in between. Almost no temperature dependence of the on-current is observed. On the other hand, as is also clear in the enlarged view of Fig. 26(B), except near the gate voltage of 20 V, the off-current is near the resolution of the measuring instrument at all temperatures and is 1 × 10 [A] or less , and no temperature dependence is visible either. That is, even at a high temperature of 120 °C, the off-current is maintained at 1 × 1 0 -12 [A] or less, and considering that the effective channel width W is 10000 μm , it can be seen that the off-current is very small. 0 -12 [A] or less, and considering that the effective channel width W is 10000 μm , it can be seen that the off-current is very small.

[0460] In a thin film transistor using a highly purified oxide semiconductor, the temperature dependence of the off-current hardly appears. This is because the energy gap of the oxide semiconductor is 3 eV or more and the number of intrinsic carriers is extremely small. In addition, since the source region and the drain region are in a degenerate state, this is also a factor that the temperature dependence does not appear. The operation of the thin film transistor is mostly due to carriers injected from the degenerate source region into the oxide semiconductor. Since there is no temperature dependence of the carrier density, the above characteristics (no temperature dependence of the off-current) can be explained.

[0461] When a logic circuit is configured using such a thin film transistor with an extremely small off-current value, the standby power of the logic circuit can be reduced or the malfunction of the logic circuit can be suppressed.

Explanation of symbols

[0462] 10 Logic circuit 11 Input terminal 12 Input terminal 13 Output terminal 14 Main logic circuit section 15 Transistor 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108a Gate insulating layer 108b Insulating layer 110a Gate electrode layer 110b Electrode layer 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulating layer 120a High-concentration impurity region 120b High-concentration impurity region 122 Metal layer 124a Metal compound region 124b Metal compound region 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode layer 130b Drain electrode layer 130c Electrode layer 132 Insulating layer 134 Conductive layer 136a Electrode layer 136b Electrode layer 136c Electrode layer 136d Gate electrode layer 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode layer 142b Drain electrode layer 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a Electrode layer 150b Electrode layer 150c Electrode layer 150d Electrode layer 150e Electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154c Electrode layer 154d Electrode layer 160 Transistor 164 Transistor 200 Logic circuit 201 AND gate 202 Flip-flop 211 Transistor 212 Transistor 213 Transistor 214 Transistor 215 Transistor 216 Transistor 221 Transistor 222 Transistor 223 Transistor 224 Transistor 225 Transistor 231 NAND Gate 232 NAND Gate 233 NAND Gate 234 NAND Gate 241 Transistor 242 Transistor 243 Transistor 244 Transistor 251 Transistor 252 Transistor 253 Transistor 320 Substrate 322 Gate Insulating Layer 323 Protection Insulating Layer 332 Oxide Semiconductor Layer 360 Thin Film Transistor 361 Gate Electrode Layer 362 Oxide Semiconductor Layer 363 Channel Formation Region 364a Source Region 364b Drain Region 365a Source Electrode Layer 365b Drain Electrode Layer 366 Oxide Insulating Layer 390 Thin Film Transistor 391 Gate Electrode Layer 392 Oxide Semiconductor Layer 393 Oxide Semiconductor Layer 394 Substrate 395a Source Electrode Layer 395b Drain Electrode Layer 396 Oxide Insulating Layer 397 Gate Insulating Layer 398 Protection Insulating Layer 399 Oxide Semiconductor Layer 423 Opening 450 Substrate 452 Gate Insulating Layer 457 Insulating Layer 460 Thin film transistor 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 500 Logic circuit 501 NOR gate 502 Flip-flop 511 Transistor 512 Transistor 513 Transistor 514 Transistor 521 Transistor 522 Transistor 523 Transistor 600 Logic circuit 601 Latch 602 Flip-flop 611 Transistor 612 Inverter 613 Inverter 621 Transistor 622 Transistor 631 Transistor 632 Transistor 800 Logic circuit 801 AND gate 802 Flip-flop 803 Flip-flop 804 Flip-flop 805 Flip-flop group 900 Logic circuit 901 Flip-flop 902 AND gate 903 Control unit 904 Flip-flop 905 Flip-Flop 906 Flip-Flop 907 Flip-Flop Group 2201 Main Body 2202 Housing 2203 Display Unit 2204 Keyboard 2211 Main Body 2212 Stylus 2213 Display Unit 2214 Operation Button 2215 External Interface 2220 E-Book 2221 Housing 2223 Housing 2225 Display Unit 2227 Display Unit 2231 Power Supply 2233 Operation Key 2235 Speaker 2237 Shaft Portion 2240 Housing 2241 Housing 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lens 2248 External Connection Terminal 2249 Solar Cell 2250 External Memory Slot 2261 Main Body 2263 Eyepiece 2264 Operation Switch 2265 Display Unit (B) 2266 Battery 2267 Display Unit (A) 2270 Television Set 2271 Housing 2273 Display Unit 2275 Stand 2277 Display Unit 2279 Operation Key 2280 Remote control unit

Claims

[Claim 1] 1. A logic circuit having a first period during which a clock signal is input and a second period during which the clock signal is not input, a transistor that is turned off during the second period while a potential difference exists between a source terminal and a drain terminal; The channel formation region of the transistor has a hydrogen concentration of 5×10 １９ (atoms / cm ３ 2. A logic circuit comprising the following oxide semiconductor:

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