Distributed interleaving control of multi-phase SMPC

Abstract

A controller for a switching mode power converter (SMPC) module for use in a multi-phase SCMP is disclosed, comprising: a signal generator configured to generate a periodic signal and a clock, each having a frequency and a signal phase, for controlling the switching mode power converter module; a first clock input and a second clock input, the first clock input and the second clock input being configured to receive respective first and second clock signals having the frequency and respective first and second phases from an adjacent controller; and wherein the signal generator includes a phase adjustment circuit configured to adjust the phase of the periodic signal to be equidistant from the first and second phases, wherein the phase adjustment circuit determines an error signal based on an offset between the phase and a midpoint between the first and second phases, and a feedback circuit configured to adjust the phase based on the error signal.

Description

Technical Field

[0001] The present invention relates to distributed interleaving control of a multiphase switched-mode power converter (SMPC). More particularly, the present invention relates to a multiphase SMPC, an SMPC module, and a controller for the multiphase SMPC and the SMPC module. The present invention further relates to methods of controlling such an SMPC module and the multiphase SMPC. Background Art

[0002] Multiphase switching mode power converters (SMPCs) are becoming increasingly important for a range of applications. They are particularly suitable for systems that need to be robust against component failures: since power is provided by multiple subunits, a fault or failure in one subunit can be compensated by appropriately adjusting the remaining subunits. Typically, control of such multiphase SMPCs is provided by a central controller. However, such controllers may represent another point of vulnerability or single point of failure (SPOF) in the system, and therefore recently, attention has turned to methods of providing distributed control that tend to reduce or minimize such single point failure vulnerabilities. Cousineau et al. discuss one such approach in U.S. Patent No. 9,608,450. However, there is still a need for simple and robust distributed control. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a controller for a switching mode power converter module for use in a multi-phase switching mode power converter, the controller comprising: a signal generator configured to generate a periodic signal having a frequency and a signal phase and for controlling the switching mode power converter module, wherein the signal generator is further configured to generate a clock signal having the frequency and the signal phase; a first clock input configured to receive a first clock signal having the frequency and the first phase from a first adjacent controller; and a second clock input configured to receive a second clock signal having the frequency and the second phase from a second adjacent controller; wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal to be equidistant from the first phase and the second phase, wherein the phase adjustment circuit comprises an error circuit and a feedback circuit, the error circuit configured to determine an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, the feedback circuit configured to adjust the phase based on the error signal.

[0004] Compared to the analog signals associated with known distributed control methods, the single-bit digital or binary signals that make up the clock signal and are transmitted between adjacent modules are less susceptible to noise. This can improve the design's robustness to noise and also simplify implementation.

[0005] In one or more embodiments, the error circuit includes digital logic for determining an error signal based on a difference between a first value and a second value, the first value being proportional to a phase difference between the signal phase and the first phase, and the second value being proportional to a phase difference between the signal phase and the second phase. Digital logic may be particularly easy to implement.

[0006] In one or more embodiments, the clock signal has a 50% duty cycle. The digital logic may include an XOR combination of the clock signal and the first clock signal to determine the first value, and an XOR combination of the clock signal and the second clock signal to determine the second value. These logic operations enable a very simple and efficient determination of the error signal with minimal signal processing.

[0007] In one or more embodiments, the controller may further include a first clock output and a second clock output, wherein the first clock output and the second clock output are configured to transmit clock signals to the first adjacent controller and the second adjacent controller, respectively, during normal operation. These clock signals can be used by the respective first adjacent controller and the second adjacent controller to determine the appropriate timing for their own clocks.

[0008] In one or more embodiments, the switching-mode power converter module includes at least one switch, and the controller further includes a control module configured to control the at least one switch based on a periodic signal. Thus, the controller may include an interleaver separate from the control module, or the interleaver may be integral to the control module.

[0009] In one or more embodiments, the controller may further include a status indicator indicating a status of the controller, and the controller may further be configured to transmit the first clock signal from the second clock output and the second clock signal from the first clock output in response to the status indicator indicating that the controller is disabled. Providing a status indicator to indicate whether the controller is disabled—whether intentionally or possibly due to a fault in an associated module—can help simplify control in such situations.

[0010] According to a second aspect of the present disclosure, there is provided a switching mode power converter module comprising a controller as described above, at least one switch and an inductive element, wherein the at least one switch is configured to switchably supply current to the inductive element under control of the controller.

[0011] In one or more embodiments, the SMPC module may further include a switch driver circuit connected to an output of the controller and to a control input or each control input of at least one switch, and adapted to drive the at least one switch. The switch driver circuit may be provided separately to the controller, and since the driver typically requires greater current and power than the controller, this may simplify the manufacture of the controller. The control and switch driver circuits may be provided in a packaged multi-chip module, or may be provided in the form of separate chips.

[0012] According to another aspect, the present disclosure provides a multi-phase switching mode power converter, comprising at least three switching mode power converter modules as described above, wherein the respective controllers are arranged in a daisy chain configuration, and the phases of the respective clock signals are evenly distributed. The daisy chain configuration may also be referred to as a ring chain configuration.

[0013] In one or more embodiments, a multi-phase SMPC may include at least one additional switching-mode power converter module, wherein in response to the controller of the at least one additional switching-mode power converter module being deactivated, the phases of the additional switching-mode power converter module are evenly distributed. The additional switching-mode power converter module may be in addition to the at least three switching-mode power converter modules, in which case the additional switching-mode power converter module is the at least three switching-mode power converter modules; alternatively, the additional switching-mode power converter module may be one of the at least three switching-mode power converter modules, in which case the additional switching-mode power converter module is the remainder of the at least three switching-mode power converter modules.

[0014] In one or more embodiments, a multi-phase SMPC may include at least six switching-mode power converter modules, each as described above, arranged into a plurality of subgroups, wherein the respective controllers within each subgroup are arranged in a daisy-chain configuration, and the phases of the respective clock signals within each subgroup are evenly distributed. Thus, in addition to a single daisy chain, more complex architectures may be suitable for some applications. The phase of the clock signal of one of the controllers may be fixed, or, in the case where the controllers are arranged into subgroups, the phase of the clock signal of one of the controllers may be fixed for each subgroup.

[0015] In one or more embodiments, the multi-phase switching mode power converter, the phase of the clock signal of one of the controllers is fixed, or according to the multi-phase switching mode power converter, wherein for each sub-group, the phase of the clock signal of one of the controllers within the sub-group is fixed.

[0016] According to another aspect of the present disclosure, a method for controlling a switching mode power converter module used in a multi-phase switching mode power converter is disclosed, the method comprising: generating a periodic signal having a frequency and a signal phase and used to control the switching mode power converter module; generating a clock signal having the frequency and the signal phase; receiving a first clock signal having the frequency and the first phase from a first adjacent controller; and receiving a second clock signal having the frequency and the second phase from a second adjacent controller; adjusting the phase of the periodic signal to be equidistant from the first phase and the second phase by means of a phase adjustment circuit, wherein adjusting the phase of the periodic signal comprises determining an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, and adjusting the phase based on the error signal by means of a feedback circuit.

[0017] A computer program may be provided that, when executed on a computer, causes the computer to configure any apparatus including the circuits, controllers, sensors, filters, or devices disclosed herein or to perform any method disclosed herein. The computer program may be a software implementation, and the computer may be considered to be any suitable hardware, including a digital signal processor, a microcontroller, and implementations in read-only memory (ROM), erasable programmable read-only memory (EPROM), or electrically erasable programmable read-only memory (EEPROM), as non-limiting examples. The software implementation may be an assembler program.

[0018] The computer program may be provided on a computer readable medium, which may be a physical computer readable medium such as a disk or a memory device, or may be embodied as another non-transitory signal.

[0019] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 A schematic diagram illustrating a control arrangement for a multi-phase switching mode power converter with distributed control according to one or more embodiments;

[0021] Figure 2 schematically depicts a multi-phase SMPC according to one or more embodiments;

[0022] Figure 3 Details of portions of the controller 220 are shown in schematic form according to one or more embodiments;

[0023] Figure 4showing various waveforms associated with the controller;

[0024] Figure 5 shows the use of digital logic to determine the error signal;

[0025] Figure 6 The signal shows an example of a feedback circuit for adjusting the phase of a periodic signal;

[0026] Figure 7 showing details of portions of a controller that implements pass-through according to one or more embodiments; and

[0027] Figure 8 The logical topology of a multi-phase SMPC with several SMPC module groups is shown.

[0028] It should be noted that the drawings are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the various parts of these drawings have been shown by enlarging or reducing them in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0029] Figure 1 A multi-phase SMPC 100 is shown in FIG. SMPC 100 includes a plurality of—in this case, four—SMPC modules 110. The modules are arranged in parallel—that is, they are powered by the same voltage source, Vin, and their current outputs, I1, I2, I3, and I4, are connected in parallel to provide the output of the multi-phase SMPC, Iout, which is smoothed by an output capacitor, Cout. It is known that such a parallel arrangement of SMPC modules results in a low level of ripple, allowing the size of the output capacitor, Cout, to be significantly smaller than that required for a single-phase SMPC.

[0030] Each SMPC module includes an interleaver 120, a control module 125, a switch driver circuit 130, and a converter circuit system 140. The interleaver and control module 125 together form a controller 160. The converter circuit system 140 of each SMPC module can adopt one of several different architectures that will be familiar to skilled artisans. For example, Figure 1The converter circuitry schematically shown for each SMPC module in FIG is a half-bridge converter, in which a half-bridge node switches between a supply voltage and a ground voltage; connected to the half-bridge node is an inductive element 142. The inductive element supplies an output current at a voltage between the supply voltage and ground, with the voltage depending on the mark-space ratio of the half-bridge switching. Similarly, the converter circuitry can include a flyback converter or other topology. Switch driver circuit 130 can drive a single switch 141—for example, in the case of a flyback converter—or multiple switches 141, for example, in the case of a half-bridge converter, where two switches are typically required in each SMPC module.

[0031] The interleaver 120 sends one or more control signals 122 to a control module 125. The control module can be a conventional SMPC controller and provides output signals to a switch driver circuit 130. The form of these control signals depends on the topology of the converter circuitry. Since the present disclosure is not dependent on the particular form of the topology of the converter circuitry 140, the control signals or their specific form are not particularly significant to the present disclosure: the skilled person will understand the required nature of the control signals based on the specific topology.

[0032] However, for a multi-phase SMPC, the control signals from each of the different control modules 125 should have the same frequency to minimize output ripple on lout, where lout is the combined output current from each SMPC module. Furthermore, to minimize ripple, the modules should operate in an interleaved manner—that is, the switching cycles of the corresponding modules should be equally spaced in phase, or in other words, with equal phase shifts between the modules. In the case of four modules, to minimize ripple on the output current lout, the switching cycles should be equally spaced in phase by π / 2, that is, with relative phases of 0, π / 2, π, and 3π / 2.

[0033] In conventional multi-phase SMPCs this requirement is met by providing a centralised controller. The inventors of US patent US9,608,450 describe an alternative arrangement in which the control of each module is local to that module. To achieve this, each module controller generates its own triangular waveform for controlling that module. The controllers are arranged in a logical daisy chain configuration and each local controller transmits its own waveform to its nearest neighbour, that is, to the controller preceding it in the daisy chain and the controller following it in the daisy chain. The authors believe that it is possible to use the triangular waveforms from two neighbouring controllers to adjust the phase of the local triangular waveform to ensure that the phases of the respective modules are equidistantly spaced. This is in Figure 11 and 2. The daisy-chain diagram of FIG1 shows a local controller and a communication link 124. The communication link 124 connects each local controller to its next neighbor and allows the local controller to provide an analog triangular waveform to the neighboring controller in the daisy chain. The communication link 126 connects the local controller to its previous neighbor and allows the local controller to receive an analog triangular waveform from the neighboring controller in front of it in the daisy chain.

[0034] Figure 2 A multi-phase SMPC according to one or more embodiments of the present disclosure is schematically depicted. Figure 2 The multi-phase SMPC shown with Figure 1 The illustrated multi-phase SMPC is similar in that it includes a plurality (in this case, four) of SMPC modules 210, each of which includes a switch driver circuit 130, a converter circuit system 140. Each SMPC module also includes a controller 260, which typically includes an interleaver 220 and a control module 225. However, in this case, the interleaver 220 does not share analog information with its neighbors. As will be discussed in more detail below, instead of transmitting an analog signal, each local interleaver 220 transmits only a one-bit digital signal to its next and previous neighbors. As will become apparent, this one-bit digital signal or binary signal takes the form of a clock signal. The links between adjacent local controllers are Figure 2 2 is depicted as a two-wire link 224. One of these wires will carry a binary signal of the clock state (high or low) of the local controller to the controller preceding it in the daisy chain; the other of the wires will carry a binary signal of the clock state (high or low) of the previous controller to the local controller.

[0035] Figure 3 Details of the interleaver 220 according to one or more embodiments are shown in schematic form. The interleaver includes a signal generator 310, which may include a voltage-controlled oscillator (VCO) 315. Signal generator 310 is configured to generate a periodic signal X 320 having a frequency and a signal phase. As will be discussed further below, periodic signal X is used to control the switching-mode power converter module. Signal generator 220 is further configured to generate a clock signal B 330. The frequency and phase of clock signal 330 are the same as those of periodic signal 320.

[0036] Interleaver 220 includes a first clock input 340 configured to receive a first clock A from a first adjacent interleaver. The first adjacent interleaver is the interleaver preceding the local interleaver in the daisy chain. The frequency of the first clock signal is the same as the frequency of the periodic signal 320 and the clock signal 330. The phase of the first clock signal will generally be different from the phase of the periodic signal 320 and the clock signal B 330.

[0037] Interleaver 220 includes a second clock input C350 configured to receive a second clock signal C from a second adjacent interleaver. The second adjacent interleaver is the interleaver after the local interleaver in the daisy chain. The frequency of the second clock signal is the same as the frequency of periodic signal 320 and clock signal 330. The phase of the second clock signal will generally be different from the phase of periodic signal 320 and clock signal 330.

[0038] Interleaver 220 includes a first clock output 390 and a second clock output 395. First clock output 390 is connected to the previous interleaver in the daisy chain; second clock output 395 is connected to the next interleaver in the daisy chain. Both first clock output 390 and second clock output 395 output clock signal B 330.

[0039] The signal generator includes a phase adjustment circuit 360 configured to adjust the phase of the periodic signal to be equidistant from a first phase and a second phase. The phase adjustment circuit 360 includes an error circuit 370 configured to determine an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, and a feedback circuit 380 configured to adjust the phase based on the error signal.

[0040] Figure 4 Various waveforms associated with the controller 220 are shown. The top three waveforms correspond to three clock signals. Each clock signal has the same frequency and, therefore, the same period T. The middle waveform shows clock signal B 420 generated by the local controller 220. The top waveform shows a first clock signal A 410, which is generated by the previous controller in the daisy chain and received at the first clock input 340. The third waveform shows a second clock signal C 430, which is generated by the next controller in the daisy chain and received at the second clock input 350.

[0041] In steady-state normal operation, the phase of the clock signal B generated by the local controller is midway between the phases of the first clock A and the second clock signal C, which are generated by two adjacent controllers in the daisy chain, such as Figure 4 That is, the phase difference t1 between the first clock signal A and the local clock signal B 420 is equal to the phase difference t2 between the local clock signal B 420 and the second clock signal C.

[0042] Figure 4The bottom four waveforms 440 depicted in FIG. 4 show four non-limiting examples of periodic signals X generated by a signal generator. These non-limiting examples include a decreasing sawtooth X1 442 and an increasing sawtooth X2 444, a symmetrical triangular waveform X3 446, and a sinusoidal regular waveform X4 448. A skilled person will appreciate that other waveforms are also possible, including, for example, a replica of clock signal B 420. The periodic signal X has a period T that corresponds to the cycle period of the SMPC module. Because SMPC modules typically operate at tens of kHz to tens of MHz, rather than hundreds of MHz or GHz, a skilled person will appreciate that a clock signal also having a period T is a relatively 'slow' clock when compared to those commonly used in communications and digital processing circuits.

[0043] The selection of a specific form for waveform 420 depends on the topology of the SMPC module and the specific control scheme used to control the SMPC module. For example, in one or more embodiments utilizing conventional PWM control, a triangular waveform is particularly suitable for easily determining the appropriate switching moments for the SMPC module converter circuitry 140 because the triangular waveform allows the use of a simple comparator associated with a preset level threshold to determine the appropriate switching moments. In other embodiments, such as those utilizing peak current detection or DPWM (digital pulse width modulation), other waveforms may be more appropriate; for example, some control methods require only the correct alignment of the rising edges of the periodic signal.

[0044] As already mentioned, in steady-state normal operation, the phase of the clock signal B generated by the local controller is midway between the phases of the first clock signal A and the second clock signal C of two adjacent controllers in the daisy chain. The phase adjustment circuit 360 determines an error signal with the aid of the error circuit 370, and the feedback circuit 380 is configured to adjust the phase based on the error signal so as to tend to minimize the error signal until the phase is midway between the phases of the adjacent clock signals A and C. The feedback circuit can generally be configured as a feedback loop filter circuit.

[0045] In one or more embodiments, the error circuit includes digital logic for determining an error signal based on a difference between a first value and a second value, wherein the first value is proportional to a phase difference between a signal phase and a first phase, and the second value is proportional to a phase difference between a signal phase and a second phase. Figure 5 The basic principle of this type of error circuit is shown in: Figure 5 Three waveforms 510 , 520 , and 530 are shown at the top, representing the phases of clock signals A, B, and C, respectively, where in this case the phase of clock signal B is later relative to the midpoint between phases A and C.

[0046] Waveforms 540 and 550 illustrate the results of a digital logic "XOR" operation between waveforms A and B, and waveforms B and C, respectively. The resulting waveforms only have a logic "high" during phase shifts corresponding to the phase delays between A and B, and B and C, respectively. Therefore, when these waveforms are "high," the area beneath the waveforms represents the corresponding phase shift (or phase delay). Subtracting waveform 550 from waveform 540, therefore, yields a signal that, when integrated over the entire clock cycle T, represents the mismatch between the phase delays A to B and B to C. This error signal can then be used to adjust the phase of B.

[0047] In summary:

[0048]

[0049] Where T is the length of the SMPC module switching cycle. Therefore, the error signal average is null only when the two phase delays are equal.

[0050] It will be appreciated that this is particularly easy to implement since only digital logic is used to generate the error signal.

[0051] In one or more embodiments, the XOR logic operation can be replaced by other logic operators to have a logic "high" only during the phase shift between A and B and B and C, near the rising edge of the clock or near the falling edge of the clock. This alternative may be useful when the clock signal duty cycle is not 50% or when the clock edge is used as a trigger. Those skilled in the art of multi-phase SMPCs will understand that there are many ways to achieve appropriate interleaving of the clock signal by rising or falling edges.

[0052] The error signal, which may be in the form of an error current Ierror as just described, is used to adjust the phase of the periodic signal with the aid of a feedback circuit. In one or more embodiments, signals 540 and 550 drive a charge pump (controlled current source) to generate current Is. Current Is flows through loop filter circuit 380 to adjust the phase of B and X, such as in a conventional phase-locked loop (PLL).

[0053] Figure 6 An example of such an embodiment is shown in , which operates as follows:

[0054] A first XOR gate 641 generates a signal 540 from the first clock signal A 510 and the local controller clock signal B 520, respectively. Signal 540 operates a switch 640 that connects a current source 645 to an output node 660. A second XOR gate 651 generates a signal 550 from the local controller clock signal B 520 and the second clock signal C 530, respectively. Signal 550 operates a switch 650 that connects a second current source 655 to the output node 660, the second current source 655 being equal in magnitude but opposite in polarity to the current source 645.

[0055] A loop filter circuit 380 according to one or more embodiments is shown in schematic form. Current Is 560 output from output node 660 flows to ground through loop filter 380, which includes resistor 680 and capacitor 685. This loop filter 380 acts as a proportional-integral (PI) compensator. The resulting voltage is fed by link 690 to correct for phase shift of the clock signal of oscillator 315, which can be a voltage-controlled oscillator (VCO). Those skilled in the art of multi-phase SMPCs will appreciate that there are many ways to implement a feedback loop filter, which need not be described herein.

[0056] It will be appreciated that the signal generator 310 can be considered a phase-locked loop circuit. However, instead of a conventional phase-locked loop circuit in which the phase of the generated signal is locked to the phase of a reference signal and there is a fixed or known phase relationship between the reference signal and the generated signal, in an embodiment according to the present disclosure, the phase is locked to the midpoint between the respective phases of two reference signals, the reference signals being the clocks of two adjacent controllers in the logical daisy chain.

[0057] To be fault-tolerant, a multi-phase SMPC should be able to adapt to and adjust to a fault in one of the SMPC modules. While the means for fault detection are not relevant to this disclosure, the controller disclosed herein, according to one or more embodiments, may be adapted to accommodate faults. As described above, during normal operation, the controller for each of the local SMPC modules can optimize the phases between their respective clock signals by interleaving the phases, such that for a multi-phase SMPC having N SMPC modules, the phase difference between adjacent modules in a logical daisy chain is 2π / N. If a fault is detected in one of the modules, the faulty module should be deactivated, and the remaining modules should adjust their phase spacing such that the phase difference between each of the remaining (N-1) operating modules is 2π / (N-1). Furthermore, even in the absence of a fault, it may be necessary to deactivate one or more modules. Specifically, the conversion efficiency of an SMPC module typically decreases as the load on the module decreases, below the optimal load. For example, if the load to be served by the SMPC decreases significantly, the losses associated with operating all modules at the relatively reduced load may be high enough to necessitate deactivating one or more modules to increase the load on the remaining modules. Those skilled in the art of multi-phase SMPCs will appreciate that there are many ways to disable module operation, which need not be described herein.

[0058] However, in order to enable the remaining operating modules to operate normally through distributed control in this situation, a "pass-through" mechanism should be provided for the clock signal.

[0059] Figure 7 This pass-through mechanism is shown in . Figure 7 Detail of a portion of the interleaver 720 according to one or more embodiments is shown. The interleaver 720 is generally Figure 2 The interleaver 220 shown is similar, except that the diagram includes a status indicator 780 and a pass-through circuit 790. The status indicator 780 can be stored, for example, as a flag in a memory within the controller, and specifically within the interleaver as shown, or can be provided by an external signal (not shown). The status indicator 780 indicates whether the SMPC module is disabled. The SMPC module is typically disabled in response to a detected fault, such as a faulty component. The fault detection circuitry can be part of the control module of the SMPC module, can be elsewhere in the controller of the SMPC module, or can be provided externally.

[0060] The interleaver 720 includes a pass-through circuit 790. The pass-through circuit 790 is arranged to transmit the first clock signal A from the second clock output instead of the clock signal B generated by the local module, and to transmit the second clock signal C from the first clock output instead of the clock signal B, in response to a status indicator indicating that the controller is disabled. The effect is to make the interleaver and associated controller transparent to the rest of the system. That is, the multi-phase SMPC will operate in a manner that: the multi-phase SMPC has only N-1 SMPC modules instead of N, and the previous interleaver and controller are directly connected to the next interleaver and controller, thereby shortening the daisy chain and "skipping" the interleaver and controller of the failed module.

[0061] Interleaver 720 achieves this pass-through operation by directing the locally generated clock signal B to a pass-through circuit rather than sending the clock signal B directly to the first and second outputs. The pass-through circuit acts as a multiplexer. Both the first clock input 340 and the second clock input 350 are connected to the pass-through circuit. A status indicator is also connected to the pass-through circuit. In normal operation, that is, when the status indicator does not indicate that the controller including the interleaver is disabled, both the first clock output 390 and the second clock output 395 output clock signal B 330. However, in the event of a module failure or in other states where the status indicator indicates that the controller including the interleaver is disabled, the pass-through circuit connects the first clock input 340 to the second clock output 395 and the second clock input 350 to the first clock output 390.

[0062] The skilled person will appreciate that, given the daisy-chain arrangement of the controllers in the modules of a multi-phase SMPC, it is possible that the phase adjustment circuits of the interleavers in the controllers may not converge to a stable operating state: instead, the phases of the modules may begin to "catch up" with each other. To prevent this, in one or more embodiments, it may be desirable to fix the phase of the clock of one of the controllers. In such embodiments, it may be appropriate to include another communication link between the controllers (not shown) to share information about which controller is acting as the fixed controller. This information can be used in situations where, if the fixed controller fails or is otherwise set to be disabled, one of the other controllers can take over the role of the fixed controller.

[0063] The embodiments described above generally have an arrangement in which the controllers of the modules of a multi-phase SMPC are logically connected in a single daisy-chain configuration, and the modules themselves are connected in parallel, that is, the current outputs from the modules are combined into a single current output. However, the present disclosure extends to other configurations. Figure 8One such logical topology is shown in FIG and includes three modules 810, 820, and 830 arranged as a primary group whose controllers are arranged in a logical daisy chain. Each of these three modules is further arranged with three additional modules to form a secondary group, each secondary group then having a total of four modules and having the controllers arranged in an independent logical daisy chain. Thus, modules 810, 812, 814, and 816 form a first secondary group, modules 820, 822, 824, and 826 form a second secondary group, and finally modules 830, 832, 834, and 836 form a third secondary group.

[0064] As shown, the phases of the primary groups are interleaved. Thus, assuming the phase of module 810 is 0, the phases of the 12 modules will be as follows:

[0065] 810-0; 820-2π / 3; 830-4π / 3;

[0066] 812-π / 2; 822-7π / 6; 832-11π / 6;

[0067] 814-π; 824-5π / 3; 834-π / 3;

[0068] 816-3π / 2; 826-π / 6; 836-5π / 6.

[0069] In this example, the modules themselves may still be arranged in parallel, that is, the output current I from each of the 12 modules i (where i=1 to 12) are combined to provide a single output I OUT Alternatively, but not limited to, the output current I of the modules belonging to the same secondary group i can be arranged in parallel, but the outputs from the groups cannot be combined, that is, in this case there will be three separate outputs: I1 (from i=1, 4, 7 and 10), I2 (from i=2, 5, 8 and 11) and I3 (from i=3, 6, 9 and 12),

[0070] Alternatively, since the phases of the secondary groups are equally spaced, a different phase relationship may be determined for the primary groups - for example the primary groups may all be arranged to have the same phase (0) rather than interleaved phases. A series-parallel arrangement may be more suitable for this application, such that the output currents I1, I4, I7 and I 10 The output currents I2, I5, I8 and I 11 And the output currents I3, I6, I9 and I from the third secondary group 12 Then the phase of each module can be as follows:

[0071] 810-0; 820-0; 830-0;

[0072] 812-π / 2; 822-π / 2; 832-π / 2;

[0073] 814-π; 824-π; 834-π;

[0074] 816-3π / 2; 826-3π / 2; 836-3π / 2.

[0075] Finally, and again without limitation, the above embodiments have been discussed with respect to so-called parallel multi-phase SMPCs. However, the present disclosure extends to so-called multi-level multi-phase SMPCs. Various such topologies exist, such as modular multi-level converter (MMC) SMPCs and flying capacitor (FC) SMPCs, which are typically used for high-power applications ranging from kW to MW.

[0076] The multi-level SMPCs are connected in series with a given number of SMPCs under the control of the controller, and the SMPCs supply current to the inductive element. As disclosed above, these series SMPCs in the multi-level converter can use appropriate interleaving to reduce the current ripple fed to the inductive element.

[0077] Thus, in one or more embodiments, the controller including the interleaver or the SMPC modules of the multi-level SMPC are logically connected in a single daisy-chain configuration, while the converter circuitry of the SMPC itself is connected in parallel. A skilled person will appreciate that such a parallel arrangement of multi-level converters results in a low level of ripple, making the size of the output capacitor Cout significantly smaller than that required for a single multi-level converter.

[0078] For example, Figure 8 The secondary groups shown can correspond to multilevel converters, where each module corresponds to an SMPC. The current outputs of these multilevel converters can be connected in parallel to provide the output Iout, as described above. This parallel arrangement of multilevel converters results in a low level of ripple, making the size of the output capacitor Cout significantly smaller than that required for a single multilevel converter. In this case, the primary groups are typically interleaved.

[0079] A three-phase alternating current (AC) electric power system requires a converter with three outputs, where each output is connected to an AC phase. The size of the output can be scaled to the size of the AC phase used. In one or more embodiments, Figure 8Each of the secondary groups shown can correspond to a multi-phase SMPC, a multi-level SMPC, or a multi-level multi-phase SMPC connected to an AC phase. In this type of application, the primary groups can all be set to have the same phase to reduce current ripple or the size of the output filter components.

[0080] The present disclosure further extends to a signal interleaving unit comprising: a signal generator configured to generate a periodic signal having a frequency and a signal phase, wherein the signal generator is configured to generate a clock signal having a frequency and a signal phase; a first clock input configured to receive a first clock signal having a frequency and a first phase from a first adjacent controller; and a second clock input configured to receive a second clock signal having a frequency and a second phase from a second adjacent controller; wherein the signal generator includes a phase adjustment circuit configured to adjust the phase of the periodic signal so that the first phase and the second phase are equidistant, wherein the phase adjustment circuit includes an error circuit and a feedback circuit, the error circuit being configured to determine an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, and the feedback circuit being configured to adjust the phase based on the error signal. In other words, the signal interleaving unit includes some functionality of the controller disclosed in other embodiments and discussed above, but in practice the controller is not necessarily from the switching-mode power converter module.

[0081] In one or more embodiments, the error circuit includes digital logic for determining an error signal based on a difference between a first value and a second value, wherein the first value is proportional to a phase difference between the signal phase and the first phase, and the second value is proportional to a phase difference between the signal phase and the second phase.

[0082] By reading this disclosure, the skilled person will understand other variations and modifications. Such variations and modifications may involve equivalent features and other features known in the art of multi-phase switching mode power converters, and the equivalent features and other features may be used instead of or in addition to the features already described herein.

[0083] Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features or any generalization of the novel features disclosed herein, whether or not the novel feature relates to the same invention as the present invention currently claimed in any claim or whether the novel feature alleviates any or all of the same technical problems as the technical problems alleviated by the present invention.

[0084] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for the sake of brevity may also be provided separately or in any suitable subcombination. Applicants hereby caution that new claims may be formulated during prosecution of this application or any further application derived therefrom to such features and / or combinations of such features.

[0085] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfil the functions of several components recited in the claims, and reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A controller (260) for a switching mode power converter module used in a multi-phase switching mode power converter, characterized in that The controller includes: a signal generator (330) configured to generate a periodic signal (X) having a frequency and a signal phase for controlling the switching mode power converter module, wherein the signal generator is further configured to generate a clock signal (B) having the frequency and the signal phase; a first clock input (340) configured to receive a first clock signal (A) having the frequency and first phase from a first adjacent controller; and a second clock input (350) configured to receive a second clock signal (B) having the frequency and second phase from a second adjacent controller; wherein the signal generator comprises a phase adjustment circuit (360) configured to adjust the phase of the periodic signal to be equidistant from the first phase and the second phase, The phase adjustment circuit includes an error circuit (370) and a feedback circuit (380), wherein the error circuit (370) is configured to determine an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, and the feedback circuit (380) is configured to adjust the phase based on the error signal.

2. The controller according to claim 1, characterized in that The error circuit includes digital logic for determining the error signal based on a difference between a first value and a second value, the first value being proportional to a phase difference between the signal phase and the first phase, and the second value being proportional to a phase difference between the signal phase and the second phase.

3. The controller according to claim 1 or 2, characterized in that: The clock signal has a duty cycle of 50%.

4. The controller according to claim 1 or 2, characterized in that: Additionally included are a first clock output and a second clock output configured to transmit the clock signal to a first adjacent controller and a second adjacent controller, respectively, during normal operation.

5. The controller according to claim 1 or 2, characterized in that: The switching mode power converter module includes at least one switch, and the controller further includes a control module (125) configured to control the at least one switch according to the periodic signal.

6. The controller according to claim 1 or 2, characterized in that: Also included is a status indicator (780) indicating a status of the controller, and wherein the controller is further configured to transmit the first clock signal from the second clock output and the second clock signal from the first clock output in response to the status indicator indicating that the controller is disabled.

7. A switching mode power converter module, characterized in that: The device comprises a controller according to any one of claims 1 to 6, at least one switch, and an inductive element, wherein the switch is configured to switchably supply current to the inductive element under control of the controller.

8. A multi-phase switching mode power converter, characterized in that: At least three switching mode power converter modules are respectively included according to claim 7, wherein the respective controllers are arranged in a daisy chain configuration, and the phases of the respective clock signals are evenly distributed.

9. A multi-phase switching mode power converter, characterized in that: The method comprises at least six switching mode power converter modules according to claim 7, which are arranged into a plurality of subgroups, wherein the respective controllers within each subgroup are arranged in a daisy chain configuration, and the phases of the respective clock signals within each subgroup are evenly distributed.

10. A method for controlling a switching mode power converter (SMPC) module used in a multi-phase SMPC, characterized in that: The method comprises: generating a periodic signal having a frequency and a signal phase for controlling the switching mode power converter module; generating a clock signal having said frequency and said signal phase; receiving a first clock signal having the frequency and a first phase from a first adjacent controller, wherein the first adjacent controller is a controller of another SMPC module of the multi-phase SMPC; and receiving a second clock signal having the frequency and a second phase from a second adjacent controller, wherein the second adjacent controller is a controller of another SMPC module of the multi-phase SMPC; adjusting the phase of the periodic signal to be equidistant from the first phase and the second phase by means of a phase adjustment circuit, Adjusting the phase of the periodic signal includes determining an error signal based on an offset between the phase and a midpoint between the first phase and the second phase, and adjusting the phase based on the error signal by means of a feedback circuit.

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