Storage device

Abstract

To provide a semiconductor device with a novel structure, in which a memory content can be held even in a situation with no power supply in a memory holding period, and the number of times of writing is not limited.SOLUTION: A semiconductor device includes a first transistor including a first channel formation region including a semiconductor material other than an oxide semiconductor, a second transistor including a second channel formation region including an oxide semiconductor material over the first transistor, and a capacitor element. One of a second source electrode and a second drain electrode of the second transistor is connected electrically to one electrode of the capacitor element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile types, which retain their memory contents even if the power supply is cut off, and non-volatile types, which retain their memory contents even if the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, when information is read from a DRAM, the charge on the capacitor is lost. Every time information is read, a write operation is required again. A leakage current exists in the transistor, and charge flows out even when the transistor is not selected. Therefore, the data retention period is short. Refresh operations are required, making it difficult to sufficiently reduce power consumption. In addition, if the power supply is cut off, the memory contents are lost, so magnetic recording is necessary for long-term memory retention. Therefore, alternative storage devices using electrical and optical materials are needed.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. For retention, a refresh operation is not required, which is advantageous over DRAM in this regard. However, since circuits such as flip - flops are used, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the fact that the stored content is lost when the power supply is cut off, there is no difference from DRAM.

[0006] A representative example of a non - volatile memory device is a flash memory. The flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi - permanent), and it has the advantage that the refresh operation required for volatile memory devices is not necessary (see, for example, Patent Document 1).

[0007] However, since the gate insulating layer constituting the memory element deteriorates due to the tunneling current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. To mitigate the influence of this problem, for example, a technique for equalizing the number of write operations of each memory element is adopted. However, to achieve this, complex peripheral circuits are required. Thus, even if such a technique is adopted, the fundamental problem of lifespan is not solved. That is, flash memory is not suitable for applications where the information rewrite frequency is high.

[0008] Also, to hold charges in the floating gate or to remove those charges, a high voltage is required, and a circuit for that is also required. Furthermore, it takes a relatively long time to hold or remove charges, and there is also a problem that it is not easy to speed up writing and erasing. ​

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, it is possible to retain the stored content even in a situation where no power is supplied during the memory retention period, and there is no limitation on the number of write operations. One of the objectives is to provide a semiconductor device with a new structure.

Means for Solving the Problems

[0011] In the disclosed invention, a semiconductor device is configured using a highly purified oxide semiconductor. A transistor configured using a highly purified oxide semiconductor has an extremely small leakage current, so it is possible to retain information over a long period of time.

[0012] One aspect of the disclosed invention includes a first channel formation region in which a semiconductor material other than an oxide semiconductor is used, an impurity region provided so as to sandwich the first channel formation region, a first gate insulating layer on the first channel formation region, a first gate electrode on the first gate insulating layer, a first source electrode and a first drain electrode electrically connected to the impurity region, a first transistor having the above components, a second source electrode and a second drain electrode above the first transistor, a second channel formation region electrically connected to the second source electrode and the second drain electrode and in which an oxide semiconductor material is used, and a second gate insulating layer on the second channel formation region. ​​​​​​​​​​ A second transistor having a first gate insulating layer and a second gate electrode on the second gate insulating layer, and a capacitor element, wherein one of the second source electrode or the second drain electrode of the second transistor and one of the electrodes of the capacitor element are electrically connected. In the above, the capacitor element can be composed of one of the second source electrode or the second drain electrode, the second gate insulating layer, and an electrode for the capacitor element on the second gate insulating layer. Also, in the above, a third source electrode and a third drain electrode above the first transistor, a third channel formation region electrically connected to the third source electrode and the third drain electrode and using an oxide semiconductor material, a third gate insulating layer on the third channel formation region, and a third gate electrode on the third gate insulating layer, a third transistor having, a source line, a bit line, a word line, a first signal line, and a second signal line, wherein the third gate electrode, one of the second source electrode or the second drain electrode, and one of the electrodes of the capacitor element are electrically connected, the source line and the third source electrode are electrically connected, the bit line and the third drain electrode are electrically connected, the first signal line and the other of the second source electrode or the second drain electrode are electrically connected, the second signal line and the second gate electrode are electrically connected, and the word line and the other of the electrodes of the capacitor element are electrically connected.

[0013] In the above, the first transistor can form a logic circuit (arithmetic circuit) or a drive circuit. .

[0014] Furthermore, in the above, the third source electrode and the third drain electrode above the first transistor, a third channel formation region electrically connected to the third source electrode and the third drain electrode and using an oxide semiconductor material, a third gate insulating layer on the third channel formation region, and a third gate electrode on the third gate insulating layer, a third transistor having, a source line, a bit line, a word line, a first signal line, and a second signal line, wherein the third gate electrode, one of the second source electrode or the second drain electrode, and one of the electrodes of the capacitor element are electrically connected, the source line and the third source electrode are electrically connected, the bit line and the third drain electrode are electrically connected, the first signal line and the other of the second source electrode or the second drain electrode are electrically connected, the second signal line and the second gate electrode are electrically connected, and the word line and the other of the electrodes of the capacitor element are electrically connected. In the above, the first transistor can form a logic circuit (arithmetic circuit) or a drive circuit.

[0015] In the above, the first transistor can form a logic circuit (arithmetic circuit) or a drive circuit. ​​​​​​​​​​​

[0016] In addition, in this specification and the like, terms such as "upper" and "lower" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer" components other than the gate insulating layer and the gate electrode are not excluded. Also, the terms "upper" and "lower" are merely expressions used for convenience of explanation, and unless otherwise specifically mentioned, they also include those with their upper and lower reversed.

[0017] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0018] Also, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0019] In addition, in this specification and the like, "electrically connected" includes cases where they are connected through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0020] For example, "something having some electrical effect" includes electrodes, wirings, and transistors ​​Switching elements such as, resistive elements, inductors, capacitors, and other elements having various functions are included.

Advantages of the Invention

[0021] In one aspect of the present invention, there is provided a semiconductor device related to a stacked structure of a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor.

[0022] Since the transistor using an oxide semiconductor has an extremely small off-current, it is possible to hold the stored content for an extremely long period of time by using this transistor. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when power supply is not provided, it is possible to hold the stored content for a long time.

[0023] In addition, in the semiconductor device according to the disclosed invention, a high voltage is not required for writing information, and there is no problem of deterioration of elements. For example, unlike a conventional nonvolatile memory, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as deterioration of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which has been a problem in conventional nonvolatile memories, and the reliability is dramatically improved. Further, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information is unnecessary.

[0024] In addition, the transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed. By using this, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation ) can be preferably realized.

[0025] In this way, by providing a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor integrally, a semiconductor device having unprecedented characteristics can be realized.

Brief Description of the Drawings

[0026]

Figure 1

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Figure 17

Embodiment for Carrying Out the Invention

[0027] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiment shown below.

[0028] Note that the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

[0029] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0030] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 5. In the circuit diagram, the symbol OS may be attached together to indicate that it is a transistor using an oxide semiconductor.

[0031] 〈Outline of the Configuration of the Semiconductor Device〉 FIG. 1 is a conceptual diagram showing an example of the configuration of a semiconductor device. A semiconductor device according to one aspect of the disclosed invention typically has a memory circuit at the upper part and a logic circuit (also referred to as an arithmetic circuit) and a drive circuit that require high-speed operation at the lower part, and is a semiconductor device having a stacked structure.

[0032] ​​​​​​ The semiconductor device shown in FIG. 1 has a memory cell array 10 at the upper part and, at the lower part, a column decoder 20, a row decoder 30, an IO controller 40, an IO buffer 50, a command buffer 60, an address buffer 70, a controller 80, and other drive circuits, such as a semiconductor device ( memory device). At the lower part, it may have an arithmetic circuit such as a CPU. Here, although a memory device is shown as an example of the semiconductor device, one aspect of the disclosed invention is not limited to this.

[0033] 〈Cross-sectional configuration of the semiconductor device〉 FIG. 2 is a cross-sectional view showing an example of the specific configuration of the semiconductor device. In FIG. 2(A), the cross-section of the semiconductor device according to the first example is shown, and in FIG. 2(B), the cross-section of the semiconductor device according to the second example is shown, respectively. The semiconductor devices shown in FIGS. 2(A) and 2(B) have transistors (transistor 170 or transistor 570) using materials other than oxide semiconductors at the lower part and have transistors 162 using oxide semiconductors and capacitor elements 164 at the upper part. Transistors using materials other than oxide semiconductors are easy to operate at high speed and are used in logic circuits (also referred to as arithmetic circuits), etc. On the other hand, transistors using oxide semiconductors are used in memory circuits that utilize their characteristics. It should be noted that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can also be used. Also, since the technical essence of the disclosed

[0034] invention lies in using an oxide semiconductor for transistor 162 to hold information, there is no need to limit the specific configuration of the semiconductor device shown here. ​​​​​

[0035] The transistor 170 in Fig. 2(A) includes a semiconductor material (e.g., silicon, etc.). A channel formation region 116 provided on a substrate 100, and impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108 provided on the channel formation region 116, a gate electrode 110 provided on the gate insulating layer 108, a source electrode or drain electrode 130a that is electrically connected to the impurity region, and a source electrode or drain electrode 130b are provided. Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from a direction perpendicular to the surface, there is a high-concentration impurity region 120, and a metal compound region 124 that contacts the high-concentration impurity region 120 exists. Further, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 170, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 170. The source electrode or drain electrode 130a, and the source electrode or drain electrode 130b

[0036] are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 12 8. That is, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130 b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. For the integration of the transistor 170, etc., the sidewall insulating layer 118 is provided, and for the integration of the transistor 170, etc., the sidewall insulating layer 118 is provided. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from a direction perpendicular to the surface, there is a high-concentration impurity region 120, and a metal compound region 124 that contacts the high-concentration impurity region 120 exists. Further, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 170, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 170. The source electrode or drain electrode 130a, and the source electrode or drain electrode 130b are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 12 8. That is, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130 b are electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 124. Note that for the integration of the transistor 170, etc., the sidewall The loop insulating layer 118 may not be formed.

[0037] The transistor 570 in FIG. 2(B) includes a channel formation region 534 provided in a layer containing a semiconductor material (e.g., silicon, etc.) on the nitrogen-containing layer 502 and the oxide film 512, a low-concentration impurity region 532 and a high-concentration impurity region 530 (collectively also simply referred to as the impurity region) provided so as to sandwich the channel formation region 534, a gate insulating layer 522a provided on the channel formation region 534, a gate electrode 524 provided on the gate insulating layer 522a, a source electrode or a drain electrode 540a that is electrically connected to the impurity region, and a source electrode or a drain electrode 540b.

[0038] Here, a sidewall insulating layer 528 is provided on the side surface of the gate electrode 524. In addition, a high-concentration impurity region 530 is provided in a region of the base substrate 500 that does not overlap with the sidewall insulating layer 528 when viewed from a direction perpendicular to the surface. Also, an interlayer insulating layer 536 and an interlayer insulating layer 538 are provided to cover the transistor 570. The source electrode or the drain electrode 540a and the source electrode or the drain electrode 540b are electrically connected to the high-concentration impurity region 530 through openings formed in the interlayer insulating layer 536 and the interlayer insulating layer 538. Note that the sidewall insulating layer 528 may not be formed for the integration of the transistor 570 or the like.

[0039] The transistor 162 in FIGS. 2(A) and 2(B) includes a source electrode or a drain electrode 142a provided on the insulating layer 138, and a source electrode or a drain electrode 142 b, the source electrode or drain electrode 142a, and the source electrode or drain electrode 1 42b are electrically connected to the oxide semiconductor layer 144, and the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and the gate insulating layer 146 that covers the oxide semiconductor layer 144 are provided so as to overlap the oxide semiconductor layer 144 on the gate insulating layer 146 and the gate electrode 148a.

[0040] Here, it is desirable that the oxide semiconductor layer 144 is highly purified by sufficiently removing impurities such as hydrogen, and also by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / c m 3 or less, desirably 5×10 18 atoms / cm 3 or less, more desirably 5×10 1 7 atoms / cm 3 or less. The hydrogen concentration in the above-mentioned oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS). In this way, in the oxide semiconductor layer 144 where the hydrogen concentration is sufficiently reduced and highly purified, and the defect levels in the energy gap caused by oxygen deficiency are reduced by supplying sufficient oxygen, the carrier concentration is less than 1×10 / cm 12 12 / cm 3 less than, preferably less than 1×10 11 / cm 3 less than, more desirably less than 1.45×10 10 / cm 3 For example, the off-current density at room temperature (the off-current divided by the channel width of the transistor) The value) is from 10 zA / μm to 100 zA / μm (1 zA (zeptoampere) is 1×10 -2 1 A). Thus, by using an i-type (true-type) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained. In the transistor 162 of FIG. 2, since the oxide semiconductor layer 144 is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented.

[0041] In the transistor 162 of FIG. 2, since the oxide semiconductor layer 144 is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented. In the transistor 162 of FIG. 2, since the oxide semiconductor layer 144 is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented.

[0042] The capacitor element 164 is composed of a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146, and an electrode 148b. That is, the source electrode or the drain electrode 142a functions as one electrode of the capacitor element 164, and the electrode 148b functions as the other electrode of the capacitor element 164. In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured. In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured. In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured.

[0043] In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured. In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured. In the capacitor element 164 of FIG. 2, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured.

[0044] In the transistor 162 and the capacitor element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably in a tapered shape. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle refers to the angle when a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) is observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate). In the transistor 162 and the capacitor element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably in a tapered shape. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle refers to the angle when a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) is observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate). In the transistor 162 and the capacitor element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably in a tapered shape. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle refers to the angle when a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) is observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate). In the transistor 162 and the capacitor element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably in a tapered shape. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle refers to the angle when a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) is observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate). layer having a tapered shape (for example, the source electrode or the drain electrode 142a) is observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate).​ It shows the inclination angle formed by the side surface and the bottom surface of the layer. By making the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b have a tapered shape, the coverage of the oxide semiconductor layer 144 can be improved, and step discontinuities can be prevented.

[0045] Also, an interlayer insulating layer 150 is provided over the transistor 162 and the capacitor element 164, and an interlayer insulating layer 152 is provided over the interlayer insulating layer 150.

[0046] <Example of Modification of Semiconductor Device> FIG. 3 is a cross-sectional view showing a modified example of the configuration of a semiconductor device. FIG. 3(A) shows a cross-section of a semiconductor device according to a first modified example, and FIG. 3(B) shows a cross-section of a semiconductor device according to a second modified example. Note that the semiconductor devices shown in FIGS. 3(A) and 3(B) both correspond to modified examples of the configuration shown in FIG. 2(A).

[0047] The difference between the semiconductor device shown in FIG. 3(A) and the semiconductor device shown in FIG. 2(A) is whether or not an insulating layer 132 and an insulating layer 134 are provided between the interlayer insulating layer 128 and the insulating layer 138. Here, silicon nitride doped with hydrogen is used for the insulating layer 132, and silicon nitride without hydrogen doping is used for the insulating layer 134. Also, it is desirable that the insulating layer 138 uses silicon oxide.

[0048] By adopting such a configuration having an insulating layer 132 made of silicon nitride doped with hydrogen in the lower layer and an insulating layer 134 made of silicon nitride without hydrogen doping in the upper layer, hydrogen can be added to the material (e.g., silicon) constituting the channel formation region 116 of the transistor 170. In addition, the characteristics of the transistor 170 are improved by supplying the Preventing hydrogen, which causes deterioration of the characteristics of the transistor 162, from entering the oxide semiconductor layer 144 The insulating layer 132 made of hydrogen-added silicon nitride can be formed by plasma. It can be formed by a method such as a CVD method. Also, silicon nitride without hydrogen added can be used. The insulating layer 134 made of copper can be formed by a sputtering method or the like. In this case, for example, the deposition atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon. The sputtering target may be silicon that does not contain hydrogen.

[0049] The difference between the semiconductor device shown in FIG. 3B and the semiconductor device shown in FIG. 2A is the interlayer insulation. The difference is whether or not there is an insulating layer 134 between the edge layer 128 and the insulating layer 138. The layer 134 is made of silicon nitride to which hydrogen is not added. The interlayer insulating layer 128 and the insulating layer 138 are made of silicon nitride to which hydrogen is added. It is preferable that the insulating layer 100 be made of silicon oxide.

[0050] In this way, the interlayer insulating layer 126 is made of hydrogen-doped silicon nitride. By adopting a configuration having an insulating layer 134 made of silicon nitride that is not Hydrogen is supplied to the material (e.g., silicon) constituting the channel forming region 116 of the stadium 170. In addition, the characteristics of the transistor 170 can be improved. To prevent hydrogen, which causes deterioration of the characteristics of the capacitor 162, from being mixed into the oxide semiconductor layer 144. The interlayer insulating layer 126 made of silicon nitride to which hydrogen is added can be etched by plasma C. It can be formed by the VD method or the like. Further, silicon nitride without hydrogen added The insulating layer 134 made of can be formed by a sputtering method or the like. In this case , for example, the film formation atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon, and for sputtering As the target, silicon containing no hydrogen may be used.

[0051] 〈Modification examples of the upper transistor and capacitor element〉 Next, modification examples of the upper transistor 162 and capacitor element 164 in FIG. 2 are shown in FIG. 4 as follows.

[0052] The transistor and capacitor element shown in FIG. 4(A) are one of the modification examples of the upper transistor and capacitor element of the semiconductor device in FIG. 2 .

[0053] The difference between the configuration shown in FIG. 4(A) and the configuration shown in FIG. 2 is that the oxide semiconductor layer is formed in an island shape . That is, in the configuration shown in FIG. 2, the oxide semiconductor layer 144 covers the entire insulating layer 138, the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b . In contrast, in the configuration shown in FIG. 4(A), the island-shaped oxide semiconductor layer 144 covers a part of the insulating layer 138, the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b. Here, the end portion of the island-shaped oxide semiconductor layer 144 is preferably in a tapered shape. The taper angle is preferably, for example, 30° or more and 60° or less.

[0054] Further, in the capacitor element 164, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146 , the insulation between the source electrode or drain electrode 142a and the electrode 148b can be sufficiently ensured.

[0055] The transistor and capacitor element shown in FIG. 4(B) are one of the modified examples of the transistor and capacitor element on the upper part of the semiconductor device in FIG. 2.

[0056] The difference between the configuration shown in FIG. 4(B) and the configuration shown in FIG. 2 is that the insulating layer 143 is formed on the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b. Further, the oxide semiconductor layer 144 is formed so as to cover the insulating layer 143, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b. Also, the oxide semiconductor layer 144 is provided in contact with the source electrode or the drain electrode 142a through an opening provided in the insulating layer 143.

[0057] By having the insulating layer 143, the capacitance formed between the gate electrode and the source electrode or the drain electrode is reduced, and the speed of the transistor operation can be increased.

[0058] The transistor and capacitor element shown in FIG. 4(C) have a configuration partially different from the transistor and capacitor element in FIG. 4(A) and FIG. 4(B).

[0059] The difference between the configuration shown in FIG. 4(C) and the configuration shown in FIG. 4(A) is that the insulating layer 143 is formed on the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b. Further, the oxide semiconductor layer 144 is formed so as to cover the insulating layer 143, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b. Also, the difference between the configuration shown in FIG. 4(C) and the configuration shown in FIG. 4(B) ​​​​​​​​ lies in that the oxide semiconductor layer 144 is formed in an island shape. With this configuration, the effects in the configuration of FIG. 4(A ) and the effects in the configuration of FIG. 4(B) can be obtained together.

[0060] <Circuit Configuration and Operation of Semiconductor Device> Next, an example of the circuit configuration of the above semiconductor device and its operation will be described. FIG. 5 is an example of a circuit configuration using the semiconductor device shown in FIG. 2 .

[0061] In the semiconductor device shown in FIG. 5(A-1), the first wiring (also called the 1st Line: source line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (also called the 2n d Line: bit line) and the drain electrode of the transistor 160 are electrically connected. Also, the third wiring (also called the 3rd Line: first signal line) and one of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (also called the 4th Line: second signal line) and the gate electrode of the transistor 162 are electrically connected. And the gate electrode of the transistor 160 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected to one of the electrodes of the capacitor element 164, and the fifth wiring (also called the 5th Line: word line) and the other electrode of the capacitor element 164 are electrically connected. Here, the transistors 160 and 162 are applied with the transistors using the above-described oxide semiconductor. The transistors using the above-described oxide semiconductor have the characteristic that the off-current is extremely small. For this reason, when the transistor 162 is turned off

[0062] Here, the transistors 160 and 162 are applied with the transistors using the above-mentioned oxide semiconductor. The transistors using the above-mentioned oxide semiconductor have the characteristic that the off-current is extremely small. Therefore, when the transistor 162 is in the off state Thus, the potential of the gate electrode of the transistor 160 can be held for an extremely long time. And, by having the capacitive element 164, it becomes easy to hold the charge applied to the gate electrode of the transistor 160, and it also becomes easy to read the held information. Note that since the transistor 162 using an oxide semiconductor has a channel length (L) of 10 nm or more and 1000 nm or less, it has characteristics of low power consumption and extremely high operation speed.

[0063] In the semiconductor device shown in FIG. 5(A-1), by taking advantage of the characteristic that the potential of the gate electrode of the transistor 160 can be held, writing, holding, and reading of information can be performed as follows.

[0064] First, writing and holding of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitive element 1 64. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (writing). Here, it is assumed that either of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off. By doing so, the charge applied to the gate electrode of the transistor 160 is held (held). Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is held for a long time.

[0065] ​

[0066] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring in a certain state, the second wiring takes on different potentials according to the amount of charge held in the gate electrode of transistor 160. Generally, when transistor 160 is an n-channel type, the apparent threshold value V when a high-level charge is applied to the gate electrode of transistor 160 is lower than the apparent threshold value V when a low-level charge is applied to the gate electrode of transistor 160. This is because here, the apparent threshold voltage refers to the potential of the fifth wiring necessary to turn transistor 160 "on". Therefore, by setting the potential of the fifth wiring to an intermediate potential V between V th_H and V the charge applied to the gate electrode of transistor 160 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring is V th_L (>V ), transistor 160 will be in the "on state". If a low-level charge was applied, even when the potential of the fifth wiring is V (<V ), transistor 160 will remain in the "off state". Thus, by observing the potential of the second wiring, the stored information can be read. th_H and V th_L and setting it to an intermediate potential V 0 of transistor 160. For example, in writing, when a high-level charge was applied, if the potential of the fifth wiring is V (>V ), transistor 160 will be in the "on state". When a low-level charge was applied, even if the potential of the fifth wiring is V 0 (>V th_H ), transistor 160 will remain in the "off state". Therefore, by observing the potential of the second wiring, the stored information can be read. When a low-level charge is applied, even if the potential of the fifth wiring is V (<V 0 (<V th_L ), transistor 160 remains in the "off state". Thus, by observing the potential of the second wiring, the stored information can be read. For this reason, by observing the potential of the second wiring, the stored information can be read. read.

[0067] Note that when memory cells are arranged and used in an array, only the information of the desired memory cell In this way, it is necessary to read the information of a specific memory cell and To prevent the information in other memory cells from being read, a transistor is placed between each memory cell. 60 are connected in parallel, the first memory cell that is not the object of reading For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H A smaller potential can be applied to each memory cell. When the transistors 160 are connected in series between the inputs, the For the fifth wiring of the memory cell that does not have a gate electrode, the transistor 1 The potential at which 60 is in the "on state," that is, V th_L The larger potential is applied to the fifth wire. should be given to

[0068] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are now given a charge related to the new information.

[0069] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. The erasing operation is unnecessary, and it is possible to suppress a decrease in the operation speed caused by the erasing operation. That is, high-speed operation of the semiconductor device is realized.

[0070] Note that the source electrode or drain electrode of the transistor 162 is electrically connected to the gate electrode of the transistor 160, so that it functions equivalently to the floating gate of a floating gate type transistor used as a non-volatile memory element. Therefore, in the figure, the portion where the source electrode or drain electrode of the transistor 162 is electrically connected to the gate electrode of the transistor 160 may be referred to as a floating gate portion FG. When the transistor 162 is off, the floating gate portion FG can be regarded as being embedded in an insulator, and charges are held in the floating gate portion FG. The off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of silicon or the like. Therefore, it is possible to ignore the disappearance of the charges accumulated in the floating gate portion FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile memory device using the transistor 162 using an oxide semiconductor. For example, when the off-current density of the transistor 162 at room temperature is about 10 zA (1 zA (zeptoampere) is 1×10 A)) and the capacitance value of the capacitor element 164 is about 1 pF, data can be retained for at least 10 seconds or more. Note that it goes without saying that the retention time varies depending on the transistor characteristics and capacitance value. Of course, the holding time varies depending on the transistor characteristics and capacitance value. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of silicon or the like, it is possible to ignore the disappearance of the charges accumulated in the floating gate portion FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile memory device using the transistor 162 using an oxide semiconductor. That is, a non-volatile memory device can be realized by the transistor 162 using an oxide semiconductor. That is, a non-volatile memory device can be realized by the transistor 162 using an oxide semiconductor.

[0071] For example, when the off-current density of the transistor 162 at room temperature is about 10 zA (1 zA (zeptoampere) is 1×10 A)) and the capacitance value of the capacitor element 164 is about 1 pF, -21 data can be retained for at least 10 seconds or more. Note that it goes without saying that the retention time varies depending on the transistor characteristics and capacitance value. 6 seconds or more. Note that it goes without saying that the retention time varies depending on the transistor characteristics and capacitance value. Of course, the holding time varies depending on the transistor characteristics and capacitance value.

[0072] Also, in this case, there is no problem of deterioration of the gate insulating film (tunnel insulating film) as pointed out in the conventional floating gate type transistor. That is, it is possible to eliminate the deterioration of the gate insulating film when injecting electrons into the floating gate, which has been a conventional problem. This means that there is no theoretical limit on the number of write operations. Also, the

[0073] high voltage that was required for writing and erasing in the conventional floating gate type transistor is not necessary. The semiconductor device shown in Fig. 5(A-1) can be replaced with a circuit as shown in Fig. 5(A-2) assuming that elements such as transistors constituting the semiconductor device include resistance and capacitance. That is, in Fig. 5(A-2), it is considered that the transistor 160 and the capacitor element 164 are each composed of resistance and capacitance. R1 and C1 are the resistance value and capacitance value of the capacitor element 164, respectively, and the resistance value R1 corresponds to the resistance value due to the insulating layer constituting the capacitor

[0074] element 164. Also, R2 and C2 are the resistance value and capacitance value of the transistor 160, respectively, and the resistance value R2 If we define ROS as the leakage resistance (also referred to as the effective resistance), when R1 and R2 satisfy R1≧ROS (R1 is greater than or equal to ROS) and R2≧ROS (R2 is greater than or equal to ROS), the charge holding period (which can also be called the information holding period) will mainly be determined by the off-current of transistor 162. Conversely, when this relationship is not satisfied, even if the off-current of transistor 162 is sufficiently small, it becomes difficult to ensure a sufficient holding period. This is because the leakage occurring outside transistor 162 is large. From this, it can be said that it is desirable for the semiconductor device disclosed in this embodiment to satisfy the above relationship. On the other hand, it is desirable for C1 and C2 to satisfy the relationship C1≧C2 (C1 is greater than or equal to C2). By increasing C1, when controlling the potential of the floating gate portion FG by the fifth wiring (for example, during reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layers of transistor 160 and transistor 162. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material and thickness of the gate insulating layer so as to satisfy the above relationship.

[0075] The semiconductor device shown in Fig. 5(B) is a semiconductor device having a configuration in which transistor 160 in Fig. 5(A-1) is not provided. In the semiconductor device shown in Fig. 5(B), the first wiring (1st

[0076]

[0077]

[0078] ​​​​​​​​​​​​​Line: Also referred to as the first signal line) and one of the source or drain electrodes of transistor 162 is electrically connected to one of the second wirings (2nd Line: Also referred to as the second signal line) and is electrically connected to the gate electrode of transistor 162. Then, the other of the source or drain electrodes of transistor 162 and one of the electrodes of capacitor element 164 are electrically connected, and the third wiring (3rd Line: Also referred to as the capacitor line) and the other of the electrodes of capacitor element 164 are electrically connected.

[0079] Here, a transistor using the above-described oxide semiconductor is applied to transistor 162. The transistor using the above-described oxide semiconductor has the characteristic that the off-current is extremely small. Therefore, by turning off transistor 162, the potential applied to capacitor element 164 can be held for an extremely long time. Note that the transistor 162 using the oxide semiconductor has a channel length (L) of 10 nm or more and 1000 nm or less. Therefore, it has the characteristics of low power consumption and extremely high operating speed.

[0080] In the semiconductor device shown in FIG. 5(B), by taking advantage of the characteristic that the potential applied to capacitor element 164 can be held, writing, holding, and reading of information are possible as follows.

[0081] First, writing and holding of information will be described. Here, for simplicity, it is assumed that the potential of the third wiring is fixed. First, the potential of the second wiring is set to a potential at which transistor 162 is turned on, and transistor 162 is turned on. As a result, the potential of the first wiring is applied to one of the electrodes of capacitor element 164. That is, capacitor element 164 A predetermined charge is applied (writing). Then, the potential of the second wiring is set to a potential at which the transistor 162 turns off, and the transistor 162 is turned off, whereby the charge applied to the capacitor element 164 is retained (holding). Since the transistor 162 has an extremely small off-current as described above, it can retain the charge for a long time.

[0082] Next, reading of information will be described. In a state where a predetermined potential (constant potential) is applied to the first wiring, when the potential of the second wiring is set to a potential at which the transistor 162 turns on, the first wiring takes on different potentials according to the amount of charge held in the capacitor element 164. Therefore, the information being held can be read by observing the potential of the first wiring.

[0083] Note that when the information is read, the charge in the capacitor element 164 is lost, so it is necessary to pay attention to performing writing again.

[0084] Next, rewriting of information will be described. Rewriting of information is performed in the same manner as the above-described writing and holding of information. That is, the potential of the second wiring is set to a potential at which the transistor 162 turns on, and the transistor 162 is turned on. As a result, the potential of the first wiring (the potential related to new information) is applied to one of the electrodes of the capacitor element 164. Then, the potential of the second wiring is set to a potential at which the transistor 162 turns off, and the transistor 162 is turned off, whereby the capacitor element 164 assumes a state in which a charge related to new information is applied.

[0085] Thus, the semiconductor device according to the disclosed invention can be directly rewritten by writing information again. It is possible to rewrite information. For this reason, high-speed operation of the semiconductor device is realized.

[0086] Note that the above description is for the case of using an n-type transistor (n-channel transistor) with electrons as majority carriers. However, it goes without saying that a p-type transistor with holes as majority carriers can be used instead of the n-type transistor. Note that the above description is for the case of using an n-type transistor (n-channel transistor) with electrons as majority carriers. However, it goes without saying that a p-type transistor with holes as majority carriers can be used instead of the n-type transistor. Note that the above description is for the case of using an n-type transistor (n-channel transistor) with electrons as majority carriers. However, it goes without saying that a p-type transistor with holes as majority carriers can be used instead of the n-type transistor.

[0087] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0088] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor, specifically, a method for manufacturing the transistor 162 in the upper part of FIG. 2 will be described with reference to FIG. 6. Note that FIG. 6 mainly shows the manufacturing process of the transistor 162 and the like, so detailed description of the transistors 170 and the like existing below the transistor 162 will be omitted. In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor, specifically, a method for manufacturing the transistor 162 in the upper part of FIG. 2 will be described with reference to FIG. 6. Note that FIG. 6 mainly shows the manufacturing process of the transistor 162 and the like, so detailed description of the transistors 170 and the like existing below the transistor 162 will be omitted. In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor, specifically, a method for manufacturing the transistor 162 in the upper part of FIG. 2 will be described with reference to FIG. 6. Note that FIG. 6 mainly shows the manufacturing process of the transistor 162 and the like, so detailed description of the transistors 170 and the like existing below the transistor 162 will be omitted. In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor, specifically, a method for manufacturing the transistor 162 in the upper part of FIG. 2 will be described with reference to FIG. 6. Note that FIG. 6 mainly shows the manufacturing process of the transistor 162 and the like, so detailed description of the transistors 170 and the like existing below the transistor 162 will be omitted.

[0089] First, an insulating layer 138 is formed over the interlayer insulating layer 128. Then, a conductive layer is formed over the insulating layer 138, and the conductive layer is selectively etched to form a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b (see FIG. 6(A)). First, an insulating layer 138 is formed over the interlayer insulating layer 128. Then, a conductive layer is formed over the insulating layer 138, and the conductive layer is selectively etched to form a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b (see FIG. 6(A)). First, an insulating layer 138 is formed over the interlayer insulating layer 128. Then, a conductive layer is formed over the insulating layer 138, and the conductive layer is selectively etched to form a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b (see FIG. 6(A)).

[0090] The insulating layer 138 functions as a base and can be formed using a PVD method, a CVD method, or the like. Further, the insulating layer 138 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that the insulating layer 138 should contain as little hydrogen and water as possible. The insulating layer 138 functions as a base and can be formed using a PVD method, a CVD method, or the like. Further, the insulating layer 138 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that the insulating layer 138 should contain as little hydrogen and water as possible. The insulating layer 138 functions as a base and can be formed using a PVD method, a CVD method, or the like. Further, the insulating layer 138 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that the insulating layer 138 should contain as little hydrogen and water as possible. The insulating layer 138 functions as a base and can be formed using a PVD method, a CVD method, or the like. Further, the insulating layer 138 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Note that the insulating layer 138 should contain as little hydrogen and water as possible. It is desirable to form. Also, a configuration without the insulating layer 138 is also possible.

[0091] The conductive layer can be formed by using PVD methods such as sputtering, or CVD methods such as plasma CVD. Also, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or alloys containing the above-mentioned elements as components can be used. Any one of manganese, magnesium, zirconium, beryllium, or a material combining a plurality of these may be used. Also, for aluminum, elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium or a material combining a plurality of these may be used.

[0092] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Also, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that processing into the source electrode or drain electrode 142a having a tapered shape, and the source electrode or drain electrode 142 b is easy. b is easy. Furthermore, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that processing into the source electrode or drain electrode 142a having a tapered shape, and the source electrode or drain electrode 142 b is easy. b has the advantage of being easy.

[0093] Also, the conductive layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), oxide Indium tin oxide alloy (In 2 O 3 ―SnO 2 , sometimes abbreviated as ITO), indium zinc oxide alloy (In O 2 O 3 ―ZnO), or a material in which silicon or silicon oxide is contained in these metal oxide materials can be used.

[0094] Etching of the conductive layer is preferably performed so that the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b to be formed become tapered. Here, the taper angle is preferably, for example, 30° or more and 60° or less. By etching the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b so as to have a tapered shape, the coverage of the gate insulating layer 14 6 formed later can be improved and step discontinuity can be prevented. Note that the taper angle is the angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or drain electrode 142a) when observed from a direction perpendicular to the cross section (a plane perpendicular to the surface of the substrate).

[0095] The channel length (L) of the transistor is determined by the distance between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142b. When performing exposure for mask formation for forming a transistor with a channel length (L) of less than 25 nm, it is desirable to perform exposure for mask formation using extreme ultraviolet light with a wavelength of several nm to several tens of nm. ​​​​​​​​The exposure has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor to be formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Further, miniaturization can also reduce the power consumption of the semiconductor device. It is also possible to set the channel length (L) of the transistor to be formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Further, miniaturization can also reduce the power consumption of the semiconductor device. It is also possible to set the channel length (L) of the transistor to be formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Further, miniaturization can also reduce the power consumption of the semiconductor device. It is also possible to set the channel length (L) of the transistor to be formed later to be 10 nm or more and 1000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Further, miniaturization can also reduce the power consumption of the semiconductor device.

[0096] Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode to be formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode to be formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode to be formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Note that an insulating layer may be formed on the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. By providing the insulating layer, it is possible to reduce the parasitic capacitance between the gate electrode to be formed later and the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

[0097] Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 6(B)). Next, an oxide semiconductor layer 144 is formed so as to cover the source electrode or drain electrode 142a and the source electrode or drain electrode 142b (see FIG. 6(B)).

[0098] The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide. The oxide semiconductor layer 144 can be formed using an oxide semiconductor such as an In-Sn-Ga-Zn-O-based quaternary metal oxide, an In-Ga-Zn-O-based ternary metal oxide, an In-Sn-Zn-O-based ternary metal oxide, an In-Al-Zn-O-based ternary metal oxide, a Sn-Ga-Zn-O-based ternary metal oxide, an Al-Ga-Zn-O-based ternary metal oxide, a Sn-Al-Zn-O-based ternary metal oxide, an In-Zn-O-based binary metal oxide, a Sn-Zn-O-based binary metal oxide, an Al-Zn-O-based binary metal oxide, a Zn-Mg-O-based binary metal oxide, a Sn-Mg-O-based binary metal oxide, an In-Mg-O-based binary metal oxide, an In-O-based unary metal oxide, a Sn-O-based unary metal oxide, or a Zn-O-based unary metal oxide.

[0099] Among them, the In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and an The leakage current can be made sufficiently small, and since the field-effect mobility is also high, it is suitable as a semiconductor material for use in semiconductor devices.

[0100] As a representative example of an In-Ga-Zn-O-based oxide semiconductor material, InGaO 3 (ZnO) m (where m > 0, m is not necessarily a natural number). Also, instead of Ga, M is used, and there is an oxide semiconductor material expressed as InMO 3 (ZnO) m (where m > 0, m is not necessarily a natural number). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga, Ga and Al , Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. It should be noted that the above composition is derived from the crystal structure and is only an example by the way. It is noted that the above composition is derived from the crystal structure and is only an example by the way.

[0101] As a target for producing the oxide semiconductor layer 144 by sputtering, those represented by the composition formula of In:Ga: Zn = 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less) are preferably used. For example, a target having a composition ratio of In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio can be used. Also, a target having a composition ratio of In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [mole ratio] or a target having a composition ratio of In 2 O3 :G a 2 O 3 : a target having a composition ratio of In:Ga:ZnO = 1:1:4 [molar ratio], or In 2 O 3 : a target having a composition ratio of In:ZnO = 1:2 [molar ratio] can also be used.

[0102] In this embodiment, the amorphous oxide semiconductor layer 144 is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

[0103] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, more preferably 99.9% or more. By using a metal oxide target with a high relative density, it is possible to form the oxide semiconductor layer 144 with a dense structure.

[0104] The formation atmosphere of the oxide semiconductor layer 144 is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less).

[0105] When forming the oxide semiconductor layer 144, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or more and less than 550°C, preferably 200°C or more and 40 0°C or less. Alternatively, the temperature of the object to be processed when forming the oxide semiconductor layer 144 may be room temperature. Then, while removing moisture in the processing chamber, hydrogen, water, etc. ​​​​Introduce the sputter gas from which moisture has been removed, and form the oxide semiconductor layer 144 using the above target. By forming the oxide semiconductor layer 144 while heating the object to be processed, impurities contained in the oxide semiconductor layer 144 can be reduced. In addition, damage caused by sputtering can be reduced. In order to remove moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Alternatively, a turbo pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0106] As the formation conditions of the oxide semiconductor layer 144, for example, the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the atmosphere is an oxygen (oxygen flow ratio 100%) atmosphere, or an argon (argon flow ratio 100%) atmosphere, or a mixed atmosphere of oxygen and argon, and the like can be applied. When using a pulsed direct current (DC) power supply, it is preferable because powdery substances (also called particles, dust) formed during film formation can be reduced and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer 144 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. By using the oxide semiconductor layer 144 having such a thickness, it is possible to suppress the short channel effect associated with miniaturization. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the use of the semiconductor device, etc., the thickness can also be selected according to the material used, the application, etc. ​

[0107] Before forming the oxide semiconductor layer 144 by sputtering, argon gas is introduced to perform reverse sputtering to generate plasma, and it is preferable to remove deposits on the formation surface (for example, the surface of the interlayer insulating layer 128). Here, reverse sputtering means that, in normal sputtering where ions are collided with the sputtering target, conversely, ions are collided with the processing surface to modify the surface. The method of colliding ions with the processing surface includes a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the object to be processed. Note that instead of an argon atmosphere, an atmosphere of nitrogen, helium, oxygen, etc. may be applied.

[0108] Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 144. By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer 144 is removed, the structure of the oxide semiconductor layer is adjusted, and defect levels in the energy gap can be reduced. The temperature of the first heat treatment is, for example, 300°C or higher and less than 550°C, or 40 0°C or higher and 500°C or lower.

[0109] The heat treatment can be performed, for example, by introducing the object to be processed into an electric furnace using a resistance heating element or the like, and under a nitrogen atmosphere, at 450°C for 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the atmosphere so as to prevent the mixing of water and hydrogen.

[0110] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be processed by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, GRTA (Gas Rap​​​​ id Thermal Anneal) equipment, LRTA (Lamp Rapid The rmal Anneal) equipment, etc., an RTA (Rapid Thermal Anneal ) equipment can be used. The LRTA equipment is a halogen lamp, a metal halide lamp , a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, a high-pressure mercury ran p, etc., and is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from such lamps. The GRTA equipment is a device that performs heat treatment using a high-temperature gas. As the gas, a noble gas such as argon , or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

[0111] For example, as the first heat treatment, the object to be processed is put into a heated inert gas atmosphere and heated for several minutes and then, a GRTA treatment of taking out the object to be processed from the inert gas atmosphere may be performed . Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be processed. During the treatment, the inert gas may be switched to a gas containing oxygen . This is because by performing the first heat treatment in an atmosphere containing oxygen, the defect levels in the energy gap caused by oxygen deficiency can be reduced . .

[0112] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc ) and not containing water, hydrogen, etc. is preferably applied . For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment equipment is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( ) That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0113] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor layer 144 that is extremely close to an i-type (intrinsic semiconductor) or an i-type, a transistor with extremely excellent characteristics can be realized.

[0114] Incidentally, since the above heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be referred to as a dehydration treatment, a dehydrogenation treatment, etc. The dehydration treatment and the dehydrogenation treatment can also be performed at timings such as after the formation of the oxide semiconductor layer, after the formation of the gate insulating layer, and after the formation of the gate electrode. Moreover, such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times.

[0115] Next, a gate insulating layer 146 in contact with the oxide semiconductor layer 144 is formed (see Fig. 6(C)). The gate insulating layer 146 can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 146 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate with nitrogen added (HfSi O x O y N z (x>0, y>0, z>0)), hafnium aluminate with nitrogen added (H fAl x O y N z (x>0, y>0, z>0)), etc. The gate insulating layer 146 may have a single-layer structure or a laminated structure. Also, ​​​The thickness is not particularly limited, but when miniaturizing a semiconductor device, the operation of the transistor For example, when silicon oxide is used, the thickness is 1n. The thickness m can be set to 100 nm or more, and preferably 10 nm or more and 50 nm or less.

[0116] As described above, when the gate insulating layer 146 is thinned, the gate resistance due to the tunnel effect and the like is reduced. To solve the gate leakage problem, the gate insulating layer 146 is provided with an oxide halide. Funium, Tantalum Oxide, Yttrium Oxide, Hafnium Silicate (HfSixOy( x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x >0, y>0, z>0), nitrogen doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)) By using a high-k material for the gate insulating layer 146, the electrical characteristics are maintained while It is possible to increase the film thickness to suppress gate leakage. A film including a material, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, It may have a laminated structure with a film containing any of aluminum oxide and the like.

[0117] After the gate insulating layer 146 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. This is good. By performing the second heat treatment, variations in the electrical characteristics of the transistor can be reduced. This can be achieved. Further, when the gate insulating layer 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144, and an oxide semiconductor layer that is i-type (intrinsic semiconductor) or infinitely close to i-type can also be formed.

[0118] Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146. However, the timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment.

[0119] Next, a gate electrode 148a is formed in a region overlapping the oxide semiconductor layer 144 on the gate insulating layer 146 (see Fig. 6(D)). The gate electrode 148a is formed by forming a conductive layer on the gate insulating layer 146 and then selectively etching the conductive layer. The conductive layer for the gate electrode 148a can be formed using a PVD method such as sputtering or a CVD method such as plasma CVD. The details are the same as in the case of the source electrode or the drain electrode 142a, and these descriptions can be referred to. Note that when forming the gate electrode 148a, the electrode 148b of the capacitor element 164 in the previous embodiment can also be formed together. Next, an interlayer insulating layer 150 and an interlayer are formed on the gate insulating layer 146 and the gate electrode 148a.

[0120] Form the insulating layer 152 (see Fig. 6(E)). The interlayer insulating layer 150 and the interlayer insulating layer 152 can be formed using methods such as PVD or CVD. Also, inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. can be used to form the material. In this embodiment, although the laminated structure of the interlayer insulating layer 150 and the interlayer insulating layer 152 is adopted, one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. Also, it is possible to adopt a configuration without providing the interlayer insulating layer. It should be noted that the surface of the above interlayer insulating layer 152 is preferably formed to be flat. By forming the interlayer insulating layer 152 so that its surface is flat, electrodes, wirings, etc. can be suitably formed on the interlayer insulating layer 152 even in the case of miniaturizing the semiconductor device. The planarization of the interlayer insulating layer 152 can be performed using a method such as CMP (chemical mechanical polishing).

[0121]

[0122] As described above, the transistor 162 using the highly purified oxide semiconductor layer 144 is completed (see Fig. 6(E)).

[0123] The transistor 162 shown in Fig. 6(E) includes an oxide semiconductor layer 144, a source electrode or a drain electrode 142a that is electrically connected to the oxide semiconductor layer 144, a source electrode or a drain electrode 142b, a gate insulating layer 146 that covers the oxide semiconductor layer 144, the source electrode or the drain electrode 142a, and the source electrode or the drain electrode 142b, a gate electrode 148a on the gate insulating layer 146, and an interlayer insulating layer on the gate insulating layer 146 and the gate electrode 148a ​​​​​​​​​​​ It has a layer 150 and an interlayer insulating layer 152 on the interlayer insulating layer 150.

[0124] In the transistor 162 shown in this embodiment, since the oxide semiconductor layer 144 has been highly purified, its hydrogen concentration is 5×10 19 atoms / cm 3 or less, desirably 5× 10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. Also, the carrier density of the oxide semiconductor layer 144 is sufficiently smaller compared to the carrier density (about 1×10 / cm 14 / cm 3 level) in a general silicon wafer, taking a value (for example, less than 1 ×10 12 / cm 3 , more preferably less than 1.45×10 10 / cm 3 ). And thereby, the off-current becomes sufficiently small. For example, the off-current density (the value obtained by dividing the off-current by the channel width of the transistor) of the transistor 162 at room temperature is from 10 zA / μm to 100 zA / μm (1 zA (zeptoampere) is 1×10 A). -21

[0125] By using such a highly purified and intrinsic oxide semiconductor layer 144, the off-current of the transistor can be sufficiently reduced. And by using such a transistor, a semiconductor device capable of retaining memory contents for an extremely long period can be obtained.

[0126] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0127] (Embodiment 3) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor (particularly an oxide semiconductor having an amorphous structure) will be described with reference to FIG. 7. The transistor can be used in place of the transistor 162 in the previous embodiment. Note that the transistor according to this embodiment has some configurations in common with the transistor according to the previous embodiment. For this reason, differences will be mainly described below. In the following description, a top-gate type transistor will be described as an example, but the configuration of the transistor is not limited to the top-gate type.

[0128] First, an insulating layer 202 is formed on a workpiece 200. Then, an oxide semiconductor layer 206 is formed on the insulating layer 202 (see FIG. 7(A)).

[0129] The workpiece 200 is, for example, the interlayer insulating layer 128 in the previous embodiment. The surface of the workpiece 200 desirably has an arithmetic mean roughness (Ra) of 1 nm or less. More desirably, it is 0.5 nm or less. As the semiconductor device is miniaturized, the requirements for the exposure conditions of the mask used for patterning increase. However, by making the surface have such high flatness, it becomes easier to cope even when the requirements for the exposure conditions are high. Note that the above-described arithmetic mean roughness can be measured, for example, in a 10 μm × 10 μm region.

[0130] The insulating layer 202 corresponds to the insulating layer 138 in the previous embodiment and functions as a base. For details, the previous embodiment can be referred to. Note that a configuration in which the insulating layer 202 is not provided is also possible.

[0131] The oxide semiconductor layer 206 corresponds to the oxide semiconductor layer 144 in the previous embodiment. For the materials that can be used, the manufacturing method, and other details, the previous embodiment can be referred to.

[0132] In this embodiment, the amorphous oxide semiconductor layer 206 is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

[0133] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask to form island-shaped oxide semiconductor layers 206a.

[0134] For the etching of the oxide semiconductor layer 206, either dry etching or wet etching may be used. Of course, both can also be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the oxide semiconductor layer can be etched into a desired shape.

[0135] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, for example, chlorine (Cl ), boron trichloride (BCl 2 ), silicon tetrachloride (SiCl 3 ), carbon tetrachloride (CCl 4 ), etc.). Also, gases containing fluorine (fluorine-based gases, for example, carbon tetrafluoride (CF ), sulfur hexafluoride (SF 4 ), nitrogen trifluoride (NF ), trifluoromethane (CHF 4 ), etc.), hydrogen bromide (HBr), oxygen (O 6 ), and helium (He 3 ) added to these gases. 3 ), etc.). 2 ), and oxygen (O A gas added with a noble gas such as argon (Ar) or the like may also be used.

[0136] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil type electrode, the amount of electric power applied to the electrode on the object to be processed, the electrode temperature on the object to be processed, etc.) can be set as appropriate so that etching can be performed into a desired shape. For wet etching, an etching solution obtained by mixing phosphoric acid, acetic acid, and nitric acid or the like can be used. Further, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0137] It is preferable to etch the end portion of the oxide semiconductor layer 206a so as to have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. Note that the taper angle indicates an inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the oxide semiconductor layer 206a) when observed from a direction perpendicular to the cross section (a plane perpendicular to the surface of the object to be processed). By etching the end portion of the oxide semiconductor layer 206a so as to have a tapered shape, the coverage of the source electrode or drain electrode 208a and the source electrode or drain electrode 208b formed later can be improved, and step discontinuity can be prevented.

[0138]

[0139] Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 206a. ​​​​​​​​​​​​Yes. By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer 206a is removed, the structure of the oxide semiconductor layer is adjusted, and the defect levels in the energy gap can be reduced. For details, reference can be made to the previous embodiments. As shown here, when the heat treatment (first heat treatment) is performed after etching, even when wet etching is used, etching can be performed in a state where the etching rate is high, so there is an advantage that the time required for etching can be shortened. Note that the first heat treatment can also be performed on the oxide semiconductor layer 206 before processing it into the island-shaped oxide semiconductor layer 206a. In that case, after the first heat treatment, the object to be processed 200 is taken out from the heating device, and a photolithography process is performed. Incidentally, since the above-described heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such dehydration treatment and dehydrogenation treatment can be performed at timings such as after the formation of the oxide semiconductor layer, after laminating a source electrode or a drain electrode on the oxide semiconductor layer 206a, and after forming a gate insulating layer. Also, such dehydration treatment and dehydrogenation treatment can be performed not only once but also multiple times. Next, a conductive layer is formed so as to be in contact with the oxide semiconductor layer 206a. Then, the conductive layer is selectively etched to form a source electrode or a drain electrode 208a and a source electrode or a drain electrode 208b (see FIG. 7(B)). The conductive layer, the source electrode or the drain electrode

[0140]

[0141]

[0142] Regarding the pole 208a, the source electrode or the drain electrode 208b, and other details, refer to the description of the conductive layer, the source electrode or the drain electrode, etc. in the previous embodiment. .

[0143] Next, a gate insulating layer 212 in contact with a part of the oxide semiconductor layer 206a is formed (see Fig. 7(C)). Regarding the details of the gate insulating layer 212, refer to the description of the gate insulating layer, etc. in the previous embodiment.

[0144] After the formation of the gate insulating layer 212, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. Regarding the details of the second heat treatment, the previous embodiment can also be referred to. .

[0145] In this embodiment, a second heat treatment is performed after the formation of the gate insulating layer 212, but the timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode.

[0146] Next, a gate electrode 214 is formed in a region overlapping the oxide semiconductor layer 206a on the gate insulating layer 212 (see Fig. 7(D)). The gate electrode 214 can be formed by forming a conductive layer on the gate insulating layer 212 and then selectively patterning the conductive layer. For details, refer to the previous embodiment. When forming the gate electrode 214, the electrodes of the capacitor element in the previous embodiment can be formed together.

[0147] Next, an interlayer insulating layer 216 and an interlayer insulating layer 218 are formed on the gate insulating layer 212 and the gate electrode 214 (see Fig. 7(E)). For details, refer to the previous embodiment. Note that it is also possible to adopt a configuration in which an interlayer insulating layer is not provided.

[0148] As described above, a transistor 250 using the highly purified amorphous oxide semiconductor layer 206a is completed (see Fig. 7(E)). Depending on the heat treatment conditions, a small amount of crystal component may be present in the oxide semiconductor layer 206a.

[0149] By using the thus highly purified and crystallized oxide semiconductor layer 206a, the off-current of the transistor can be sufficiently reduced. Then, by using such a transistor, a semiconductor device capable of retaining the stored content for an extremely long period can be obtained.

[0150] Note that in this embodiment, a top-gate type transistor has been described, in which the lower portions of the source electrode and the drain electrode are in contact with the upper portion of the oxide semiconductor layer. However, the transistor to which the configuration of this embodiment can be applied is not limited to this. For example, in a top-gate type transistor, a configuration in which the upper portions of the source electrode and the drain electrode are in contact with the lower portion of the oxide semiconductor layer (such as the configurations shown in Fig. 2 and Fig. 4), a part of the configuration of this embodiment can be applied. Further, in a bottom-gate type transistor, a configuration in which the lower portions of the source electrode and the drain electrode are in contact with the upper portion of the oxide semiconductor layer, or in a bottom-gate type transistor, a configuration in which the upper portions of the source electrode and the drain electrode are in contact with the lower portion of the oxide semiconductor layer, a part of the configuration of this embodiment can be applied. That is, according to this embodiment, various transistors including an amorphous oxide semiconductor can be realized.

[0151] ​​​​​​​​​​​ As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0152] (Embodiment 4) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIG. 8. In this embodiment, as the oxide semiconductor layer, a first oxide semiconductor layer having a crystal region and a second oxide semiconductor layer crystal-grown from the crystal region of the first oxide semiconductor layer are used. The case will be described in detail. The transistor can be used in place of the transistor 162 in the previous embodiment. Note that the transistor according to this embodiment has some configurations in common with the transistor according to the previous embodiment. Therefore, the differences will be mainly described below.

[0153] If the required thickness can be ensured only by the first oxide semiconductor layer, the second oxide semiconductor layer is not necessary. In the following, a top-gate type transistor will be described as an example, but the configuration of the transistor is not limited to the top-gate type.

[0154] First, an insulating layer 302 is formed on a workpiece 300. Then, a first oxide semiconductor layer is formed on the insulating layer 302, and at least the surface of the first oxide semiconductor layer is crystallized by a first heat treatment to form a first oxide semiconductor layer 304 (see FIG. 8(A)).

[0155] Regarding the details of the workpiece 300 (details such as the surface), the previous embodiments can be referred to.

[0156] The insulating layer 302 functions as a base. For details of the insulating layer 302, refer to the previous embodiments. Note that a configuration without the insulating layer 302 may also be adopted. The first oxide semiconductor layer can be formed in the same manner as the oxide semiconductor layer in the previous embodiments. Therefore, for details of the first oxide semiconductor layer and its film formation method, refer to the previous embodiments. However, in this embodiment, since the first oxide semiconductor layer is intentionally crystallized by the first heat treatment, it is desirable to use an oxide semiconductor that is likely to crystallize to form the first oxide semiconductor layer. Examples of such an oxide semiconductor include ZnO. Also, among In-Ga-Zn-O-based oxide semiconductors, for example, those with a high Zn concentration are likely to crystallize, and those with a Zn occupancy ratio of 60 atom% or more among the metal elements (In, Ga, and Zn) are desirable for this purpose. Also, the thickness of the first oxide semiconductor layer is desirably 1 nm or more and 10 nm or less. In this embodiment, the thickness is 3 nm as an example. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the use, etc. of the semiconductor device, the thickness may be selected according to the material and use to be used.

[0157] The first oxide semiconductor layer can be formed in the same manner as the oxide semiconductor layer in the previous embodiments. Therefore, for details of the first oxide semiconductor layer and its film formation method, refer to the previous embodiments. However, in this embodiment, since the first oxide semiconductor layer is intentionally crystallized by the first heat treatment, it is desirable to use an oxide semiconductor that is likely to crystallize to form the first oxide semiconductor layer. Examples of such an oxide semiconductor include ZnO. Also, among In-Ga-Zn-O-based oxide semiconductors, for example, those with a high Zn concentration are likely to crystallize, and those with a Zn occupancy ratio of 60 atom% or more among the metal elements (In, Ga, and Zn) are desirable for this purpose. Also, the thickness of the first oxide semiconductor layer is desirably 1 nm or more and 10 nm or less. In this embodiment, the thickness is 3 nm as an example. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied, the use, etc. of the semiconductor device, the thickness may be selected according to the material and use to be used. The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. Also, the heat treatment time is desirably 1 minute or more and 24 hours or less. Note that the heat treatment temperature and the heat treatment time vary depending on the type of the oxide semiconductor.

[0158] The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. Also, the heat treatment time is desirably 1 minute or more and 24 hours or less. Note that the heat treatment temperature and the heat treatment time vary depending on the type of the oxide semiconductor.

[0159] Also, the atmosphere of the first heat treatment is desirably an atmosphere that does not contain hydrogen, water, etc. For example, it is possible to use an atmosphere of nitrogen, oxygen, rare gases (helium, neon, argon, etc.) from which water has been sufficiently removed. This can be the atmosphere.

[0160] In addition to an electric furnace, the heat treatment apparatus can use a device that heats the object to be treated by heat conduction from a medium such as heated gas or by heat radiation. For example, an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, rare gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. For example, LRTA (Lamp Rapid Thermal Anneal) device, GRTA (Gas Rapid Thermal Anneal) device, etc. apid Thermal Anneal) device, GRTA (Gas Rapid Th ermal Anneal) device, etc. of RTA (Rapid Thermal Annea l) device can be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. プ, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp, etc. The radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. . The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, rare gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. As the gas, rare gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. is used.

[0161] By the above-described first heat treatment, at least a region including the surface of the first oxide semiconductor layer crystallizes. The crystal region is a region formed by crystal growth proceeding from the surface of the first oxide semiconductor layer toward the inside of the first oxide semiconductor layer. Note that the crystal region may include plate-like crystals having an average thickness of 1 nm or more and 10 nm or less. Also, the crystal region may include crystals that are c-axis oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, substantially parallel means a state within ±10° from the parallel direction, and substantially perpendicular means a state within ±10° from the perpendicular direction. The crystal region is a region formed by crystal growth proceeding from the surface of the first oxide semiconductor layer toward the inside of the first oxide semiconductor layer. is a region formed by crystal growth proceeding from the surface of the first oxide semiconductor layer toward the inside of the first oxide semiconductor layer. Note that the crystal region may include plate-like crystals having an average thickness of 1 nm or more and 10 nm or less. Also, the crystal region may include crystals that are c-axis oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, substantially parallel means a state within ±10° from the parallel direction, and substantially perpendicular means a state within ±10° from the perpendicular direction. The crystal region may include plate-like crystals having an average thickness of 1 nm or more and 10 nm or less. The crystal region may include crystals that are c-axis oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, substantially parallel means a state within ±10° from the parallel direction, and substantially perpendicular means a state within ±10° from the perpendicular direction. Here, substantially parallel means a state within ±10° from the parallel direction, and substantially perpendicular means a state within ±10° from the perpendicular direction. is a state within ±10° from the perpendicular direction.

[0162] In addition, the first heat treatment forms a crystalline region and removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and oxygen with a purity of 6N (99.9999%) or more (i.e. impurity concentration of 1ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 ppm or less). 2 In ultra-dry air with O of 20 ppm or less, H 2 The first heat treatment may be performed in ultra-dry air having an O content of 1 ppm or less.

[0163] In addition, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by performing the heat treatment in an oxygen atmosphere, the first oxide Oxygen can be supplied to the semiconductor layer.

[0164] In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere is switched to an oxygen atmosphere, The first heat treatment is performed to supply oxygen to the inside of the oxide semiconductor layer. Since the structure is the same, it is possible to carry out separate processes for the purpose of removing hydrogen and supplying oxygen. For example, after heat treatment to remove hydrogen, etc., or treatment to supply oxygen, In this case, it is possible to carry out a heat treatment for crystallization.

[0165] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. Thus, a first oxide semiconductor layer to which oxygen is supplied is obtained.

[0166] Next, on the first oxide semiconductor layer 304 having a crystal region in a region including at least the surface, a second oxide semiconductor layer 305 is formed (see FIG. 8(B)). If the required thickness can be ensured only by the first oxide semiconductor layer 304, the second oxide semiconductor layer 305 is unnecessary. In this case, the process for the second oxide semiconductor layer 305 can be omitted.

[0167] The second oxide semiconductor layer 305 can be formed in the same manner as the oxide semiconductor layer in the previous embodiment. Therefore, for details of the second oxide semiconductor layer 305 and its film formation method, the previous embodiment may be referred to. However, it is desirable that the second oxide semiconductor layer 305 be formed thicker than the first oxide semiconductor layer 304. Also, it is desirable that the second oxide semiconductor layer 305 be formed such that the sum of the thicknesses of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 10 nm or less. In this embodiment, as an example, the thickness is 7 nm. Note that an appropriate thickness varies depending on the oxide semiconductor material to be applied and the use of the semiconductor device, and thus the thickness may be selected according to the material and use to be used.

[0168] For the second oxide semiconductor layer 305, it is desirable to use a material having the same main component as the first oxide semiconductor layer 304 and a lattice constant close to that after crystallization (mismatch of 1% or less). When such a material is used, in the crystallization of the second oxide semiconductor layer 305, crystal growth using the crystal region of the first oxide semiconductor layer 304 as a seed is likely to proceed. Therefore, ​It is so. Further, in the case of the same main component material, the interfacial physical properties and electrical properties also become good.

[0169] In addition, when a desired film quality is obtained by crystallization, the second oxide semiconductor layer 305 may be formed using materials of different main components. is formed.

[0170] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and crystal growth is performed using the crystal region of the first oxide semiconductor layer 304 as a seed to form the second oxide semiconductor layer 306 (see Fig. 8( C)). If the second oxide semiconductor layer 305 is not formed, this step can be omitted. is possible.

[0171] The temperature of the second heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The heating time of the second heat treatment is 1 minute or longer and 100 hours or shorter, preferably 5 hours or longer and 20 hours or shorter, and typically 10 hours. In addition, also in the second heat treatment, it is desirable that the heat treatment atmosphere does not contain hydrogen, water, or the like.

[0172] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. Also, the heat treatment apparatus that can be used is the same as in the case of the first heat treatment. For example, by setting the inside of the furnace to a nitrogen atmosphere during the temperature rise of the second heat treatment and to an oxygen atmosphere during cooling, removal of hydrogen and the like can be performed in the nitrogen atmosphere, and oxygen supply can be performed in the oxygen atmosphere.

[0173] By performing the second heat treatment as described above, crystal growth proceeds from the crystal region formed in the first oxide semiconductor layer 304 to the entire second oxide semiconductor layer 305, and the second oxide semiconductor layer 306 can be formed. Also, hydrogen (including water and hydroxyl groups) and the like are removed. ​​​​​​​​ , a second oxide semiconductor layer 306 supplied with oxygen can be formed. Also, the second By heat treatment, it is also possible to enhance the orientation of the crystal regions of the first oxide semiconductor layer 304 .

[0174] For example, when an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 306 , the second oxide semiconductor layer 306 may include a crystal represented by InGaO 3 (ZnO) m (m: a natural number is not limited), or a crystal represented by In 2 Ga 2 ZnO 7 (In:Ga:Zn:O = 2:2: 1:7 [atomic ratio]), etc. Such crystals are oriented by the second heat treatment so that their c-axis is substantially perpendicular to the surface of the second oxide semiconductor layer 306 .

[0175] Here, the above-mentioned crystal has a layered structure of layers parallel to the a-axis and b-axis . Also, each layer contains any one of In, Ga, and Zn. Specifically, the above-mentioned crystal has a structure in which a layer containing In and a layer not containing In (a layer containing Ga or Zn) are laminated in the c-axis direction.

[0176] In an In-Ga-Zn-O-based oxide semiconductor crystal, the conductivity in the in-plane direction of the layer containing In, that is, the direction parallel to the a-axis and b-axis, is good. This is because in an In-G a-Zn-O-based oxide semiconductor crystal, electrical conduction is mainly controlled by In , and the 5s orbit of one In overlaps with the 5s orbit of an adjacent In, thereby forming a carrier path, etc.​​

[0177] Also, in the case of a structure in which the first oxide semiconductor layer 304 has an amorphous region at the interface with the insulating layer 302, by performing a second heat treatment, crystal growth proceeds from the crystal region formed on the surface of the first oxide semiconductor layer 304 downward to the lower part of the first oxide semiconductor layer 304 and the amorphous region may be crystallized. Note that depending on the material constituting the insulating layer 302, the heat treatment conditions, etc., the amorphous region may remain.

[0178] Also, when an oxide semiconductor material having the same main component is used for the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305, as shown in FIG. 8(C), the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 may have the same crystal structure. For this reason, although shown by a dotted line in FIG. 8(C), the boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable, and the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 may be regarded as the same layer.

[0179] Next, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are processed by a method such as etching using a mask to form island-shaped first oxide semiconductor layer 304a and second oxide semiconductor layer 306a (see FIG. 8(D)). Here, after the second heat treatment, processing into an island-shaped oxide semiconductor layer is performed. However, after processing into an island-shaped oxide semiconductor layer, the second heat treatment may be performed. In this case, even when wet etching is used, since etching can be performed in a state where the etching rate is high, there is an advantage that the time required for etching can be shortened.

[0180] For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to. For the etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, either dry etching or wet etching may be used. Of course, both can be used in combination. In order to be able to etch the oxide semiconductor layer into a desired shape, the etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material. The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 can be carried out in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. For details, the previous embodiment may be referred to.

[0181] Note that, among the oxide semiconductor layers, the region that becomes the channel formation region preferably has a flat surface. For example, the height difference (P-V) on the surface of the second oxide semiconductor layer 306 is preferably 1 nm or less (more preferably 0.5 nm or less) in the region that overlaps with the gate electrode (channel formation region). The above-mentioned height difference can be measured, for example, in a region of 10 μm × 10 μm. Note that, among the oxide semiconductor layers, the region that becomes the channel formation region preferably has a flat surface. For example, the height difference (P-V) on the surface of the second oxide semiconductor layer 306 is preferably 1 nm or less (more preferably 0.5 nm or less) in the region that overlaps with the gate electrode (channel formation region). The above-mentioned height difference can be measured, for example, in a region of 10 μm × 10 μm. Note that, among the oxide semiconductor layers, the region that becomes the channel formation region preferably has a flat surface. For example, the height difference (P-V) on the surface of the second oxide semiconductor layer 306 is preferably 1 nm or less (more preferably 0.5 nm or less) in the region that overlaps with the gate electrode (channel formation region). The above-mentioned height difference can be measured, for example, in a region of 10 μm × 10 μm. Note that, among the oxide semiconductor layers, the region that becomes the channel formation region preferably has a flat surface. For example, the height difference (P-V) on the surface of the second oxide semiconductor layer 306 is preferably 1 nm or less (more preferably 0.5 nm or less) in the region that overlaps with the gate electrode (channel formation region). The above-mentioned height difference can be measured, for example, in a region of 10 μm × 10 μm. Note that, among the oxide semiconductor layers, the region that becomes the channel formation region preferably has a flat surface. For example, the height difference (P-V) on the surface of the second oxide semiconductor layer 306 is preferably 1 nm or less (more preferably 0.5 nm or less) in the region that overlaps with the gate electrode (channel formation region). The above-mentioned height difference can be measured, for example, in a region of 10 μm × 10 μm.

[0182] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. Then, the conductive layer is selectively etched to form a source electrode or a drain electrode 308a and a source electrode or a drain electrode 308b (see FIG. 8(D)). For details, the previous embodiment may be referred to. Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. Then, the conductive layer is selectively etched to form a source electrode or a drain electrode 308a and a source electrode or a drain electrode 308b (see FIG. 8(D)). For details, the previous embodiment may be referred to. Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. Then, the conductive layer is selectively etched to form a source electrode or a drain electrode 308a and a source electrode or a drain electrode 308b (see FIG. 8(D)). For details, the previous embodiment may be referred to. Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. Then, the conductive layer is selectively etched to form a source electrode or a drain electrode 308a and a source electrode or a drain electrode 308b (see FIG. 8(D)). For details, the previous embodiment may be referred to.

[0183] Note that, in the process shown in FIG. 8(D), the source electrode or the drain electrode 308a and the source electrode or the drain electrode 308b of the first oxide semiconductor layer 304a or the second oxide semiconductor layer 306a Note that, in the process shown in FIG. 8(D), the source electrode or the drain electrode 308a and the source electrode or the drain electrode 308b of the first oxide semiconductor layer 304a or the second oxide semiconductor layer 306a The crystal layer in contact with the pole 308b may be in an amorphous state. Therefore, not all regions of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are necessarily crystalline. .

[0184] Next, a gate insulating layer 312 is formed in contact with a part of the second oxide semiconductor layer 306a. For details, refer to the previous embodiment. Thereafter, a gate electrode 314 is formed in a region on the gate insulating layer 312 that overlaps with the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a. Then, an interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate insulating layer 312 and the gate electrode 314 (see Fig. 8(E)). For details, refer to the previous embodiment.

[0185] After the formation of the gate insulating layer 312, it is desirable to perform a third heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is 200°C or higher and 450°C or lower, preferably 250°C or higher and 350°C or lower. For example, a heat treatment at 250°C for 1 hour in an atmosphere containing oxygen may be performed. By performing the third heat treatment, the electrical property variations of the transistor can be reduced. Also, when the gate insulating layer 312 is an insulating layer containing oxygen, oxygen can be supplied to the second oxide semiconductor layer 306a.

[0186] In this embodiment, the third heat treatment is performed after the formation of the gate insulating layer 312, but the timing of the third heat treatment is not limited to this. Also, when oxygen is supplied to the second oxide semiconductor layer 306a by other processes such as the second heat treatment, the third heat treatment may be omitted.

[0187] ​ As described above, the transistor 350 using the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a is completed (see FIG. 8(E)).

[0188] By using the thus highly purified and intrinsic first oxide semiconductor layer 304a and second oxide semiconductor layer 306a, the off-current of the transistor can be sufficiently reduced. And by using such a transistor, a semiconductor device capable of holding memory contents for an extremely long period can be obtained.

[0189] Note that in this embodiment, a top-gate type transistor in which the lower portions of the source electrode and the drain electrode are in contact with the upper portion of the oxide semiconductor layer has been described. However, the transistor to which the configuration of this embodiment can be applied is not limited to this. For example, in a top-gate type transistor in which the upper portions of the source electrode and the drain electrode are in contact with the lower portion of the oxide semiconductor layer (such as the configurations shown in FIGS. 2 and 4), a part of the configuration of this embodiment can be applied. Further, in a bottom-gate type transistor in which the lower portions of the source electrode and the drain electrode are in contact with the upper portion of the oxide semiconductor layer, or in a bottom-gate type transistor in which the upper portions of the source electrode and the drain electrode are in contact with the lower portion of the oxide semiconductor layer, a part of the configuration of this embodiment can be applied. That is, according to this embodiment, various transistors including an oxide semiconductor layer having a crystal region can be realized.

[0190] Furthermore, in this embodiment, as the oxide semiconductor layer, a first oxide semiconductor having a crystal region ​​​​​​​​​​​​​Using the layer 304a and the second oxide semiconductor layer 306a crystal-grown from the crystal region of the first oxide semiconductor layer 304a, it is possible to improve the field-effect mobility and realize a transistor having good electrical characteristics. For example, it is also possible to realize a field-effect mobility μ>100 cm / V·s. Thus, it is also possible to apply the above transistor to various logic circuits that require high-speed operation. For example, it is also possible to realize a field-effect mobility μ>100 cm 2 / V·s. Thus, it is also possible to apply the above transistor to various logic circuits that require high-speed operation. / V·s. Thus, it is also possible to apply the above transistor to various logic circuits that require high-speed operation.

[0191] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0192] (Embodiment 5) In the present embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIG. 9. The transistor can be used in place of the transistor 162 in the previous embodiment. Note that the transistor according to the present embodiment has some configurations in common with the transistor according to the previous embodiment. Therefore, hereinafter, the differences will be mainly described. In the following, a top-gate type transistor will be described as an example, but the configuration of the transistor is not limited to the top-gate type. configurations in common with the transistor according to the previous embodiment. Therefore, hereinafter, the differences will be mainly described. In the following, a top-gate type transistor will be described as an example, but the configuration of the transistor is not limited to the top-gate type. but the configuration of the transistor is not limited to the top-gate type.

[0193] First, an insulating layer 402 is formed on the object to be processed 400. Then, an oxide semiconductor layer 406 is formed on the insulating layer 402 (see FIG. 9(A)). For details, refer to the previous embodiment. First, an insulating layer 402 is formed on the object to be processed 400. Then, an oxide semiconductor layer 406 is formed on the insulating layer 402 (see FIG. 9(A)). For details, refer to the previous embodiment. First, an insulating layer 402 is formed on the object to be processed 400. Then, an oxide semiconductor layer 406 is formed on the insulating layer 402 (see FIG. 9(A)). For details, refer to the previous embodiment.

[0194] Next, the oxide semiconductor layer 406 is processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 406a, and a conductive layer is formed so as to cover the oxide semiconductor layer 406a. Next, the oxide semiconductor layer 406 is processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 406a, and a conductive layer is formed so as to cover the oxide semiconductor layer 406a. Form the conductive layer 408 and the insulating layer 410 (see FIG. 9(B)). Note that the insulating layer 410 is not an essential component, but it is effective for selectively oxidizing the side surfaces of the source electrode or drain electrode to be formed later. It is also effective in reducing the capacitance between the gate electrode and the source electrode or drain electrode. For details such as the formation and heat treatment of the island-shaped oxide semiconductor layer 406a, refer to the previous embodiments. Also, for details of the conductive layer 408, refer to the previous embodiments. The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc.

[0195] For details such as the formation and heat treatment of the island-shaped oxide semiconductor layer 406a, refer to the previous embodiments. Also, for details of the conductive layer 408, refer to the previous embodiments. For details such as the formation and heat treatment of the island-shaped oxide semiconductor layer 406a, refer to the previous embodiments. Also, for details of the conductive layer 408, refer to the previous embodiments. For details such as the formation and heat treatment of the island-shaped oxide semiconductor layer 406a, refer to the previous embodiments. Also, for details of the conductive layer 408, refer to the previous embodiments.

[0196] The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less. The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less. The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less. The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less. The insulating layer 410 can be formed using a method such as CVD or sputtering. The insulating layer 410 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 410 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 410 is not particularly limited, but can be, for example, 10 nm or more and 200 nm or less.

[0197] Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc. Next, selectively etch the conductive layer 408 and the insulating layer 410 to form the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, the insulating layer 410a, and the insulating layer 410b (see FIG. 9(C)). The details are the same as the formation process of the source electrode or drain electrode in the previous embodiments. Materials such as aluminum, titanium, molybdenum, and copper are suitable for the plasma oxidation treatment to be performed later and are suitable as materials for the source electrode or drain electrode 408a, the source electrode or drain electrode 408b, etc.

[0198] Next, an oxidation treatment for supplying oxygen to the oxide semiconductor layer 406a is performed (see Fig. 9(D)). ) Due to this oxidation treatment, an oxidation region 411a is formed in a part of the source electrode or drain electrode 408a (particularly, the part corresponding to its side surface), and an oxidation region 411b is formed in a part of the source electrode or drain electrode 408b (particularly, the part corresponding to its side surface) (see Fig. 9(D)). In addition, an oxidation region is also formed in the outer peripheral part of the source electrode or drain electrode 408a and the source electrode or drain electrode 408b by this oxidation treatment. The oxidation treatment is preferably a plasma oxidation treatment using oxygen plasma excited by microwaves (300 MHz to 300 GHz). By exciting plasma with microwaves, high-density plasma is realized, and damage to the oxide semiconductor layer 406a can be sufficiently reduced. More specifically, for example, the frequency is 300 MHz to 300 GHz (typically 2.45 GHz), the pressure is 50 Pa to 5000 Pa (typically 500 Pa), the temperature of the object to be treated is 200 to 400 °C (typically 300 °C), and the above treatment can be performed using a mixed gas of oxygen and argon. Since oxygen is supplied to the oxide semiconductor layer 406a by the above oxidation treatment, it is possible to reduce the defects in the energy gap caused by oxygen deficiency while sufficiently reducing the damage to the oxide semiconductor layer 406a. That is, the characteristics of the oxide semiconductor layer 406a can be further improved.

[0199]

[0200]

[0201]

[0202] ​​​​​​​​​​​​Note that as long as the method can supply oxygen to the oxide semiconductor layer 406a while sufficiently reducing the damage to the oxide semiconductor layer 406 it is not limited to the plasma oxidation treatment using microwaves. For example, a method such as heat treatment in an atmosphere containing oxygen can also be used .

[0203] In addition, a treatment for removing water, hydrogen, etc. from the oxide semiconductor layer 406a may be performed in combination with the above oxidation treatment . In this case, for example, plasma treatment using a gas such as nitrogen or argon can be used .

[0204] Note that the oxidation regions 411a and 411b formed by the above oxidation treatment are particularly effective when the transistor 450 is miniaturized (for example, when the channel length is less than 1000 nm) . As the transistor is miniaturized, it is required to reduce the thickness of the gate insulating layer. By having the oxidation region, it is possible to prevent a short circuit between the gate electrode and the source electrode or the drain electrode that may occur due to thinning or coverage failure of the gate insulating layer . Note that the oxidation region is sufficiently effective if it has a thickness of 5 nm or more (preferably 10 nm or more) . .

[0205] In addition, the above oxidation treatment is also effective from the viewpoint of improving the film quality of the exposed insulating layer 402

[0206] Note that the insulating layers 410a and 410b are important in that they have a role of preventing oxidation of the upper portions of the source electrode or drain electrode 408a and the source electrode or drain electrode 408 b. This is because it is very difficult to perform the above plasma treatment while leaving the mask used during etching . ​​​​

[0207] Next, a gate insulating layer 412 that contacts a part of the oxide semiconductor layer 406a is formed without exposing it to the atmosphere. Then, a gate electrode 414 is formed in a region that overlaps with the oxide semiconductor layer 406a on the gate insulating layer 412, and an interlayer insulating layer 416 and an interlayer insulating layer 418 are formed on the gate insulating layer 412 and the gate electrode 414 (see Fig. 9(E)). For details, the previous embodiments can be referred to. 412 is formed. And a gate electrode 414 is formed in a region that overlaps with the oxide semiconductor layer 406a on the gate insulating layer 412, and an interlayer insulating layer 416 and an interlayer insulating layer 418 are formed on the gate insulating layer 412 and the gate electrode 414 (see Fig. 9(E)). For details, the previous embodiments can be referred to. region, and an interlayer insulating layer 416 and an interlayer insulating layer 418 are formed on the gate insulating layer 412 and the gate electrode 414 (see Fig. 9(E)). For details, the previous embodiments can be referred to. Next, a gate insulating layer 412 that contacts a part of the oxide semiconductor layer 406a is formed without exposing it to the atmosphere. Then, a gate electrode 414 is formed in a region that overlaps with the oxide semiconductor layer 406a on the gate insulating layer 412, and an interlayer insulating layer 416 and an interlayer insulating layer 418 are formed on the gate insulating layer 412 and the gate electrode 414 (see Fig. 9(E)). For details, the previous embodiments can be referred to. Next, a gate insulating layer 412 that contacts a part of the oxide semiconductor layer 406a is formed without exposing it to the atmosphere. Then, a gate electrode 414 is formed in a region that overlaps with the oxide semiconductor layer 406a on the gate insulating layer 412, and an interlayer insulating layer 416 and an interlayer insulating layer 418 are formed on the gate insulating layer 412 and the gate electrode 414 (see Fig. 9(E)). For details, the previous embodiments can be referred to.

[0208] As described above, the transistor 450 using the oxide semiconductor is completed.

[0209] In this embodiment, in order to supply oxygen to the oxide semiconductor layer 406a, the oxide semiconductor layer 4 06a is subjected to oxygen plasma treatment. Therefore, the characteristics of the transistor 450 are further improved. Also, since the region corresponding to the side surface of the source electrode or the drain electrode is oxidized, it is possible to prevent a short circuit between the gate electrode and the source electrode (or the drain electrode) that may occur due to the thinning of the gate insulating layer. Further, the oxidation regions 4 high. Also, since the region corresponding to the side surface of the source electrode or the drain electrode is oxidized, it is possible to prevent a short circuit between the gate electrode and the source electrode (or the drain electrode) that may occur due to the thinning of the gate insulating layer. Further, the oxidation regions 4 source electrode (or drain electrode) can be prevented. Also, the oxidation regions 4 source electrode (or drain electrode) can be prevented. Also, the oxidation regions 4 11a and 411b form an appropriate offset region, so that the change in the electric field from the oxide semiconductor layer to the interface with the source electrode (or drain electrode) can be kept low. layer to the interface with the source electrode (or drain electrode) can be kept low. It is also possible.

[0210] Further, by providing an insulating layer on the source electrode and the drain electrode, the capacitance (parasitic capacitance) formed between the source electrode and the drain electrode and the gate electrode can be reduced, and further high-speed operation can be realized. and the drain electrode and the gate electrode can be reduced, and further high-speed operation can be realized. operation can be realized.

[0211] Note that in this embodiment, it is a top-gate type transistor, and the source electrode and the drain Although the structure in which the lower part of the rain electrode contacts the upper part of the oxide semiconductor layer has been described, the transistor to which the structure of this embodiment can be applied is not limited to this. For example, in the case of a bottom gate type transistor, a part of the structure of this embodiment can be applied to a structure in which the lower parts of the source electrode and the drain electrode contact the upper part of the oxide semiconductor layer. That is, according to this embodiment, various transistors provided with an oxide semiconductor supplied with oxygen, an electrode having an oxidized region, etc. can be realized

[0212] As described above, the structures, methods, etc. shown in this embodiment can be used in appropriate combination with the structures, methods, etc. shown in other embodiments.

[0213] (Embodiment 6) In this embodiment, a method for manufacturing a semiconductor device using a semiconductor material other than an oxide semiconductor, specifically, a method for manufacturing the transistor 170 at the lower part of FIG. 2(A) will be described with reference to FIGS. 10 and 2 (A). (A).

[0214] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 10(A)). As the substrate 100 containing a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, an example in the case of using a single crystal silicon substrate as the substrate 100 containing a semiconductor material will be shown. In general, the "SOI substrate" refers to a substrate having a silicon layer provided on an insulating surface, but in this specification, etc., it is used as a concept including a substrate having a semiconductor layer made of a material other than silicon provided on an insulating surface. That is, "S" ​​​​​​​​The semiconductor layer included in the "OI substrate" is not limited to a silicon layer. Also, the SOI substrate includes those having a structure in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. shall be assumed.

[0215] On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see Fig. 10(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, etc. can be used. Note that before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium, etc. can be used.

[0216] Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). Thereby, a semiconductor region 104 separated from other semiconductor regions is formed (see Fig. 10(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching liquid can be appropriately selected according to the material to be etched.

[0217] Next, an insulating layer is formed so as to cover the semiconductor region 104, and by selectively removing the insulating layer in the region overlapping the semiconductor region 104, an element isolation insulating layer 106 is formed (see Fig. 10(B)). ​​​​​​​​​​​​​​The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. As methods for removing the insulating layer, there are polishing processes such as CMP and etching processes, and any of them may be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed. Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. The insulating layer will be the subsequent gate insulating layer, and it can be obtained using methods such as CVD or sputtering, including single-layer or laminated structures of films containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate with nitrogen added (HfSiON (x>0, y>0, z>0)), hafnium aluminate with nitrogen added (HfAlON (x>0, y>0, z>0)), etc. Alternatively, the surface of the semiconductor region 104 can be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above insulating layer. High-density plasma treatment can be performed using, for example, mixed gases of noble gases such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer can be, for example, 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0218]

[0219] x y z x y z

[0220] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Alternatively, a layer containing the conductive material may be formed using a semiconductor material such as polycrystalline silicon. The forming method is not particularly limited, and various film forming methods such as vapor deposition, CVD method, sputtering method, spin coating method, etc. can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is shown.

[0221] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see Fig. 10(C)).

[0222] Next, an insulating layer 112 covering the gate electrode 110 is formed (see Fig. 10(C)). Then, phosphorus (P), arsenic (As), etc. are added to the semiconductor region 104 to form an impurity region 114 with a shallow junction depth (see Fig. 10(C)). Here, phosphorus or arsenic is added to form an n-type transistor, but when forming a p-type transistor, impurities such as boron (B) or aluminum (Al) may be added. Due to the formation of the above impurity region 114, a channel formation region 116 is formed below the gate insulating layer 108 in the semiconductor region 104 (see Fig. 10(C)). Here, the concentration of the impurity to be added can be set as appropriate However, when the semiconductor element is highly miniaturized, it is desirable to increase the concentration. Also, here, the step of forming the impurity region 114 after forming the insulating layer 112 is adopted However, it may also be a step of forming the insulating layer 112 after forming the impurity region 114.

[0223] ​​​​Next, a sidewall insulating layer 118 is formed (see FIG. 10(D)). The sidewall insulating layer 118 can be self-alignedly formed by forming an insulating layer so as to cover the insulating layer 112 and then performing an anisotropic high-etching process on the insulating layer. At this time, it is preferable to partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110 and the upper surface of the impurity region 114. Note that the sidewall insulating layer 118 may not be formed for the purpose of high integration or the like. After forming the insulating layer so as to cover the insulating layer 112, the sidewall insulating layer 118 can be self-alignedly formed by performing an anisotropic high-etching process on the insulating layer. In addition, at this time, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the upper surface of the impurity region 11 4. Note that the sidewall insulating layer 118 may not be formed for the purpose of high integration or the like. Next, an insulating layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (

[0224] As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see FIG. 10(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed so as to cover the gate electrode 110, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see FIG. 10(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that becomes a low-resistance metal compound by reacting with the semiconductor material constituting the semiconductor region 104. Examples of such a metal material include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc. Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see FIG. 10(F)). When polycrystalline silicon or the like is used as the gate electrode 110, it is formed using a metal material that becomes a low-resistance metal compound by reacting with the semiconductor material constituting the semiconductor region 104. Examples of such a metal material include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc. Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see FIG. 10(F)). Note that when polycrystalline silicon or the like is used as the gate electrode 110,

[0225] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see FIG. 10(F)). Note that when polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 11 A metal compound region is also formed in the portion of the first insulating film 110 that comes into contact with the metal layer 122.

[0226] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0227] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The insulating layer 126 and the insulating layer 128 are stacked in a stacked structure. The interlayer insulating layer is not limited to the above. It may be a single layer or a laminated structure of three or more layers. After the formation of 128, the surface is planarized by CMP or etching. It is desirable.

[0228] Thereafter, openings are formed in the interlayer insulating layers 126 and 128, reaching the metal compound region 124. Form, and form a source electrode or a drain electrode 130a and a source electrode or a drain electrode 130b in the opening (see FIG. 10(H)). The source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b are formed, for example, by forming a conductive layer in a region including the opening using a PVD method, a CVD method, or the like, and then removing a part of the conductive layer using a method such as an etching process or CMP to form them.

[0229] More specifically, for example, a titanium film is thinly formed in a region including the opening by a PVD method, and a titanium nitride film is thinly formed by a CVD method, and then a tungsten film is formed so as to be embedded in the opening can be applied. Here, the titanium film formed by the PVD method reduces the oxide film (such as a natural oxide film) on the formation surface and has a function of reducing the contact resistance with the lower electrode (here, the metal compound region 124 ). Further, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material. Further, a copper film may be formed by a plating method after forming a barrier film made of titanium, titanium nitride, or the like ). In addition, when removing a part of the conductive layer to form the source electrode or the drain electrode 130a or the source electrode or the drain electrode 130b, it is desirable to process it so that its surface becomes flat

[0230] . For example, when a tungsten film is formed so as to be embedded in the opening after thinly forming a titanium film or a titanium nitride film in a region including the opening , unnecessary tungsten film, titanium film, titanium nitride film, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b By planarizing the surface including the source electrode or the drain electrode 130b, in subsequent processes, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc.

[0231] Here, only the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b in contact with the metal compound region 124 are shown, but in this process, electrodes in contact with the gate electrode 110, etc. can also be formed together. There is no particular limitation on the material that can be used as the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium can be used. Also, considering the heat treatment to be performed later, it is desirable that the source electrode or the drain electrode 130a and the source electrode or the drain electrode 130b be formed using a material having heat resistance enough to withstand the heat treatment. can be used For the materials that

[0232] As described above, the transistor 170 using the substrate 100 including the semiconductor material is formed (see Fig. 10(H)). Since the transistor 170 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment.

[0233] Note that after the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure which is a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure, ​​​​​​​A highly integrated semiconductor device can be provided.

[0234] For example, an insulating layer 138 may be formed after the above process, and an opening may be formed in the insulating layer 138. Furthermore, an electrode 142c connected to the source electrode or drain electrode 130a, and an electrode 142d connected to the source electrode or drain electrode 130b may be formed. (See FIG. 2(A).)

[0235] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0236] (Embodiment 7) In this embodiment, a method for manufacturing a semiconductor device using a semiconductor material other than an oxide semiconductor will be specifically described with reference to FIGS. 11 and 12 for the manufacturing method of the transistor 570 at the bottom of FIG. 2(B). First, the manufacturing method of an SOI substrate in which a single-crystalline semiconductor layer is provided on a base substrate will be described with reference to FIG. 11, and then the manufacturing method of a transistor using the SOI substrate will be described with reference to FIG. 12.

[0237] <Manufacturing method of SOI substrate> First, a base substrate 500 is prepared (see FIG. 11(A)). As the base substrate 500, a substrate made of an insulator can be used. Specifically, various glass substrates used in the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, quartz substrates, ceramic substrates, sapphire substrates can be mentioned. Also, a ceramic substrate mainly composed of silicon nitride and aluminum oxide and having a thermal expansion coefficient close to that of silicon may be used.

[0238] The base substrate 500 may be a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate. When a semiconductor substrate is used as the base substrate 500, a glass substrate is used. The upper limit of the heat treatment temperature is higher than when using a substrate, so it is possible to obtain a high-quality SOI substrate. Here, the semiconductor substrate is solar cell grade silicon (SOG-Si A polycrystalline silicon (Solar Grade Silicon) substrate may also be used. A conductive substrate may be used. When using solar cell grade silicon or polycrystalline semiconductor substrate, In comparison with the case where a single crystal silicon substrate is used, the manufacturing cost can be reduced. do.

[0239] In this embodiment mode, a case where a glass substrate is used as the base substrate 500 will be described. By using a glass substrate, which is inexpensive and can be made large, as the base substrate 500, the cost can be reduced. It is possible to streamline the process.

[0240] It is preferable that the surface of the base substrate 500 be cleaned in advance. Specifically, a mixture of hydrochloric acid and hydrogen peroxide (HPM), sulfuric acid, and hydrogen peroxide is applied to the base substrate 500. SPM, APM, Dilute Hydrogen Peroxide (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. By carrying out such a cleaning process, the flatness of the surface of the base substrate 500 can be improved and the base This achieves the removal of abrasive particles remaining on the surface of the base substrate 500, etc.

[0241] Next, a nitrogen-containing layer 502 (e.g., a silicon nitride film (SiN x ) and silicon oxynitride film (SiNx O y including an insulating film containing nitrogen such as )(x>y) layer) is formed (see FIG. 11(B)). The nitrogen-containing layer 502 can be formed by using a CVD method, sputtering method or the like.

[0242] In the present embodiment, the nitrogen-containing layer 502 formed becomes a layer (bonding layer) for bonding a single-crystalline semiconductor layer later. Further, the nitrogen-containing layer 502 also functions as a barrier layer for preventing impurities such as sodium (Na) contained in the base substrate from diffusing into the single-crystalline semiconductor layer. functions.

[0243] As described above, in the present embodiment, since the nitrogen-containing layer 502 is used as a bonding layer, it is preferable to form the nitrogen-containing layer 502 so that its surface has a predetermined flatness. Specifically , the average surface roughness (Ra, also referred to as arithmetic mean roughness) of the surface is 0.5 nm or less, and the root mean square roughness (Rms) is 0.60 nm or less. More preferably, the average surface roughness is 0.35 nm or less, and the root mean square average roughness is 0.45 nm or less. The nitrogen-containing layer 502 is formed so as to satisfy the above conditions. Note that the above average surface roughness and root mean square roughness can be measured in, for example, a 10 μm × 10 μm region. The film thickness is in the range of 10 nm or more and 200 nm or less, preferably 50 nm or more and 100 nm or less. By increasing the flatness of the surface in this way, it is possible to prevent defective bonding of the single-crystalline semiconductor layer .

[0244] Next, a bond substrate is prepared. Here, a single-crystalline semiconductor substrate 510 is used as the bond substrate (see FIG. 11(C)). Here, although a single-crystalline substrate is used as the bond substrate , it is not necessary to limit the crystallinity of the bond substrate to single-crystalline.

[0245] ​ As the single-crystalline semiconductor substrate 510, for example, a single-crystalline silicon substrate, a single-crystalline germanium substrate, a single-crystalline silicon germanium substrate, etc., a single-crystalline semiconductor substrate composed of Group 14 elements can be used. Also, a compound semiconductor substrate such as gallium arsenide or indium phosphide can be used. As commercially available silicon substrates, those having a circular shape with a diameter of 5 inches (125 mm), 6 inches (150 mm), 8 inches (200 mm), 12 inches (300 mm), 16 inches (400 mm) are typical. Note that the shape of the single-crystalline semiconductor substrate 510 is not limited to circular, and it may be processed into, for example, a rectangular shape. Also, the single-crystalline semiconductor substrate 510 can be manufactured using the CZ (Czochralski) method or the FZ (floating zone) method. On the surface of the single-crystalline semiconductor substrate 510, an oxide film 512 is formed (see Fig. 11(D)). Note that from the viewpoint of removing contaminants, before forming the oxide film 512, a hydrochloric acid hydrogen peroxide water mixed solution (HPM

[0246] ), a sulfuric acid hydrogen peroxide water mixed solution (SPM), an ammonia hydrogen peroxide water mixed solution (APM), dilute hydrofluoric acid (DHF), FPM (a mixed solution of hydrofluoric acid, hydrogen peroxide water, and pure water), etc. are preferably used to clean the surface of the single-crystalline semiconductor substrate 510. The surface may be cleaned by alternately discharging dilute hydrofluoric acid and ozone water.

[0247] The oxide film 512 can be formed, for example, as a single layer or by laminating a silicon oxide film, a silicon oxynitride film, etc. As a method for manufacturing the above oxide film 512, there are a thermal oxidation method, a CVD method, a sputtering method, etc. Also, when forming the oxide film 512 using the CVD method, ​, To achieve good bonding, it is preferable to form a silicon oxide film using an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si(OC 2 H 5 ) 4 ) and the like. preferable.

[0248] In this embodiment, a thermal oxidation treatment is performed on the single crystal semiconductor substrate 510 to form an oxide film 512 (here, SiO x film). The thermal oxidation treatment is preferably performed by adding a halogen to an oxidizing atmosphere. preferable.

[0249] For example, by performing a thermal oxidation treatment on the single crystal semiconductor substrate 510 in an oxidizing atmosphere to which chlorine (Cl) is added, an oxide film 512 oxidized by chlorine can be formed. In this case, the oxide film 512 becomes a film containing chlorine atoms. By such chlorine oxidation, heavy metals (for example, Fe, Cr, Ni, Mo, etc.), which are exogenous impurities, are collected to form metal chlorides, and these can be removed to the outside to reduce the contamination of the single crystal semiconductor substrate 510. Also, after bonding with the base substrate 500, impurities such as Na from the base substrate can be fixed, and contamination of the single crystal semiconductor substrate 510 can be prevented.

[0250] Note that the halogen atom contained in the oxide film 512 is not limited to a chlorine atom. The oxide film 512 may contain a fluorine atom. As a method of fluorine oxidizing the surface of the single crystal semiconductor substrate 510, a method of immersing it in an HF solution and then performing a thermal oxidation treatment in an oxidizing atmosphere, or a method of adding NF 3 to an oxidizing atmosphere and performing a thermal oxidation treatment, etc. are available.

[0251] Next, ions are accelerated by an electric field and irradiated onto the single crystal semiconductor substrate 510, and by adding them, a brittle region 514 where the crystal structure is damaged is formed at a predetermined depth of the single crystal semiconductor substrate 510 (see Fig. 1(E)). The depth of the region where the brittle region 514 is formed can be adjusted by the kinetic energy of the ions, the mass and charge, the incident angle of the ions, etc. Also, the brittle region 514 is formed in a region having substantially the same depth as the average penetration depth of the ions. Therefore, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 510 can be adjusted at the depth where the ions are added. For example, the average penetration depth may be adjusted so that the thickness of the single crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably about 50 nm or more and 200 nm or less.

[0252] The irradiation treatment of the ions can be performed using an ion doping apparatus or an ion implantation apparatus. As a typical example of an ion doping apparatus, there is a non-mass separation type apparatus that irradiates all ion species generated by plasma-exciting a process gas onto an object to be processed. In this apparatus, the ion species in the plasma are irradiated onto the object to be processed without mass separation. On the other hand, an ion implantation apparatus is a mass separation type apparatus. In an ion implantation apparatus, the ion species in the plasma are mass-separated, and an ion species of a specific mass is irradiated onto the object to be processed.

[0253] In this embodiment, an example of adding hydrogen to the single crystal semiconductor substrate 510 using an ion doping apparatus will be described. As the source gas, a gas containing hydrogen is used. Regarding the ions to be irradiated, it is preferable to increase the ratio of H

[0254] 3 + Specifically, H + H​​​​​​​​​​​​​​2 + , H 3 + total of For the amount, the proportion of H 3 + is made to be 50% or more (more preferably 80% or more). H 3 + By increasing the proportion of H, the efficiency of ion irradiation can be improved.

[0255] Note that the ions to be added are not limited to hydrogen. Ions such as helium may be added. Also, the ions to be added are not limited to one type, and multiple types of ions may be added. For example, when simultaneously irradiating hydrogen and helium using an ion doping apparatus, the number of processes can be reduced compared to the case of irradiating in separate processes, and it is possible to suppress the surface roughness of the subsequent single-crystal semiconductor layer.

[0256] Note that when forming the embrittlement region 514 using an ion doping apparatus, heavy metals may also be added simultaneously. However, by performing ion irradiation through the oxide film 512 containing halogen atoms, contamination of the single-crystal semiconductor substrate 510 by these heavy metals can be prevented.

[0257] Next, the base substrate 500 and the single-crystal semiconductor substrate 510 are opposed to each other, and the surface of the nitrogen-containing layer 502 and the oxide film 512 are brought into close contact with each other. Thereby, the base substrate 500 and the single-crystal semiconductor substrate 510 are bonded together (see Fig. 11(F)).

[0258] At the time of bonding, at one location on the base substrate 500 or the single-crystal semiconductor substrate 510, 0. 001 N / cm 2 or more and 100 N / cm 2 or less, for example, 1 N / cm​2 20 N / cm or more 2 It is desirable to apply the following pressure. When the pressure is applied to bring the bonding surfaces closer and into close contact, bonding between the nitrogen-containing layer 502 and the oxide film 512 occurs at the portion where they are in close contact, and spontaneous bonding occurs almost entirely starting from this portion. This bonding is effected by van der Waals forces and hydrogen bonds, and can be carried out at room temperature.

[0259] Before bonding the single-crystalline semiconductor substrate 510 and the base substrate 500, it is preferable to perform surface treatment on the surface related to the bonding. By performing surface treatment, the bonding strength at the interface between the single-crystalline semiconductor substrate 510 and the base substrate 500 can be improved.

[0260] As the surface treatment, wet treatment, dry treatment, or a combination of wet treatment and dry treatment can be used. Also, different wet treatments can be combined and used, or different dry treatments can be combined and used.

[0261] After bonding, heat treatment may be performed to increase the bonding strength. The temperature of this heat treatment should be a temperature at which separation in the embrittlement region 514 does not occur (for example, room temperature or higher and less than 400 °C ). Also, while heating within this temperature range, the nitrogen-containing layer 502 and the oxide film 512 may be bonded. For the above heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (rapid thermal anneal) apparatus, a microwave heating apparatus, etc. can be used. Note that the above temperature conditions are merely an example, and one aspect of the disclosed invention should not be construed as being limited thereto.

[0262] Next, by performing heat treatment, the single-crystal semiconductor substrate 510 is separated in the embrittled region, and a single-crystal semiconductor layer 5 16 is formed on the base substrate 500 via a nitrogen-containing layer 502 and an oxide film 512 (see FIG. 11(G)).

[0263] Note that it is desirable that the heat treatment temperature during the above separation be as low as possible. This is because the lower the temperature during separation, the more the surface roughness of the single-crystal semiconductor layer 516 can be suppressed. Specifically, for example, the heat treatment temperature during the above separation may be 300°C or higher and 600°C or lower, and it is more effective if it is 400°C or higher and 500°C or lower.

[0264] Note that after separating the single-crystal semiconductor substrate 510, the single-crystal semiconductor layer 516 may be heat-treated at a temperature of 50 0°C or higher to reduce the concentration of hydrogen remaining in the single-crystal semiconductor layer 516.

[0265] Next, by irradiating the surface of the single-crystal semiconductor layer 516 with laser light, a single-crystal semiconductor layer 518 with improved surface flatness and reduced defects is formed. Note that instead of the irradiation treatment with laser light, heat treatment may be performed.

[0266] Note that in the present embodiment, the irradiation treatment with laser light is performed immediately after the heat treatment related to the separation of the single-crystal semiconductor layer 516. However, one aspect of the disclosed invention is not construed as being limited to this. After performing an etching treatment after the heat treatment related to the separation of the single-crystal semiconductor layer 516 to remove a region with many defects on the surface of the single-crystal semiconductor layer 516, the irradiation treatment with laser light may be performed, and after improving the surface flatness of the single-crystal semiconductor layer 516, the irradiation treatment with laser light may be performed. This is also acceptable. Note that, as the etching process, either wet etching or dry etching may be used. Also, in this embodiment, after irradiating the laser light as described above, a thinning process may be performed to reduce the film thickness of the single-crystal semiconductor layer 516. For thinning the single-crystal semiconductor layer 516, either dry etching or wet etching, or both may be used.

[0267] Through the above steps, an SOI substrate having a single-crystal semiconductor layer 518 with good characteristics can be obtained (see Fig. 11(H)).

[0268] <Manufacturing method of transistor> Next, a method for manufacturing a transistor 570 using the above SOI substrate will be described with reference to Fig. 12.

[0269] Fig. 12(A) is a cross-sectional view showing a part of the SOI substrate manufactured by the method shown in Fig. 11.

[0270] First, the single-crystal semiconductor layer 518 is processed into an island shape to form a semiconductor layer 520 (see Fig. 12(B ). Note that, before and after this step, in order to control the threshold voltage of the transistor, impurities that impart n-type conductivity or impurities that impart p-type conductivity may be added to the semiconductor layer. When the semiconductor is silicon, as impurities that impart n-type conductivity, for example, , phosphorus, arsenic, etc. can be used. Also, as impurities that impart p-type conductivity, , for example, boron, aluminum, gallium, etc. can be used.

[0271] Next, an insulating layer 522 is formed so as to cover the semiconductor layer 520 (see Fig. 12(C)). The insulating layer 522 will later become the gate insulating layer. Here, the plasma CVD method is used Then, a single-layer silicon oxide film is to be formed. The material and formation method of the insulating layer 522 are such that reference can be made to the description of the gate insulating layer (such as the gate insulating layer 108) according to the previous embodiment.

[0272] Next, after forming a conductive layer on the insulating layer 522, the conductive layer is selectively etched to form a gate electrode 524 above the semiconductor layer 520 (see FIG. 12(D)). The material and formation method of the gate electrode 52 4 are such that reference can be made to the description of the gate electrode (such as the gate electrode 110) according to the previous embodiment.

[0273] Next, using the gate electrode 524 as a mask, impurities for imparting one conductivity type are added to the semiconductor layer 520 to form an impurity region 526 (see FIG. 12(E)). Here, for forming an n-type transistor, phosphorus (P) or arsenic (As) is added, but when forming a p-type transistor, impurities such as boron (B) or aluminum (Al) may be added. Here, the concentration of the added impurities can be set as appropriate.

[0274] Next, a sidewall insulating layer 528 is formed on the side surface of the gate electrode 524. The sidewall insulating layer 528 can be self-alignedly formed by forming an insulating layer so as to cover the insulating layer 522 and the gate electrode 524 and then applying an anisotropic etching process to the insulating layer. At this time, it is preferable to partially etch the insulating layer 522 to form a gate insulating layer 5 22a and expose the impurity region 526.

[0275] Next, using the gate electrode 524 and the sidewall insulating layer 528 as masks, one conductivity type is ​​​​​​​​​​The impurity element to be imparted is added to the impurity region 526. Note that the impurity element to be added to the impurity region 526 is an impurity element having the same conductivity type as the impurity element added in the previous step. And its concentration is made higher than that in the previous step. By adding the impurity element, a pair of high-concentration impurity regions 530, a pair of low-concentration impurity regions 532, and a channel formation region 534 are formed in the semiconductor layer 520 (see Fig. 12(G)). The high-concentration impurity region 530 functions as a source region or a drain region. Note that when the semiconductor layer 520 is made of a material containing silicon, in order to further reduce the resistance of the source region and the drain region, a silicide region obtained by siliciding a part of the semiconductor layer 520 may be formed. The siliciding is performed by bringing a metal into contact with the semiconductor layer and reacting silicon and the metal in the semiconductor layer by heat treatment (for example, GRTA method, LRTA method, etc.). As the silicide region, cobalt silicide or nickel silicide may be formed. When the semiconductor layer 520 is thin, the silicide reaction may proceed to the bottom of the semiconductor layer 520. Examples of the metal material that can be used for siliciding include titanium, nickel, tungsten, molybdenum, cobalt, zirconium, hafnium, tantalum, vanadium, neodymium, chromium, platinum, palladium, etc. Also, a silicide region can be formed by irradiation with laser light or the like. Next, an interlayer insulating layer 536 and an interlayer insulating layer 538 are formed so as to cover each component formed by the above-described steps (see Fig. 12(H)). The interlayer insulating layer 536 and the interlayer insulating layer 538 are made of an oxide.

[0276]

[0277] Materials including inorganic insulating materials such as silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. can be used for formation. Also, it is possible to form using organic insulating materials such as polyimide and acrylic resin. Here, although a laminated structure of the interlayer insulating layer 536 and the interlayer insulating layer 538 is shown, one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. After the formation of the interlayer insulating layer 538, it is desirable to planarize its surface by CMP, etching treatment, etc. Next, openings reaching the high-concentration impurity region 530 are formed in the interlayer insulating layers 536 and 538, and a source electrode or drain electrode 540a and a source electrode or drain electrode 540b are formed in the openings (see Fig. 12(H)). The materials and manufacturing methods of the source electrode or drain electrode 540a and the source electrode or drain electrode 540b may be referred to the descriptions regarding the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, etc. As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment. Note that after the above steps, electrodes, wirings, insulating layers, etc. may be further formed. The structure of the wiring It can be formed using materials including inorganic insulating materials such as silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form using organic insulating materials such as polyimide and acrylic resin. Here, although a laminated structure of the interlayer insulating layer 536 and the interlayer insulating layer 538 is shown, one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. After the formation of the interlayer insulating layer 538, it is desirable to planarize its surface by CMP, etching treatment, etc. Next, openings reaching the high-concentration impurity region 530 are formed in the interlayer insulating layers 536 and 538, and a source electrode or drain electrode 540a and a source electrode or drain electrode 540b are formed in the openings (see Fig. 12(H)). The materials and manufacturing methods of the source electrode or drain electrode 540a and the source electrode or drain electrode 540b may be referred to the descriptions regarding the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, etc. As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment.

[0278] Next, openings reaching the high-concentration impurity region 530 are formed in the interlayer insulating layers 536 and 538, and a source electrode or drain electrode 540a and a source electrode or drain electrode 540b are formed in the openings (see Fig. 12(H)). The materials and manufacturing methods of the source electrode or drain electrode 540a and the source electrode or drain electrode 540b may be referred to the descriptions regarding the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, etc. As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment. Note that after the above steps, electrodes, wirings, insulating layers, etc. may be further formed. The structure of the wiring It can be formed using materials including inorganic insulating materials such as silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form using organic insulating materials such as polyimide and acrylic resin. Here, although a laminated structure of the interlayer insulating layer 536 and the interlayer insulating layer 538 is shown, one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. After the formation of the interlayer insulating layer 538, it is desirable to planarize its surface by CMP, etching treatment, etc. Next, openings reaching the high-concentration impurity region 530 are formed in the interlayer insulating layers 536 and 538, and a source electrode or drain electrode 540a and a source electrode or drain electrode 540b are formed in the openings (see Fig. 12(H)). The materials and manufacturing methods of the source electrode or drain electrode 540a and the source electrode or drain electrode 540b may be referred to the descriptions regarding the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, etc. As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment.

[0279] As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment. Note that after the above steps, electrodes, wirings, insulating layers, etc. may be further formed. The structure of the wiring It can be formed using materials including inorganic insulating materials such as silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form using organic insulating materials such as polyimide and acrylic resin. Here, although a laminated structure of the interlayer insulating layer 536 and the interlayer insulating layer 538 is shown, one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. After the formation of the interlayer insulating layer 538, it is desirable to planarize its surface by CMP, etching treatment, etc. Next, openings reaching the high-concentration impurity region 530 are formed in the interlayer insulating layers 536 and 538, and a source electrode or drain electrode 540a and a source electrode or drain electrode 540b are formed in the openings (see Fig. 12(H)). The materials and manufacturing methods of the source electrode or drain electrode 540a and the source electrode or drain electrode 540b may be referred to the descriptions regarding the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, etc. As described above, the transistor 570 using the SOI substrate is formed (see Fig. 12(H)). Since the transistor 570 using a material other than the oxide semiconductor can operate at high speed, a logic circuit (also referred to as an arithmetic circuit) etc. can be configured using the transistor. Also, it can be used for a drive circuit etc. for driving the memory circuit shown in the previous embodiment.

[0280] Note that after the above steps, electrodes, wirings, insulating layers, etc. may be further formed. The structure of the wiring By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer, a highly integrated semiconductor device can be provided.

[0281] As described above, the configurations, methods, etc. shown in the present embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0282] (Embodiment 8) In the present embodiment, an application example of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 13 and 1 4.

[0283] FIGS. 13(A) and 13(B) are circuit diagrams of a semiconductor device formed by using a plurality of semiconductor devices (hereinafter also referred to as memory cell 190) shown in FIG. 5(A-1). FIG. 13(A ) is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 190 are connected in series. FIG. 13(B) is a circuit diagram of a so-called NOR type semiconductor device in which memory cells 190 are connected in parallel.

[0284] The semiconductor device shown in FIG. 13(A) includes a source line SL, a bit line BL, a first signal line S1, m second signal lines S2, m word lines WL, and a plurality of memory cells 190(1, 1) to 190 (m, 1) arranged in m (rows) × 1 (column) vertically. In FIG. 13(A), the source line SL and the bit line BL are configured to have one each, but the present invention is not limited to this. By having n source lines SL and n bit lines BL, a configuration having a memory cell array of m (rows) × n (columns ) may be adopted.

[0285] In each memory cell 190, the gate electrode of the transistor 160 and the transistor 162 One of the source electrodes or drain electrodes is electrically connected to one of the electrodes of the capacitor element 164. Also, the first signal line S1 is electrically connected to the other of the source electrode or drain electrode of the transistor 162, and the second signal line S2 is electrically connected to the gate electrode of the transistor 162. And the word line WL is electrically connected to the other of the electrodes of the capacitor element 164. Also, the source electrode of the transistor 160 included in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 of the adjacent memory cell 190, and the drain electrode of the transistor 160 included in the memory cell 190 is electrically connected to the source electrode of the transistor 160 of the adjacent memory cell 190. However, among a plurality of memory cells connected in series, the drain electrode of the transistor 160 included in the memory cell 190 provided at one end is electrically connected to the bit line.

[0286] Also, the source electrode of the transistor 160 included in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 of the adjacent memory cell 190, and the drain electrode of the transistor 160 included in the memory cell 190 is electrically connected to the source electrode of the transistor 160 of the adjacent memory cell 190. However, among a plurality of memory cells connected in series, the drain electrode of the transistor 160 included in the memory cell 190 provided at one end is electrically connected to the bit line. Also, the source electrode of the transistor 160 included in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 of the adjacent memory cell 190, and the drain electrode of the transistor 160 included in the memory cell 190 is electrically connected to the source electrode of the transistor 160 of the adjacent memory cell 190. However, among a plurality of memory cells connected in series, the drain electrode of the transistor 160 included in the memory cell 190 provided at one end is electrically connected to the bit line. Also, the source electrode of the transistor 160 included in the memory cell 190 provided at the other end of a plurality of memory cells connected in series is electrically connected to the source line. The semiconductor device shown in FIG. 13(A) performs a write operation and a read operation for each row. The write operation is performed as follows. A potential that turns on the transistor 162 is applied to the second signal line S2 of the row to be written, and the transistor 162 of the row to be written is turned on.

[0287] Thereby, the potential of the first signal line S1 is applied to the gate electrode of the transistor 160 of the specified row, and a predetermined charge is applied to the gate electrode. In this way, data can be written into the memory cells of the specified row. The write operation is performed as follows. A potential that turns on the transistor 162 is applied to the second signal line S2 of the row to be written, and the transistor 162 of the row to be written is turned on. Thereby, the potential of the first signal line S1 is applied to the gate electrode of the transistor 160 of the specified row, and a predetermined charge is applied to the gate electrode. In this way, data can be written into the memory cells of the specified row.

[0288] Also, the read operation is performed as follows. First, a potential is applied to the word lines WL other than the line where reading is to be performed, regardless of the charge on the gate electrode of the transistor 160, to turn on the transistors 160 other than the line where reading is to be performed. Then, a potential (read potential) is applied to the word line WL of the line where reading is to be performed such that the on-state or off-state of the transistor 160 is selected according to the charge on the gate electrode of the transistor 160. Then, a constant potential is applied to the source line SL, and a read circuit (not shown) connected to the bit line BL is brought into an operating state. Here, since the plurality of transistors 160 between the source line SL and the bit line BL are in an on-state except for the line where reading is to be performed, the conductance between the source line SL and the bit line BL is determined by the state of the transistor 160 of the line where reading is to be performed. That is, the potential of the bit line BL read by the read circuit differs depending on the charge on the gate electrode of the transistor 160 of the line where reading is to be performed. In this way, data can be read from the memory cell of the specified line. The semiconductor device shown in FIG. 13(B) includes n source lines SL, bit lines BL and a first signal line S1, m second signal lines S2 and word lines WL, and a plurality of memory cells 190(1, 1 )~190(m, n) are arranged in a matrix of m (rows) × n (columns) to form a memory cell array 181. One of the gate electrodes of each transistor 160, one of the source electrodes or drain electrodes of the transistor 160, and one of the electrodes of the capacitor element 164 are electrically connected. Also, the source line SL and the source electrode of the transistor 160 are electrically connected.

[0289] The semiconductor device shown in FIG. 13(B) has n source lines SL, bit lines BL, and a first signal line S1, m second signal lines S2, word lines WL, and a plurality of memory cells 190(1, 1 )~190(m, n) arranged in a matrix of m (rows) × n (columns) to form a memory cell array 181. One of the gate electrodes of each transistor 160, one of the source electrodes or drain electrodes of the transistor 160, and one of the electrodes of the capacitor element 164 are electrically connected. Also, the source line SL and the source electrode of the transistor 160 are electrically connected. ​​​is connected, and the bit line BL and the drain electrode of the transistor 160 are electrically connected are. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 on the other side are electrically connected, and the second signal line S2 and the gate electrode of the transistor 162 are electrically connected. And the word line WL and the other electrode of the capacitor element 164 are electrically connected

[0290] The semiconductor device shown in Fig. 13(B) performs a write operation and a read operation for each row. The write operation is performed in the same manner as the semiconductor device shown in Fig. 13(A) described above. The read operation is performed as follows. First, a potential is applied to the word lines WL other than the row for which reading is to be performed such that the transistor 160 is in the off state regardless of the charge on the gate electrode of the transistor 160, turning off the transistors 160 other than the row for which reading is to be performed. Then, a potential (read potential ) is applied to the word line WL of the row for which reading is to be performed such that the on state or the off state of the transistor 160 is selected by the charge on the gate electrode of the transistor 160. And a constant potential is applied to the source line SL to put the readout circuit (not shown) connected to the bit line BL into an operating state. Here, the conductance between the source line SL and the bit line BL is determined by the state of the transistor 160 in the row for which reading is to be performed. That is, the potential of the bit line BL read by the readout circuit differs depending on the charge on the gate electrode of the transistor 160 in the row for which reading is to be performed. In this way, data can be read from the memory cell of the specified row ) is applied. And a constant potential is applied to the source line SL to put the readout circuit (not shown) connected to the bit line BL into an operating state. Here, the conductance between the source line SL and the bit line BL is determined by the state of the transistor 160 in the row for which reading is to be performed. That is, the potential of the bit line BL read by the readout circuit differs depending on the charge on the gate electrode of the transistor 160 in the row for which reading is to be performed. In this way, data can be read from the memory cell of the specified row

[0291] Next, an example of a readout circuit that can be used in the semiconductor device shown in Fig. 13 and the like will be described with reference to Fig. 1​​​​​​​​ This will be described with reference to 4.

[0292] Fig. 14(A) shows an outline of the read circuit. The read circuit includes a transistor and a sense amplifier circuit.

[0293] At the time of reading, terminal A is connected to a bit line to which a memory cell that performs reading is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and the potential of terminal A is controlled.

[0294] Memory cell 190 exhibits different resistance values according to the data stored therein. Specifically, when the transistor 160 of the selected memory cell 190 is in the on state, it is in a low resistance state, and when the transistor 160 of the selected memory cell 190 is in the off state, it is in a high resistance state. .

[0295] When the memory cell is in the high resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A. On the other hand, when the memory cell is in the low resistance state, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "0") corresponding to the potential of terminal A.

[0296] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit of this embodiment is an example. Other known circuits may be used. In addition, the read circuit may include a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected.

[0297] FIG. 14(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output.

[0298] FIG. 14(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signal Sp is set to High and the control signal Sn is set to Low to cut off the power supply potential (Vdd). Then, the potentials for comparison are applied to V1 and V2. After that, when the control signal Sp is set to Low and the control signal Sn is set to High to supply the power supply potential (Vdd), if the potentials for comparison V1in and V2in are in the relationship V1in > V2in, the output of V1 is Hi gh and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is L ow and the output of V2 is High. Utilizing such a relationship, the difference between V1in and V2in can be amplified.

[0299] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0300] (Embodiment 9) In this embodiment, an example of a semiconductor device using the transistor shown in the previous embodiment will be described with reference to FIG. 15.

[0301] ​​​​FIG. 15(A) shows an example of a semiconductor device having a configuration corresponding to a so-called DRAM (Dynamic Random Access Memory). The memory cell array 620 shown in FIG. 15(A) has a configuration in which a plurality of memory cells 630 are arranged in a matrix . Further, the memory cell array 620 has m first wirings and n second wirings . Note that the memory cell 630 corresponds to the semiconductor device shown in FIG. 5(B). In the present embodiment, the first wiring in FIG. 5(B) is referred to as a bit line BL, and the second wiring is referred to as a word line WL .

[0302] The memory cell 630 includes a transistor 631 and a capacitor element 632 . The gate electrode of the transistor 631 is connected to the first wiring (word line WL). Also , one of the source electrode or the drain electrode of the transistor 631 is connected to the second wiring (bit line BL), and the other of the source electrode or the drain electrode of the transistor 631 is connected to one of the electrodes of the capacitor element. The other electrode of the capacitor element is connected to a capacitor line CL and is given a constant potential. The transistor shown in the previous embodiment is applied to the transistor 631 .

[0303] The transistor shown in the previous embodiment has a feature that the off-current is extremely small . Therefore, when the transistor is applied to the semiconductor device shown in FIG. 15(A) which is recognized as a so-called DRAM , it is possible to obtain a substantial non-volatile memory

[0304] FIG. 15(B) shows an example of a so-called SRAM (Static Random Access M An example of a semiconductor device having a configuration corresponding to (emory) is shown. The memory cell shown in FIG. 15(B) The memory cell array 640 may have a configuration in which a plurality of memory cells 650 are arranged in a matrix and. The memory cell array 640 also has a plurality of first wirings (word lines WL), second wirings ( bit lines BL), and third wirings (inverted bit lines / BL).

[0305] The memory cell 650 has first transistors 651 to sixth transistors 656 . The first transistor 651 and the second transistor 652 function as selection transistors . Also, among the third transistor 653 and the fourth transistor 654, one is an n-channel transistor (here, the fourth transistor 654), and the other is a p-channel transistor (here, the third transistor 653). That is, a CMOS circuit is formed by the third transistor 653 and the fourth transistor 654 . Similarly, a CMOS circuit is formed by the fifth transistor 655 and the sixth transistor 656 .

[0306] The first transistor 651, the second transistor 652, the fourth transistor 654, and the sixth transistor 656 are n-channel transistors, and the transistors shown in the previous embodiments can be applied . The third transistor 653 and the fifth transistor 655 are p-channel transistors and can be formed using an oxide semiconductor or other materials (for example, silicon, etc.).

[0307] The configurations, methods, etc. shown in this embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments ​They can be used in combination.

[0308] (Embodiment 10) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, it will be described with reference to FIG. 16. In this embodiment, when applying the above semiconductor device to an electronic device such as a computer, a mobile phone (also referred to as a cellular phone, a mobile phone device), a portable information terminal (including a portable game machine, an audio playback device, etc.), a camera such as a digital camera, a digital video camera, an electronic paper, a television device (also referred to as a television or a television receiver), it will be described.

[0309] FIG. 16(A) is a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. Inside the housing 701 and the housing 702, the semiconductor device shown in the previous embodiment is provided. The semiconductor device shown in the previous embodiment can write and read information at high speed, can retain memory for a long time, and has sufficiently reduced power consumption. Therefore, a notebook personal computer that can write and read information at high speed, can retain memory for a long time, and has sufficiently reduced power consumption is realized.

[0310] FIG. 16(B) is a portable information terminal (PDA). The main body 711 is provided with a display unit 713, an external interface 715, operation buttons 714, etc. In addition, it is equipped with a stylus 712 for operating the portable information terminal. Inside the main body 711, the semiconductor device shown in the previous embodiment is provided. The semiconductor device shown in the previous embodiment can write information and has fast reading speed, can retain memory for a long time, and has sufficiently reduced power consumption Therefore, a portable information terminal capable of fast writing and reading of information, retaining memory for a long time, and having sufficiently reduced power consumption is realized.

[0311] FIG. 16(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two casings, a casing 721 and a casing 72 3. Display units 7 25 and a display unit 727 are respectively provided on the casing 721 and the casing 723. The casing 721 and the casing 723 are connected by a shaft portion 737 and can perform an opening / closing operation about the shaft portion 737 as an axis. Further, the casing 7 21 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the casing 721 and the casing 723 is provided with the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment has fast writing and reading speeds of information, can retain memory for a long time, and has sufficiently reduced power consumption. Therefore, an electronic book with fast writing and reading of information, capable of retaining memory for a long time, and having sufficiently reduced power consumption is realized.

[0312] FIG. 16(D) shows a mobile phone, which is composed of two casings, a casing 740 and a casing 741. Further, the casing 740 and the casing 741 can slide and be overlapped from the state of being unfolded as shown in FIG. 16(D), enabling miniaturization suitable for portability. Also, the casing 741 is provided with a display panel 742, a speaker 743, a microphone 744, operation keys 745, a pointing device 746, a camera lens 747, an external connection terminal 74 ​​​​It includes 8 etc. Further, the housing 740 has a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. Further, the antenna is built in the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment enables high-speed writing and reading of information, long-term memory retention, and sufficient reduction of power consumption. Therefore, a mobile phone is realized in which writing and reading of information are fast, long-term memory retention is possible, and power consumption is sufficiently reduced. Therefore, a mobile phone in which writing and reading of information are fast, long-term memory retention is possible, and power consumption is sufficiently reduced is realized.

[0313] Fig. 16(E) is a digital camera, which is composed of a main body 761, a display unit 767, an eyepiece 763, an operation switch 764, a display unit 765, a battery 766, etc. Inside the main body 761, the semiconductor device shown in the previous embodiment is provided. The semiconductor device shown in the previous embodiment enables high-speed writing and reading of information, long-term memory retention, and sufficient reduction of power consumption. The semiconductor device shown in the previous embodiment enables high-speed writing and reading of information, long-term memory retention, and sufficient reduction of power consumption. Therefore, a digital camera is realized in which writing and reading of information are fast, long-term memory retention is possible, and power consumption is sufficiently reduced. Therefore, a digital camera in which writing and reading of information are fast, long-term memory retention is possible, and power consumption is sufficiently reduced is realized.

[0314] Fig. 16(F) is a television device 770, which is composed of a housing 771, a display unit 773, a stand 775, etc. The operation of the television device 770 can be performed by switches provided in the housing 771 and a remote control operation unit 780. The housing 771 and the remote control operation unit 780 are equipped with the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment enables high-speed writing and reading of information, long-term memory retention, and sufficient reduction of power consumption. The semiconductor device shown in the previous embodiment enables high-speed writing and reading of information, long-term memory retention, and sufficient reduction of power consumption. and the power consumption is sufficiently reduced. Therefore, high-speed writing and reading of information are possible, long-term memory retention is achievable, and a television device with sufficiently reduced power consumption is realized.

[0315] As described above, the electronic device shown in this embodiment incorporates the semiconductor device according to the previous embodiment. Therefore, an electronic device with reduced power consumption is realized.

Example

[0316] An investigation was conducted on the number of rewritable times of the semiconductor device according to one aspect of the disclosed invention. In this example, the investigation results will be described with reference to FIG. 17.

[0317] The semiconductor device used in the investigation is the semiconductor device with the circuit configuration shown in FIG. 5(A-1). Here, an oxide semiconductor was used for the transistor corresponding to transistor 162. Also, as the capacitor element corresponding to capacitor element 164, one with a capacitance value of 0.33 pF was used.

[0318] The investigation was carried out by comparing the initial memory window width with the memory window width after repeatedly holding and writing data a predetermined number of times. Holding and writing of data were performed by applying either 0V or 5V to the wiring corresponding to the third wiring in FIG. 5(A-1) and applying either 0V or 5V to the wiring corresponding to the fourth wiring. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor corresponding to transistor 162 is in the off state, so the potential applied to the floating gate portion FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the off state, so the potential applied to the floating gate portion FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the off state, so the potential applied to the floating gate portion FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the off state, so the potential applied to the floating gate portion FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5V, the ​​Since the transistor corresponding to the transistor 162 is in the on state, the potential of the wiring corresponding to the third wiring is applied to the floating gate portion FG. The potential of the wiring corresponding to the third wiring is applied to the floating gate portion FG.

[0319] The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The potential of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. The shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to the transistor 160 between different memory states is defined. Different memory states refer to the state in which 0V is applied to the floating gate portion FG (hereinafter referred to as the Low state) and the state in which 5V is applied to the floating gate portion FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Also, in the case of deviation, Vds = 1V was set. Also, in the case of deviation, Vds = 1V was set.

[0320] Fig. 17 shows the investigation results of the memory window width in the initial state and after 1×10 9 write operations. In Fig. 17, the solid line indicates the first write operation, and the broken line indicates the 1×10 write operation. Also, in both the solid line and the broken line, the left curve indicates the write operation in the High state, and the right curve indicates the write operation in the Low state. Also, the horizontal axis indicates Vcg (V), and the vertical axis indicates Id (A). From Fig. 17, it can be confirmed that the memory window width does not change when the potential Vcg is swept in the High state and the Low state before and after 1×10 write operations. Before and after 1×10 9 write operations, the memory window width does not change when the potential Vcg is swept in the High state and the Low state. write operations. Before and after 1×10 write operations, the memory window width does not change when the potential Vcg is swept in the High state and the Low state. 9 Before and after 1×10 write operations, it can be confirmed that the memory window width does not change when the potential Vcg is swept in the High state and the Low state. 9 Before and after 1×10 The fact that the window width does not change indicates that, at least during this period, the characteristics of the semiconductor device do not change. This is what it shows.

[0321] As described above, the semiconductor device according to one aspect of the disclosed invention does not change its characteristics even when holding and writing are repeated many times. That is, it can be said that a highly reliable semiconductor device is realized by one aspect of the disclosed invention.

Explanation of Reference Numerals

[0322] 10 Memory cell array 20 Column decoder 30 Row decoder 40 IO controller 50 IO buffer 60 Command buffer 70 Address buffer 80 Controller 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound region 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 132 Insulating layer 134 Insulating layer 138 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 142c electrode 142d electrode 143 insulating layer 144 oxide semiconductor layer 146 gate insulating layer 148a gate electrode 148b electrode 150 interlayer insulating layer 152 interlayer insulating layer 160 transistor 162 transistor 164 capacitor element 170 transistor 181 memory cell array 190 memory cell 200 object to be processed 202 insulating layer 206 oxide semiconductor layer 206a oxide semiconductor layer 208a source electrode or drain electrode 208b source electrode or drain electrode 212 gate insulating layer 214 gate electrode 216 interlayer insulating layer 218 interlayer insulating layer 250 transistor 300 object to be processed 302 insulating layer 304 first oxide semiconductor layer 304a first oxide semiconductor layer 305 second oxide semiconductor layer 306 second oxide semiconductor layer 306a second oxide semiconductor layer 308a source electrode or drain electrode 308b source electrode or drain electrode 312 gate insulating layer 314 gate electrode 316 interlayer insulating layer 318 interlayer insulating layer 350 transistor 400 object to be processed 402 insulating layer 406 Oxide semiconductor layer 406a Oxide semiconductor layer 408 Conductive layer 408a Source electrode or drain electrode 408b Source electrode or drain electrode 410 Insulating layer 410a Insulating layer 410b Insulating layer 411a Oxidation region 411b Oxidation region 412 Gate insulating layer 414 Gate electrode 416 Interlayer insulating layer 418 Interlayer insulating layer 450 Transistor 500 Base substrate 502 Nitrogen-containing layer 510 Single-crystal semiconductor substrate 512 Oxide film 514 Brittleness region 516 Single-crystal semiconductor layer 518 Single-crystal semiconductor layer 520 Semiconductor layer 522 Insulating layer 522a Gate insulating layer 524 Gate electrode 526 Impurity region 528 Sidewall insulating layer 530 High-concentration impurity region 532 Low-concentration impurity region 534 Channel formation region 536 Interlayer insulating layer 538 Interlayer insulating layer 540a Source electrode or drain electrode 540b Source electrode or drain electrode 570 Transistor 620 Memory cell array 630 Memory cell 631 Transistor 632 Capacitor element 640 Memory cell array 650 Memory cell 651 Transistor 652 Transistor 653 Transistor 654 Transistor 655 Transistor 656 Transistor 701 Housing 702 Housing 703 Display Unit 704 Keyboard 711 Main Body 712 Stylus 713 Display Unit 714 Operation Button 715 External Interface 720 E-book 721 Housing 723 Housing 725 Display Unit 727 Display Unit 731 Power Supply 733 Operation Key 735 Speaker 737 Shaft Portion 740 Housing 741 Housing 742 Display Panel 743 Speaker 744 Microphone 745 Operation Key 746 Pointing Device 747 Camera Lens 748 External Connection Terminal 749 Solar Cell 750 External Memory Slot 761 Main Body 763 Eyepiece 764 Operation Switch 765 Display Unit 766 Battery 767 Display Unit 770 Television Set 771 Housing 773 Display Unit 775 Stand 780 Remote Control Unit

Claims

[Claim 1] a memory cell array having a plurality of memory cells arranged in a matrix; a first driver circuit electrically connected to the bit line; a second drive circuit electrically connected to the word line; Each of the plurality of memory cells includes a transistor and a capacitance element; One of the source and the drain of the transistor is electrically connected to the bit line; the other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor; a gate electrode of the transistor is electrically connected to the word line; the transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that a c-axis is perpendicular to a surface of the oxide semiconductor layer, The memory device, in which the transistor is turned on to apply a potential to one electrode of the capacitor, and then the transistor is turned off to hold the charge applied to the capacitor.

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