Semiconductor device

Abstract

To achieve high reliability by giving stabilized electrical characteristics to a semiconductor device using an oxide semiconductor.SOLUTION: A semiconductor device has an insulating film, a first metal oxide film on the insulating film in contact therewith, an oxide semiconductor film partially in contact with the first metal oxide film, a source electrode and a drain electrode for connection electrically with the oxide semiconductor film, a second metal oxide film partially in contact with the oxide semiconductor film, a gate insulator film on the second metal oxide film in contact therewith, and a gate electrode on the gate insulator film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In this specification, the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

Background Art

Background Art

[0003] Techniques for forming transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Amorphous silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. For example, transistors using amorphous oxides containing indium (In), gallium (Ga), and zinc (Zn) with an electron carrier concentration of less than 10 / cm have been disclosed as the active layer of transistors (see Patent Document 1). Transistors using oxide semiconductors are known to have problems in that their electrical characteristics are likely to vary and their reliability is low, although they have a higher operating speed than transistors using amorphous silicon and are easier to manufacture than transistors using polycrystalline silicon. For example, the threshold voltage of a transistor varies before and after a photo-BT test. In contrast, Patent Documents 2 and 3 disclose techniques for stabilizing the threshold voltage of transistors using oxide semiconductors.

[0004] For example, as the active layer of a transistor, an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) with an electron carrier concentration of less than 10 18 / cm 3 has been disclosed (see Patent Document 1).

[0005] In order to suppress the shift, it is provided on at least one of the upper surface and the lower surface of the oxide semiconductor layer A technique for preventing charge trapping at the interface of the oxide semiconductor layer by an interface stabilization layer provided is disclosed It is shown

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, the transistors disclosed in Patent Document 2 or Patent Document 3 use a layer having the same quality as the gate insulating layer and the protective layer as the interface stabilization layer, and the interface with the active layer Since the state of cannot be maintained well, it is difficult to suppress charge trapping at the interface between the active layer and the interface stabilization layer. In particular, when the interface stabilization layer and the active layer have the same band gap Charge accumulation can easily occur Therefore, it cannot be said that the transistor using the oxide semiconductor has sufficient reliability yet

[0008] Therefore, one of the purposes is to impart stable electrical characteristics to a semiconductor device using an oxide semiconductor and to improve the reliability

[0009] In view of such problems, one of the purposes is to impart stable electrical characteristics to a semiconductor device using an oxide semiconductor and to improve the reliability

Means for Solving the Problems

[0010] ​One aspect of the disclosed invention is that an insulating film such as a gate insulating film or a protective insulating film and an oxide semiconductor film as an active layer do not directly contact each other, but there is a metal oxide film in contact with these between them, and the metal oxide film is made of the same components as the oxide semiconductor film in terms of technical concept. That is, one aspect of the disclosed invention has a structure in which an insulating film made of components different from those of the metal oxide film and the oxide semiconductor film, a metal oxide film, and an oxide semiconductor film are laminated. Here, "the same components as the oxide semiconductor film" means including one or more metal elements selected from the constituent elements of the oxide semiconductor film. Instead, a metal oxide film exists between them, and the metal oxide film is made of the same components as the oxide semiconductor film in terms of technical concept. That is, one aspect of the disclosed invention has a structure in which an insulating film made of components different from those of the metal oxide film and the oxide semiconductor film, a metal oxide film, and an oxide semiconductor film are laminated. Here, "the same components as the oxide semiconductor film" means including one or more metal elements selected from the constituent elements of the oxide semiconductor film. By having such a laminated structure, it is possible to sufficiently suppress charges and the like that may be generated due to the operation of the semiconductor device from being trapped at the interface between the insulating film and the oxide semiconductor film. This effect is achieved by arranging a metal oxide film made of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, so that charges and the like that may be generated due to the operation of the semiconductor device are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Furthermore, by arranging an insulating film made of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulating film according to this mechanism.

[0011] That is, when only the metal oxide film is present, it becomes difficult to suppress the trapping of charges at the interface between the oxide semiconductor film in a situation where a large amount of charges are generated. However, by providing an insulating film in contact with the metal oxide film, charges are preferentially trapped at the interface between the metal oxide film and the insulating film. This mechanism enables the suppression of charge trapping at the interface between the oxide semiconductor film and the metal oxide film, and further, by providing an insulating film made of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulating film. That is, in a situation where a large amount of charges are generated, it is difficult to suppress the trapping of charges at the interface between the oxide semiconductor film and the metal oxide film when only the metal oxide film is present. However, by providing an insulating film in contact with the metal oxide film, charges are preferentially trapped at the interface between the metal oxide film and the insulating film. Furthermore, by arranging an insulating film made of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulating film according to this mechanism. That is, when only the metal oxide film is present, it becomes difficult to suppress the trapping of charges at the interface between the oxide semiconductor film in a situation where a large amount of charges are generated. However, by providing an insulating film in contact with the metal oxide film, charges are preferentially trapped at the interface between the metal oxide film and the insulating film.

[0012] That is, when only the metal oxide film is present, it becomes difficult to suppress the trapping of charges at the interface between the oxide semiconductor film in a situation where a large amount of charges are generated. However, by providing an insulating film in contact with the metal oxide film, charges are preferentially trapped at the interface between the metal oxide film and the insulating film. That is, when only the metal oxide film is present, it becomes difficult to suppress the trapping of charges at the interface between the oxide semiconductor film in a situation where a large amount of charges are generated. Since it is possible to suppress the trapping of charges at the interface between the oxide semiconductor film and the metal oxide film there is. Thus, the effect according to one aspect of the disclosed invention is due to the structure in which the insulating film, the metal oxide film, and the oxide semiconductor film are laminated, and it can be said that it is different from the effect of generating the laminated structure of the metal oxide film and the oxide semiconductor film .

[0013] And, by the above-described effect of suppressing the trapping of charges at the interface of the oxide semiconductor film and moving the charge trapping center away from the oxide semiconductor film, malfunctions of the semiconductor device can be suppressed, and the reliability of the semiconductor device can be improved .

[0014] From the above mechanism, it is desirable that the metal oxide film has a sufficient thickness . This is because when the metal oxide film is thin, the influence of charges trapped at the interface between the metal oxide film and the insulating film may increase . For example, it is preferable that the metal oxide film is thicker than the oxide semiconductor film .

[0015] In addition, since the insulating metal oxide film is formed in a manner that does not prevent the connection between the source electrode and the drain electrode and the oxide semiconductor film, an increase in resistance can be prevented as compared with the case where a metal oxide film exists between the source electrode or the drain electrode and the oxide semiconductor film . Therefore, a decrease in the electrical characteristics of the transistor can be suppressed . .

[0016] In addition, in the thin film formation process of the oxide semiconductor, if there is a deviation from the stoichiometric composition due to an excess or deficiency of oxygen, or if hydrogen or moisture that forms an electron donor is mixed in, the electrical conductivity changes. Such a phenomenon is electrical for a transistor using an oxide semiconductor . become factors that cause fluctuations in characteristics. Therefore, impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) are intentionally removed from the oxide semiconductor, and at the same time, oxygen, which is the main component material constituting the oxide semiconductor and would otherwise decrease due to the impurity removal process, is supplied. By doing so, the oxide semiconductor film is purified to a high purity and electrically made into an i-type (intrinsic) state. An i-type (intrinsic) oxide semiconductor is obtained by removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that it contains as few impurities as possible other than the main components of the oxide semiconductor, thereby making it an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is as close as possible to the i-type (intrinsic) state. In the process of making the oxide semiconductor film into an i-type, it is also possible to simultaneously make a metal oxide film made of the same components as the oxide semiconductor film into an i-type. In one aspect of the disclosed invention, it is desirable that the metal oxide films provided on the upper and lower surfaces of the oxide semiconductor film have sufficiently reduced impurities such as moisture and hydrogen and are electrically i-type metal oxide films. A transistor having a highly purified oxide semiconductor film has almost no temperature dependence in electrical characteristics such as threshold voltage and on-current. Also, the variation in transistor characteristics due to photo-degradation is small.

[0017] become factors that cause fluctuations in characteristics. Therefore, impurities such as hydrogen, moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) are intentionally removed from the oxide semiconductor, and at the same time, oxygen, which is the main component material constituting the oxide semiconductor and would otherwise decrease due to the impurity removal process, is supplied. By doing so, the oxide semiconductor film is purified to a high purity and electrically made into an i-type (intrinsic) state. An i-type (intrinsic) oxide semiconductor is obtained by removing hydrogen, which is an n-type impurity, from the oxide semiconductor and purifying it to a high purity so that it contains as few impurities as possible other than the main components of the oxide semiconductor, thereby making it an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is as close as possible to the i-type (intrinsic) state. In the process of making the oxide semiconductor film into an i-type, it is also possible to simultaneously make a metal oxide film made of the same components as the oxide semiconductor film into an i-type. In one aspect of the disclosed invention, it is desirable that the metal oxide films provided on the upper and lower surfaces of the oxide semiconductor film have sufficiently reduced impurities such as moisture and hydrogen and are electrically i-type metal oxide films. exists.

[0018] In the process of making the oxide semiconductor film into an i-type, it is also possible to simultaneously make a metal oxide film made of the same components as the oxide semiconductor film into an i-type. In one aspect of the disclosed invention, it is desirable that the metal oxide films provided on the upper and lower surfaces of the oxide semiconductor film have sufficiently reduced impurities such as moisture and hydrogen and are electrically i-type metal oxide films. A transistor having a highly purified oxide semiconductor film has almost no temperature dependence in electrical characteristics such as threshold voltage and on-current. Also, the variation in transistor characteristics due to photo-degradation is small. One aspect of the disclosed invention is an insulating film, a first metal oxide film in contact with the insulating film on the insulating film, an oxide semiconductor film partially in contact with the first metal oxide film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, and a second metal that is partially in contact with the oxide semiconductor film

[0019] A transistor having a highly purified oxide semiconductor film has almost no temperature dependence in electrical characteristics such as threshold voltage and on-current. Also, the variation in transistor characteristics due to photo-degradation is small. One aspect of the disclosed invention is an insulating film, a first metal oxide film in contact with the insulating film on the insulating film, an oxide semiconductor film partially in contact with the first metal oxide film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, and a second metal that is partially in contact with the oxide semiconductor film

[0020] One aspect of the disclosed invention is an insulating film, a first metal oxide film in contact with the insulating film on the insulating film, an oxide semiconductor film partially in contact with the first metal oxide film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, and a second metal oxide film in contact with the oxide semiconductor film, and a gate electrode provided on the first metal oxide film and electrically insulated from the oxide semiconductor film. oxide film in contact with the oxide semiconductor film, and a gate electrode provided on the first metal oxide film and electrically insulated from the oxide semiconductor film. A first metal oxide film, a gate insulating film in contact with the second metal oxide film on the second metal oxide film, and a gate electrode on the gate insulating film, are provided in a semiconductor device.

[0021] In the above, the first metal oxide film and the second metal oxide film may be formed to contain constituent elements of an oxide semiconductor film. Further, the energy gap of the first metal oxide film and the second metal oxide film may be larger than the energy gap of the oxide semiconductor film. Further, the energy at the lower end of the conduction band of the first metal oxide film and the second metal oxide film may be higher than the energy at the lower end of the conduction band of the oxide semiconductor film.

[0022] In the above, the first metal oxide film and the second metal oxide film may be formed to contain gallium oxide. Further, the ratio of the constituent elements of the first metal oxide film may be equal to the ratio of the constituent elements of the second metal oxide film. Further, the insulating film may be formed to contain silicon oxide. Further, the gate insulating film may be formed to contain silicon oxide or hafnium oxide.

[0023] In the above, the second metal oxide film may cover the source electrode and the drain electrode and may be provided in contact with the first metal oxide film. Further, the oxide semiconductor film may be surrounded by the first metal oxide film and the second metal oxide film.

[0024] In the above, the side end portion in the channel length direction of the oxide semiconductor film may coincide with the side end portion in the channel length direction of the first metal oxide film. Further, the side end portion in the channel length direction of the oxide semiconductor film may coincide with the side end portion in the channel length direction of the second metal oxide film. ​​​​​​​​​​​​​

[0025] In addition, in the above, having a second insulating film covering the gate insulating film and the gate electrode There is also a case of having a conductive film below the oxide semiconductor film.

[0026] Note that in the above, the channel length L of the transistor determined by the distance between the source electrode and the drain electrode is 10 nm or more and 10 μm or less, for example, 0.1 μm to 0.5 μm can be set. Of course, the channel length L may be 1 μm or more. Also, regarding the channel width W, it can be 10 nm or more.

Advantages of the Invention

[0027] According to one embodiment of the present invention, a transistor having stable electrical characteristics is provided.

[0028] Alternatively, according to one embodiment of the present invention, a semiconductor device having a transistor with good electrical characteristics and high reliability is provided.

Brief Description of the Drawings

[0029]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that its form and details can be variously changed. Also, the present invention is not construed to be limited to the description content of the embodiments shown below.

[0031] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, it does not indicate a unique name as a matter for specifying the invention in this specification.

[0032] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 5 .

[0033] 〈Example of the Configuration of the Semiconductor Device〉 In FIG. 1, as an example of a semiconductor device according to one aspect of the disclosed invention, a plan view and a cross-sectional view of a transistor 110 are shown. Here, FIG. 1(A) is a plan view, and FIGS. 1(B) and 1 (C) are cross-sectional views related to the A-B cross-section and the C-D cross-section in FIG. 1(A), respectively . Note that in FIG. 1(A), some of the components of the transistor 110 (for example, the second metal oxide film 210, etc.) are omitted to avoid complication. The transistor 110 shown in FIG. 1 is on a substrate 200, an insulating film 202, and a first metal oxide .

[0034] ​​The film 204, the oxide semiconductor film 206, the source electrode 208a, the drain electrode 208b, and the second metal oxide film 210, the gate insulating film 212, and the gate electrode 214 are included.

[0035] In the transistor shown in FIG. 1, the second metal oxide film 210 covers the source electrode 208a and the drain electrode 208b, and is provided so as to be in contact with a part of the first metal oxide film 204. Also, in FIG. 1, the first metal oxide film 204 and the second metal oxide film 210 are in contact with each other in a region where the oxide semiconductor film 206 does not exist. That is, the oxide semiconductor film 206 is surrounded by the first metal oxide film 204 and the second metal oxide film 210.

[0036] Here, it is desirable to use an oxide made of the same kind of components as the oxide semiconductor film 206 for the first metal oxide film 204 and the second metal oxide film 210. Specifically, it is a film made of an oxide of one or more metal elements selected from the constituent elements of the oxide semiconductor film. Such a material has good compatibility with the oxide semiconductor film 206, and by using it for the first metal oxide film 204 and the second metal oxide film 210, the state of the interface with the oxide semiconductor film can be kept good. That is, by using the above-mentioned material for the first metal oxide film 204 and the second metal oxide film 210, the capture of charges at the interface between the oxide semiconductor film and the metal oxide film in contact therewith (here, the interface between the first metal oxide film 204 and the oxide semiconductor film 206, or the interface between the second metal oxide film 210 and the oxide semiconductor film 206) can be suppressed.

[0037] Note that both the first metal oxide film 204 and the second metal oxide film 210 are oxide semiconductors Since the film is made of the same components as the membrane, when the first metal oxide film 204 and the second metal oxide film 210 are in contact with each other in a region where the oxide semiconductor film 206 does not exist, the adhesion between them can be improved. Also, it is more desirable to make the ratio of the constituent elements of the first metal oxide film 204 equal to the ratio of the constituent elements of the second metal oxide film 210.

[0038] In addition, due to the use of the oxide semiconductor film 206 as the active layer, the energy gaps of the first metal oxide film 204 and the second metal oxide film 210 are required to be larger than the energy gap of the oxide semiconductor film 206. Also, between the first metal oxide film 204 and the oxide semiconductor film 206, or between the second metal oxide film 210 and the oxide semiconductor film 206, at least at room temperature (20 °C), the formation of an energy barrier is required such that carriers do not flow out of the oxide semiconductor film 206. For example, the energy difference between the lower end of the conduction band of the first metal oxide film 204 or the second metal oxide film 210 and the lower end of the conduction band of the oxide semiconductor film 206, or the energy difference between the upper end of the valence band of the first metal oxide film 204 or the second metal oxide film 210 and the upper end of the valence band of the oxide semiconductor film 206 is desirably 0.5 eV or more, more desirably 0.7 eV or more. Also, it is desirably 1.5 eV or less.

[0039] Specifically, for example, when an In-Ga-Zn-O-based material is used for the oxide semiconductor film 206, the first metal oxide film 204 and the second metal oxide film 210 may be formed using a material containing gallium oxide. Note that gallium oxide and the In-Ga-Zn-O-based material The energy barrier when in contact is about 0.8 eV on the conduction band side and about 0.9 eV on the valence band side.

[0040] Note that gallium oxide is also denoted as GaO x and it is preferable to set the value of x such that oxygen is in excess of the stoichiometric ratio. For example, it is preferable that the value of x is 1.4 or more and 2.0 or less, and more preferably the value of x is 1.5 or more and 1.8 or less. However, in the gallium oxide film, impurity elements other than hydrogen such as group 3 elements like yttrium, group 4 elements like hafnium, group 13 elements like aluminum, group 14 elements like silicon, nitrogen, etc. may be included and by doing so, the energy gap of gallium oxide may be expanded to enhance the insulation. The energy gap of a gallium oxide film without impurities is 4.9 eV, but by including the above-mentioned impurities for example, in an amount exceeding 0 atomic % and up to about 20 atomic %, the energy gap can be expanded to about 6 eV.

[0041] Note that from the viewpoint of reducing the charge generation source and trapping center, it is desirable that impurities such as hydrogen and water in the metal oxide film are sufficiently reduced. This concept is common to the concept of impurity reduction in oxide semiconductor films.

[0042] Also, for the insulating film 202 and the gate insulating film 212, it is desirable to use a material that can form a charge trapping center at the interface by contacting with the first metal oxide film 204 and the second metal oxide film 210. By using such a material for the insulating film 202 and the gate insulating film 212, the charge is at the interface between the insulating film 202 and the first metal oxide film 204, or at the gate insulating ​​​​​​​​Since it is captured at the interface between the edge film 212 and the second metal oxide film 210, the first metal oxide film Charge trapping at the interface between 204 and the oxide semiconductor film 206, or the second metal oxide film 210 It becomes possible to sufficiently suppress charge trapping at the interface with the oxide semiconductor film 206. However, when a large number of charge trapping centers are formed at the interface between the gate insulating film 212 and the second metal oxide film 210, the transistor characteristics may rather deteriorate. Therefore, compared with the interface between the oxide semiconductor film 206 and the second metal oxide film 210, it is preferable that charge trapping centers are formed to a slightly easier extent.

[0043] Specifically, for the insulating film 202 and the gate insulating film 212, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, a mixed material thereof, etc. may be used. For example when the first metal oxide film 204 and the second metal oxide film 210 contain a material containing gallium oxide, it is preferable to use silicon oxide or silicon nitride for the insulating film 202 and the gate insulating film 212. Also, due to the contact relationship with the first metal oxide film 204 and the second metal oxide film 21 0, it is desirable that the energy gap of the insulating film 202 and the gate insulating film 212 is larger than the energy gap of the first metal oxide film 204 and the second metal oxide film 210.

[0044] Note that since charge trapping centers can be formed at the interface between the insulating film 202 and the first metal oxide film 204, or at the interface between the gate insulating film 21 2 and the second metal oxide film 210, it is not necessary to limit the materials of the insulating film 202 and the gate insulating film 212 to those described above. Also the interface between the insulating film 202 and the first metal oxide film 204, or the gate insulating film 212 and A process of forming a charge trapping center may be performed at the interface with the second metal oxide film 210. Examples of such a process include plasma treatment and element addition treatment (such as ion implantation). There is.

[0045] A second insulating film may be further provided on the transistor 110. Also, in order to electrically connect the source electrode 208a and the drain electrode 208b to the wiring, the insulating film 2 02, the first metal oxide film 204, the second metal oxide film 210, the gate insulating film 212, etc. An opening may be formed. Further, below the oxide semiconductor film 206, a second gate electrode may be provided. Note that the oxide semiconductor film 206 is preferably processed into an island shape, but it does not have to be processed into an island shape. Although it is desirable that it is processed into an island shape, it does not have to be processed into an island shape. Although it is desirable that the oxide semiconductor film 206 is processed into an island shape, it does not have to be processed into an island shape.

[0046] FIG. 2 is an energy band diagram (schematic diagram) in the structure in which the above-described transistor 110, that is, the insulating film, the metal oxide film, the oxide semiconductor film, the metal oxide film, and the insulating film are joined from the gate electrode GE side, and E is the Fermi level of the oxide semiconductor film. In FIG. 2, an ideal situation where all of the insulating film, the metal oxide film, and the oxide semiconductor film are intrinsic is assumed, and silicon oxide (SiO F )(band gap Eg 8 eV to 9 eV) is used as the insulating film and gallium oxide (GaO )(band gap Eg 4.9 eV) is used as the metal oxide film, and an In-Ga-Zn-O-based polycrystalline film (band gap Eg x )(band gap Eg 8 eV to 9 eV) is used as the insulating film and gallium oxide (GaO x )(band gap Eg 4.9 eV) is used as the metal oxide film, and an In-Ga-Zn-O-based polycrystalline film (band gap Eg 3.15 eV) is used as the oxide semiconductor film (OS). Note that the energy difference between the vacuum level and the lower end of the conduction band of silicon oxide is 0.95 eV, and the energy difference between the vacuum level and the lower end of the conduction band of gallium oxide is 3.15 eV) is shown for the case where an In-Ga-Zn-O-based polycrystalline film (band gap Eg 3.15 eV) is used as the oxide semiconductor film (OS). Note that the energy difference between the vacuum level and the lower end of the conduction band of silicon oxide is 0.95 eV, and the energy difference between the vacuum level and the lower end of the conduction band of gallium oxide is The energy difference is 3.5 eV, which is the energy difference between the vacuum level and the conduction band of the In-Ga-Zn-O based amorphous film. The energy difference between the lower end of the vacuum level and the conduction band is 4.3 eV.

[0047] As shown in FIG. 2, on the gate electrode side (channel side) of the oxide semiconductor film, there are energy barriers of about 0.8 eV and about 0.95 eV at the interface between the oxide semiconductor and the metal oxide. Similarly, on the back channel side (opposite side of the gate electrode) of the oxide semiconductor film, there are also energy barriers of about 0.8 eV and about 0.95 eV at the interface between the oxide semiconductor and the metal oxide. Due to the existence of such energy barriers at the interface between the oxide semiconductor and the metal oxide, the movement of carriers is hindered at that interface. Therefore, the carriers move in the oxide semiconductor without moving from the oxide semiconductor to the metal oxide. As shown in FIG. 2, when the oxide semiconductor film, the metal oxide layer, and the insulating layer are provided so that the oxide semiconductor film is sandwiched between materials with a gradually increasing band gap (the band gap of the insulating film is larger than that of the metal oxide film), such beneficial results can be obtained. exist. exist. exist, the movement of carriers is hindered at that interface. Therefore, the carriers move in the oxide semiconductor without moving from the oxide semiconductor to the metal oxide. As shown in FIG. 2, when the oxide semiconductor film, the metal oxide layer, and the insulating layer are provided so that the oxide semiconductor film is sandwiched between materials with a gradually increasing band gap (the band gap of the insulating film is larger than that of the metal oxide film), such beneficial results can be obtained. oxide semiconductor film, the metal oxide layer, and the insulating layer are provided so that the oxide semiconductor film is sandwiched between materials with a gradually increasing band gap (the band gap of the insulating film is larger than that of the metal oxide film), such beneficial results can be obtained. oxide semiconductor film is sandwiched between materials with a gradually increasing band gap (the band gap of the insulating film is larger than that of the metal oxide film), such beneficial results can be obtained. is larger), such beneficial results can be obtained.

[0048] FIGS. 3(A) to 3(G) show cross-sectional structures of transistors having configurations different from that of the transistor 110. In FIGS. 3(A) to 3(G), a top-gate type transistor is shown as a transistor according to one aspect of the disclosed invention. is shown.

[0049] The transistor 120 shown in FIG. 3(A) includes an insulating film 202, a first metal oxide film 204, an oxide semiconductor film 206, a source electrode 208a, a drain electrode 208b, a second metal oxide film 210, a gate insulating film 212, and a gate electrode 214, and is common with the transistor 110 in that regard. is continuous. The difference between transistor 120 and transistor 110 lies in the oxide semiconductor film 20 6 and the positions where the source electrode 208a and the drain electrode 208b are connected. That is, in transistor 120, the source electrode 208a and the drain electrode 208b are in contact with the lower part of the oxide semiconductor film 206. For other components, they are the same as those of transistor 11 0 in FIG. 1. Details can be referred to the description related to FIG. 1.

[0050] The transistor 130 shown in FIG. 3(B) is common to the transistor 120 shown in FIG. 3(A) in that it includes each of the above-described components. The difference between transistor 130 and transistor 120 is that the insulating film 202 has a convex shape, and the oxide semiconductor film 206 is not completely covered by the first metal oxide film 204 and the second metal oxide film 210. For other components, they are the same as those in FIG. 3(A). . For other components, they are the same as those in FIG. 3(A).

[0051] The transistor 140 shown in FIG. 3(C) is common to the transistor 130 shown in FIG. 3(B) in that it includes each of the above-described components. The difference between transistor 140 and transistor 130 is that the insulating film 202 has a flat shape and the first metal oxide film 204 has a convex shape. When the substrate 200 has the function of the insulating film 202, the insulating film 202 may not be provided. For other components, they are the same as those in FIG. 3(B). . For other components, they are the same as those in FIG. 3(B).

[0052] The transistors 150, 160, 170, and 180 shown in FIGS. 3(D) to 3(G) each include each of the above-described components and are the same as the transistors 110, 120, and 130 shown in FIGS. 1, 3(A) to 3(C), respectively, in this regard. is common to the Ta 130 and the transistor 140. These differences lie in whether the first metal oxide film 204 or the second metal oxide film 210 is processed into an island shape. For other components, they are the same as those in FIGS. 1, 3(A) to 3(C).

[0053] <Example of the manufacturing process of the transistor> Hereinafter, with reference to FIGS. 4 and 5, an example of the manufacturing process of the transistor shown in FIG. 1 or FIG. 3(A) will be described.

[0054] <Manufacturing process of the transistor 110> Using FIGS. 4(A) to 4(E), an example of the manufacturing process of the transistor 110 shown in FIG. 1 will be described. Note that the manufacturing process of the transistor 150 shown in FIG. 3(D) is the same as that of the transistor 110, except that the first metal oxide film 204 etc. are processed according to the shape of the oxide semiconductor film 206.

[0055] First, an insulating film 202 is formed on the substrate 200, and the first metal oxide film 204 is formed so as to be in contact with the insulating film 202 (see FIG. 4(A)).

[0056] There is no significant limitation on the material of the substrate 200 etc., but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate , a sapphire substrate, etc. can be used as the substrate 200. Also, a single crystal semiconductor substrate such as silicon or silicon carbide , a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 200.

[0057] ​​Further, a flexible substrate may be used as the substrate 200. When transistors are provided on the flexible substrate, the transistors may be directly fabricated on the flexible substrate, or transistors may be formed on another substrate and then peeled off and transferred onto the flexible substrate. In addition, in order to peel off the transistors and transfer them onto the flexible substrate, it is preferable to form a release layer between the other substrate and the transistors.

[0058] For the insulating film 202, it is desirable to use a material capable of forming a charge trapping center at the interface by contacting with the first metal oxide film 204. By using such a material for the insulating film 20 2, charges are trapped at the interface between the insulating film 202 and the first metal oxide film 204, so that charge trapping at the interface between the first metal oxide film 204 and the oxide semiconductor film 206 can be sufficiently suppressed.

[0059] Specifically, for the insulating film 202, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, mixed materials thereof, etc. may be used. For example, when a material containing gallium oxide is used for the first metal oxide film 204, it is preferable to use silicon oxide or silicon nitride for the insulating film 202. Also, due to the relationship of contacting with the first metal oxide film 204, it is desirable that the energy gap of the insulating film 202 is larger than the energy gap of the first metal oxide film 204.

[0060] In addition, if a charge trapping center can be formed at the interface between the insulating film 202 and the first metal oxide film 204, it is not necessary to limit the material of the insulating film 202 to the above-mentioned ones. Also, at the interface between the insulating film 202 and the first metal oxide film 204, the place where a charge trapping center is formed​​​​ Processing may be performed. Examples of such processing include plasma processing and element addition processing ( ion implantation, etc.).

[0061] There is no particular limitation on the method for manufacturing the insulating film 202. For example, the insulating film 202 can be manufactured using a film formation method such as plasma CVD method or sputtering method. Further, the insulating film 20 2 may have a single-layer structure of an insulating film containing the above-described material, or may have a laminated structure.

[0062] When a substrate 200 containing an insulating material as described above is used, the substrate 200 can be treated as the insulating film 202. That is, the insulating film 202 mentioned here can be omitted. In this case, it is more desirable that the substrate 200 is made of silicon oxide or the like .

[0063] It is desirable that the first metal oxide film 204 uses an oxide having the same components as the oxide semiconductor film 206 . Such a material has good compatibility with the oxide semiconductor film 206, and by using this for the first metal oxide film 204, the state of the interface with the oxide semiconductor film can be kept good . That is, by using the above-described material for the first metal oxide film 204, the capture of charges at the interface between the oxide semiconductor film and the metal oxide film in contact therewith (here, the interface between the first metal oxide film 204 and the oxide semiconductor film 206) can be suppressed. .

[0064] In addition, due to the relationship of using the oxide semiconductor film 206 as the active layer, the energy gap of the first metal oxide film 204 should be larger than the energy gap of the oxide semiconductor film 206. is required. Further, between the first metal oxide film 204 and the oxide semiconductor film 206, at least , at room temperature (20 ° C), a carrier does not flow out of the oxide semiconductor film 206 to such an extent that the formation of an energy barrier is required. For example, the lower end of the conduction band of the first metal oxide film 204 and the energy difference between the lower end of the conduction band of the oxide semiconductor film 206, or the upper end of the valence band of the first metal oxide film 204 and the energy difference between the upper end of the valence band of the oxide semiconductor film 206 is desirably 0.5 eV or more, more desirably 0.7 eV or more. Also, 1. is desirably 5 eV or less.

[0065] Incidentally, from the viewpoint of reducing the charge generation source and the trapping center, impurities such as hydrogen and water in the metal oxide film are desirably sufficiently reduced. This idea is common to the idea of impurity reduction in the oxide semiconductor film.

[0066] There is no particular limitation on the method for producing the first metal oxide film 204. For example, the first metal oxide film 204 can be produced using a film formation method such as plasma CVD method or sputtering method. In terms of being difficult to mix hydrogen, water, etc., a sputtering method or the like is appropriate . On the other hand, in terms of improving the film quality, a plasma CVD method or the like is appropriate.

[0067] Next, an oxide semiconductor film is formed on the first metal oxide film 204, and the oxide semiconductor film is processed to form an island-shaped oxide semiconductor film 206 (see Fig. 4(B)).

[0068] The oxide semiconductor film is desirably produced by a method in which hydrogen, water, etc. are difficult to mix in. For example , it can be produced using a sputtering method or the like. Also, the thickness of the oxide semiconductor film is It is preferably 3 nm or more and 30 nm or less. If the oxide semiconductor film is made too thick (for example, when the film thickness is 50 nm or more), the transistor may become normally on. Note that the insulating film 202, the first metal oxide film 204, and the oxide semiconductor film are preferably formed continuously without being exposed to the air.

[0069] As the material used for the oxide semiconductor film, In-Sn-Ga-Zn-O-based quaternary metal oxide, In-Ga-Zn-O-based ternary metal oxide, In-Sn-Zn-O-based ternary metal oxide, In-Al-Zn-O-based ternary metal oxide, Sn-Ga-Zn-O-based ternary metal oxide, Al-Ga-Zn-O-based ternary metal oxide, Sn- Al-Zn-O-based ternary metal oxide, In-Zn-O-based binary metal oxide, Sn-Zn-O-based binary metal oxide, Al- Zn-O-based binary metal oxide, Zn-Mg-O-based binary metal oxide, Sn-Mg-O-based binary metal oxide, In-Mg-O-based binary metal oxide, In-Ga- O-based binary metal oxide, or In-O-based single-element metal oxide, Sn-O-based single-element metal oxide, Zn-O-based single-element metal oxide, etc. can be used. In addition, SiO may be included in the above materials. Here, for example, the In-Ga-Zn-O-based material means an oxide film containing indium (In), gallium (Ga), and zinc (Zn), and the composition ratio is not particularly limited. In addition, elements other than In, Ga, and Zn may be included. 2

[0070] In addition, the oxide semiconductor film can be a thin film using a material represented by the chemical formula InMO 3 (ZnO) m (m > 0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co can be used.

[0071] In this embodiment, the oxide semiconductor film is formed by a sputtering method using a target for forming an In-Ga-Zn-O-based oxide semiconductor. When using an In-Ga-Zn-O-based material as the oxide semiconductor, as the target to be used, for example, in terms of the composition ratio, In

[0072] :Ga :ZnO = 1:1:1 [mol 2 O 3 ratio] can be used as the target for forming the oxide semiconductor film. Note that the material and 2 O 3 composition of the target do not necessarily need to be limited as described above. For example, In :Ga :ZnO = 1: 2 O 3 :Ga 2 O 3 :ZnO = 1: 1:2 [mol ratio] can also be used as the target for forming the oxide semiconductor film.

[0073] When using an In-Zn-O-based material as the oxide semiconductor, the composition ratio of the target to be used is, in terms of the atomic ratio, In:Zn = 50:1 to 1:2 (when converted to the molar ratio, In :ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (when converted to the molar ratio, In 2 O 3 :ZnO = 10:1 to 1:2), more preferably In:Zn = 15 :1 to 1.5:1 (when converted to the molar ratio, In 2 O 3 :ZnO = 15:2 to 3:4). For example, when the target used for forming the In-Zn-O-based oxide semiconductor has an atomic ratio of In :Zn:O = X:Y:Z, then Z> 1.5X + Y. 2 O 3 :ZnO = 15:2 to 3:4). For example, when forming an In-Zn-O-based oxide semiconductor, for the target to be used, when the atomic ratio is In :Zn:O = X:Y:Z, then Z> 1.5X + Y.

[0074] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99. 9% or less. By using an oxide semiconductor film-forming target with a high filling rate, the formed oxide semiconductor film can be made dense.

[0075] The film formation atmosphere may be an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas and oxygen. Also, in order to prevent the incorporation of hydrogen, water, hydroxyl groups, hydrides, etc. into the oxide semiconductor film, it is desirable to use an atmosphere with a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently removed.

[0076] For example, the oxide semiconductor film can be formed as follows.

[0077] First, the substrate 200 is held in a film formation chamber maintained in a reduced pressure state, and the substrate temperature is set to 100°C or more and 600°C or less, preferably 200°C or more and 400°C or less. By performing film formation with the substrate 200 heated, the impurity concentration in the oxide semiconductor film can be reduced and the damage to the oxide semiconductor film due to sputtering can be reduced.

[0078] Next, while removing the residual moisture in the film formation chamber, a high-purity gas in which impurities such as hydrogen and moisture are sufficiently removed is introduced, and an oxide semiconductor film is formed on the substrate 200 using the above target. To remove the residual moisture in the film formation chamber, it is desirable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump as the evacuation means. Also, the evacuation means may be a turbo pump with a cold trap added. 。The film formation chamber evacuated using a cryopump has, for example, hydrogen molecules, water (H 2 O), etc. Compounds containing hydrogen atoms (more preferably also compounds containing carbon atoms) are removed, so that the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0079] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 P a, the DC power supply is 0.5 kW, and the film formation atmosphere can be an oxygen (oxygen flow rate ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles, dust) generated during film formation can be reduced, and the variation in film thickness can also be reduced, which is preferable.

[0080] Before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove the powdery substances (also called particles, dust) adhering to the surface of the first metal oxide film 204. Reverse sputtering is a method of applying a voltage to the substrate to form plasma near the substrate to modify the surface on the substrate side. Note that instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0081] Processing of the oxide semiconductor film can be performed by forming a mask of a desired shape on the oxide semiconductor film and then etching the oxide semiconductor film. The above-mentioned mask can be formed using a method such as photolithography. Or, the mask can be formed using any method such as the inkjet method. When processing the oxide semiconductor film, by also performing processing of the first metal oxide film 204, etc., the transistor 150 shown in FIG. 3(D) can be fabricated. ​

[0082] Note that the etching of the oxide semiconductor film can be either dry etching or wet etching. Of course, these may be used in combination.

[0083] Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor film. By this first heat treatment, excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor film can be removed, the structure of the oxide semiconductor film can be adjusted, and the defect levels in the energy gap can be reduced. The temperature of the first heat treatment is 250°C or higher and 650°C or lower, preferably 450°C or higher and 600 °C or lower. Note that the temperature of the first heat treatment is preferably lower than the distortion point of the substrate.

[0084] Furthermore, by this first heat treatment, it is also possible to remove excess hydrogen (including water and hydroxyl groups) in the first metal oxide film 204.

[0085] The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, under a nitrogen atmosphere at 450°C for 1 hour. During this time, the oxide semiconductor film should not be exposed to the atmosphere so as to prevent the incorporation of water and hydrogen.

[0086] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation can also be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp R apid Thermal Anneal) apparatus or a GRTA (Gas Rapid Th ermal Anneal) apparatus can be used. The LRTA apparatus uses a halogen lamp, a metal halide lamp l) apparatus can be used. The LRTA apparatus uses a halogen lamp, a metal halide lamp A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. The GRTA device is a device that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon or an inert gas that does not react with the object to be processed by heat treatment, such as nitrogen, is used.

[0087] For example, as the first heat treatment, the object to be processed may be put into an atmosphere of heated inert gas and heated for several minutes, and then a GRTA treatment may be performed to take out the object to be processed from the inert gas atmosphere. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the object to be processed. During the treatment, the inert gas may be switched to a gas containing oxygen. By performing the first heat treatment in an atmosphere containing oxygen, it is possible to reduce the defect levels in the energy gap caused by oxygen deficiency.

[0088] As the inert gas atmosphere, an atmosphere mainly composed of nitrogen or noble gas (helium, neon, argon, etc.) and not containing water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gas such as helium, neon, argon, etc. introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0089] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor film that is extremely close to an i-type (intrinsic) semiconductor or an i-type semiconductor, transistors with extremely excellent characteristics can be obtained. ​ A stud can be realized.

[0090] By the way, since the above heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. This dehydration treatment and dehydrogenation treatment can be carried out, for example, at the timing such as after processing the oxide semiconductor film into an island shape. Also, such dehydration treatment and dehydrogenation treatment may be carried out a plurality of times, not limited to once.

[0091] Here, the configuration in which the first heat treatment is performed after processing the oxide semiconductor film into an island shape has been described, but one aspect of the disclosed invention is not construed as being limited thereto. The oxide semiconductor film may be processed after the first heat treatment.

[0092] Next, a conductive film for forming a source electrode and a drain electrode (including wiring formed in the same layer) is formed on the first metal oxide film 204 and the oxide semiconductor film 206, and the conductive film is processed to form a source electrode 208a and a drain electrode 208b (see FIG. 4(C)). Note that the channel length L of the transistor is determined by the distance between the end of the source electrode 208a and the end of the drain electrode 208b formed here.

[0093] As the conductive film used for the source electrode 208a and the drain electrode 208b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film containing the above-described element as a component (titanium nitride film, molybdenum nitride film, tungsten nitride film ) etc. can be used. Also, on one side or both sides of the lower or upper side of a metal film such as Al or Cu, ​ Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film A laminated structure of a metal film (a molybdenum nitride film, a tungsten nitride film, etc.) may be used.

[0094] The conductive film used for the source electrode 208a and the drain electrode 208b is a conductive gold film. The conductive metal oxide may be indium oxide (In 2 O 3 ) , tin oxide (SnO 2 ), zinc oxide (ZnO), indium oxide tin oxide alloy (In 2 O 3 - SnO 2 , abbreviated as ITO), indium oxide zinc oxide alloy (In 2 O 3 -ZnO ) or a material obtained by incorporating silicon oxide into these metal oxide materials can be used.

[0095] The conductive film can be processed by etching using a resist mask. The exposure to light used in forming the resist mask used in etching is ultraviolet light, KrF laser light, or ArF A laser beam or the like may be used.

[0096] In addition, when performing exposure with a channel length L of less than 25 nm, for example, several nm to several tens of nm Using extreme ultraviolet light with an extremely short wavelength of 1.5 m, It is recommended to perform exposure when forming a resist mask. Exposure to extreme ultraviolet light has high resolution and focal depth. Therefore, the channel length L of the transistor to be formed later can be reduced. This makes it possible to increase the operating speed of the circuit.

[0097] In addition, etching is performed using a resist mask formed by a so-called multi-tone mask. This process may be carried out. The resist mask formed using a multi-tone mask has a plurality of film thicknesses and has a shape that can be further deformed by ashing, so it can be used in a plurality of etching processes for processing different patterns. Therefore, with a single multi-tone mask, resist masks corresponding to at least two or more different patterns can be formed. That is, the process can be simplified.

[0098] Note that during the etching of the conductive film, a part of the oxide semiconductor film 206 may be etched to form an oxide semiconductor film having a groove portion (recess).

[0099] After that, plasma treatment using a gas such as N 2 O, N 2 , or Ar may be performed to remove adsorbed water or the like attached to the surface of the exposed oxide semiconductor film. When plasma treatment is performed, it is desirable to prevent contact with the atmosphere following the plasma treatment and form a second metal oxide film 210 in contact with a part of the oxide semiconductor film 206.

[0100] Next, a second metal oxide film 210 is formed to cover the source electrode 208a and the drain electrode 208b and be in contact with a part of the oxide semiconductor film 206. Then, a gate insulating film 212 is formed in contact with the second metal oxide film 210 (see FIG. 4(D)).

[0101] Since the second metal oxide film 210 is the same as the first metal oxide film 204, details are omitted.

[0102] The gate insulating film 212 is also the same as the insulating film 202. However, for the gate insulation of the transistor Considering its function as an edge film, a material with a high relative dielectric constant such as hafnium oxide may be adopted. However, even in this case, it is still desirable to use a material that can form a charge trapping center at the interface by contacting the second metal oxide film 210. This remains unchanged.

[0103] After the formation of the second metal oxide film 210 or after the formation of the gate insulating film 212, it is desirable to perform a second heat treatment. The temperature of the second heat treatment is 250°C or higher and 700°C or lower, preferably 450°C or higher and 600°C or lower. Note that the temperature of the second heat treatment preferably does not reach the distortion point of the substrate.

[0104] The second heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (such as argon or helium). However, it is preferable that the atmosphere of nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. Also, the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0105] In the second heat treatment, the oxide semiconductor film 206 and the second metal oxide film 210 are heated while in contact. Therefore, oxygen, which is one of the main component materials constituting the oxide semiconductor that may be slightly reduced by the above dehydration (or dehydrogenation) treatment, can be supplied from the second metal oxide film 210 containing oxygen to the oxide semiconductor film. ​​​​​​​​​​​​​Thus, the charge trapping centers in the oxide semiconductor film can be reduced.

[0106] Also, by this heat treatment, impurities in the first metal oxide film 204 or the second metal oxide film 21 0 can be removed simultaneously and can be purified to a high purity.

[0107] Note that the timing of the second heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor film 206. For example, the second heat treatment may be performed after the formation of the gate electrode 214. Or, the second heat treatment may be performed following the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0108] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor film 206 can be purified to a high purity so that it contains as few impurities as possible other than its main components. In the highly purified oxide semiconductor film 206, carriers derived from donors are extremely few (close to zero), and the carrier concentration is less than 1×10 14 / cm 3 , preferably less than 1×1 0 12 / cm 3 , more preferably less than 1×10 11 / cm 3 .

[0109] Thereafter, the gate electrode 214 is formed (see FIG. 4(E)). The gate electrode 214 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium or an alloy material having these as main components. Note that the gate electrode 214 may have a single-layer structure or a stacked structure.

[0110] Through the above steps, the transistor 110 is formed.

[0111] <Fabrication process of transistor 120> 5A to 5E, a manufacturing process of the transistor 120 shown in FIG. Note that the manufacturing process of the transistor 160 shown in FIG. The second metal oxide film 210 is processed to match the shape of the metal oxide semiconductor film 206. The manufacturing process is the same as that of the transistor 120 .

[0112] First, an insulating film 202 is formed on a substrate 200, and a first A metal oxide film 204 is formed (see FIG. 5A). Please refer to the description of the manufacturing process of 0.

[0113] Next, a source electrode and a drain electrode (the same layer as this) are formed on the first metal oxide film 204. A conductive film for forming a semiconductor device (including wiring formed by the method described above) is formed, and the conductive film is processed to form a semiconductor device. A source electrode 208a and a drain electrode 208b are formed (see FIG. 5(B)). For this, the description of the manufacturing process of the transistor 110 can be referred to.

[0114] Next, a source electrode 208a and a drain electrode 208 are formed on the first metal oxide film 204. b) forming an oxide semiconductor film connected to the first oxide semiconductor layer; and Then, a thin film 206 is formed (see FIG. 5(C)). For details, see the fabrication of the transistor 110. Please refer to the process description.

[0115] Next, a semiconductor oxide film is formed on the source electrode 208a and the drain electrode 208b. A second metal oxide film 210 is formed so as to be in contact with a part of 206, and then a gate insulating film 212 is formed so as to be in contact with the second metal oxide film 210 (see FIG. 5(D)). For details, reference can be made to the description of the manufacturing process of the transistor 110. Then, a gate electrode 214 is formed (see FIG. 5(E)). For details, reference can be made to the description of the manufacturing process of the transistor 110. In the above steps, the transistor 120 is formed.

[0116] In the transistor according to this embodiment, metal oxide films made of components of the same kind as the oxide semiconductor film are laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. In addition, the oxide semiconductor film used for the active layer of the transistor is, by heat treatment, hydrogen, moisture

[0117] In the above steps, the transistor 120 is formed.

[0118] The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed. The transistor according to this embodiment has metal oxide films made of components of the same kind as the oxide semiconductor film laminated on the upper surface portion and the lower surface portion of the oxide semiconductor film. Further, on the surface of the metal oxide film facing the surface in contact with the oxide semiconductor film, an insulating film made of a component different from the metal oxide film and the oxide semiconductor film is provided in contact. By arranging the metal oxide film composed of a material having good compatibility with the oxide semiconductor film in contact with the oxide semiconductor film, charges that may be generated due to the operation of the semiconductor device or the like are suppressed from being trapped at the interface between the oxide semiconductor film and the metal oxide film. Further, by arranging an insulator composed of a material that can form a charge trapping center at the interface in contact with the metal oxide film, the above-mentioned charges can be trapped at the interface between the metal oxide film and the insulator. As a result, the influence of charges on the oxide semiconductor film can be mitigated, so that the threshold voltage variation of the transistor caused by charge trapping at the oxide semiconductor film interface can be suppressed.

[0119] In addition, the oxide semiconductor film used for the active layer of the transistor is, by heat treatment, hydrogen, moisture Remove impurities such as a hydroxyl group or a hydride (also referred to as a hydrogen compound) from the oxide semiconductor and supply oxygen, which is the main component material constituting the oxide semiconductor that would otherwise decrease simultaneously during the impurity removal process to obtain an oxide semiconductor film that is highly purified and electrically i-type ( intrinsic). A transistor including such a highly purified oxide semiconductor film has suppressed fluctuations in electrical characteristics and is electrically stable. When charges are trapped at the interface of the oxide semiconductor film, the threshold voltage of the transistor shifts (for example, when positive charges are trapped on the back channel side, the threshold voltage of the transistor shifts in the negative direction). As one of the factors causing such charge trapping, a model of the movement and trapping of cations (or the atoms causing them) can be assumed.

[0120] In a transistor using an oxide semiconductor, a hydrogen atom can be considered as such a cation source. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. When positive charges are trapped on the back channel side, the threshold voltage of the transistor shifts in the negative direction). As one of the factors causing such charge trapping, a model of the movement and trapping of cations (or the atoms causing them) can be assumed. In a transistor using an oxide semiconductor, a hydrogen atom can be considered as such a cation source. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. In a transistor using an oxide semiconductor, a hydrogen atom can be considered as such a cation source. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. And in a transistor using an oxide semiconductor, a hydrogen atom can be considered as such a cation source. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%. In the disclosed invention, since a highly purified oxide semiconductor is used and it is configured to be in contact with a stacked structure of a metal oxide film and an insulating film, even charge trapping caused by hydrogen assumed in the above model can be suppressed. Note that the above model is considered to hold when the ionization rate of hydrogen is, for example, about 10%.

[0121] As described above, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided. As described above, a semiconductor device using an oxide semiconductor having stable electrical characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided.

[0122] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0123] (Embodiment 2) A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor exemplified in Embodiment 1. Further, part or all of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0124] In FIG. 6(A), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001, and is sealed by a second substrate 4006. In FIG. 6(A), a scanning line drive circuit 4004 and a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film are mounted on a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Further, various signals and potentials supplied to the separately formed signal line drive circuit 4003 and the scanning line drive circuit 4004 or the pixel portion 4002 are supplied from FPC (Flexible printed circuit) 4018a and FPC 4018b.

[0125] In FIGS. 6(B) and 6(C), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001 and a scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005, and the second substrate 4006. In FIGS. 6(B) and 6(C), Therefore, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the surrounded region. In FIGS. 6(B) and 6(C), various signals and potentials supplied from the FPC 4018 are given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002. Also, in FIGS. 6(B) and 6(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. In addition, the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 6(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 6(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Furthermore, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Note that the display device in this specification refers to an image display device, a display device, or is supplied.

[0126] In FIGS. 6(B) and 6(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. In addition, the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 6(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 6(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Furthermore, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Note that the display device in this specification refers to an image display device, a display device, or is mounted.

[0127] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 6(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 6(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. In addition, the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 6(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 6(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Furthermore, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Note that the display device in this specification refers to an image display device, a display device, or is mounted. In addition, the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 6(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 6(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 6(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Furthermore, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Note that the display device in this specification refers to an image display device, a display device, or

[0128] Furthermore, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Note that the display device in this specification refers to an image display device, a display device, or

[0129] Note that the display device in this specification refers to an image display device, a display device, or Refers to a light source (including a lighting device). Also, a connector, for example, an FPC or a TAB tape, or a module to which a TCP is attached, a printed wiring board at the tip of the TAB tape or TCP a module provided with, or an IC (integrated circuit) directly mounted on a display element by the COG method All modules are also included in the display device.

[0130] Also, the pixel portion and the scanning line driving circuit provided on the first substrate have a plurality of transistors, and the transistors shown as an example in Embodiment 1 can be applied.

[0131] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage in its category. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Also, a display medium such as electronic ink, whose contrast changes by an electrical action, can also be applied.

[0132] One form of the semiconductor device will be described with reference to FIGS. 7 to 9. FIGS. 7 to 9 correspond to a cross-sectional view taken along M-N in FIG. 6 (B).

[0133] As shown in FIGS. 7 to 9, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 401 6. The connection terminal electrodes 4015 and the terminal electrodes 4016 are electrically connected via an anisotropic conductive film 4019 to the terminals of the FPC 4018.

[0134] The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode ​​4016 is formed of the same conductive film as the source electrode and drain of transistor 4010 and transistor 4011. It is formed of the same conductive film as the electrodes.

[0135] Also, a pixel portion 4002 provided on a first substrate 4001 and a scanning line driving circuit 4004 have a plurality of transistors. In FIGS. 7 to 9, transistor 4010 included in pixel portion 4002 and transistor 4011 included in scanning line driving circuit 4004 are exemplified. It is shown.

[0136] In the present embodiment, as transistor 4010 and transistor 4011, the transistor shown in Embodiment 1 can be applied. Transistor 4010 and transistor 4011 have suppressed electrical characteristic variations and are electrically stable. Therefore, a highly reliable semiconductor device can be provided as the semiconductor device of the present embodiment shown in FIGS. 7 to 9. It is possible.

[0137] Transistor 4010 provided in pixel portion 4002 is electrically connected to a display element and constitutes a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

[0138] FIG. 7 shows an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 7, liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating films 4032 and 4033 that function as alignment films are provided so as to sandwich liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4 006 side, and the first electrode layer 4030 and the second electrode layer 4031 are stacked via liquid crystal layer 4008. It has a configuration. It is layered via.

[0139] Further, the columnar spacer 4035 is obtained by selectively etching an insulating film and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical spacer may be used. When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a polymer liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0140] When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a polymer liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0141] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0142] Also, the resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11Ω cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in the specification are values ​​measured at 20°C.

[0143] The size of the storage capacitor provided in the liquid crystal display device is determined by the capacitance of the transistor arranged in the pixel portion. The charge is set so that it can be held for a certain period of time, taking into account factors such as the leakage current. By using a transistor having a semiconductor film, the liquid crystal capacitance of each pixel is It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0144] The transistor including the purified oxide semiconductor film used in this embodiment has an off-state Therefore, the current value in the OFF state (off-state current value) can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which is effective in reducing power consumption. To bear fruit.

[0145] In addition, the transistor including the purified oxide semiconductor film used in this embodiment has the following characteristics: Since a relatively high field effect mobility can be obtained, high speed operation is possible. By using such a transistor in a pixel portion of a display device, a high-quality image can be provided. In addition, the above transistors are separately manufactured for a driver circuit portion and a pixel portion on the same substrate. This makes it possible to reduce the number of components in the liquid crystal display device.

[0146] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In- (Plane-Switching) mode, FFS (Fringe Field Swi tching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, etc. can be used.

[0147] Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Here, the vertical alignment mode is a kind of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and it is a method in which the liquid crystal molecules face the vertical direction with respect to the panel surface when no voltage is applied. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-domain Vertical Alignm ent) mode, PVA (Patterned Vertical Alignment ) mode, ASV (Advanced Super View) mode, etc. can be used. Also, a method called multi-domain or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. For example, MVA (Multi-domain Vertical Alignm ent) mode, PVA (Patterned Vertical Alignment ) mode, ASV (Advanced Super View) mode, etc. can be used. Also, a method called multi-domain or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. ) mode, ASV (Advanced Super View) mode, etc. can be used. Also, a method called multi-domain or multi-domain design in which pixels are divided into several regions (sub-pixels) and the molecules are tilted in different directions can be used. Also, in the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, a polarizing substrate and a retardation member, etc. can be used. Also, in the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, a polarizing substrate and a retardation

[0148] Also, in the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, a polarizing substrate and a retardation member, etc. can be used. Circular polarization using a retardation substrate may also be used. Further, a backlight, a side light, etc. may be used as the light source. It may also be used.

[0149] Further, a plurality of light-emitting diodes (LEDs) may be used as the backlight to perform a time-division display method (field sequential drive method). By applying the field sequential drive method, color display can be performed without using a color filter. It is also possible. By applying the field sequential drive method, color display can be performed without using a color filter. It can be done.

[0150] Further, the display method in the pixel portion can use a progressive method, an interlace method, etc. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, there are RGBW (W represents white), or those obtained by adding one or more of yellow, cyan, magenta, etc. to RGB. In addition, the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device and can also be applied to a monochrome display device. It can be used. It is not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white). ) or those obtained by adding one or more of yellow, cyan, magenta, etc. to RGB. Also, the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device and can also be applied to a monochrome display device. In addition, the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device and can also be applied to a monochrome display device. It can also be applied to a monochrome display device. It can also be done.

[0151] Further, as the display element included in the display device, a light-emitting element utilizing electroluminescence can be applied. The light-emitting element utilizing electroluminescence is distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. The light-emitting element utilizing electroluminescence is distinguished by whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. It is called.

[0152] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are injected into the layer containing the light-emitting organic compound from a pair of electrodes, and current flows. Then, those carriers are injected into the layer containing the light-emitting organic compound from a pair of electrodes, and current flows. By the recombination of carriers (electrons and holes), a light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Based on such a mechanism, such a light-emitting device is called a current-excited type light-emitting device. According to this mechanism, such a light-emitting device is called a current-excited type light-emitting device. According to this mechanism, such a light-emitting device is called a current-excited type light-emitting device.

[0153] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device. Here, an organic EL device is used for explanation as the light-emitting device.

[0154] For the light-emitting device to extract light, at least one of a pair of electrodes may be transparent. Thus, there are light-emitting devices with an upper surface emission structure that forms a transistor and a light-emitting device on a substrate and extracts light from the surface opposite to the substrate, a lower surface emission structure that extracts light from the surface on the substrate side, and a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. Any of these emission structure light-emitting devices can be applied. For the light-emitting device to extract light, at least one of a pair of electrodes may be transparent. Thus, there are light-emitting devices with an upper surface emission structure that forms a transistor and a light-emitting device on a substrate and extracts light from the surface opposite to the substrate, a lower surface emission structure that extracts light from the surface on the substrate side, and a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. Any of these emission structure light-emitting devices can be applied. For the light-emitting device to extract light, at least one of a pair of electrodes may be transparent. Thus, there are light-emitting devices with an upper surface emission structure that forms a transistor and a light-emitting device on a substrate and extracts light from the surface opposite to the substrate, a lower surface emission structure that extracts light from the surface on the substrate side, and a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. Any of these emission structure light-emitting devices can be applied. For the light-emitting device to extract light, at least one of a pair of electrodes may be transparent. Thus, there are light-emitting devices with an upper surface emission structure that forms a transistor and a light-emitting device on a substrate and extracts light from the surface opposite to the substrate, a lower surface emission structure that extracts light from the surface on the substrate side, and a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. Any of these emission structure light-emitting devices can be applied. For the light-emitting device to extract light, at least one of a pair of electrodes may be transparent. Thus, there are light-emitting devices with an upper surface emission structure that forms a transistor and a light-emitting device on a substrate and extracts light from the surface opposite to the substrate, a lower surface emission structure that extracts light from the surface on the substrate side, and a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate. Any of these emission structure light-emitting devices can be applied.

[0155] Fig. 8 shows an example of a light-emitting device using a light-emitting device as a display element. The light-emitting device 4513, which is a display element, is electrically connected to a transistor 4010 provided in a pixel portion 4002. Note that the structure of the light-emitting device 4513 is a laminated structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. Whether it is the light-emitting device 4513 Fig. 8 shows an example of a light-emitting device using a light-emitting device as a display element. The light-emitting device 4513, which is a display element, is electrically connected to a transistor 4010 provided in a pixel portion 4002. Note that the structure of the light-emitting device 4513 is a laminated structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. Whether it is the light-emitting device 4513 Fig. 8 shows an example of a light-emitting device using a light-emitting device as a display element. The light-emitting device 4513, which is a display element, is electrically connected to a transistor 4010 provided in a pixel portion 4002. Note that the structure of the light-emitting device 4513 is a laminated structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. Whether it is the light-emitting device 4513 Fig. 8 shows an example of a light-emitting device using a light-emitting device as a display element. The light-emitting device 4513, which is a display element, is electrically connected to a transistor 4010 provided in a pixel portion 4002. Note that the structure of the light-emitting device 4513 is a laminated structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the shown structure. Whether it is the light-emitting device 4513 The structure of the light-emitting element 4513 can be appropriately changed according to the direction of the light to be extracted, etc. 。

[0156] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, a photosensitive resin material is used to form an opening on the first electrode layer 4030, and it is preferable that the side wall of the opening is formed as an inclined surface having a continuous curvature.

[0157] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers may be stacked. Either way is acceptable.

[0158] A protective film may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4513. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC (Diamond-Like Carbon) film, etc. can be formed. Further, a filling material 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing.

[0159] As the filling material 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, poly imide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA ( ethylene vinyl acetate) can be used. For example, if nitrogen is used as the filling material Good.

[0160] Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate ), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or other optical films may be appropriately provided . Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0161] Also, as a display device, it is possible to provide an electronic paper that drives electronic ink . Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light.

[0162] Although various forms of electrophoretic display devices are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0163] Thus, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0164] A dispersion of the above microcapsules in a solvent is called an electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using color filters or particles having dyes.

[0165] Note that the first particles and the second particles in the microcapsules may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0166] Also, as an electronic paper, a display device using a twist ball display method can also be applied. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer, which are electrode layers using the spherical particles as display elements, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0167] Fig. 9 shows an active matrix type electronic paper as one form of a semiconductor device. Fig. 9's electronic paper is an example of a display device using the twist ball display method.

[0168] Between a first electrode layer 4030 connected to a transistor 4010 and a second electrode layer 4031 provided on a second substrate 4006, there are provided spherical particles 4613 including a black region 4615a and a white region 4615b and having a cavity 4612 filled with a liquid around them, and the periphery of the spherical particles 4613 is filled with a filler 4614 such as resin. The second ​​​​The electrode layer 4031 corresponds to a common electrode (opposing electrode). The second electrode layer 4031 is electrically connected to a common potential line.

[0169] In FIGS. 7 to 9, as the first substrate 4001 and the second substrate 4006, in addition to a glass substrate, a flexible substrate can also be used. For example, a translucent plastic chip substrate or the like can be used. As the plastic, an FRP (Fiber-gl ass-Reinforced Plastics) board, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used . Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used.

[0170] The insulating layer 4021 can be formed using an inorganic insulating material or an organic insulating material. In addition, when using an organic insulating material having heat resistance such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin , etc., it is suitable as a planarizing insulating film. Also, in addition to the above organic insulating materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that an insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0171] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a spin coating method, a dipping method, spray coating, a droplet ejection method (inkjet method, screen printing, offset printing, etc.) etc. can be applied. Roll coating, curtain The insulating layer 4021 can also be formed using spin coating, knife coating, etc. It can be done.

[0172] The display device performs display by transmitting light from a light source or a display element. Therefore, all thin films such as the substrate, insulating film, and conductive film provided in the pixel portion through which light passes are made translucent to light in the wavelength region of visible light. In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, the light transmittance and reflectivity may be selected according to the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer. It is sufficient to select the light transmittance and reflectivity according to the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0173] For the first electrode layer 4030 and the second electrode layer 4031, a conductive material having light transmittance such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used. In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or nitrides thereof. It can be formed using one or more of them.

[0174]

[0175]

[0176] ​​​​​​​​​​​The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For this purpose, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, Or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or Derivatives and the like.

[0177] In addition, since transistors are easily damaged by static electricity, etc., It is preferable to provide a protection circuit using a non-linear element.

[0178] As described above, by using the transistor described in Embodiment 1 as an example, a highly reliable semiconductor device can be obtained. The semiconductor device can be provided by using the transistor exemplified in the first embodiment. Not only semiconductor devices with display functions, but also power devices mounted on power supply circuits, LSI semiconductor integrated circuits such as semiconductor devices having an image sensor function for reading information of an object, The present invention can be applied to semiconductor devices having various functions.

[0179] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0180] (Embodiment 3) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. Examples include cameras such as a digital camera, digital photo frames, mobile phones (also referred to as cellular phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. Examples of electronic devices equipped with the liquid crystal display device described in the above embodiments will be described.

[0181] Figure 10(A) shows a notebook personal computer, which is composed of a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable notebook personal computer can be obtained.

[0182] Figure 10(B) shows a portable information terminal (PDA). The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. Also, there is a stylus 3022 as an accessory for operation. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a more reliable portable information terminal (PDA) can be obtained.

[0183] Figure 10(C) shows an example of an e - book. For example, the e - book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can perform an opening and closing operation around the shaft portion 2711. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0184] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. It is incorporated. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By configuring to display different screens, for example, a text can be displayed on the right display unit (display unit 2705 in FIG. 10(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 10(C)). By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable electronic book 2700 can be obtained. It may be. In this case, for example, a text can be displayed on the right display unit (display unit 2705 in FIG. 10(C)), and an image can be displayed on the left display unit (display unit 2707 in FIG. 10(C)). By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable electronic book 2700 can be obtained.

[0185] Also, FIG. 10(C) shows an example in which the housing 2701 is provided with an operation unit or the like. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided. By the operation keys 2723, pages can be sent. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit. Also, the back surface or side surface of the housing may be configured to be provided with external connection terminals (earphone terminals, USB terminals, etc.), a recording medium insertion part, etc. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. It is also possible to configure to purchase and download desired book data, etc. from an electronic book server wirelessly.

[0186] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wirelessly it is also possible to configure to purchase and download desired book data, etc. from an electronic book server.

[0187] FIG. 10(D) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection It is provided with terminals 2808 and the like. Further, the housing 2800 is for charging a portable information terminal. It is provided with a solar cell 2810, an external memory slot 2811, and the like. Further, the antenna is built inside the housing 2801. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable mobile phone can be obtained.

[0188] In addition, the display panel 2802 is provided with a touch panel, and a plurality of operation keys 2805 shown with dotted lines in which video is displayed in FIG. 10(D) are shown. Note that a booster circuit for boosting the voltage generated by the solar cell 2810 to the voltage required for each circuit is also mounted. The voltage generated by the solar cell 2810 is boosted to the voltage required for each circuit. A booster circuit for boosting the voltage generated by the solar cell 2810 to the voltage required for each circuit is also mounted.

[0189] The display panel 2802 changes the display direction as appropriate according to the usage form. Further, since a camera lens 2807 is provided on the same surface as the display panel 2802, a video phone is possible. The display panel 2802 is provided with a camera lens 2807 on the same surface, so a video phone is possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, and video calls, recording, playback, etc. are possible. Further, the housing 2800 and the housing 2801 can be slid and can be changed from the unfolded state as shown in FIG. 10(D) to an overlapping state, enabling miniaturization suitable for portability. The housing 2800 and the housing 2801 can be slid and can be changed from the unfolded state as shown in FIG. 10(D) to an overlapping state, enabling miniaturization suitable for portability. The housing 2800 and the housing 2801 can be slid and can be changed from the unfolded state as shown in FIG. 10(D) to an overlapping state, enabling miniaturization suitable for portability.

[0190] The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication with a personal computer and the like. Also the external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication with a personal computer and the like. Also by inserting a recording medium into the external memory slot 2811, it is possible to handle larger amounts of data storage and transfer. By inserting a recording medium into the external memory slot 2811, it is possible to handle larger amounts of data storage and transfer.

[0191] In addition to the above functions, it may be provided with an infrared communication function, a television reception function, and the like. In addition to the above functions, it may be provided with an infrared communication function, a television reception function, and the like.

[0192] FIG. 10(E) is a digital video camera, which includes a main body 3051, a display unit (A) 3057 , an eyepiece 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056 , etc. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable digital video camera can be obtained.

[0193] FIG. 10(F) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. By applying the semiconductor device shown in Embodiment 1 or Embodiment 2, a highly reliable television device can be obtained.

[0194] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit. Further, the remote control unit may be configured to include a display unit for displaying information output from the remote control unit.

[0195] Note that the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts, and can further be connected to a communication network by wire or wirelessly via the modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication. .

[0196] As described above, the configurations, methods, etc. shown in this embodiment are the same as those shown in other embodiments They can be used in appropriate combinations.

Explanation of Signs

[0197] 110 Transistor 120 Transistor 130 Transistor 140 Transistor 150 Transistor 160 Transistor 170 Transistor 180 Transistor 200 Substrate 202 Insulating Film 204 Metal Oxide Film 206 Oxide Semiconductor Film 208a Source Electrode 208b Drain Electrode 210 Metal Oxide Film 212 Gate Insulating Film 214 Gate Electrode 2700 E - book 2701 Housing 2703 Housing 2705 Display Unit 2707 Display Unit 2711 Shaft Portion 2721 Power Supply 2723 Operation Key 2725 Speaker 2800 Housing 2801 Housing 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera Lens 2808 External Connection Terminal 2810 Solar Cell 2811 External Memory Slot 3001 Main Body 3002 Housing 3003 Display Unit 3004 Keyboard 3021 Main body 3022 Stylus 3023 Display unit 3024 Operation button 3025 External interface 3051 Main body 3053 Eyepiece 3054 Operation switch 3055 Display unit (B) 3056 Battery 3057 Display unit (A) 4001 Substrate 4002 Pixel section 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4018a FPC 4018b FPC 4019 Anisotropic conductive film 4021 Insulating layer 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4035 Spacer 4510 Partition wall 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling material 4612 Cavity 4613 Spherical particle 4614 Filling material 4615a Black region 4615b White region 9600 Television device 9601 Housing 9603 display unit 9605 stand

Claims

1. an insulating film on a substrate; a first oxide film having a region on the insulating film; a first conductive film having a region on the first oxide film; a second conductive film having an area on the first oxide film; an oxide semiconductor film having a region on the first oxide film; a second oxide film having a region on the oxide semiconductor film; and a third conductive film having an area on the second oxide film; the insulating film comprises silicon nitride; the second oxide film has the same material as the first oxide film; the oxide semiconductor film has a channel formation region of a transistor, the first conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the second conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the third conductive film has a region that functions as a gate electrode of the transistor, the second oxide film has a region in contact with an upper surface of the oxide semiconductor film, the oxide semiconductor film has a region in contact with an upper surface of the first oxide film, the oxide semiconductor film has a region in contact with a top surface of the first conductive film and a region in contact with a side surface of the first conductive film; the oxide semiconductor film has a region in contact with a top surface of the second conductive film and a region in contact with a side surface of the second conductive film; the third conductive film has a region overlapping with the oxide semiconductor film with the second oxide film interposed therebetween; the second oxide film has a region that does not overlap with the third conductive film, the first conductive film has a region that does not overlap with the second oxide film; the second conductive film has a region that does not overlap with the second oxide film, an end portion of the second oxide film is disposed above the oxide semiconductor film in a cross-sectional view taken along a channel length direction of the transistor.

2. an insulating film on a substrate; a first oxide film having a region on the insulating film; a first conductive film having a region on the first oxide film; a second conductive film having an area on the first oxide film; an oxide semiconductor film having a region on the first oxide film; a second oxide film having a region on the oxide semiconductor film; and a third conductive film having an area on the second oxide film; the insulating film comprises silicon nitride; the second oxide film has the same material as the first oxide film; the oxide semiconductor film has a channel formation region of a transistor, the first conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the second conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the third conductive film has a region that functions as a gate electrode of the transistor, the second oxide film has a region in contact with an upper surface of the oxide semiconductor film, the oxide semiconductor film has a region in contact with an upper surface of the first oxide film, the oxide semiconductor film has a region in contact with a top surface of the first conductive film and a region in contact with a side surface of the first conductive film; the oxide semiconductor film has a region in contact with a top surface of the second conductive film and a region in contact with a side surface of the second conductive film; the third conductive film has a region overlapping with the oxide semiconductor film with the second oxide film interposed therebetween; the second oxide film has a region that does not overlap with the third conductive film, the first conductive film has a region that does not overlap with the second oxide film; the second conductive film has a region that does not overlap with the second oxide film, in a cross-sectional view of a cross section cut along a channel length direction of the transistor, an end of the second oxide film is disposed above the oxide semiconductor film, and an end of the third conductive film is disposed above the second oxide film.

3. In claim 1 or 2, the first conductive film has a region overlapping with the oxide semiconductor film and a region not overlapping with the oxide semiconductor film, the second conductive film has a region overlapping with the oxide semiconductor film and a region not overlapping with the oxide semiconductor film.

Images