Information processing apparatus, information processing system, and method for controlling information processing apparatus

Abstract

To reduce degradation in processing power while keeping the size of each device small.SOLUTION: A processor 101 and an FPGA 102 make access requests. A memory 103 accepts the access requests from the processor 101 and the FPGA 102. A bus includes a shared connection path to the memory 103 shared by the processor 101 and the FPGA 102, a first path connecting the processor 101 to the shared connection path, and a second path connecting the FPGA 102 to the connection path. A control IC 104 blocks the first path during the access to the memory 103 by the FPGA 102.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an information processing apparatus, an information processing system, and a control method for an information processing apparatus.

Background Art

[0002] Conventionally, in an information processing apparatus, it has been common to connect various devices such as a processor on the same bus. For example, in a conventional information processing apparatus, a processor, an FPGA (Field Programmable Gate Array), and a memory are connected on the same bus. The FPGA has functions such as connecting a plurality of other devices such as USB devices and arbitrating bus access of each device. In such an information processing apparatus, a parallel bus is used. And devices are connected to each other by an address line, a data line, and a control line for bus communication.

[0003] Here, in place of or in addition to the FPGA in the above configuration, an ASIC (Application Specific Integrated Circuit) may be arranged. In the following description, the case where the FPGA is connected will be described as an example, but a configuration using an ASIC instead of the FPGA may also be used, or a configuration using both the FPGA and the ASIC may be used. Here, the FPGA and the ASIC may be collectively referred to as a customizable integrated circuit.

[0004] Generally, when a plurality of devices are connected on the same bus, they are divided into a side that makes an access request and a side that is the target of the access request according to the role of each device. The device that makes an access request is called a master, and the device that is the target of the access request is called a slave. A configuration in which a plurality of masters exist on the same bus is called a multi-master. In a multi-master, a bus arbitration function for arbitrating bus access is generally used. In an information processing apparatus equipped with a device having a bus arbitration function, a bus arbitration line is added for bus communication between devices.

[0005] Thus, conventional information processing devices have been designed assuming a configuration that allows access by multiple masters on the same bus, i.e., a multi-master configuration. However, in recent information processing devices, many functions are integrated into one device, and the introduction of a configuration in which one device serves as the master is progressing. In such a configuration, devices without a bus arbitration function are often used. When a device without a bus arbitration function is used, the bus arbitration path is not arranged between devices.

[0006] However, when multiple devices without a bus arbitration function are connected on the same bus, the following problems occur. For example, a configuration in which a processor, an FPGA, and a memory are connected on the same bus, and the processor and the FPGA access the memory, which is a slave, as masters will be described as an example. In this configuration, since each device does not have a bus arbitration function, arbitration of the bus usage right using a bus arbitration signal cannot be performed between devices. Therefore, there is a risk of a bus collision occurring when the processor accesses the memory while the FPGA is accessing the memory.

[0007] As a configuration for avoiding such a bus collision, a configuration in which the processor and the FPGA are connected by a first bus and the FPGA and the memory are connected by a second bus can be considered. In this case, between the processor and the FPGA, the processor serves as the master and the FPGA serves as the slave, and between the FPGA and the memory, the FPGA serves as the master and the memory serves as the slave. The processor accesses the memory via the FPGA, and the FPGA arbitrates access between the processor and its own memory. In this case, a response standby signal line connecting the processor and the FPGA is arranged. The response standby signal is activated by the FPGA and serves to put the processor in a response standby state.

[0008] Note that, as a communication technology between devices using the bus arbitration function in an information processing apparatus, technologies have been proposed that limit the processing of a bus master to a single process and suppress sending signals to other masters to become a bus master. In addition, a technology has been proposed that sets the time of occupying a multi-master bus and stops access when the set time is exceeded.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] However, since signal lines are wired between the FPGA and the processor, and between the FPGA and the memory respectively, the FPGA will have a large number of pins. Therefore, the enlargement of the FPGA and the increase in cost due to the enlargement become problems. In addition, the FPGA intervenes in the communication between the processor and the memory, which increases the access time of the processor to the memory, and there is a risk of a decrease in processing ability due to the deterioration of the bus communication performance.

[0011] One aspect of the present invention reduces the reduction in processing ability while suppressing the size of each device.

Means for Solving the Problems

[0012] The information processing apparatus according to one aspect has the following components. The first device and the second device make access requests. The third device receives the access requests from the first device and the second device. The bus has a connection path to the third device shared by the first device and the second device, a first path connecting the first device to the connection path, and a second path connecting the second device to the connection path. The first control IC blocks the first path during access to the third device by the second device.

Effect of the Invention

[0013] According to the present invention, it is possible to reduce a decrease in processing ability while suppressing the size of each device.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9A

Figure 9B

Figure 9C

Figure 10

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of an information processing apparatus, an information processing system, and a control method of the information processing apparatus will be described with reference to the drawings. Note that the same elements are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate. Also, the embodiments can be combined as appropriate within a non - conflicting range.

[0016] (Description of the Conventional Configuration) FIG. 1 is a circuit diagram of a multi - master configuration using a device having a conventional bus arbitration function. In the configuration shown in FIG. 1, a processor 301, an FPGA 302, and a memory 303 are connected to the same bus. In this case, between the processor 301 and the FPGA 302, for bus communication, they are connected by an address line 111, a data line 112, a control line 113, and a bus arbitration line 114, and each line is connected to the memory 303.

[0017] Both the processor 301 and the FPGA 302 are masters with the memory 303 as a slave. In FIG. 1, state 11 indicates the case where the processor 301 accesses the memory 303. Also, state 12 indicates the case where the FPGA 302 accesses the memory 303.

[0018] When the processor 301 accesses the memory 303 as shown in state 11, the following access operation is performed.

[0019] The processor 301 activates the bus arbitration signal using the bus arbitration line 114 and owns the bus usage right (step S101). If the FPGA 302, which is already another master, occupies the bus usage right, the processor 301 waits until it is released.

[0020] Next, the processor 301 starts an access request to the memory 303 using the address line 111, the data line 112, and the control line 113 (step S102). While the processor 301 accesses the memory 303, the FPGA 302 determines whether to own the bus usage right based on the usage status of the bus arbitration signal. The FPGA 302 waits until the processor 301 releases the bus usage right.

[0021] After the access to the memory 303 is completed, the processor 301 deactivates the bus arbitration signal on the bus arbitration line 114 and releases the bus usage right (step S103). As a result, the FPGA 302 can issue an access request to the memory 303.

[0022] When the FPGA 302 shown in state 12 accesses the memory 303, the following access operation is performed.

[0023] The FPGA 302 checks whether the bus arbitration signal on the bus arbitration line 114 is active. If the bus usage right is not owned by the processor 301, which is another master, the FPGA 302 activates the bus arbitration signal and owns the bus usage right (step S104). If it is owned by the processor 301, the FPGA 302 waits until it is released.

[0024] FPGA 302 starts an access request to memory 303 using address line 111, data line 112, and control line 113 (step S105). While FPGA 302 is accessing memory 303, processor 301 determines ownership of the bus usage based on the usage status of the bus arbitration signal. Processor 301 waits until FPGA 302 releases the bus usage right.

[0025] After completing the access to memory 303, FPGA 302 invalidates the bus arbitration signal on bus arbitration line 114 to release the bus usage right (step S106). As a result, processor 301 can issue an access request to memory 303.

[0026] FIG. 2 is a circuit diagram of an example of a multi-master configuration using a device without a conventional bus arbitration function. Next, with reference to FIG. 2, the configuration when the bus arbitration line 114 is simply removed from the circuit of FIG. 1 will be described. In FIG. 1, state 13 indicates the case where processor 311 accesses memory 313. Also, state 14 indicates the case where processor 311 issues an access request to memory 313 while FPGA 312 is accessing memory 313.

[0027] When processor 311 accesses memory 313 as shown in state 13, the following access operations are performed.

[0028] Processor 311 starts an access request to memory 313 using address line 111, data line 112, and control line 113 (step S111). Since FPGA 312 can confirm the access state based on the usage status of control line 113, it waits until processor 311 completes the access to memory 313. After processor 311 finishes accessing memory 313, FPGA 312 can issue an access request to memory 313.

[0029] When the processor 311 issues an access request to the memory 313 while the FPGA 312 shown in state 14 is accessing the memory 313, the following access operation occurs.

[0030] The FPGA 312 starts an access request to the memory 313 using the address line 111, data line 112, and control line 113 (step S112). Since the processor 311 does not check the usage state of the control line 113, it starts an access request to the memory 313 regardless of the access situation of the FPGA 312 (step S113). In this case, a bus collision occurs between the processor 311 and the FPGA 312, and the processor 311 fails to access the memory 313 (step S114).

[0031] Next, a conventional general configuration for avoiding the occurrence of bus collisions in FIG. 2 will be described. FIG. 3 is a circuit diagram of a configuration in which a processor accesses a memory via a conventional FPGA. Here, the processor 321 and the FPGA 322 are directly connected by a bus, and the FPGA 322 and the memory 323 are directly connected by a bus. And the processor 321 and the memory 323 are connected by a bus via the FPGA 322. In this case, an address line 121, a data line 122, a control line 123, and a response waiting line 124 are connected between the processor 321 and the FPGA 322 for bus communication. Also, an address line 125, a data line 126, and a control line 127 are connected between the FPGA 322 and the memory 323 for bus communication.

[0032] Both the processor 321 and the FPGA 322 are masters with the memory 323 as a slave. In FIG. 3, state 15 shows the case where the processor 321 accesses the memory 323. Also, state 16 shows the case where the FPGA 322 accesses the memory 323.

[0033] When the processor 321 shown in state 15 accesses the memory 323, the following access operation is performed.

[0034] The processor 321 starts an access request to the FPGA 322 using the address line 121, data line 122, and control line 123 (step S121).

[0035] Upon receiving the access request from the processor 321, the FPGA 322 starts an access request to the memory 323 using the address line 125, data line 126, and control line 127 (step S122). Also, the FPGA 322 outputs a response waiting signal to the processor 321 using the response waiting line 124, putting the processor 321 in a response waiting state (step S123).

[0036] During the access to the memory 323 by the processor 321, since the access request from the processor 321 passes through the FPGA 322, the FPGA 322 can determine the ownership status of the bus usage right and waits until the access by the processor 321 ends. After the access by the processor 321 ends, the FPGA 322 can execute an access request to the memory 323.

[0037] When the FPGA 322 accesses the memory 323 as shown in state 16, the following access operations are performed.

[0038] The FPGA 322 starts an access request to the memory 323 using the address line 125, data line 126, and control line 127 (step S124). After the access by the FPGA 322 ends, the processor 321 can request an access to the memory 323.

[0039] During the access to the memory 323 by the FPGA 322, if the processor 321 starts an access request to the memory 323 using the address line 121, data line 122, and control line 123 (step S125), the FPGA 322 outputs a response waiting signal to the processor 321, putting the processor 321 in a response waiting state (step S126).

[0040] After the access to the memory 323 of the FPGA 322 is completed, the FPGA 322 receives an access request to the memory 323 from the processor 321 and starts an access request to the memory 323 using the address line 125, the data line 126, and the control line 127.

[0041] In this case, the FPGA 322 has signal lines between the processor 321 and the FPGA 322 and between the FPGA 322 and the memory 323, respectively. Therefore, the FPGA 322 has a large number of pins, which causes the FPGA 322 to be enlarged and the cost to be increased. In addition, the presence of the FPGA 322 between the processor 321 and the memory 323 increases the access time of the processor 321 to the memory 323, which causes the performance of the bus communication to deteriorate.

[0042] (First Embodiment) (Overall Configuration) FIG. 4 is a circuit diagram of an information processing apparatus according to the first embodiment. The information processing apparatus 1 according to the present embodiment realizes access by a multi-master on the same bus using a processor 101 and an FPGA 102 that do not have a bus arbitration function. The information processing apparatus 1 according to the present embodiment can suppress the enlargement of the FPGA 102 and suppress the deterioration of the performance of the bus communication. Hereinafter, the details of the information processing apparatus 1 according to the present embodiment will be described with reference to FIG. 4.

[0043] In the information processing apparatus 1 according to the first embodiment, the processor 101, the FPGA 102, and the memory 103 are connected to the same bus. The processor 101 and the FPGA 102 are master devices that issue access requests to the memory 103. The memory 103 is a slave device that receives access requests from the processor 101 and the FPGA 102. The processor 101 corresponds to an example of the "first device", and the FPGA 102 corresponds to an example of the "second device". The memory 103 corresponds to an example of the "third device".

[0044] Also, between the processor 101 and the FPGA 102, for bus communication, they are connected by an address line 111, a data line 112, and a control line 113. Also, the address line 111, the data line 112, and the control line 113 branch at a branch point between the processor 101 and the FPGA 102, and each line is connected to the memory 103. The address line 111, the data line 112, and the control line 113 are an example of a "bus". Also, among the address line 111, the data line 112, and the control line 113, the path from the processor 101 to the branch point is an example of a "first path". Also, among the address line 111, the data line 112, and the control line 113, the path from the FPGA 102 to the branch point is an example of a "second path". And among the address line 111, the data line 112, and the control line 113, the path from the branch point to the memory 103 is an example of a "shared connection path". That is, the bus has a shared connection path to a third device shared by a first device and a second device, a path connecting the first device to the shared connection path, and a second path connecting the second device to the shared connection path.

[0045] Furthermore, a control IC (Integrated Circuit) 104 is arranged in the vicinity of the processor 101 on the bus. The control IC 104 is arranged between the processor 101 and the branch point of each line for extending bus communication. Furthermore, an access request line 115 extending from the control IC 104 is connected to the FPGA 102. Also, a response waiting line 116 extending from the FPGA 102 is connected to the processor 101 and the control IC 104.

[0046] The FPGA 102 activates a response waiting signal on the response waiting line 116 in an initial state and when it makes an access request to the memory 103. Here, the FPGA 102 outputs the response waiting signal to both the processor 101 and the control IC 104.

[0047] Also, when an access request by the processor 101 is initiated, the FPGA 102 receives an input of an access request signal activated on the access request line 115 from the control IC 104. Then, if the FPGA 102 is not accessing the memory 103 itself, it deactivates the response waiting signal for the processor 101 and the control IC 104.

[0048] On the other hand, when the FPGA 102 receives an input of the access request signal and is accessing the memory 103 itself, it maintains the activation of the response waiting signal for the processor 101 and the control IC 104. After that, when the access to the memory 103 is completed, the FPGA 102 deactivates the response waiting signal for the processor 101 and the control IC 104.

[0049] The response waiting signal is an example of the "first signal". That is, when the FPGA 102, which is the second device, is accessing the memory 103, which is the third device, it activates the first signal output to the control IC 104, which is the first control IC. Also, when the FPGA 102, which is the second device, is not accessing the memory 103, which is the third device, it deactivates the first signal when the processor 101, which is the first device, makes an access request. Also, the access request signal is an example of the "second signal". That is, when the access request signal, which is the second signal, is activated in the FPGA 102, which is the second device, it deactivates the response waiting signal, which is the first signal.

[0050] Also, a plurality of devices such as USBs are connected to the FPGA 102, for example. Then, the FPGA 102 receives an access request to the memory 103 from the connected devices. When there are multiple access requests, the FPGA 102 performs arbitration and makes access requests to the memory 103 in order according to the requests of each device.

[0051] When the FPGA 102 makes an access request, it determines whether the processor 101 is accessing the memory 103 based on whether the access request signal input from the control IC 104 via the access request line 115 is valid or not.

[0052] When the processor 101 is not accessing the memory 103 and the response waiting signal is enabled, if the FPGA 102, it directly sends an access request to the memory 103 to perform the access. On the contrary, when the response waiting signal is disabled, the FPGA 102 enables the response waiting signal. Then, the FPGA 102 sends an access request to the memory 103 to perform the access.

[0053] On the other hand, when the processor 101 is accessing the memory 103, the FPGA 102 waits until the access request signal input via the access request line 115 is disabled. After that, when the access request signal is disabled by the control IC 105, the FPGA 102 enables the response waiting signal. Then, the FPGA 102 sends an access request to the memory 103 to perform the access.

[0054] When in the initial state or when the FPGA 102 makes an access request to the memory 103, the processor 101 receives the input of the response waiting signal enabled via the response waiting line 116 from the FPGA 102. As a result, the processor 101 enters the access waiting state. In this case, if the processor 101 does not receive a response to the access request sent to the memory 103, it does not determine it as an error and continues to output the access request.

[0055] When a process involving access to the memory 103 occurs, the processor 101 outputs an access request to the control IC 104 using the address line 111, data line 112, and control line 113. If the FPGA 102 is not using the bus, the processor 101 receives an input of an activated response standby signal from the FPGA 102 using the response standby line 116. Then, the processor 101 accesses the memory 103 using the bus.

[0056] On the other hand, when the FPGA 102 is using the bus, the processor 101 does not receive a response to the access request. However, if the response standby signal is activated, the processor 101 repeats the output of the access request without determining it as an error. After that, when the access of the FPGA 102 is completed, the processor 101 receives an input of a deactivated response standby signal from the FPGA 102 using the response standby line 116. Then, the processor 101 accesses the memory 103 using the bus.

[0057] The control IC 104 receives an input of an access request from the processor 101. When receiving the input of the access request, the control IC 104 activates an access request signal sent to the FPGA 102 using the access request line 115. The control IC 104 keeps the access request signal activated during the access of the processor 101 to the memory 103. After that, when the access of the processor 101 to the memory 103 is completed, the control IC 104 deactivates the access request signal.

[0058] Also, the control IC 104 receives an input of an activated response standby signal from the FPGA 102 using the response standby line 116. When receiving the input of the activated response standby signal, the control IC 104 cuts off the address line 111, data line 112, and control line 113. After that, when the response standby signal on the response standby line 116 is deactivated, the control IC 104 connects the address line 111, data line 112, and control line 113 to release the bus between the processor 101 and the memory 103.

[0059] This control IC 104 is an example of the "first control IC". That is, the first control IC blocks the first path from the processor 101 to the branch point during access by the FPGA 102, which is the second device, to the memory 103, which is the third device. Further, the first control IC blocks the path from the processor 101, which is the first path, to the branch point when the response wait signal, which is the first signal, is activated, and connects the path from the processor 101, which is the first path, to the branch point when the response wait signal, which is the wait signal, is deactivated.

[0060] Also, when the processor 101, which is the first device, makes an access request, the first control IC activates the second signal output to the FPGA 102, which is the second device.

[0061] When the memory 103 receives an access request input from the FPGA 102, it permits access by the FPGA 102. Also, when the memory 103 receives an access request input from the processor 101, it permits access by the processor 101.

[0062] (Flow of access control processing) FIG. 5 is a diagram for explaining the access operations from each device to the memory in the information processing apparatus according to the first embodiment. Next, with reference to FIG. 5, the access operations from the processor 101 or the FPGA 102 to the memory 103 in the information processing apparatus 1 in the present embodiment will be collectively described. State 21 in FIG. 5 shows the case where the processor 101 accesses the memory 103. Also, state 22 shows the case where the FPGA 102 accesses the memory 103.

[0063] In the information processing apparatus 1 according to the present embodiment, when the processor 101 shown in state 21 accesses the memory 103, the following access operations are performed.

[0064] In the initial state, the FPGA 102 enables the response waiting signal on the response waiting line 116 (step S1). As a result, the control IC 104 cuts off the bus connected to the memory 103 of the processor 101. Also, the processor 101 enters a waiting state for access.

[0065] Next, upon receiving the activation of the access request signal on the access request line 115 by the control IC 104, the FPGA 102 disables the response waiting signal on the response waiting line 116 (step S2). As a result, the control IC 104 releases the bus connected to the memory 103 of the processor 101. Also, the processor 101 becomes accessible.

[0066] The access request from the processor 101 to the memory 103 that had been blocked becomes reachable, and the processor 101 accesses the memory 103 (step S3).

[0067] After the access by the processor 101 is completed, the FPGA 102 receives the deactivation of the access request signal on the access request line 115 by the control IC 104. The FPGA 102 confirms the end of the access to the memory 103 of the processor 101 due to the deactivation of the access request signal and enables the response waiting signal on the response waiting line 116 (step S4). As a result, the control IC 104 cuts off the bus connected to the memory 103 of the processor 101. Also, the processor 101 enters a waiting state for access.

[0068] In the information processing apparatus 1 according to this embodiment, when the FPGA 102 indicated by the state 22 accesses the memory 103, the following access operation is performed.

[0069] When the processor 101 accesses the memory 103, the FPGA 102 waits for the completion of the access by the processor 101 and then enables the response waiting signal on the response waiting line 116 (step S11). However, if the response waiting signal has already been enabled and the processor 101 is not accessing the memory 103, the FPGA 102 maintains the state in which the response waiting signal on the response waiting line 116 is enabled. When the response waiting signal is enabled, the control IC 104 cuts off the bus connecting the processor 101 to the memory 103. Also, the processor 101 enters a state of waiting for access.

[0070] Next, the FPGA 102 starts an access request to the memory 103 using the address line 111, the data line 112, and the control line 113 (step S12).

[0071] Until the access by the FPGA 102 to the memory 103 is completed, the FPGA 102 keeps the response waiting signal on the response waiting line 116 enabled. As a result, the control IC 104 cuts off the bus connecting to the memory 103 of the processor 101 (step S13). During this time, the access request output from the processor 101 is blocked from being sent to the memory 103 by the control IC 104, and a bus collision with the access request between the FPGA 102 and the memory 103 is suppressed.

[0072] When an access request is input from the processor 101 to the control IC 104 during the access from the FPGA 102 to the memory 103, the control IC 104 enables the access request signal on the access request line 115 (step S14). In this case, since the processor 101 is in a waiting-for-access state, it repeats the output of the access request without making an error determination even without a response to the access request.

[0073] After the access to the memory 103 by the FPGA 102 ends, if the access request signal is valid, the FPGA 102 invalidates the response standby signal on the response standby line 116 (step S15). As a result, the control IC 104 releases the bus connecting to the memory 103 of the processor 101. The access request from the blocked processor 101 to the memory 103 can reach the memory 103, and the processor 101 can access the memory 103.

[0074] Figure 6 is a flowchart showing the access control process of the FPGA. Next, with reference to Figure 6, the flow of the access control process of the FPGA 102 will be described.

[0075] When the information processing apparatus 1 starts operating, the FPGA 102 validates the response standby signal on the response standby line 116 as an initial state (step S201). As a result, the control IC 104 blocks the bus connecting to the memory 103 of the processor 101. Also, the processor 101 enters a state of waiting for access.

[0076] Next, the FPGA 102 monitors whether the access request signal sent on the access request line 115 is validated, and determines whether an access request from the processor 101 has occurred (step S202).

[0077] When an access request from the processor 101 has occurred (step S202: affirmative), the FPGA 102 determines whether it is accessing the memory 103 itself (step S203).

[0078] When the FPGA 102 is accessing the memory 103 (step S203: affirmative), the FPGA 102 waits and determines whether its access to the memory 103 has been completed (step S204).

[0079] If the access to its own memory 103 is not completed (step S204: NO), the FPGA 102 waits until the access to the memory 103 is completed.

[0080] If the FPGA 102 is not accessing the memory 103 (step S203: NO) or the access to the memory 103 is completed (step S204: YES), the FPGA 102 invalidates the response wait signal (step S205).

[0081] If there is no access request from the processor 101 (step S202: NO) or after invalidating the response wait signal in step S205, the FPGA 102 determines whether a memory access request of the connection device has occurred (step S206).

[0082] If a memory access request of the connection device has occurred (step S206: YES), the FPGA 102 determines whether the processor 101 is accessing the memory 103 based on whether the access request signal is valid or invalid (step S207).

[0083] If the processor 101 is accessing the memory 103 (step S207: YES), the FPGA 102 waits and determines whether the access of the processor 101 to the memory 103 is completed (step S208).

[0084] If the access of the processor 101 to the memory 103 is not completed (step S208: NO), the FPGA 102 waits until the access of the processor 101 to the memory 103 is completed.

[0085] If the processor 101 is not accessing the memory 103 (step S207: NO) or the access to the memory 103 is completed (step S208: YES), the FPGA 102 validates the response wait signal on the response wait line 116 (step S209).

[0086] Next, the FPGA 102 executes an access request to the memory 103 (step S210).

[0087] Next, the FPGA 102 executes an access to the memory 103 (step S211). Then, the FPGA 102 returns to step S202.

[0088] On the other hand, when there is no memory access request from the connected device (step S206: NO), the FPGA 102 determines whether to end the operation based on, for example, the power supply to the information processing apparatus 1 being cut off (step S212). If the operation is not to end (step S212: NO), the FPGA 102 returns to step S202. In contrast, if the operation is to end (step S212: YES), the FPGA 102 ends the access control process.

[0089] FIG. 7 is a flowchart showing the access control process of the processor and the control IC. Next, with reference to FIG. 7, the access control flow of the processor 101 and the control IC 104 will be described.

[0090] The processor 101 and the control IC 104 detect the activation of the response waiting signal sent from the FPGA 102 at startup (step S301).

[0091] Then, the control IC 104 cuts off the bus connecting the processor 101 and the memory 103. Also, the processor 101 transitions to an access waiting state (step S302).

[0092] Next, the processor 101 determines whether an access request to the memory 103 has occurred (step S303). If no access request to the memory 103 has occurred (step S303: NO), the processor 101 waits for the output of an access request until an access request to the memory 103 occurs.

[0093] On the other hand, when an access request to the memory 103 occurs (step S303: affirmative), the processor 101 outputs the access request to the control IC 104 (step S304).

[0094] Upon receiving the input of the access request from the processor 101, the control IC 104 enables the access request signal on the access request line 115 (step S305).

[0095] Then, the processor 101 and the control IC 104 determine whether the response standby signal on the response standby line 116 has been disabled by the FPGA 102 (step S306). If the response standby signal has not been disabled (step S306: negative), the processor 101 and the control IC 104 return to step S304.

[0096] On the other hand, when the response standby signal has been disabled (step S306: affirmative), the control IC 104 releases the bus connecting the processor 101 and the memory 103. Also, the processor 101 releases the access waiting state (step S307).

[0097] Next, the processor 101 executes a memory access to the memory 103 using the bus released by the control IC 104 (step S308).

[0098] Thereafter, the processor 101 executes an access to the memory 103 (step S309).

[0099] The control IC 104 determines whether the access by the processor 101 to the memory 103 has been completed (step S310). If the access has not been completed (step S310: negative), the processor 101 and the control IC 104 return to step S309.

[0100] On the other hand, when the access is completed (step S310: affirmative), the control IC 104 invalidates the access request signal on the access request line 115 (step S311).

[0101] Thereafter, the processor 101 and the control IC 104 detect the activation of the response waiting signal sent from the FPGA 102 (step S312).

[0102] Then, the control IC 104 cuts off the bus connecting the processor 101 and the memory 103. Also, the processor 101 transitions to the access waiting state (step S313).

[0103] Thereafter, the processor 101 and the control IC 104 determine whether to end the operation based on, for example, the power supply to the information processing apparatus 1 being cut off (step S314). If the operation does not end (step S314: negative), the processor 101 and the control IC 104 return to step S303. On the other hand, if the operation ends (step S314: affirmative), the processor 101 and the control IC 104 end the access control process.

[0104] Here, in the above description, the case where the processor 101 and the FPGA 102 operate as multi-masters on the same bus has been described as an example, but it is not limited to this. As long as there are a plurality of devices that act as masters with respect to a slave device and those devices are connected on the same bus, other configurations may be used. For example, the FPGA 102 may be another customizable integrated circuit such as an ASIC.

[0105] In this embodiment, the control IC 104 outputs an access request signal using the access request line 115. However, other configurations can also be used. For example, for the output of the access request signal, the processor 101 and the FPGA 102 may be connected by the access request line 115, and the processor 101 may output the access request signal to the FPGA 102 without going through the control IC 104. Also, instead of the access request line 115, the control line 113 from the processor 101 may be regarded as the access request line 115, and the processor 101 may output an access request signal to the FPGA 102 using the control line 113.

[0106] (Effect) As described above, in the information processing apparatus according to this embodiment, the control IC is arranged between the processor and the memory up to the branch point in the same bus to which the memory, the processor, and the FPGA are connected. When the response standby signal output from the FPGA is activated, the control IC cuts off the bus and the processor transitions to the access waiting state. The FPGA detects the presence or absence of an access request from the processor based on the access request signal sent from the control IC, and if it is not accessing the memory itself, it gives the bus ownership to the processor. Conversely, when accessing the memory, the FPGA makes the processor wait until the memory access is completed and then gives the bus ownership. Also, the FPGA detects the access state of the processor to the memory based on the access request signal sent from the control IC, and if the processor is accessing, it waits until the access is completed and then executes its own access.

[0107] With such a configuration, a multi-master access configuration on the same bus using a processor without a bus arbitration function can be realized. Also, an increase in the number of pins of the customizable integrated circuit can be suppressed, and the enlargement and high cost of the customizable integrated circuit can be prevented. Furthermore, the access time between the processor and the memory can be shortened, and deterioration of the bus communication performance can be suppressed.

[0108] (Modification) In the first embodiment, the FPGA 102 was the main component for access control, but it is also possible to design with the processor 101 as the main component. The access operation in that case will be described below.

[0109] First, the case where the processor 101 accesses the memory 103 will be described. The processor 101 starts an access request to the memory 103 using the address line 111, the data line 112, and the control line 113. While the processor 101 is accessing the memory 103, the FPGA 102 can check whether the processor 101 is accessing the memory 103 based on the usage status of the control line 113. That is, the FPGA 102, which is the second device, can determine whether the processor 101, which is the first device, is accessing the memory 103, which is the third device, based on the usage status of the control line for accessing the memory 103 of the processor 101, which is the first device.

[0110] The FPGA 102 determines the ownership status of the bus usage based on the usage status of the control line 113 and waits until the access of the processor 101 to the memory 103 is completed. After the access of the processor 101 to the memory 103 is completed, the FPGA 102 can issue an access request to the memory 103.

[0111] Next, the case where the FPGA 102 accesses the memory 103 will be described. The FPGA 102 checks whether the processor 101 is not using the control line 113. If the control line 113 is not being used by the processor 101, the FPGA 102 activates the response waiting signal on the response waiting line 116. The control IC 104 cuts off the bus connected to the memory 103 of the processor 101 when the response waiting signal is activated.

[0112] On the other hand, when the control line 113 is being used by the processor 101, the FPGA 102 waits until the access to the memory 103 of the processor 101 is completed. After that, the FPGA 102 starts an access request to the memory 103 using the address line 111, the data line 112, and the control line 113.

[0113] Until the access from the FPGA 102 to the memory 103 is completed, the FPGA 102 enables the response waiting signal on the response waiting line 116. As a result, the control IC 104 cuts off the bus connected to the memory 103 of the processor 101. During this period, the access request output from the processor 101 is blocked from being sent to the memory 103 by the control IC 104, preventing a bus collision between the access between the FPGA 102 and the memory 103.

[0114] Also, when an access request is input from the processor 101 to the control IC 104 during the access to the memory 103 by the FPGA 102, the control IC 104 enables the access request signal on the access request line 115 connected to the FPGA 102. After the access to the memory 103 by the FPGA 102 is completed, if the access request signal is active, the FPGA 102 disables the response waiting signal on the response waiting line 116. The control IC 104 releases the bus connected to the memory 103 of the processor 101 upon receiving the disabling of the response waiting signal. As a result, the blocked access request from the processor 101 to the memory 103 becomes reachable, and the processor 101 can access the memory 103.

[0115] (Effect) As described above, in the information processing apparatus according to this modification example, the processor mainly executes access control to the memory that is a slave. In this way, even in access control mainly performed by the processor, a multi-master access configuration on the same bus using a processor without a bus arbitration function can be realized. Further, an increase in the number of pins of the customizable integrated circuit can be suppressed, and the enlargement and high cost of the customizable integrated circuit can be prevented. Furthermore, it is possible to shorten the access time between the processor and the memory and suppress the deterioration of the performance of bus communication.

[0116] (Second Embodiment) (Overall Configuration) FIG. 8 is a circuit diagram of an information processing apparatus according to the second embodiment. The information processing apparatus 1 according to this embodiment has three devices 201 and 202 that are masters, and an FPGA 102 on the same bus, and performs access control to realize access by multi-masters on the same bus. The information processing apparatus 1 according to this embodiment will be described below.

[0117] As shown in FIG. 8, the information processing apparatus 1 according to this embodiment includes an FPGA 102, a memory 103, a device 201, a device 202, a control IC 203, and a control IC 204. The FPGA 102, the memory 103, the device 201, and the device 202 are connected on the same bus. Also, an address line 111, a data line 112, and a control line 113 are connected between the FPGA 102, the memory 103, the device 201, and the device 202 for communication. The control IC 203 is arranged at the output end of the device 201 on the bus. The control IC 204 is arranged at the output end of the device 202 on the bus. The device 201 may be, for example, the processor 101 shown in FIG. 4. The control IC 203 may be, for example, the control IC 104 shown in FIG. 4.

[0118] FPGA 102 is an example of the "second device", and similar to Embodiment 1, the path from FPGA 102 to the branch point among the address line 111, data line 112, and control line 113 is an example of the "second path". Also, the memory 103 is an example of the "third device", and similar to Embodiment 1, the path from the branch point to the memory 103 among the address line 111, data line 112, and control line 113 is an example of the "shared connection path".

[0119] FPGA 102 is connected to the control IC 203 by the access request line 211. Also, FPGA 102 is connected to the control IC 204 by the access request line 213. Further, the response waiting line 212 extending from FPGA 102 is connected to the device 201 and the control IC 203. Also, the response waiting line 214 extending from FPGA 102 is connected to the device 202 and the control IC 204.

[0120] In the initial state, FPGA 102 enables the response waiting signals on the response waiting lines 212 and 214. For example, when the response waiting signal is disabled in the initial state, if the devices 201 and 202 start access requests simultaneously while the control ICs 203 and 204 have released the bus, a bus collision will occur and the access will fail. Therefore, FPGA 102 enables each response waiting signal in the initial state.

[0121] When the access request signal on the access request line 211 is activated by the control IC 203, the FPGA 102 confirms that the device 201 has output an access request. Then, when neither the FPGA 102 itself nor the device 202 is accessing the memory 103, the FPGA 102 deactivates the response standby signal on the response standby line 212. As a result, the device 201 can access the memory 103. Also, when either the FPGA 102 itself or the device 202 is accessing the memory 103, the FPGA 102 waits for the end of the access and then deactivates the response standby signal on the response standby line 212. Further, when access requests from a plurality of devices including the FPGA 102 itself overlap, the FPGA 102 arbitrates the access requests and causes the access to the memory 103 to be performed in order.

[0122] When the access request signal on the access request line 213 is activated by the control IC 204, the FPGA 102 confirms that the device 202 has output an access request. Then, when neither the FPGA 102 itself nor the device 201 is accessing the memory 103, the FPGA 102 deactivates the response standby signal on the response standby line 214. As a result, the device 202 can access the memory 103. Also, when either the FPGA 102 itself or the device 201 is accessing the memory 103, the FPGA 102 waits for the end of the access and then deactivates the response standby signal on the response standby line 214. In this case too, when access requests from a plurality of devices including the FPGA 102 itself overlap, the FPGA 102 arbitrates the access requests and causes the access to the memory 103 to be performed in order.

[0123] Also, when the FPGA 102 receives an access request from a connected device, it checks the validity of the access request signals on the access request lines 211 and 213 to determine whether either the device 201 or 202 is accessing the memory 103. If neither the device 201 nor 202 is accessing the memory 103, the FPGA 102 sends the access request to the memory 103 to access the memory 103. Also, if either the device 201 or 202 is accessing the memory 103, the FPGA 102 waits for the access to end, then sends the access request to the memory 103 to access the memory 103. Also in this case, when access requests from multiple devices including itself overlap, the FPGA 102 arbitrates the access requests to cause access to the memory 103 in order.

[0124] The device 201 and the device 202 perform the same access operation as the processor 101 in the first embodiment. Therefore, the operation will be briefly described below using the device 201 as an example. This device 201 corresponds to an example of the "first device", and the device 202 corresponds to an example of the "fourth device". Also, among the address line 111, the data line 112, and the control line 113, the path from the device 201 to the branch point corresponds to an example of the "first path". Also, among the address line 111, the data line 112, and the control line 113, the path from the device 202 to the branch point corresponds to an example of the "third path".

[0125] When the response standby signal on the response standby line 212 is enabled by the FPGA 102, the device 201 transitions to an access waiting state. Also, when the response standby signal on the response standby line 212 is disabled by the FPGA 102, the device 201 releases the access waiting state.

[0126] When device 201 accesses memory 103, it outputs an access request to control IC 203. In the access waiting state, without making an error determination even if there is no response to the access request, device 201 repeats the transmission of the access request. Also, when not in the access waiting state and the access request reaches memory 103, device 201 executes the access to memory 103.

[0127] Control ICs 203 and 204 perform the same access control as control IC 104 in the first embodiment. Therefore, the operation will be briefly described below using control IC 203 as an example. This control IC 203 corresponds to an example of the "first control IC", and control IC 204 corresponds to an example of the "second control IC".

[0128] Control IC 203 receives the input of the access request from device 201. Also, when the response waiting signal on response waiting line 212 is enabled by FPGA 102, control IC 203 cuts off the bus connected to memory 103 of device 201. As a result, the access request output from device 201 is stopped by control IC 203. Also, when the response waiting signal on response waiting line 212 is disabled by FPGA 102, control IC 203 releases the bus connected to memory 103 of device 201. As a result, the access request output from device 201 can reach memory 103 through control IC 203.

[0129] Control IC 204 also performs the same operation as control IC 203. That is, the second control IC cuts off the third path from the third device 202 to the branch point during the access to the third device, memory 103, by the first device, device 201, or the second device, FPGA 102. Also, the first control IC cuts off the first path from the first device 201 to the branch point during the access to the third device, memory 103, by the second device, FPGA 102, or the fourth device, device 202.

[0130] (Flow of access control processing) FIG. 9A is a diagram for explaining an access operation when one device in the information processing apparatus according to the second embodiment accesses the memory. FIG. 9B is a diagram for explaining an access operation when the FPGA in the information processing apparatus according to the second embodiment accesses the memory. FIG. 9C is a diagram for explaining an access operation when the other device in the information processing apparatus according to the second embodiment accesses the memory. Next, with reference to FIGS. 9A to 9C, the access operations from the device 201, the device 202, or the FPGA 102 to the memory 103 in the information processing apparatus 1 in the present embodiment will be collectively described.

[0131] In the information processing apparatus 1 according to the present embodiment, when the device 201 shown in FIG. 9A accesses the memory 103, the following access operation is performed.

[0132] The FPGA 102 activates the response standby signals on both the response standby lines 212 and 214 (step S21). As a result, the control IC 203 cuts off the bus connected to the memory 103 of the device 201. Also, the control IC 204 cuts off the bus connected to the memory 103 of the device 202. Also, both the devices 201 and 202 are in a state of waiting for access.

[0133] Next, the FPGA 102 receives the activation of the access request signal on the access request line 211 by the control IC 203 and deactivates the response standby signal on the response standby line 212 (step S22). As a result, the control IC 203 releases the bus connected to the memory 103 of the device 201. Also, the device 201 becomes accessible to the memory 103.

[0134] As a result, the access request from the device 201 that had been blocked reaches the memory 103, and the device 201 accesses the memory 103 (step S23). During this time, the access request output from the device 202 is blocked by the control IC 204, thereby suppressing a bus collision with the access between the device 201 and the memory 103.

[0135] After the access of the device 201 to the memory 103 ends, the FPGA 102 enables the response waiting signal on the response waiting line 212. The control IC 203 blocks the bus connected to the memory 103 of the device 201 (step S24).

[0136] When the FPGA 102 shown in FIG. 9B accesses the memory 103 in the information processing apparatus 1 according to the present embodiment, the following access operation is performed.

[0137] The FPGA 102 enables the response waiting signals on both the response waiting lines 212 and 214 (step S31). However, if the devices 201 and 202 are not accessing the memory 103, the FPGA 102 maintains the state in which the response waiting signals on the response waiting lines 212 and 214 are enabled. When the response waiting signal is enabled, the control IC 203 blocks the bus connected to the memory 103 of the device 201. Also, the control IC 204 blocks the bus connected to the memory 103 of the device 202. Also, both the devices 201 and 202 are in a state of waiting for access.

[0138] Next, the FPGA 102 starts an access request to the memory 103 using the address line 111, the data line 112, and the control line 113 (step S32).

[0139] Until the access to the memory 103 in the FPGA 102 is completed, the FPGA 102 keeps the response waiting signals on the response waiting lines 212 and 214 enabled. As a result, the control IC 203 cuts off the bus connecting to the memory 103 of the device 201. Also, the control IC 204 cuts off the bus connecting to the memory 103 of the device 202 (step S33). During this period, the access requests output from the devices 201 and 202 are blocked from being transmitted to the memory 103 by the control IC 104, and bus collisions with the access between the FPGA 102 and the memory 103 are suppressed.

[0140] During the access from the FPGA 102 to the memory 103, if an access request input from the device 201 to the control IC 203 occurs, the control IC 203 enables the access request signal on the access request line 211. Also, during the access from the FPGA 102 to the memory 103, if an access request input from the device 202 to the control IC 204 occurs, the control IC 204 enables the access request signal on the access request line 213 (step S34).

[0141] When an access request is issued during access from FPGA 102 to memory 103, the operations of device 201 and control IC 203 and those of device 202 and control IC 204 are the same. Therefore, hereinafter, the case where an access request is generated from device 201 will be described as an example. After the access from FPGA 102 to memory 103 is completed, if the access request signal on access request line 211 is valid, FPGA 102 invalidates the response standby signal on response standby line 212 (step S35). Control IC 203 releases the bus connected to memory 103 of device 201. As a result, the access request from device 201 that has been blocked can reach, and device 201 can access memory 103. When the access request from device 201 to memory 103 is started, FPGA 102 keeps the response standby signal on response standby line 214 valid. Thereby, control IC 204 keeps the bus connected to memory 103 of device 202 blocked, and bus collision with the access between device 201 and memory 103 is suppressed.

[0142] In the information processing apparatus 1 according to the present embodiment, when device 202 shown in FIG. 9C accesses memory 103, the following access operation is performed.

[0143] FPGA 102 validates the response standby signals on both response standby lines 212 and 214 (step S41). Thereby, control IC 203 blocks the bus connected to memory 103 of device 201. Also, control IC 204 blocks the bus connected to memory 103 of device 202. Also, both devices 201 and 202 are in a state of waiting for access.

[0144] Next, upon receiving the activation of the access request signal on the access request line 213 by the control IC 204, the FPGA 102 deactivates the response standby signal on the response standby line 214 (step S42). As a result, the control IC 204 releases the bus connected to the memory 103 of the device 202. Also, the device 202 becomes accessible to the memory 103.

[0145] Thereby, the access request from the device 202 to the memory 103 that was blocked becomes reachable, and the device 202 accesses the memory 103 (step S43). During this time, the access request output from the device 201 is blocked by the control IC 203, suppressing a bus collision with the access between the device 202 and the memory 103.

[0146] After the access to the memory 103 of the device 202 is completed, the FPGA 102 activates the response standby signal on the response standby line 214. The control IC 204 blocks the bus connected to the memory 103 of the device 202 (step S44).

[0147] Note that in this embodiment, the control ICs 203 and 204 output the access request signal using the access request lines 211 and 213, but other configurations are also possible. For example, for the output of the access request signal, the devices 201 and 202 and the FPGA 102 may be connected by the access request lines 211 and 213, and the devices 201 and 202 may output the access request signal to the FPGA 102 without going through the control ICs 203 and 204. Also, instead of the access request lines 211 and 213, the control lines 113 from the devices 201 and 202 may be regarded as the access request lines 211 and 213, and the devices 201 and 202 may output the access request signal to the FPGA 102 using the control lines 113.

[0148] Also, here, a multi-master configuration using three devices, namely devices 201 and 202, and FPGA 102, has been described as an example. However, even in a configuration where four or more devices are connected, it can be implemented in the same manner as in this embodiment. Also, the order and number of times of invalidating the response waiting signal by FPGA 102 for devices 201 and 202, etc., can be appropriately changed according to the operation. For example, FPGA 102 may invalidate the response waiting signal for device 202 after accessing memory 103 multiple times continuously while invalidating the response waiting signal for device 201.

[0149] (Effect) As described above, the information processing apparatus according to this modification example executes access control to a slave memory in a configuration where three or more devices having a bus interface without a bus arbitration function are connected on the same bus. In this way, even in a configuration where three or more devices are connected on the same bus, a multi-master access configuration on the same bus using a device without a bus arbitration function can be realized. Also, an increase in the number of pins of the customizable integrated circuit can be suppressed, and the enlargement and high cost of the customizable integrated circuit can be prevented. Furthermore, it is possible to shorten the access time between the device and the memory and suppress the deterioration of the performance of bus communication.

[0150] (System) Regarding the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above document and drawings, they can be arbitrarily changed unless otherwise specified.

[0151] Also, each component of each illustrated device is conceptually functional and does not necessarily have to be physically configured as shown in the figure. That is, the specific form of the dispersion and integration of each device is not limited to that shown in the figure. In other words, all or part of it can be functionally or physically dispersed and integrated in arbitrary units according to various loads and usage situations, etc.

[0152] Furthermore, all or any part of each processing function performed by each device can be realized by a CPU (Central Processing Unit) and a program analyzed and executed by the CPU, or can be realized as hardware by wired logic.

[0153] (Computer) FIG. 10 is a hardware configuration diagram of a computer. Next, a hardware configuration example of a computer 90 using the information processing apparatus 1 will be described. This computer 10 corresponds to an example of an "information processing system".

[0154] As shown in FIG. 10, the computer 90 includes an information processing apparatus 1, an HDD (Hard Disk Drive) 91, and a communication apparatus 92. The information processing apparatus 1 is connected to the HDD 91 and the communication apparatus 92 via a bus.

[0155] The communication apparatus 92 is a network interface card or the like and is used for communication with other information processing apparatuses.

[0156] The HDD 91 is an auxiliary storage device. The HDD 91 stores various programs including an OS (Operating System).

[0157] The information processing apparatus 1 reads and executes various programs stored in the HDD 91. For example, when using the information processing apparatus 1 illustrated in FIG. 4, the processor 101 reads various programs stored in the HDD 91, expands them in the memory 103, and executes them.

[0158] Some examples of combinations of the disclosed technical features are described below.

[0159] (1) A first device and a second device that issue an access request, A third device that receives the access request from the first device and the second device, A bus having a shared connection path to the third device shared by the first device and the second device, a first path connecting the first device to the shared connection path, and a second path connecting the second device to the shared connection path, a first control IC that blocks the first path during access to the third device by the second device An information processing apparatus characterized by comprising the same. (2) When the second device is accessing the third device, the second device activates a first signal output to the first control IC, and when the second device is not accessing the third device, the second device deactivates the first signal when the first device makes the access request. When the first signal is activated, the first control IC blocks the first path, and when the first signal is deactivated, the first control IC connects the first path. The information processing apparatus according to (1), characterized by the above. (3) When the first device makes the access request, the first control IC activates a second signal output to the second device. When the second signal is activated, the second device deactivates the first signal. The information processing apparatus according to (2), characterized by the above. (4) The second device determines whether or not the first device is accessing the third device based on the usage status of a control line for the first device to access the third device, and when the first device is not accessing the third device, the second device activates a first signal output to the first control IC. The information processing apparatus according to (2), characterized by the above. (5) The second device also outputs a first signal output to the first control IC to the first device, and when the first signal is activated, the first device transitions to an access waiting state. The information processing apparatus according to any one of (2) to (4), characterized in that... (6) The information processing apparatus according to any one of (1) to (5), characterized in that when the first bus is accessing the third device, the second device does not issue the access request. (7) When the first device issues the access request, the first control IC activates a second signal to be output to the second device. When the second signal is activated, the second device determines that the first bus is accessing the third device and does not issue the access request. The information processing apparatus according to (6), characterized in that... (8) A fourth device that is connected to the shared connection path in the bus using a third path and issues the access request, and A second control IC that blocks the third path during access of the first device or the second device to the third device. The first control IC blocks the first path during access of the second device or the fourth device to the third device. The information processing apparatus according to any one of (1) to (7), characterized in that... (9) The information processing apparatus according to any one of (1) to (8), characterized in that the first device and the second device do not have a function of arbitrating the use of the bus. (10) An information processing system having an information processing apparatus and an auxiliary storage device, wherein the information processing apparatus includes a first device and a second device that issue access requests, and a third device that receives the access requests from the first device and the second device. A bus having a shared connection path to a third device shared by the first device and the second device, a first path connecting the first device to the shared connection path, and a second path connecting the second device to the shared connection path, and a first control IC that blocks the first path during access to the third device by the second device. An information processing system characterized by the above. (11) A control method for an information processing apparatus having a first device and a second device that issue access requests, a third device that receives the access requests from the first device and the second device, a shared connection path to the third device shared by the first device and the second device, a bus having a first path connecting the first device to the shared connection path and a second path connecting the second device to the shared connection path, causing the first control IC to block the first path during access to the third device by the second device. A control method for an information processing apparatus characterized by the above.

Explanation of Signs

[0160] 1 Information processing apparatus 101 Processor 102 FPGA 103 Memory 104 Control IC 111 Address line 112 Data line 113 Control line 115 Access request line 116 Response waiting line 201, 202 Devices 203, 204 Control ICs 211, 213 Access request lines 212, 214 Response waiting lines

Claims

1. A first device and a second device that make access requests, A third device that receives the access request from the first device and the second device, A shared connection path to the third device shared by the first device and the second device, a bus having a first path connecting the first device to the shared connection path and a second path connecting the second device to the shared connection path, A first control IC that blocks the first path during access to the third device by the second device An information processing apparatus comprising the same.

2. When the second device is accessing the third device, the second device activates a first signal output to the first control IC, and when the second device is not accessing the third device, the second device deactivates the first signal when the first device makes the access request, When the first signal is activated, the first control IC blocks the first path, and when the first signal is deactivated, the first control IC connects the first path The information processing apparatus according to claim 1, characterized in that.

3. When the first device makes the access request, the first control IC activates a second signal output to the second device, When the second signal is activated, the second device deactivates the first signal The information processing apparatus according to claim 2, characterized in that.

4. The second device, Based on the usage status of the control line for the first device to access the third device, determines whether the first device is accessing the third device, When the first device is not accessing the third device, activates a first signal output to the first control IC The information processing apparatus according to claim 2, characterized in that

5. The second device also outputs a first signal output to the first control IC to the first device, When the first signal is activated, the first device transitions to an access waiting state The information processing apparatus according to claim 2, characterized in that

6. The information processing apparatus according to claim 1, characterized in that when the first device is accessing the third device, the second device does not issue the access request.

7. When the first device issues the access request, the first control IC activates a second signal output to the second device, When the second signal is activated, the second device determines that the first device is accessing the third device and does not issue the access request The information processing apparatus according to claim 6, characterized in that

8. A fourth device connected to the shared connection path in the bus using a third path and issuing the access request, and A second control IC that blocks the third path during the access of the first device or the second device to the third device, and The first control IC blocks the first path during the access of the second device or the fourth device to the third device The information processing apparatus according to claim 1, characterized in that

9. The information processing apparatus according to claim 1, characterized in that the first device and the second device do not have a function of arbitrating the use of the bus.

10. An information processing system having an information processing apparatus and an auxiliary storage device, wherein The information processing apparatus is A first device and a second device that make an access request, a third device that receives the access request from the first device and the second device, a bus having a shared connection path to the third device shared by the first device and the second device, a first path connecting the first device to the shared connection path, and a second path connecting the second device to the shared connection path, and a first control IC that blocks the first path during access to the third device by the second device. An information processing system characterized by the above.

11. A control method for an information processing apparatus having a first device and a second device that make an access request, a third device that receives the access request from the first device and the second device, a shared connection path to the third device shared by the first device and the second device, a bus having a first path connecting the first device to the shared connection path and a second path connecting the second device to the shared connection path, causing the first control IC to block the first path during access to the third device by the second device. A control method for an information processing apparatus characterized by the above.

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