Electronic device

Abstract

To provide an electronic device capable of suppressing peeling of a solder.SOLUTION: A substrate 30 includes a plurality of lands 34. An electron component 40 includes a plurality of terminals 41 that is provided so as to be corresponded to each land 34. A solder 50 is interposed to between each land 34 and each terminal 41. The substrate 30 contains each land 34 as a conductor 32, and includes a wiring 33 to be arranged to a multilayer to an insulation base material 31, and a via hole 35. Each land 34 contains: a land 341 to which the via hole 35 is electrically connected; and a land 342 that is arranged to an adjacent to the land 341, and in which the via hole 35 is not arranged just under in a plan view from a thickness direction of the substrate 30. At least one of the via hole 35 electrically connected to the land 341 is provided so as to be deviated to a portion that is not overlapped with the land 341 in the plan view.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The disclosure in this specification relates to an electronic device.

Background Art

[0002] Patent Document 1 discloses an electronic device. The description of the prior art document is incorporated by reference as an explanation of the technical elements in this specification.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, a ball-shaped solder (solder bump) is interposed between the land (pad) of a substrate (printed wiring board) and the terminal of an electronic component to join the land and the terminal. In such a configuration, due to the difference in the coefficient of thermal expansion (linear expansion coefficient) of the portions directly below adjacent lands on the substrate, solder peeling may occur during the second and subsequent reflows. This solder peeling may be referred to as ball drop or the like. From the above viewpoints, or from other viewpoints not mentioned, further improvement of the electronic device is required.

[0005] One object of the present disclosure is to provide an electronic device capable of suppressing solder peeling.

Means for Solving the Problems

[0006] One aspect of the disclosure is a substrate (30, 30S) having a plurality of lands (34) provided on one surface, an electronic component (40) disposed on one surface and having a plurality of terminals (41) provided on the surface opposite to the one surface corresponding to the lands, Solder (50) that is interposed between the land and the terminal and joins the land and the terminal, is provided, The substrate includes a land as a conductor (32) disposed on an insulating base material (31), wirings (33) disposed in multiple layers on the insulating base material, and an interlayer connection portion (35) that electrically connects the wirings of different layers. The land includes a first land (341) to which the interlayer connection portion is electrically connected, and a second land (342) that is disposed adjacent to the first land and in which the interlayer connection portion is not disposed directly below in a plan view from the thickness direction of the substrate. At least one of the interlayer connection portions electrically connected to the first land is provided offset at a position that does not overlap the first land in a plan view.

[0007] According to the disclosed electronic device, at least one of the interlayer connection portions electrically connected to the first land is intentionally offset to a position that does not overlap the first land. Thereby, the difference in the coefficient of thermal expansion between the portion directly below the first land and the portion directly below the second land on the substrate can be reduced. Therefore, at the time of the multiple reflows, it is possible to suppress the solder disposed on the first land from being pulled downward (substrate side) and solder peeling from occurring at the interface with the electronic component (terminal).

[0008] In order to achieve their respective objects, the multiple aspects disclosed in this specification employ different technical means. The claims and the reference numerals in parentheses described in this column exemplarily show the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The objects, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Embodiments for Carrying Out the Invention

[0010] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, the same reference numerals may be given to corresponding components, and redundant descriptions may be omitted. When only a part of the configuration is described in each embodiment, the configuration of the other embodiments described previously can be applied to the other parts of the said configuration. Also, not only the combinations of configurations explicitly shown in the description of each embodiment, but also the configurations of a plurality of embodiments can be partially combined with each other without any problem in the combination, even if not explicitly shown.

[0011] (First Embodiment) First, based on FIGS. 1 and 2, the schematic configuration of the electronic device will be described.

[0012] <Electronic Device> FIG. 1 is a plan view showing an example of an electronic device. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. For convenience, in FIG. 2, conductors on the substrate and terminals of some electronic components are omitted.

[0013] Hereinafter, the thickness direction of the sub-substrate is indicated as the Z direction. Also, one direction orthogonal to the Z direction is indicated as the X direction, and a direction orthogonal to both the Z direction and the X direction is indicated as the Y direction. Unless otherwise specified, the shape viewed in plan from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction, is defined as the planar shape. The plan view from the Z direction may be simply indicated as a plan view.

[0014] The electronic device 10 illustrated in FIGS. 1 and 2 includes a main substrate 20, a sub-substrate 30, electronic components 40, and solder 50. The electronic device 10 may further include a housing (not shown). The housing houses the main substrate 20, the sub-substrate 30, the electronic components 40, etc. The electronic device 10 has, for example, a predetermined control function. Such an electronic device 10 may be referred to as an electronic control unit (ECU). ECU is an abbreviation for Electronic Control Unit.

[0015] The main substrate 20 and the sub-substrate 30 may be referred to as a substrate, a printed circuit board, a wiring board, etc. The sub-substrate 30 is mounted on the main substrate 20. For this reason, the main substrate 20 may be referred to as a mother substrate. The thickness direction of the main substrate 20 is substantially parallel to the Z direction. The main substrate 20 has a front surface 20a and a back surface 20b. The front surface 20a is a surface on one end side in the Z direction, and the back surface 20b is a surface on the other end side in the Z direction. That is, the back surface 20b is a surface opposite to the front surface 20a in the Z direction. The sub-substrate 30 is disposed on the front surface 20a. The planar shape of the main substrate 20 is not particularly limited. As an example, the main substrate 20 of the present embodiment has a substantially rectangular planar shape with the X direction as the longitudinal direction. In plan view, the main substrate 20 encloses the sub-substrate 30.

[0016] The thickness direction of the sub-substrate 30 is the Z direction. The sub-substrate 30 has a front surface 30a and a back surface 30b. The front surface 30a is the surface on one end side in the Z direction, and the back surface 30b is the surface on the other end side in the Z direction. That is, the back surface 30b is the surface opposite to the front surface 30a in the Z direction. The back surface 30b is the surface facing the front surface 20a of the main substrate 20 in the Z direction. The planar shape of the sub-substrate 30 is not particularly limited. As an example, the sub-substrate 30 of the present embodiment has a substantially rectangular shape in plan view with the X direction as the longitudinal direction. In plan view, the size of the sub-substrate 30 is smaller than that of the main substrate 20. The entire sub-substrate 30 is enclosed within the main substrate 20.

[0017] The sub-substrate 30 is laminated and arranged with respect to the main substrate 20. The lamination direction of the sub-substrate 30 and the main substrate 20 is substantially parallel to the Z direction. An electronic component 40 is arranged on the front surface 30a of the sub-substrate 30. The electronic component 40 is connected to the sub-substrate 30 via a solder 50. Although details will be described later, the electronic component 40 is an electronic component having a plurality of terminals on the surface facing the sub-substrate 30. The solder 50 joins the terminals and the lands of the sub-substrate 30.

[0018] The electronic device 10 includes at least one electronic component 40 as an electronic component mounted on the sub-substrate 30. As an example, the electronic device 10 of the present embodiment includes a plurality of electronic components 40. The electronic device 10 further includes an electronic component 60. The electronic component 60 is the remaining electronic component excluding the electronic component 40 among the electronic components mounted on the sub-substrate 30. The electronic component 60 is an electronic component having a different structure from the electronic component 40. The electronic component 60 is arranged on the front surface 30a of the sub-substrate 30 together with the electronic component 40.

[0019] The exemplary electronic device 10 further includes a solder 70, electronic components 80, and a connector 90. The solder 70 joins, for example, the sub-board 30 and the main board 20. The solder 70 joins a land provided on the back surface 30b of the sub-board 30 and a land provided on one surface 20a of the main board 20. The electronic components 80 and the connector 90 are mounted on the main board 20 together with the sub-board 30. The electronic components 80 and the connector 90 are joined to the lands of the main board 20 via, for example, the solder 70.

[0020] The connector 90 is mounted on the main board 20 to electrically connect the circuit configured in the electronic device 10 and the outside (external device) of the electronic device 10. As an example, the connector 90 of the present embodiment electrically connects the circuit configured by the main board 20, the sub-board 30, and the electronic components 40, 60, 80 and an external device.

[0021] In the exemplary electronic device 10, at least one of the electronic components 40 includes an arithmetic processing circuit including a processor, a memory, a storage, etc. The processor executes various processes for realizing each function by accessing the memory. The memory is, for example, a RAM. RAM is an abbreviation for Random Access Memory. The storage includes a non-volatile storage medium such as a flash memory. A control program executed by the processor is stored in the storage. The circuit configured by the sub-board 30 and the electronic components 40, 60 provides a predetermined control function. The circuit configured by the main board 20 and the electronic component 80 provides, for example, a power supply circuit for supplying an operating power to the circuit configured by the sub-board 30 and the electronic components 40, 60, a communication interface, etc.

[0022] <Sub-board, Electronic Component, and Mounting Structure> FIG. 3 is an enlarged view of the III region indicated by the dashed-dotted line in FIG. 1. FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. FIGS. 3 and 4 show the arrangement region of the electronic component 40 and its peripheral region.

[0023] The sub-substrate 30 includes an insulating base material 31 and a conductor 32. The insulating base material 31 is formed using an electrical insulating material such as resin. The conductor 32 is disposed on the insulating base material 31. The conductor 32 is formed using a metal material with good conductivity such as Cu. The conductor 32 has a wiring 33 including a land 34 and a via hole 35. The conductor 32 includes at least a conductor that provides a wiring function (circuit function). The conductor 32 may include a conductor that does not provide a wiring function, such as a conductor for heat dissipation. The sub-substrate 30 further has a solder resist 36. The solder resist 36 is disposed on both surfaces of the insulating base material 31 in the Z direction.

[0024] The wiring 33 is disposed in multiple layers with respect to the insulating base material 31. That is, the sub-substrate 30 is a multilayer substrate. The wiring 33 includes an inner layer wiring 331 disposed inside the insulating base material 31 and a surface layer wiring disposed on the surface of the insulating base material 31. The wiring 33 is formed, for example, by patterning a metal foil. The wiring 33 may be referred to as a wiring pattern, a conductor pattern, etc.

[0025] The land 34 is a part of the wiring 33 (surface layer wiring) and is disposed on the surface of the insulating base material 31. In FIG. 4, only the land 34 of the surface layer wiring is shown. The land 34 is a portion of the surface layer wiring that is exposed from the solder resist 36. The other portions of the surface layer wiring are covered by the solder resist 36. The positional relationship between the land 34 and the solder resist 36 may be a normal resist or an over resist.

[0026] The via hole 35 is connected to the wiring 33 including the land 34. The via hole 35 corresponds to an interlayer connection portion. The via holes 35 constituting the circuit electrically connect the wirings 33 arranged in different layers. The via hole 35 is formed, for example, by arranging a conductor such as metal plating in a hole formed in the insulating base material 31. The via hole 35 may be referred to as a via conductor. The via hole 35 may be a through hole (through-hole via) penetrating the insulating base material 31 in the Z direction or a non-through hole. The via hole 35 may penetrate one (single layer) of the insulating layers constituting the insulating base material 31 or may penetrate a plurality of insulating layers (multiple layers). In the via hole 35, the conductor may be provided only on the wall surface of the hole or may be provided so as to fill the hole. It is also possible to adopt a configuration in which the gap of the via hole 35 is filled with resin in a state where the conductor is provided on the wall surface. For the sake of convenience, in the cross-sectional views after FIG. 4, the via hole 35 with the gap omitted is illustrated.

[0027] The electronic component 40 is an IC package. The electronic component 40 includes, for example, an IC chip (not shown), a wiring member, and a sealing body. The electronic component 40 is a surface-mount type component. The electronic component 40 is provided with a plurality of terminals 41 on the opposing surface 40a to the sub-board 30. The terminals 41 are arranged in a matrix (matrix) on the opposing surface 40a. The plurality of terminals 41 are arranged side by side in the X direction and the Y direction. The electronic component 40 is, for example, BGA, LGA, etc. BGA is an abbreviation for Ball Grid Array. LGA is an abbreviation for Land Grid Array. In the case of BGA, the electronic component 40 includes ball-shaped solder 50. The solder 50 is provided individually for the plurality of terminals 41.

[0028] The lands 34 connected to the terminal 41 via the solder 50 are arranged in a matrix corresponding to the terminal 41. The plurality of lands 34 are arranged side by side in the X direction and the Y direction. The lands 34 connected to the terminal 41 include the lands 341 and 342 arranged on one surface 30a. The land 341 is a land to which the via hole 35 is electrically connected. The plurality of lands 34 connected to a single electronic component 40 include at least one land 341. It may include only one land 341 or may include a plurality of lands 341.

[0029] The land 342 is arranged next to the land 341 and is a land where no via hole 35 is arranged directly below the land 342 in plan view. No via hole 35 is arranged in the region overlapping the land 342 in plan view. The plurality of lands 34 connected to a single electronic component 40 include at least one land 342. It may include only one land 342 or may include a plurality of lands 342. The land 341 corresponds to the first land, and the land 342 corresponds to the second land.

[0030] As an example in the present embodiment, as shown in FIGS. 3 and 4, the lands 342 are arranged on both sides of one land 341 in the Y direction. Note that the lands 342 may be arranged on both sides of the land 341 in the X direction, or the lands 342 may be arranged on both sides of the land 341 in both the X direction and the Y direction. The lands 34 connected to the terminal 41 may include lands where no via hole 35 is electrically connected and which are not located next to the land 341 in the X direction and the Y direction. For example, lands to which no via hole 35 is connected may be adjacent to each other. The lands 34 connected to the terminal 41 may include non-connected lands that do not provide a wiring function.

[0031] The sub-substrate 30 is a build-up substrate having a core layer 301 and a build-up layer 302 laminated on the core layer 301. The number of layers of the build-up substrate is not particularly limited. Also, the number of layers of the build-up layer 302 is not particularly limited. In FIG. 4, for the sake of convenience, the build-up layer 302 disposed on both sides of the core layer 301 is taken as one layer.

[0032] The build-up layer 302 is provided with an LVH351 which is a via hole 35. LVH is an abbreviation for Laser Via Hole. The LVH351 provided in the build-up layer 302 forming the surface layer on the 30a side is connected to the land 341. The LVH351 is continuous with the land 341. The LVH351 is provided at a position overlapping at least a part of the land 341 in plan view. The LVH351 is disposed directly below the land 341. As an example, the LVH351 of the present embodiment is included in the land 341 in plan view.

[0033] The core layer 301 is provided with an IVH352 which is a via hole 35. IVH is an abbreviation for Inner Via Hole. The IVH352 is formed to penetrate the core layer 301. The IVH352 is provided at a position not overlapping the land 341 in plan view. The IVH352 is provided offset from the land 341 in plan view. The IVH352 is provided offset from the LVH351 in plan view. Inner layer wirings 331 are connected to both ends of the IVH352 in the Z direction. The IVH352 is connected to the land 341 via the inner layer wiring 331 and the LVH351. As an example, the IVH352 of the present embodiment is provided offset from the land 341 and the LVH351 in the Y direction. The inner layer wiring 331 intervening between the IVH352 and the LVH351 extends in the Y direction. The IVH352 is connected to the vicinity of one end of the inner layer wiring 331, and the LVH351 is connected to the vicinity of the other end of the end.

[0034] At least one of the lands 342 may be connected to a surface wiring (not shown). At least one of the lands 342 may be a land to which the via hole 35 is not electrically connected. At least one of the lands 342 may be electrically connected to the via hole 35 via the surface wiring. In this case, the via hole 35 electrically connected to the land 342 is provided at a position that does not overlap the land 342 in plan view. At least one of the lands 342 may be a non-connected land.

[0035] The land 34 includes a land 343 disposed on the back surface 30b. The land 343 is connected to the land 21 of the main substrate 20 via the solder 70. Note that the main substrate 20 has the same configuration as the sub-substrate 30. The land 21 is disposed on one surface 20a of the main substrate 20. The land 21 is exposed from a solder resist (not shown). For convenience, in the cross-sectional views after FIG. 4, only the land 21 is shown as the conductor of the main substrate 20. Also, the solder resist of the main substrate 20 is omitted. The arrangement of the lands 21 and 343 shown in FIG. 4 is merely an example. The positions of the lands 21 and 343 are not particularly limited by the positions of the lands 341 and 342.

[0036] <Summary of the First Embodiment> FIG. 5 shows a reference example. FIG. 5 corresponds to FIG. 4. FIG. 5 shows the reflow process for the multiple times in a manufacturing process of the electronic device shown in the reference example. FIG. 5 shows the state during the multiple reflows. In the reference example, an R is added to the end of the reference numeral of the related element shown in this embodiment. In FIG. 5, for convenience, the build-up substrate is shown in a simplified manner.

[0037] As shown in FIG. 5, the sub-substrate 30R of the reference example has lands 341R and 342R, similar to the configuration shown in the present embodiment (see FIGS. 3 and 4). In the Y direction, lands 342R are arranged on both sides of the land 341R. A via hole 35R is electrically connected to the land 341R. The via hole 35R includes an LVH351R continuous with the land 341 and an IVH352R connected to the land 341R via the LVH351R. The LVH351R and the IVH352R are located directly below the corresponding land 341R. The LVH351R and the IVH352R are arranged at positions overlapping the land 341R in plan view. No via hole 35R is arranged directly below the land 342R.

[0038] The electronic component 40R is mounted on the sub-substrate 30R by the first reflow. The sub-substrate 30R on which the electronic component 40R is mounted is mounted on the main substrate 20R by the multiple (for example, the second) reflow. The solid arrows shown in FIG. 5 indicate the heat (hot air and radiant heat) during the multiple reflows. During reflow, heat, hot air, and radiant heat are received from both sides in the Z direction.

[0039] In the sub-substrate 30R, the coefficient of thermal expansion in the Z direction is different between the portion directly below the land 341R where the via hole 35R is arranged and the portion directly below the land 342R where the via hole 35R is not arranged. The coefficient of linear expansion of the resin constituting the insulating base material 31R is larger than that of the conductor (for example, copper) constituting the via hole 35R. For this reason, as indicated by the white arrows in FIG. 5, the expansion of the sub-substrate 30R during reflow is larger in the portion directly below the land 342R than in the portion directly below the land 341R. That is, since the expansion is small in the portion directly below the land 341R, a pulling force acts on the solder 50R on the land 341R toward the lower side (main substrate 20R side). In other words, the facing interval between the sub-substrate 30R and the electronic component 40R expands more at the land 341R than at the land 342R.

[0040] Also, in the multiple reflows, the solder 50R solidified by the previous reflow is heated and melted. The heat from above is transmitted to the sub-board 30R through the electronic component 40R. However, in the case of the land 341R, as shown by the dashed arrow, the heat escapes to the via hole 35R side through the land 341R. Since there is no via hole 35R directly below the land 342R, it is difficult for the heat to escape from the land 342R into the interior of the sub-board 30R. Therefore, the melting of the solder on the land 341R is delayed compared to the melting of the solder on the land 342R.

[0041] When there is a certain amount of unmelted solder 50R on the land 341R and a downward pulling force acts on the solder 50R on the land 341R, there is a risk of the solder 50R peeling off from the terminal 41R. That is, the unmelted solder 50R may not be able to follow the expansion of the opposing interval, and there is a risk of peeling off from the terminal 41R. In the case of BGA, solder peeling may be referred to as ball drop.

[0042] Figure 6 shows the state during the multiple reflows in the electronic device according to this embodiment. Figure 6 corresponds to Figure 4. Figure 6 shows the multiple reflow process. The solid arrows shown in Figure 6 indicate the heat (hot air and radiant heat) during the multiple reflows, similar to Figure 5. In Figure 6, for the sake of convenience, the build-up substrate is shown in a simplified manner as in Figure 5.

[0043] The via hole 35 has a great influence on the thermal expansion rate of the sub-substrate 30. In the present embodiment, at least one of the via holes 35 (interlayer connection portions) electrically connected to the land 341 (first land) is intentionally shifted to a position that does not overlap with the land 341. Therefore, the difference in the thermal expansion rate, that is, the difference in the magnitude of thermal expansion, between the portion directly under the land 341 and the portion directly under the land 342 (second land) in the sub-substrate 30 can be reduced as indicated by the white arrow in FIG. 6. According to the configuration shown in FIG. 6, the amount of expansion of the portion directly under the land 341 approaches the amount of expansion of the portion directly under the land 342 as compared with the configuration shown in FIG. 5. As a result, the force that pulls the solder 50 on the land 341 downward becomes weaker during the multiple reflow processes. Therefore, it is possible to suppress the occurrence of solder peeling at the interface with the terminal 41 of the electronic component 40.

[0044] As illustrated, the lands 342 (second lands) may be arranged on both sides of the land 341 (first land) in one direction orthogonal to the Z direction (plate thickness direction). In this configuration, since the thermal expansion is large directly under the adjacent lands 342, the solder 50 on the land 341 sandwiched between the lands 342 is likely to peel. However, by shifting the position of at least one of the via holes 35 away from the land 341, the difference in the thermal expansion rate directly under the lands 341 and 342 can be reduced. Therefore, it is possible to suppress the peeling of the solder 50 on the land 341 sandwiched between the lands 342.

[0045] As illustrated, a build-up substrate may be used as the sub-substrate 30. Then, the position of the IVH 352 formed in the core layer 301 and electrically connected to the land 341 (first land) may be shifted with respect to the land 341. In the build-up substrate, the IVH 352 has a great influence on the thermal expansion rate. Therefore, by intentionally shifting the position of the IVH 352 so as not to overlap with the land 341, the thermal expansion rate of the portion directly under the land 341 can be made closer to the thermal expansion rate of the portion directly under the land 342. That is, it is possible to effectively suppress the occurrence of solder peeling.

[0046] As illustrated, in the sub-substrate 30 which is a build-up substrate, the positions of the IVH352 (first via hole) and the LVH351 (second via hole) connected to the land 341 may be shifted with respect to the land 341. In this way, by intentionally shifting the positions of both the LVH351 and the IVH352 so as not to overlap with the land 341, the coefficient of thermal expansion of the portion directly below the land 341 can be made closer to the coefficient of thermal expansion of the portion directly below the land 342.

[0047] As illustrated, the sub-substrate 30 may be laminated on the main substrate 20, and the electronic component 40 may be disposed on one surface 30a which is the surface opposite to the surface facing the main substrate 20 in the sub-substrate 30. In this configuration, after mounting the electronic component 40 on the sub-substrate 30, the sub-substrate 30 is mounted on the main substrate 20 by performing reflow a plurality of times. However, at least one of the via holes 35 electrically connected to the land 341 is intentionally shifted to a position that does not overlap with the land 341. Therefore, during the reflow for the plurality of times, the solder 50 on the land 341 is pulled downward, thereby suppressing the occurrence of solder peeling at the interface with the terminal 41 of the electronic component 40.

[0048] <Modification Example> Among the via holes 35 electrically connected to the land 341, the via holes 35 arranged to be shifted so as not to overlap with the land 341 are not limited to the above-described IVH352. For example, as shown in FIG. 7, the positions of the LVH351 and the IVH352 connected to the land 341 may be shifted with respect to the land 341. According to this, compared with the configuration shown in FIG. 6, the arrangement of the via holes 35 in the portion directly below the land 341 is reduced. Therefore, the coefficient of thermal expansion of the portion directly below the land 341 can be made closer to the coefficient of thermal expansion of the portion directly below the land 342. Therefore, the occurrence of peeling of the solder 50 on the land 341 can be more effectively suppressed.

[0049] As shown in FIG. 8, the position of the LVH 351 adjacent to the land 341 may be shifted so as not to overlap the land 341, and the position of the IVH 352 may be directly below the land 341. The surface wiring 332 is connected to the land 341, and the LVH 351 is electrically connected to the land 341 via the surface wiring 332. In the extending direction of the surface wiring 332, one of the ends is provided with the land 341, and the LVH 351 is connected to the other end. Also by this, as compared with the reference example shown in FIG. 5, the coefficient of thermal expansion in the portion directly below the land 341 can be made closer to the coefficient of thermal expansion in the portion directly below the land 342. Therefore, it is possible to suppress the occurrence of peeling of the solder 50 on the land 341.

[0050] Note that FIGS. 7 and 8 correspond to FIG. 4. In FIGS. 7 and 8, for the sake of convenience, the build-up substrate is shown in a simplified manner as in FIGS. 5 and 6. The sub-substrate 30 is not limited to the build-up substrate. The sub-substrate 30 may be, for example, a multilayer substrate formed by laminating insulating sheets each provided with a copper foil. In such a multilayer substrate, for example, the position of the via hole 35 adjacent to the land 341 may be shifted with respect to the land 341 so as not to overlap the land 341 in plan view. Also, the via hole 35 that is electrically connected to the land 341 and is located away from the land 341 in the Z direction may be shifted so as not to overlap the land 341.

[0051] (Second Embodiment) This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be incorporated by reference. In the preceding embodiment, the position of the via hole was shifted in the sub-substrate on the main substrate. Instead of this, the position of the via hole may be shifted in a single substrate.

[0052] FIG. 9 shows the electronic device according to this embodiment. In FIG. 9, for the sake of convenience, the conductors are shown omitted. FIG. 10 is a cross-sectional view taken along the line X-X of FIG. 9.

[0053] As shown in FIGS. 9 and 10, the electronic device 10 includes a substrate 30S, electronic components 40, and solder 50. The electronic device 10 further includes an electronic component 60 and a connector 90. The electronic device 10 may include a housing (not shown). The electronic device 10 has a configuration in which the main substrate 20, solder 70, and electronic components 80 are excluded from the configuration shown in the previous embodiment (see FIGS. 3 and 4). The connector 90 is mounted on the substrate 30S.

[0054] The electronic component 40 includes a plurality of terminals 41 on the opposing surface 40a to the substrate 30S. The terminals 41 are arranged in a matrix (matrix shape) on the opposing surface 40a. The plurality of terminals 41 are arranged side by side in the X direction and the Y direction.

[0055] The substrate 30S is not mounted on another substrate. The substrate 30S has the same configuration as the sub-substrate 30. The thickness direction of the substrate 30S is the Z direction. The substrate 30S has a front surface 30a and a back surface 30b. As an example, the substrate 30S of the present embodiment has a substantially rectangular planar shape with the X direction as the longitudinal direction.

[0056] The substrate 30S includes an insulating base material 31 and a conductor 32. The conductor 32 has a wiring 33 including a land 34 and a via hole 35. The wiring 33 is arranged in multiple layers with respect to the insulating base material 31. The wiring 33 includes a surface wiring (not shown) arranged on the surface of the insulating base material 31 and an inner layer wiring 331 arranged inside the insulating base material 31.

[0057] The lands 34 connected to the terminals 41 via the solder 50 are arranged in a matrix corresponding to the terminals 41. The plurality of lands 34 are arranged side by side in the X direction and the Y direction. The lands 34 connected to the terminals 41 include lands 341 and 342 arranged on the front surface 30a. Similar to the previous embodiment, the land 341 is a land electrically connected to the via hole 35 among the plurality of lands 34. The land 342 is arranged adjacent to the land 341 and has no via hole 35 directly below it in a plan view. The lands 34 include lands 343 arranged on the back surface 30b.

[0058] As an example, in the present embodiment, in the Y direction, lands 342 are arranged on both sides of one land 341. The substrate 30S is a build-up substrate. The via hole 35 includes an IVH 351 and an LVH 352. The LVH 351 formed in the build-up layer 302 and connected to the land 341 is provided directly below the land 341 in the same configuration as shown in the previous embodiment (see FIG. 4). The IVH 352 formed in the core layer 301 is provided at a position that does not overlap the land 341 in plan view. The IVH 352 is connected to the land 341 via the inner layer wiring 331 and the LVH 351. Other configurations are the same as those described in the previous embodiment.

[0059] <Summary of the Second Embodiment> In a configuration including a single substrate 30S, multiple reflows may be performed by surface-mounting electronic components on both sides. In the present embodiment, at least one of the via holes 35 (interlayer connection portions) electrically connected to the land 341 (first land) on the substrate 30S is intentionally shifted to a position that does not overlap the land 341. Thereby, the difference in the coefficient of thermal expansion, that is, the difference in the magnitude of thermal expansion, between the portion directly below the land 341 and the portion directly below the land 342 (second land) on the substrate 30S can be reduced. Therefore, the same effect as the configuration shown in the previous embodiment can be achieved. That is, during the second and subsequent reflows, the solder 50 on the land 341 is pulled downward, thereby suppressing the occurrence of solder peeling at the interface with the terminal 41 of the electronic component 40.

[0060] As illustrated, the lands 342 (second lands) may be arranged on both sides of the land 341 (first land) in one direction orthogonal to the Z direction (plate thickness direction). As illustrated, a build-up substrate may be used as the substrate 30S, and the position of the IVH 352 may be shifted with respect to the land 341. These configurations are the same as the configuration of the sub-substrate 30 shown in the previous embodiment. Therefore, the same effect as the effect described in the previous embodiment can be achieved.

[0061] The configuration of the substrate 30S is not limited to the example shown in FIG. 10. For example, as the via holes 35 of the substrate 30S, the arrangements shown in FIGS. 7 and 8 may be applied. For example, in the substrate 30S which is a build-up substrate, the positions of the IVH352 (first via hole) and the LVH351 (second via hole) connected to the land 341 may be shifted with respect to the land 341. The substrate 30S is not limited to a build-up substrate.

[0062] (Third Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, the position of the via hole was shifted in the row direction or the column direction. Instead of this, it may be shifted in the diagonal direction.

[0063] FIG. 11 shows a sub-substrate in the electronic device according to this embodiment. FIG. 11 shows a part of the portion where electronic components are arranged on the sub-substrate. In FIG. 11, the electronic components are shown omitted. The basic configuration of the electronic device 10 is the same as the configuration shown in the preceding embodiment (see FIGS. 3 and 4). The sub-substrate 30 is mounted on the main substrate 20. Electronic components 40 are arranged on one surface 30a of the sub-substrate 30.

[0064] Similar to the configuration shown in the preceding embodiment, the sub-substrate 30 has lands 34 arranged in a matrix (matrix shape) corresponding to the terminals 41 of the electronic components 40. The plurality of lands 34 are arranged in a matrix with a predetermined pitch. The lands 34 are arranged in the X direction at a predetermined pitch and in the Y direction at a predetermined pitch. One of the X direction and the Y direction is the row direction, and the other is the column direction. The lands 34 include the land 341 and the land 342.

[0065] At least one of the via holes 35 electrically connected to the land 341 is provided so as to be shifted in the diagonal direction (D1 direction) of the matrix arrangement with respect to the land 341. The diagonal direction with respect to the land 341 is the direction connecting the land 341 and the land 344 located diagonally to the land 341 in a virtual quadrilateral (square) formed by four lands 34 including the land 341. At least one of the via holes 351 is provided on a virtual line connecting the centers of the lands 341 and 344 in a plan view. At least one of the via holes 351 is provided so as to be shifted toward the land 344 side with respect to the land 341.

[0066] As an example in this embodiment, the IVH352 which is the via hole 35 is provided on a virtual line indicated by a dashed line. The IVH352 is provided at the center positions 34C of the lands 341 and 344 in the diagonal direction. The center positions 34C are the center positions of a virtual quadrilateral formed by four lands 34 including the lands 341 and 344. Also, in the X direction and the Y direction, the land 342 is arranged adjacent to the land 341. The land 344 is not particularly limited. In the example shown in FIG. 11, it is the land 342. The land 344 may be a land different from the land 342. As shown in the previous embodiment, the land 342 may be arranged adjacent to the land 341 in one direction. The land 344 may be, for example, the land 341 or a non-connected land. Other configurations are the same as those described in the previous embodiment.

[0067] <Summary of the Third Embodiment> As exemplified in this embodiment, a configuration may be adopted in which a plurality of lands 34 corresponding to the terminals 41 of the electronic component 40 are arranged in a matrix at a predetermined pitch. In this configuration, at least one of the via holes 35 (interlayer connection portions) electrically connected to the land 341 (first land) may be intentionally shifted in the diagonal direction of the matrix arrangement with respect to the land 341. Compared with a configuration in which the via hole 35 is shifted in the row direction or the column direction, the distance from the land 341 can be increased. That is, the via hole 35 can be moved away from the land 341. Therefore, the coefficient of thermal expansion of the portion directly below the land 341 can be made closer to the coefficient of thermal expansion of the portion directly below the land 342 (second land). Accordingly, at the time of the second and subsequent reflows, it is possible to effectively suppress the solder 50 on the land 341 from being pulled downward, thereby causing solder peeling at the interface with the terminal 41 of the electronic component 40.

[0068] As exemplified, at least one of the via holes 35 electrically connected to the land 341 may be provided at the center position 34C between the land 341 and the land 344 located adjacent to the land 341 in the diagonal direction. In a plan view, the center position of the via hole 35 may substantially coincide with the center position 34C.

[0069] Assuming that the pitch is L and the distance from the center of the land 341 to the center of the land 344 is R, the distance R is the length obtained by dividing the pitch L by the square root of 2. When provided at the center position in the row direction or the column direction, the distance R is half of the pitch L. By providing at the diagonal center position 34C, while making the via hole 35 equidistant from the lands 341 and 344, the distance from each of the lands 341 and 344 can be increased. Therefore, while suppressing the influence of the via hole 35 on the surrounding lands 344, it is possible to effectively suppress the peeling of the solder 50 on the land 341.

[0070] <Modification Example> The arrangement of via holes 35 is not limited to the arrangement illustrated in FIG. 11. For example, as shown in FIG. 12, at least one of the via holes 35 may be provided at a position shifted from the center position 34C on a virtual line connecting the centers of lands 341 and 344. FIG. 12 corresponds to FIG. 11. In FIG. 12, land 344 is land 342 where no via hole 35 is disposed directly below. Therefore, the via hole 35 (IVH352) is provided so as to be offset toward land 344 from the center position 34C. Although not shown, the via hole 35 may be provided so as to be offset toward land 341 from the center position 34C. In FIG. 12, LVH351 is provided directly below land 341.

[0071] The via hole 35 whose position is shifted with respect to land 341 is not limited to IVH352. As shown in the previous embodiment, LVH351 and IVH352 may be shifted, or only LVH351 may be shifted. The sub-substrate 30 is not limited to a build-up substrate. The above-described configuration may be applied to substrate 30S instead of sub-substrate 30.

[0072] (Fourth Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated by reference. In the preceding embodiment, the position of the via hole was shifted within the range overlapping the electronic component in a plan view. In addition to this, the via hole may be shifted to a position where it does not overlap the electronic component.

[0073] FIG. 13 shows a sub-substrate in the electronic device according to this embodiment. FIG. 13 shows the periphery of the portion of the sub-substrate where the electronic components are arranged. The basic configuration of the electronic device 10 is the same as the configuration shown in the preceding embodiment (see FIGS. 3 and 4). The sub-substrate 30 is mounted on the main substrate 20. A plurality of electronic components 40 are arranged on one surface 30a of the sub-substrate 30.

[0074] As shown in FIG. 13, at least one of the via holes 35 electrically connected to the land 341 is provided at a position that does not overlap with the electronic component 40 in a plan view. That is, at least one of the via holes 35 is arranged outside the electronic component 40. As an example, the sub-substrate 30 in the present embodiment is a build-up substrate. Among the via holes 35 electrically connected to the land 341, the IVH 352 is arranged outside the electronic component 40.

[0075] Similar to the configuration shown in the previous embodiment, the sub-substrate 30 has lands 34 arranged in a matrix (matrix shape) corresponding to the terminals 41 of the electronic component 40. The lands 34 are arranged side by side in the X direction and the Y direction. The lands 34 include the lands 34OM arranged on the outermost periphery and the lands 34I arranged one inside from the outermost peripheral lands 34OM. The lands 34I are lands arranged in the vicinity of the lands 34OM. Hereinafter, the lands 34OM may be referred to as outermost peripheral lands, and the lands 34I may be referred to as adjacent lands.

[0076] At least one of the outermost peripheral lands 34OM and the adjacent lands 34I includes the land 341. That is, the outermost peripheral land 34OM may include the land 341, or the adjacent land 34I may include the land 341. Both the outermost peripheral land 34OM and the adjacent land 34I may include the land 341. As an example, in the present embodiment, the outermost peripheral land 34OM includes the land 341. The position of the IVH 352 is provided so as to be shifted with respect to the land 341 arranged on the outermost periphery. The outermost peripheral land 34OM also includes the land 342. The land 342 is arranged adjacent to the land 341 on the outermost periphery. Other configurations are the same as those described in the previous embodiment.

[0077] <Summary of the Fourth Embodiment> As exemplified in this embodiment, at least one of the via holes 35 (interlayer connection portions) electrically connected to the land 341 (first land) may be shifted to a position that does not overlap with the electronic component 40 in a plan view. By providing it outside the electronic component 40, the distance from the land 341 can be increased. For example, it is also possible to move the via hole 35 away from the land 341 as compared with a configuration in which the position is shifted within the range overlapping the electronic component 40. Therefore, it is possible to effectively suppress the occurrence of solder peeling at the interface with the terminal 41 of the electronic component 40.

[0078] As exemplified, a configuration may be adopted in which a plurality of lands 34 corresponding to the terminals 41 of the electronic component 40 are arranged in a matrix. In this configuration, at least one of the outermost peripheral land 34OM and the adjacent land 34I may include the land 341. The outermost peripheral land 34OM and the adjacent land 34I are close to the outer peripheral end portion of the electronic component 40 in a plan view. Therefore, it is easy to draw a wiring from the land 341 arranged on the outermost periphery or one inside thereof to the outside of the electronic component 40. That is, it is easy to shift the position of the via hole 35 outside the electronic component 40.

[0079] The via hole 35 whose position is shifted with respect to the land 341 is not limited to the IVH352. As shown in the previous embodiment, the LVH351 and the IVH352 may be shifted, or only the LVH351 may be shifted. The sub-substrate 30 is not limited to a build-up substrate. The above-described configuration may be applied to the substrate 30S instead of the sub-substrate 30.

[0080] (Other embodiments) The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes those in which parts and / or elements of the embodiments are omitted. The disclosure includes the replacement or combination of parts and / or elements between one embodiment and another. The technical scope disclosed is not limited to the description of the embodiments. Some of the technical scopes disclosed are indicated by the description of the claims and should be construed to include all changes within the meaning and scope equivalent to the description of the claims.

[0081] The disclosure in the specification, drawings, etc. is not limited by the description of the claims. The disclosure in the specification, drawings, etc. includes the technical idea described in the claims and extends to more diverse and extensive technical ideas than the technical idea described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being restricted by the description of the claims.

[0082] When an element or layer is referred to as being "on", "connected to", "attached to", or "coupled to" another element or layer, it may be directly on, connected to, attached to, or coupled to the other element or layer, and there may also be intervening elements or intervening layers. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly attached to", or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). As used in this specification, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. That is, the description of A and / or B means at least one of A and B.

[0083] Spatially relative terms such as "inside", "outside", "beneath", "below", "lower", "above", "upper", etc. are used herein to facilitate the description of the relationship of one element or feature to another element or feature as illustrated. Spatially relative terms can be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. For example, if the device in the figures is turned over, an element described as "beneath" or "directly beneath" another element or feature will be oriented "above" the other element or feature. Thus, the term "beneath" can encompass both an orientation of above and below. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0084] For example, some or all of the functions provided by the processor may be implemented as hardware. Modes of implementing a certain function as hardware include modes of implementing using one or more ICs or the like. As the processor, a CPU, MPU, GPU, DFP, etc. can be adopted. CPU is an abbreviation for Central Processing Unit. MPU is an abbreviation for Micro-Processing Unit. GPU is an abbreviation for Graphics Processing Unit. DFP is an abbreviation for Data Flow Processor.

[0085] Some or all of the functions provided by the processor may be implemented by combining multiple types of arithmetic processing units. Some or all of the functions provided by the processor may be implemented using an SoC, ASIC, FPGA, etc. SoC is an abbreviation for System on Chip. ASIC is an abbreviation for Application Specific Integrated Circuit. FPGA is an abbreviation for Field-Programmable Gate Array.

[0086] The control program may be stored in a computer-readable non-transitory tangible storage medium as instructions to be executed by a computer. As the storage medium for the control program, the above-mentioned flash memory may be used, or ROM, HDD, SSD, etc. may be used. ROM is an abbreviation for Read Only Memory. HDD is an abbreviation for Hard-disk Drive. SSD is an abbreviation for Solid State Drive.

[0087] (Disclosure of Technical Idea) This specification discloses a plurality of technical ideas described in a plurality of clauses listed below. Some clauses may be described in a multiple dependent form that alternatively cites preceding clauses in subsequent clauses. Further, some clauses may be described in a multiple dependent form that cites clauses in other multiple dependent forms. The clauses described in these multiple dependent forms define a plurality of technical ideas.

[0088] <Technical Idea 1> A substrate (30, 30S) having a plurality of lands (34) provided on one surface, An electronic component (40) disposed on the one surface and having a plurality of terminals (41) provided on a surface opposite to the one surface corresponding to the lands, A solder (50) interposed between the land and the terminal and joining the land and the terminal, Comprising, The substrate includes the land as a conductor (32) disposed on an insulating base material (31), wiring (33) disposed in multiple layers on the insulating base material, and an interlayer connection portion (35) that electrically connects the wirings in different layers. The land includes a first land (341) to which the interlayer connection portion is electrically connected, and a second land (342) disposed adjacent to the first land and having no interlayer connection portion disposed directly below in a plan view from the thickness direction of the substrate. At least one of the interlayer connection portions electrically connected to the first land is provided offset at a position that does not overlap the first land in the plan view. An electronic device.

[0089] <Technical Idea 2> The electronic device according to Technical Idea 1, wherein the second lands are disposed on both sides of the first land in a direction orthogonal to the thickness direction.

[0090] <Technical Idea 3> The substrate is a build-up substrate having a core layer (301) and a build-up layer (302) laminated on the core layer. The interlayer connection portion electrically connected to the first land includes a via hole (352) penetrating the core layer. The electronic device according to Technical Idea 1 or Technical Idea 2, wherein the via hole is provided offset from a position overlapping the first land in the plan view.

[0091] <Technical Idea 4> The interlayer connection portion electrically connected to the first land includes a second via hole (351) provided in the build-up layer and continuous with the first land, in addition to a first via hole which is a via hole penetrating the core layer. The electronic device according to Technical Idea 3, wherein the first via hole and the second via hole are provided offset from a position overlapping the first land in the plan view.

[0092] <Technical Idea 5> The interlayer connection portion electrically connected to the first land includes a via hole (351) continuous with the first land. The electronic device according to Technical Idea 1 or Technical Idea 2, wherein the via hole is provided offset from a position overlapping the first land in the plan view.

[0093] <Technical Idea 6> The plurality of lands corresponding to the terminals are arranged in a matrix at a predetermined pitch. The electronic device according to any one of Technical Ideas 1 to 5, wherein at least one of the interlayer connection portions electrically connected to the first land is provided offset in a diagonal direction of the matrix arrangement with respect to the first land.

[0094] <Technical Idea 7> At least one of the interlayer connection portions electrically connected to the first land is provided at the center position between the first land and the land located adjacent to the first land in the diagonal direction, according to the electronic device described in Technical Idea 6.

[0095] <Technical Idea 8> At least one of the interlayer connection portions electrically connected to the first land is provided offset at a position that does not overlap with the electronic component in the plan view, according to the electronic device described in any one of Technical Ideas 1 to 5.

[0096] <Technical Idea 9> The plurality of lands corresponding to the terminals are arranged in a matrix. Among the plurality of lands, at least one of the land (34OM) arranged on the outermost periphery and the land (34I) arranged one inside from the outermost peripheral land includes the first land, according to the electronic device described in Technical Idea 8.

[0097] <Technical Idea 10> Comprising a main board (20). The substrate is a sub-substrate laminated on the main board. The electronic component is arranged on the one surface which is the surface opposite to the surface facing the main board on the sub-substrate, according to the electronic device described in any one of Technical Ideas 1 to 9.

Explanation of Reference Numerals

[0098] 10... Electronic device, 20... Main board, 20a... One surface, 20b... Back surface, 21... Land, 30... Sub-substrate, 30S... Substrate, 30a... One surface, 30b... Back surface, 301... Core layer, 302... Build-up layer, 31... Insulating base material, 32... Conductor, 33... Wiring, 331... Inner layer wiring, 332... Surface layer wiring, 34, 341, 342, 343, 344... Lands, 34OM... Outermost peripheral land, 34I... Nearby land, 35... Via hole, 351... LVH, 352... IVH, 36... Solder resist, 40... Electronic component, 40a... Opposite surface, 41... Terminal, 50, 70... Solder, 60, 80... Electronic components, 90... Connector

Claims

1. A substrate (30, 30S) having a plurality of lands (34) provided on one surface, An electronic component (40) disposed on the one surface and having a plurality of terminals (41) provided on a surface opposite to the one surface corresponding to the lands, Solder (50) interposed between the land and the terminal and joining the land and the terminal, comprising: The substrate includes the lands as conductors (32) disposed on an insulating base material (31), wirings (33) disposed in multiple layers on the insulating base material, and an interlayer connection portion (35) for electrically connecting the wirings in different layers. The lands include a first land (341) to which the interlayer connection portion is electrically connected, and a second land (342) disposed adjacent to the first land and having no interlayer connection portion disposed directly below in a plan view from the thickness direction of the substrate. At least one of the interlayer connection portions electrically connected to the first land is provided offset at a position not overlapping the first land in the plan view. An electronic device.

2. The electronic device according to claim 1, wherein the second lands are disposed on both sides of the first land in a direction orthogonal to the thickness direction.

3. The substrate is a build-up substrate having a core layer (301) and a build-up layer (302) laminated on the core layer. The interlayer connection portion electrically connected to the first land includes a via hole (352) penetrating the core layer. The electronic device according to claim 1 or claim 2, wherein the via hole is provided offset at a position not overlapping the first land in the plan view.

4. In addition to a first via hole which is a via hole penetrating the core layer, the interlayer connection portion electrically connected to the first land includes a second via hole (351) provided in the build-up layer and continuous with the first land. The electronic device according to claim 3, wherein the first via hole and the second via hole are provided offset at a position not overlapping the first land in the plan view.

5. The interlayer connection portion electrically connected to the first land includes a via hole (351) continuous with the first land. The electronic device according to claim 1 or 2, wherein the via hole is provided offset at a position not overlapping the first land in the plan view.

6. The plurality of lands corresponding to the terminals are arranged in a matrix at a predetermined pitch. The electronic device according to claim 1 or 2, wherein at least one of the interlayer connection portions electrically connected to the first land is provided offset in the diagonal direction of the matrix arrangement with respect to the first land.

7. The electronic device according to claim 6, wherein at least one of the interlayer connection portions electrically connected to the first land is provided at the center position between the first land and the land located adjacent to the first land in the diagonal direction.

8. The electronic device according to claim 1 or 2, wherein at least one of the interlayer connection portions electrically connected to the first land is provided offset at a position not overlapping the electronic component in the plan view.

9. The plurality of lands corresponding to the terminals are arranged in a matrix. The electronic device according to claim 8, wherein at least one of the outermost peripheral land (34OM) arranged among the plurality of lands and the land (34I) arranged one inside from the outermost peripheral land includes the first land.

10. Comprising a main board (20). The board is a sub-board laminated on the main board. The electronic component is disposed on the one surface of the sub-substrate, which is the surface opposite to the surface facing the main substrate, in the electronic device according to claim 1 or claim 2.

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