Circuit board and electronic device package

Abstract

To provide a circuit board that can reduce the risk of cracks occurring in a pad, improve the reliability, and improve adhesion between an insulating layer and the pad, and an electronic element package including the same.SOLUTION: The disclosed circuit board 10 includes an insulating layer 110 having at least one wiring layer 120 and at least one via layer 130 embedded therein and having a first surface and a second surface facing a first direction, and a pad 200 including a protruding portion 201 protruding from the first surface of the insulating layer 110 and a buried portion 202 buried in the insulating layer 110, and electrically connected to the wiring layer 120, the protruding portion 201 is located at the outermost edge along the first direction and including a first portion aligned in a second direction parallel to the first surface, and a second portion connected to the buried portion 202 and adjacent to the first surface, and the width of the first portion and the width of the second portion differ in the width along the second direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a circuit board and an electronic component package.

Background Art

[0002] In recent years, as semiconductors have become more highly performance, memories and passive components such as MLCCs and IPDs are mounted together on a single substrate, and the substrate tends to become thinner.

[0003] However, in the case of such a substrate, reliability problems may occur, such as warpage defects occurring and the adhesion between the pad and the insulating layer decreasing.

[0004] Therefore, there is a need to develop a circuit board that can improve the adhesion between the pad and the insulating layer to achieve high reliability.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One aspect of the present disclosure provides a circuit board that can reduce the risk of cracks occurring in pads, improve reliability, improve the adhesion between the insulating layer and the pads, and reduce the risk of delamination defects, and an electronic component package including the same.

[0006] However, the problems to be solved by the embodiments of the present invention are not limited to the above problems, and can be variously extended within the scope of the technical idea included in the present invention.

Means for Solving the Problems

[0007] The circuit board according to the embodiment includes at least one wiring layer and at least one buried via layer, an insulating layer having a first surface and a second surface facing each other in a first direction, a protruding portion protruding from the first surface of the insulating layer, and an embedded portion embedded in the insulating layer, and includes pads electrically connected to the wiring layer. The protruding portion is located on the outermost contour along the first direction, and includes a first portion aligned with a second direction parallel to the first surface and a second portion connected to the embedded portion and adjacent to the first surface. In the width along the second direction, the width of the first portion is different from the width of the second portion.

[0008] The width of the first portion may be smaller than the width of the second portion.

[0009] The protruding portion includes a third portion connecting the first portion and the second portion, and at least a part of the third portion may have a round shape in which the width gradually increases from the first portion to the second portion.

[0010] At least a part of the third portion may have a shape convex to the outside of the protruding portion.

[0011] The embedded portion is located to face the first portion of the protruding portion in the first direction, and includes a fourth portion aligned with the second direction and a fifth portion connecting the fourth portion and the protruding portion. The fourth portion and the fifth portion can be in contact with the insulating layer.

[0012] The fourth portion and the fifth portion of the embedded portion can have irregularities.

[0013] The second portion of the protruding portion can include a first region in contact with the insulating layer and a second region in contact with the embedded portion.

[0014] The first region of the second portion of the protruding portion can have irregularities.

[0015] The central axes of the embedded portion and the protruding portion can coincide.

[0016] The embedding part and the protruding part can contain the same substance.

[0017] The electronic device package according to the embodiment includes at least one wiring layer and at least one via layer embedded, an insulating layer having a first surface and a second surface facing each other in a first direction, a protruding part protruding from the first surface of the insulating layer, and an embedding part embedded in the insulating layer, a pad electrically connected to the wiring layer, and an electronic device disposed on the insulating layer and electrically connected to the pad. The protruding part is located on the outermost contour along the first direction, and includes a first part aligned with a second direction parallel to the first surface and a second part connected to the embedding part and adjacent to the first surface. In the width along the second direction, the width of the first part is different from the width of the second part.

[0018] The width of the first part may be smaller than the width of the second part.

[0019] The protruding part includes a third part connecting the first part and the second part, and at least a part of the third part can have a round shape in which the width gradually increases from the first part to the second part.

[0020] At least a part of the third part can have a shape convex to the outside of the protruding part.

[0021] The embedding part is located to face the second part of the protruding part in the first direction, and includes a fourth part aligned with the second direction and a fifth part connecting the fourth part and the protruding part. The fourth part and the fifth part can be in contact with the insulating layer.

[0022] The fourth part and the fifth part of the embedding part can have unevenness.

[0023] The second part of the protruding part can include a first region in contact with the insulating layer and a second region in contact with the embedding part.

[0024] The first region of the second part of the protruding portion can have unevenness.

[0025] The central axes of the embedded portion and the protruding portion can coincide.

[0026] It can be arranged between the electronic element and the pad and include a connection portion that electrically connects the electronic element and the wiring layer.

Advantages of the Invention

[0027] According to the circuit board according to the embodiment and the electronic element package including the same, the risk of cracks occurring in the pad can be reduced, the reliability can be improved, the adhesion between the insulating layer and the pad can be improved, and the risk of delamination failure can be reduced.

Brief Description of the Drawings

[0028]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Best Mode for Carrying Out the Invention

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement it. In order to clearly explain the present invention in the drawings, parts that are unnecessary for the explanation are omitted, and the same or similar components throughout the specification are denoted by the same reference numerals. Also, in the accompanying drawings, some components are exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect the actual size.

[0030] The accompanying drawings are only for making it easy to understand the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings, and should be understood to include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0031] Terms including ordinal numbers such as first, second, etc. can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0032] Also, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is directly above the other part, but also the case where there is yet another part in between. Conversely, when a part is "directly above" another part, it means there is no other part in between. Also, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity.

[0033] Throughout the specification, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part "comprises" a certain component, this means that it can further comprise other components rather than excluding other components, unless otherwise stated to the contrary.

[0034] Also, throughout the specification, when referring to "in a plane", this means when viewing the target part from above, and when referring to "in a cross-section", this means when viewing the cross-section obtained by vertically cutting the target part from the side.

[0035] Throughout the specification, when a part is "coupled" to another part, this includes not only the case where it is "directly or physically coupled", but also the case where it is "indirectly or non-contact coupled" with another element interposed in between.

[0036] Also, throughout the specification, when it is stated that "connected", this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, not only physically connected but also electrically connected, or can mean that they are integrated although referred to by different names depending on their positions and functions.

[0037] Hereinafter, with reference to FIGS. 1 and 2, a circuit board according to an embodiment will be described.

[0038] FIG. 1 is a cross-sectional view schematically showing a circuit board according to an embodiment, and FIG. 2 is an enlarged view of part A in FIG. 1.

[0039] Referring to FIG. 1, a circuit board 10 according to this embodiment includes at least one wiring layer and at least one via layer embedded, an insulating layer 110 having a first surface and a second surface facing each other in a first direction, and a protruding portion 201 protruding from a first portion 201a of the insulating layer 110 and an embedded portion 202 embedded in the insulating layer 110, and may include a pad 200 electrically connected to the wiring layer 120. The protruding portion 201 is located on the outermost contour along the first direction, includes a first portion 201a aligned with a second direction parallel to the first surface, and a second portion 201b adjacent to the embedded portion 202 and protruding from the first surface. In the width along the second direction, the width (d1) of the first portion 201a and the width (d2) of the second portion 201b may be different.

[0040] The circuit board 10 according to this embodiment may include an insulating layer 110. The insulating layer may include at least one of insulating layers 111, 112, 113, 114. For example, the insulating layer 110 may include first to fourth insulating layers 111, 112, 113, 114. The third insulating layer may be located on the fourth insulating layer 114. The second insulating layer 112 may be located on the third insulating layer 113. The first insulating layer 111 may be located on the second insulating layer 112.

[0041] As the material of each of the insulating layers 110, an insulating substance can be used. The insulating substance can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material in which inorganic fillers such as silica and reinforcing materials such as glass fibers are included in these resins. For example, as the material of the insulating layer 110, prepreg, RCC (Resin Coated Copper foil), etc. are used, but it is not limited thereto, and materials that do not include reinforcing materials such as glass fibers, for example, ABF (Ajinomoto - Build up Film), etc. may be used. If necessary, a photosensitive insulating material such as PID (Photo Image - able Dielectric) may be used as the material of the insulating layer 110.

[0042] Referring to FIG. 1, the insulating layer 110 is shown as one of four layers, but it is not limited thereto. The insulating layer 110 may be composed of more layers than shown or fewer layers.

[0043] The circuit board 10 according to this embodiment can include a wiring layer 120. The wiring layer 120 can include at least one of the wiring layers 121, 122, 123, 124. For example, the wiring layer 120 can include the first to fourth wiring layers 121, 122, 123, 124. The wiring layer 120 can be located on one side of the insulating layer 110. The first wiring layer 120 can be located on one side of the first insulating layer 111. The second wiring layer 122 can be located on one side of the second insulating layer 112. The third wiring layer 123 can be located on one side of the third insulating layer 113. The fourth wiring layer 124 can be located on one side of the fourth insulating layer 114.

[0044] The wiring layer 120 can transmit the signals of the circuit board 10. As the material of the wiring layer 120, a metallic substance can be used. The metallic substance may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layer 120 can perform various functions according to design patterns such as a ground pattern, a power pattern, a signal pattern, etc. These patterns can each have forms such as a line or a plane. In the case of the wiring layer 124 located in the outermost layer of the wiring layer 120, it can function for connection with other substrates or components.

[0045] Referring to FIG. 1, the wiring layer 120 is illustrated as including the first to fourth wiring layers 121, 122, 123, and 124, but is not limited thereto, and a larger number of wiring layers than those illustrated may be arranged, or a smaller number of wiring layers may be arranged.

[0046] The circuit board 10 according to this embodiment can include pads 200. The pads 200 can be located on one surface of the insulating layer 110. The pads 200 can include a protruding portion 201 protruding from the insulating layer 110 and an embedded portion 202 embedded in the insulating layer 110. The pads 200 can be electrically connected to the wiring layer 120. For example, the pads 200 can be located on one surface of the first insulating layer 111. The embedded portion 202 of the pads 200 is embedded in the first insulating layer 111, and the remaining protruding portion 201 can protrude from one surface of the first insulating layer 111.

[0047] As the material of the pads 200, a metallic substance can be used. The metallic substance may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0048] The circuit board 10 according to this embodiment can include a via layer 130. The via layer 130 can be arranged to electrically connect the first to fourth wiring layers 121, 122, 123, 124 to each other. The via layer 130 can include at least one of the via layers 131, 132, 133, 134. The insulating layer 110 can embed at least one of the via layers 131, 132, 133, 134. For example, the via layer 130 can include the first to fourth via layers 131, 132, 133, 134.

[0049] Each via electrode of the via layer 130 can have a tapered shape in which the width of one side is larger than the width of the other side. As the material of the via layer 130, a metallic substance can be used. The metallic substance may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0050] The via layer 130 can include signal vias, ground vias, power vias, etc. according to the design. Each via electrode of the via layer 130 may be one in which the via hole is completely filled with a metallic substance, or one in which the metallic substance is formed along the wall surface of the via hole. The via layer 130 can be formed by a plating process, for example, processes such as AP (Additive Process), SAP (Semi AP), MSAP (Modified SAP), TT (Tenting). The via layer 130 can include a seed layer of an electroless plating layer and an electroplating layer formed based on such a seed layer.

[0051] The first via layer 131 can be located within the first insulating layer 110. The first via layer 131 can penetrate the first insulating layer 110 and connect to the pad 200 and the first wiring layer 120. Therefore, the first via layer 131 can electrically connect the pad 200 and the first wiring layer 120.

[0052] The second via layer 132 can penetrate the second insulating layer 112 and connect to the first wiring layer 120 and the second wiring layer 122. Therefore, the second via layer 132 can electrically connect the first wiring layer 120 and the second wiring layer 122.

[0053] The third via layer 133 can penetrate the third insulating layer 113 and connect to the second wiring layer 122 and the third wiring layer 123. Therefore, the third via layer 133 can electrically connect the second wiring layer 122 and the third wiring layer 123.

[0054] The fourth via layer 134 can penetrate the fourth insulating layer 114 and connect to the third wiring layer 123 and the fourth wiring layer 124. Therefore, the fourth via layer 134 can electrically connect the third wiring layer 123 and the fourth wiring layer 124.

[0055] Referring to FIG. 1, only the first to third via layers 131, 132, 133, 134 are shown, but it is not limited thereto, and more or fewer via layers can be arranged as needed.

[0056] The solder resist layer 140 can be located on one surface of the insulating layer 110 so as to cover a part of the fourth wiring layer 124 to prevent unnecessary short circuits. The solder resist layer 140 can be arranged to expose at least a part of the fourth wiring layer 124. The solder resist layer 140 can include a photosensitive resin material.

[0057] The first surface treatment layer 151 can be disposed on the surface of the protruding portion 201. The first surface treatment layer 151 can be formed to prevent an oxide film from being formed on the surface of the pad 200. For example, the first surface treatment layer 151 can be formed by the ENEPIG (Electroless Ni Electroless Pd Immersion Gold) method and can contain nickel (Ni), palladium (Pd), and gold (Au). However, it is not limited thereto, and the first surface treatment layer 151 can be formed by a surface treatment method known in the circuit board field, such as plating nickel (Ni), tin (Sn), gold (Au), palladium (Pd), or coating an organic protective film (Organic Solder ability Preservative; OSP).

[0058] The second surface treatment layer 152 can be disposed on the surface of the fourth wiring layer 124. The second surface treatment layer 152 can be formed to prevent an oxide film from being formed on the surface of the fourth wiring layer 124. For example, the second surface treatment layer 152 can be formed by the ENEPIG (Electroless Ni Electroless Pd Immersion Gold) method and can contain nickel (Ni), palladium (Pd), and gold (Au). However, it is not limited thereto, and the second surface treatment layer 152 can be formed by a surface treatment method known in the circuit board field, such as plating nickel (Ni), tin (Sn), gold (Au), palladium (Pd), or coating an organic protective film (Organic Solder ability Preservative; OSP).

[0059] Hereinafter, with reference to FIG. 2, the pad 200 will be specifically described.

[0060] Referring to FIG. 2, the protruding portion 201 can be located at the outermost contour along the first direction, and includes a first portion 201a aligned with the second direction and a second portion 201b connected to the embedded portion 202 and adjacent to the first surface. The second direction can be a direction parallel to the first surface and perpendicular to the first direction. The first portion 201a can be located at one end of the protruding portion 201 along the first direction. The second portion 201b can be located in the other end region of the protruding portion 201 along the first direction. The second portion 201b is adjacent to the embedded portion 202 and can protrude from the first surface. For example, in the width along the second direction, the width of the second portion 201b may be constant.

[0061] In the width along the second direction, the width (d1) of the first portion 201a and the width (d2) of the second portion 201b may be different. In the width along the second direction, the width (d1) of the first portion 201a may be smaller than the width (d2) of the second portion 201b. The width (d1) of the first portion 201a can be the maximum length, the minimum length, or the average value of the lengths of a plurality of line segments measured from one end to the other end of the first portion 201a along the second direction in the cross section. The width (d2) of the second portion 201b can be the maximum length, the minimum length, or the average value of the lengths of a plurality of line segments measured from one end to the other end of the second portion 201b along the second direction in the cross section.

[0062] The protruding portion 201 can include a third portion 201c connecting the first portion 201a and the second portion 201b. At least a part of the third portion 201c of the protruding portion 201 has a height gradually decreasing from the first surface as going from the first portion 201a to the second portion 201b. At least a part of the third portion 201c of the protruding portion 201 has a width gradually increasing along the second direction as going from the first portion 201a to the second portion 201b. At least a part of the third portion 201c can have a round shape. The upper surface corner region of the protruding portion 201 may be round. At least a part of the third portion 201c can have a shape convex to the outside of the protruding portion 201.

[0063] The second part 201b of the protrusion 201 can include a first region in contact with the insulating layer 110 and a second region in contact with the embedded portion 202. The second region may be a region where the protrusion 201 is connected to the embedded portion 202. The first region of the protrusion 201 that is in contact with the insulating layer 110 can have unevenness on its surface. The first region of the protrusion 201 can have surface roughness. In FIG. 2, the unevenness is illustrated in a sharp shape, but this is exemplary, and any shape that forms surface roughness in the first region is possible.

[0064] The embedded portion 202 is positioned to face the first part 201a of the protrusion 201 in a first direction, and can include a fourth part 202a aligned with a second direction and a fifth part 202b connecting the fourth part 202a and the protrusion 201. The fourth part 202a can be positioned at one end of the embedded portion 202 along the first direction. The fifth part 202b can be a side surface connecting the fourth part 202a. The fourth part 202a and the fifth part 202b can be adjacent to the insulating layer.

[0065] The fourth part 202a and the fifth part 202b can be in contact with the insulating layer 110. The fourth part 202a and the fifth part 202b can have unevenness on their surfaces. The fourth part 202a and the fifth part 202b can have surface roughness. In FIG. 2, the unevenness is illustrated in a sharp shape, but this is exemplary, and any shape that forms surface roughness in the fourth part 202a and the fifth part 202b is possible.

[0066] The width (d3) of the embedded portion 202 may be constant at the top and bottom. That is, the width of the fourth part 202a and the width at the surface adjacent to the protrusion 201 are the same or similar. The width (d3) of the embedded portion 202 can be the maximum length, minimum length, or the average value of the lengths of a plurality of line segments measured from one end to the other end of the embedded portion 202 along the second direction in a cross-section.

[0067] The embedded portion 202 and the protruding portion 201 can be formed by a single plating. Therefore, the central axes of the embedded portion 202 and the protruding portion 201 can coincide. Also, the embedded portion 202 and the protruding portion 201 can contain the same material.

[0068] According to the circuit board according to this embodiment, by forming the upper part of the protruding portion into a round shape, the risk of cracks occurring in the pad can be reduced, and the reliability can be improved. Also, by forming irregularities on the surface of the protruding portion in contact with the insulating layer and the surface of the embedded portion in contact with the insulating layer, the adhesion between the insulating layer and the pad can be improved, and the risk of delamination failure can be reduced. By forming the pad with a single piece of metal without an interface in the middle, the reliability of the pad can be strengthened.

[0069] Hereinafter, with reference to FIGS. 3 to 11, a method for manufacturing a circuit board according to an embodiment will be described. FIGS. 3 to 11 are cross-sectional views illustrating a method for manufacturing a circuit board according to an embodiment.

[0070] Referring to FIG. 3, a seed layer 2001 can be formed on a carrier substrate (CS) including a core portion (CO) and a thin film metal layer (MS) laminated on the core portion (CO). The seed layer 2001 can be formed by a plating process. For example, the seed layer 2001 can contain nickel. The thin film metal layer (MS) can be formed of a material different from that of the seed layer 2001. The thin film metal layer (MS) can contain copper. The thin film metal layer (MS) can contain nickel having a composition different from that of the seed layer 2001.

[0071] Referring to FIG. 4, a mask layer 2002 can be formed on the seed layer 2001. The portion except for the region where the pad 200 (see FIG. 1) is formed may be covered by the mask layer 2002. The mask layer 2002 can be formed including a dry film.

[0072] Referring to FIG. 5, using the mask layer 2002 as an etching mask, a part of the seed layer 2001' can be etched. For example, a part of the seed layer 2001' can be etched using an etching solution. In this case, the seed layer 2001' and the thin film metal layer (MS) can contain metal substances that can be selectively removed by different etching solutions. As described above, for example, the seed layer 2001' can contain nickel, and the thin film metal layer (MS) can contain copper. However, it is not limited thereto.

[0073] Referring to FIG. 6, a pad structure 2003 can be formed in the openings of the seed layer 2001' and the mask layer 2002 by a plating process. For example, the pad structure 2003 can contain copper.

[0074] Referring to FIG. 7, the mask layer 2002 can be removed, and at least one insulating layer, at least one wiring layer, and at least one via layer can be formed on the seed layer 2001' to form a build-up structure. Here, roughness can be formed on the surface of the pad structure 2003'. That is, the pad structure 2003' can have irregularities on the surface in contact with the mask layer 2002.

[0075] For example, the first insulating layer 111 can be formed to embed the pad structure 2003'. The first wiring layer 121 can be formed on the first insulating layer 111, and the first via layer 131 can be formed through at least a part of the first insulating layer 111. Also, the second insulating layer 112 can be formed to embed the first wiring layer 120. The second wiring layer 122 can be formed on the second insulating layer 112, and the second via layer 132 can be formed through at least a part of the second insulating layer 112.

[0076] Referring to FIG. 8, at least one insulating layer, at least one wiring layer, and at least one via layer can be formed on the second insulating layer 112 to form a build-up structure. For example, the third insulating layer 113 can be formed to embed the second wiring layer 122. The third wiring layer 123 can be formed on the third insulating layer 113, and the third via layer can be formed through at least a part of the third insulating layer 113. Also, the fourth insulating layer 114 can be formed to embed the third wiring layer 123. The fourth wiring layer 124 can be formed on the fourth insulating layer 114, and the fourth via layer 134 can be formed through at least a part of the fourth insulating layer 114.

[0077] A solder resist layer 140 can be formed on one surface of the fourth insulating layer 114. The solder resist layer 140 can be formed to expose a part of the fourth wiring layer 124.

[0078] Referring to FIG. 9, the carrier substrate (CS) can be separated.

[0079] Referring to FIG. 10, the seed layer 2001 can be removed to form the pad 200 including the protrusion 201 and the embedded portion 202. Here, at least a part of the protrusion 201 can be formed to have a round shape. For example, the corner region of the protrusion 201 can be formed into a round shape by chemical etching such as soft etching. As another example, the surface of the protrusion 201 such as jet scrub can be physically treated to form the corner region of the protrusion 201 into a round shape.

[0080] Referring to FIG. 11, a first surface treatment layer 151 can be formed on the surface of the protruding portion 201. Also, a second surface treatment layer 152 can be formed on the surface of the fourth wiring layer 124 exposed to the outside to form a circuit board 10 as shown in FIG. 1. For example, the first and second surface treatment layers 151, 152 can be formed by OSP (Organic Solder ability Preservative) or ENEPIG (Electroless Nickel / Electroless Palladium / Immersion Gold) method. Also, as the surface treatment layer, an electroless Ni / Pd / Au plating layer or an electrolytic Ni / Au plating layer etc. can be formed, but it is not limited thereto. By the pad 200 contacting the insulating layer 110, it is possible to prevent a surface treatment layer from being formed between the pad 200 and the insulating layer 110, and thus the adhesion of the pad 200 can be improved.

[0081] According to the method for manufacturing a circuit board according to this embodiment, by forming the upper part of the protruding portion into a round shape, the risk of cracks occurring in the pad can be reduced and the reliability can be improved. Also, by forming irregularities on the surface of the protruding portion in contact with the insulating layer and the surface of the embedded portion in contact with the insulating layer, the adhesion between the insulating layer and the pad can be improved, and the risk of delamination failure can be reduced. By forming the entire pad shape in one plating, the reliability of the pad can be improved.

[0082] Also, according to the method for manufacturing a circuit board according to this embodiment, by forming a protruding pad without etching the insulating layer, the adhesion between the pad and the insulating layer can be improved and high reliability can be realized. Also, by forming a protruding pad by etching, the process cost can be reduced, and the pad can be freely designed according to the combination of the thickness of the seed layer and the surface treatment.

[0083] Hereinafter, referring to FIGS. 12 and 13, an electronic element package according to an embodiment will be described.

[0084] FIG. 12 is a cross-sectional view schematically showing an electronic device package according to an embodiment.

[0085] Referring to FIG. 12, the electronic device package 1000 according to the present embodiment can include the circuit board 10 according to the above-described embodiment. Hereinafter, the description regarding the circuit board is similarly applicable to the circuit board 10 according to the above-described embodiment.

[0086] The electronic device package 1000 according to an embodiment can include a circuit board 10, an electronic device 300 mounted on one surface of the circuit board 10, a connection portion 400 that electrically connects the circuit board 10 and the electronic device 300, a first conductive member 500 that connects the connection portion 400 and the circuit board 10, a second conductive member 600 that electrically connects the circuit board 10 and another substrate or an electronic device (not shown), and an underfill 700.

[0087] The electronic device 300 can be an integrated circuit (IC) die in which hundreds to millions or more of device elements are integrated in one chip. For example, the electronic device 300 is a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, specifically, an application processor (AP), but is not limited thereto, and may be other volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), memories such as flash memories, or logics such as analog-to-digital converters or application-specific ICs (ASICs). If necessary, the electronic device 300 may be a chip-shaped passive component, for example, a chip-shaped capacitor such as a multi-layer ceramic capacitor (MLCC), a chip-shaped inductor such as a power inductor (PI), or the like.

[0088] The connection part 400 can be arranged between the electronic element 300 and the pad 200. The connection part 400 can electrically connect the electronic element 300 and the wiring layer 120. The connection part 400 can physically and / or electrically connect the electronic element 300 and the circuit board 10. For example, the connection part 400 can electrically connect the exposed circuit of the electronic element and the pad 200. The connection part 400 is formed of copper or the like, but is not limited thereto. For example, the connection part 400 is a columnar metal post, but is not limited thereto, and may have a shape such as a land, a ball, or a pin.

[0089] The first conductive member 500 can be arranged on the first surface treatment layer 151. The first conductive members 500 are each formed of tin (Sn) or an alloy containing tin (Sn), such as solder, but are not limited thereto. For example, the first conductive member 500 is in the shape of a ball, but is not limited thereto, and may have a shape such as a land, a pin, or a columnar metal post.

[0090] The second conductive member 600 can be arranged in at least a part of the opening of the solder resist layer 140. The second conductive member 600 can be located on the fourth wiring layer 124. The second conductive member 600 can physically and / or electrically connect the circuit board 10 to the outside. For example, the second conductive member 600 can electrically connect the exposed wiring layer of the circuit board 10 and an external board or an electronic element. The second conductive members 600 are each formed of tin (Sn) or an alloy containing tin (Sn), such as solder, but are not limited thereto. For example, the first conductive member 500 has a visible shape, but is not limited thereto, and may have a shape such as a land, a pin, or a columnar metal post.

[0091] The underfill 700 can fix the electronic component 300 with a material filled between the electronic component 300 mounted on the circuit board 10 and the circuit board 10. In particular, when the connection part 400 is formed to protrude and a gap is generated between one surface of the electronic component 300 and the circuit board 10, the underfill 700 can be filled in the gap.

[0092] According to the electronic component package according to this embodiment, by forming the upper part of the protrusion into a round shape, the risk of cracks occurring in the pad can be reduced and the reliability can be improved. Further, by forming irregularities on the surface of the protrusion in contact with the insulating layer and the surface of the embedded part in contact with the insulating layer, the adhesion between the insulating layer and the pad can be improved, and the risk of delamination failure can be reduced. By forming the pad with a single piece of metal without an interface in the middle, the reliability of the pad can be strengthened, a highly reliable circuit board can be provided, and the thickness of the electronic component package can be reduced.

[0093] As described above, the preferred embodiments of the present invention have been described. However, the present invention is not limited thereto, and various modifications can be made within the scope of the claims, the description of the invention, and the accompanying drawings, and it is natural that these also belong to the scope of the present invention.

Description of Reference Numerals

[0094] 10 Circuit board 110 Insulating layer 120 Wiring layer 130 Via layer 140 Solder resist layer 151 First surface treatment layer 152 Second surface treatment layer 200 Pad 201 Protrusion 201a First part 201b Second part 201c Third part 202 Embedded part 202a Fourth part 202b Fifth part 300 Electronic component 400 Connection part 500 First conductive member 600 Second conductive member 700 Underfill 1000 Electronic component package

Claims

1. an insulating layer having at least one wiring layer and at least one via layer embedded therein and having a first surface and a second surface opposed to each other in a first direction; a pad including a protruding portion protruding from the first surface of the insulating layer and a buried portion buried in the insulating layer, the pad being electrically connected to the wiring layer; Including, the protruding portion includes a first portion located at the outermost portion along the first direction and aligned in a second direction parallel to the first surface, and a second portion connected to the embedded portion and adjacent to the first surface; A circuit board, wherein the width of the first portion and the width of the second portion are different in the second direction.

2. The circuit board of claim 1 , wherein the first portion has a width smaller than a width of the second portion.

3. the protrusion includes a third portion connecting the first portion and the second portion, The circuit board according to claim 1 , wherein at least a part of the third portion has a rounded shape whose width gradually increases from the first portion to the second portion.

4. The circuit board according to claim 3 , wherein at least a part of the third portion has a shape that is convex outwardly of the protruding portion.

5. the embedded portion includes a fourth portion positioned to face the first portion of the protruding portion in the first direction and aligned in the second direction, and a fifth portion connecting the fourth portion and the protruding portion, The circuit board of claim 1 , wherein the fourth portion and the fifth portion contact the insulating layer.

6. The circuit board according to claim 5 , wherein the fourth portion and the fifth portion of the embedded portion have projections and recesses.

7. The circuit board according to claim 1 , wherein the second portion of the protruding portion includes a first region in contact with the insulating layer and a second region in contact with the buried portion.

8. The circuit board according to claim 7 , wherein the first region of the second portion of the protrusion has projections and recesses.

9. The circuit board according to claim 1 , wherein the embedded portion and the protruding portion have the same central axis.

10. The circuit board of claim 1 , wherein the embedded portion and the protruding portion comprise the same material.

11. an insulating layer having at least one wiring layer and at least one via layer embedded therein and having a first surface and a second surface opposed to each other in a first direction; a pad including a protruding portion protruding from the first surface of the insulating layer and a buried portion buried in the insulating layer, the pad being electrically connected to the wiring layer; an electronic element disposed on the insulating layer and electrically connected to the pad; Including, the protruding portion includes a first portion located at the outermost portion along the first direction and aligned in a second direction parallel to the first surface, and a second portion connected to the embedded portion and adjacent to the first surface; An electronic element package, wherein the width of the first portion and the width of the second portion are different in the width along the second direction.

12. The electronic device package of claim 11 , wherein the width of the first portion is less than the width of the second portion.

13. the protrusion includes a third portion connecting the first portion and the second portion, The electronic device package of claim 11 , wherein at least a portion of the third portion has a rounded shape whose width gradually increases from the first portion to the second portion.

14. The electronic device package according to claim 13 , wherein at least a part of the third portion has a shape that is convex outwardly of the protruding portion.

15. the embedded portion includes a fourth portion positioned to face the first portion of the protruding portion in the first direction and aligned in the second direction, and a fifth portion connecting the fourth portion and the protruding portion, The electronic device package of claim 11 , wherein the fourth portion and the fifth portion contact the insulating layer.

16. The electronic device package according to claim 15 , wherein the fourth and fifth portions of the embedded portion have projections and recesses.

17. The electronic device package of claim 11 , wherein the second portion of the protruding portion includes a first region in contact with the insulating layer and a second region in contact with the recessed portion.

18. The electronic device package of claim 17 , wherein the first region of the second portion of the protrusion has an uneven surface.

19. The electronic device package according to claim 11 , wherein the embedded portion and the protruding portion have the same central axis.

20. The electronic element package according to claim 11 , further comprising a connection portion disposed between the electronic element and the pad, electrically connecting the electronic element and the wiring layer.

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