Manufacturing method of semiconductor element

Abstract

To provide a light emitter having a base semiconductor portion including a nitride semiconductor and a compound semiconductor portion including a nitride semiconductor, which can improve light emission efficiency and reliability.SOLUTION: A light emitter includes a base semiconductor portion 8 including a nitride semiconductor, a compound semiconductor portion 9 including a nitride semiconductor and located above the base semiconductor portion, a first electrode E1 and a second electrode E2, the base semiconductor portion has a first portion and a second portion in which the density of threading dislocations extending in the thickness direction is lower than that of the first portion, at least a portion of the first electrode and at least a portion of the second electrode are located on the compound semiconductor portion, and at least a portion of the first electrode is located above the second portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] In the nitride semiconductor laser described in Patent Document 1, an anode and a cathode are formed on one side of a chip including a semiconductor layer. When a portion parallel to the c-plane of the semiconductor layer is included in the current path from the anode to the cathode, the light emission efficiency decreases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The light emitter according to the present disclosure includes a base semiconductor part including a nitride semiconductor, a compound semiconductor part including a nitride semiconductor and located above the base semiconductor part, a first electrode, and a second electrode. The base semiconductor part has a first part and a second part in which the density of through dislocations extending in the thickness direction is less than that of the first part. At least a part of the first electrode and at least a part of the second electrode are located on the compound semiconductor part, and at least a part of the first electrode is located above the second part.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0006] 〔Light-emitting body〕 FIG. 1 is a perspective view showing the configuration of a light-emitting body according to the present embodiment. As shown in FIG. 1, the light-emitting body 21 according to the present embodiment includes a base semiconductor part 8 containing a nitride semiconductor, a compound semiconductor part 9 containing a nitride semiconductor and located above the base semiconductor part 8, and a first electrode E1 and a second electrode E2. The base semiconductor part 8 has a first part B1 and a second part B2 whose density of through dislocations extending in the thickness direction (Z direction) is less than that of the first part B1. At least a part of the first electrode E1 and at least a part of the second electrode E2 are located on the compound semiconductor part 9. At least a part of the first electrode E1 may be located above the second part B2. Hereinafter, the direction from the base semiconductor part 8 to the compound semiconductor part 9 is defined as the upward direction. In the light-emitting body 21, the base semiconductor part 8 may be a base semiconductor layer 8, and the compound semiconductor part 9 may be a compound semiconductor layer 9. The light-emitting body 21 may be a light-emitting diode (LED) chip or a semiconductor laser chip.

[0007] Since the base semiconductor part 8 of the light-emitting body 21 includes a second part B2 (low defect part) with a low density of through dislocations, the luminous efficiency and reliability can be improved in a configuration where the first and second electrodes E1 and E2 are provided on one side of the chip. This is because through dislocations cause heat generation.

[0008] In the present embodiment, in plan view, the second part B2 of the base semiconductor part 8 and the first electrode E1 may overlap. "Two members overlap" means that at least a part of one member overlaps the other member in a plan view (including a perspective plan view) viewed in the thickness direction of each member, and these members may or may not be in contact with each other.

[0009] The nitride semiconductors included in the base semiconductor part 8 and the compound semiconductor part 9 can be represented, for example, as AlxGayInzN (0 ≦ x ≦ 1; 0 ≦ y ≦ 1; 0 ≦ z ≦ 1; x + y + z = 1). Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). The GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor part 8 may be of a doped type (for example, an n-type containing donors) or an undoped type.

[0010] The base semiconductor part 8 containing a nitride semiconductor can be formed by the ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, for example, the base semiconductor part 8 is grown laterally on a template substrate having a mask pattern (selective growth mask) including an opening part and a mask part (described later). In this way, a low defect part (second part B2) with a small threading dislocation density can be formed on the mask part. Since the threading dislocations (dislocations extending in the thickness direction) inherited by the compound semiconductor part 9 (for example, GaN-based semiconductor layer) on the second part B2 are reduced, the light emission efficiency can be increased.

[0011] 〔Light Emitting Device〕 FIG. 2 is a schematic diagram showing the configuration of the light emitting device according to the present embodiment. The light emitting substrate 22 according to the present embodiment includes a plurality of light emitters 21 (chips) and a support substrate SK on which the plurality of light emitters 21 are mounted. The light emitting element 23 according to the present embodiment includes one or more light emitters 21 and a support ST on which one or more light emitters 21 are mounted. Hereinafter, the light emitter 21, the light emitting substrate 22, the light emitting element (a light emitting element) 23, and the light emitting module described later may be collectively referred to as a light emitting device (a light emitting device).

[0012] 〔Manufacture of Light Emitter〕 FIG. 3 is a flowchart showing an example of a method for manufacturing a light emitter according to the present embodiment. In the manufacturing method of FIG. 3, after the step of preparing a template substrate (substrate for ELO growth), a step of forming the base semiconductor portion 8 using the ELO method, a step of forming the compound semiconductor portion 9, and a step of forming the first and second electrodes E1 and E2 are performed.

[0013] FIG. 4 is a block diagram showing an example of a manufacturing apparatus for a light emitter according to the present embodiment. The light emitter manufacturing apparatus 70 of FIG. 4 includes a semiconductor forming portion 72 that forms the base semiconductor portion 8 and the compound semiconductor portion 9 on a template substrate, an electrode forming portion 73 that forms the first and second electrodes E1 and E2, and a control portion 74 that controls the semiconductor forming portion 72 and the electrode forming portion 73.

[0014] The semiconductor forming portion 72 may include a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and the control portion 74 may include a processor and a memory. The control portion 74 may be configured to control the semiconductor forming portion 72 and the electrode forming portion 73 by executing a program stored in a built-in memory, a communicable communication device, or an accessible network, for example. The above program and a recording medium on which the above program is stored are also included in the present embodiment.

[0015] 〔Example 1〕 (Configuration) FIG. 5 is a perspective view showing the configuration of a light emitter according to Example 1. FIG. 6 is a plan view showing the configuration of the compound semiconductor portion. FIG. 7 is a cross-sectional view showing the configuration of a light emitter according to Example 1. As shown in FIGS. 5 to 7, the light emitter 21 according to Example 1 includes a base semiconductor portion 8, a compound semiconductor portion 9 located on the base semiconductor portion 8, a first electrode E1 that is an anode, and a second electrode E2 that is a cathode. The light emitter 21 can also be referred to as a semiconductor laser chip.

[0016] The base semiconductor part 8 and the compound semiconductor part 9 are nitride semiconductor layers (for example, GaN-based semiconductor layers), and the base semiconductor part 8 is an n-type semiconductor layer having donors. In FIG. 5 and the like, the <11-20> direction of the base semiconductor part 8 is defined as the X direction, the <1-100> direction as the Y direction, and the <0001> direction as the Z direction (thickness direction).

[0017] The base semiconductor part 8 is a self-supporting layer without a support material. The upper surface of the base semiconductor part 8 is in contact with the compound semiconductor part 9, and the lower surface 8U of the base semiconductor part 8 is exposed (the lower surface 8U is exposed in chip units, but may not be exposed after mounting).

[0018] The base semiconductor part 8 includes a first part B1 containing a through dislocation KD extending in the Z direction, and a second part B2 and a third part B3 having a through dislocation density smaller than that of the first part B1. The second part B2, the first part B1, and the third part B3 are arranged in this order in the X direction, and the first part B1 is located between the second part B2 and the third part B3. The first part B1 is a portion that was located on the opening of the mask layer 6 when the base semiconductor part 8 was formed by the ELO method (described later). The through dislocation density of the second part B2 and the third part B3 is 1 / 5 or less of the through dislocation density of the first part B1 (for example, 5×10 6 / cm 2 or less).

[0019] The compound semiconductor part 9 is formed by sequentially forming a first-type (n-type) semiconductor layer 9N having donors, an active layer 9K, and a second-type (p-type) semiconductor layer 9P having acceptors. The first-type semiconductor layer 9N is formed by sequentially forming a first contact layer 9A, a first cladding layer 9B, and a first optical guide layer 9C. The second-type semiconductor layer 9P is formed by sequentially forming an electron blocking layer 9D, a second optical guide layer 9E, a second cladding layer 9F, and a second contact layer 9G, and a first electrode E1 (anode) is formed on the second contact layer 9G.

[0020] The second electrode E2 is provided on the same side of the base semiconductor portion 8 as the first electrode E1. The second electrode E2 is in contact with the first contact layer 9A, and in plan view, the first and second electrodes E1 and E2 may not overlap. Specifically, a part of the compound semiconductor portion 9 may be dug into the first contact layer 9A, and the second electrode E2 may be formed so as to be in contact with the first contact layer 9A exposed in the dug portion 9Q of the compound semiconductor portion 9. The first electrode E1 is located, for example, on the (0001) plane of the second-type semiconductor layer 9P (second contact layer 9G), and the second electrode E2 is located on the (0001) plane of the first-type semiconductor layer 9N (first contact layer 9A). In Example 1, the region of the first contact layer 9A in contact with the second electrode E2 has the same thickness as other regions, but the region of the first contact layer 9A in contact with the second electrode E2 may have a smaller thickness than other regions. For example, by digging into a part of the first contact layer 9A, a thin film portion having a smaller film thickness than the surroundings may be formed on the first contact layer 9A, and the second electrode E2 (cathode) may be provided so as to be in contact with this thin film portion. The upper surface of the thin film portion (contact surface with the second electrode E2) may be the (0001) plane of the first contact layer 9A which is a nitride semiconductor layer, for example.

[0021] When the compound semiconductor portion 9 is dug by etching or the like, the c-plane ((0001) plane) of the first contact layer 9A (for example, n-GaN layer) is exposed, and by bringing the second electrode E2 (cathode) into contact with the c-plane of the first contact layer 9A, the contact resistance can be reduced (compared with the case of contacting the -c plane). The c-plane is a gallium-polarity plane, and the -c plane is a nitrogen-polarity plane.

[0022] In plan view, the first electrode E1 and the second electrode E2 are arranged in the X direction (first direction). The first and second electrodes E1 and E2 have a shape with the Y direction (second direction) as the longitudinal direction. The size WC of the second electrode E2 in the X direction may be smaller than the size W3 of the third portion B3 in the X direction. The size WC of the second electrode E2 in the X direction may be larger than the size of the first electrode E1 in the X direction.

[0023] As shown in FIG. 7, the first electrode E1 has a first region L1 in contact with the ridge portion RJ, and in a plan view, the entire first region L1 may overlap with the second portion B2 (low defect portion) of the base semiconductor portion 8. The size WR of the first region L1 in the X direction may be smaller than the size W2 of the second portion B2 in the X direction.

[0024] The compound semiconductor portion 9 has an optical resonator LK including a pair of resonant end faces F1 and F2, and the resonance length (resonator length) K1, which is the distance between the pair of resonant end faces F1 and F2, is 200 [μm] or less. The resonance length K1 may be 20 [μm] or more and 200 [μm] or less. Each of the resonant end faces F1 and F2 is the m-plane of the compound semiconductor portion 9 and is included in the cleavage plane of the compound semiconductor portion 9. That is, each of the resonant end faces F1 and F2 can be formed by cleavage of the compound semiconductor portion 9, which is a nitride semiconductor layer (for example, a GaN-based semiconductor layer), along the m-plane. A scribe mark (trace of the cleavage starting point) for cleavage may be present in at least one of the base semiconductor portion 8 and the compound semiconductor portion 9. Note that the resonant end faces F1 and F2 can also be formed by etching.

[0025] Each of the resonant end faces F1 and F2 is covered with a mirror film UF (for example, a dielectric film), and the light reflectivity of the resonant end face F1 on the light emission surface side is, for example, 50% or more. The light reflectivity of the resonant end face F2 on the light reflection surface side is larger than the light reflectivity of the resonant end face F1. Although not shown in FIGS. 5 and 7, the mirror film UF can be formed over the entire cleavage plane (m-plane) of the base semiconductor portion 8 and the compound semiconductor portion 9.

[0026] The first electrode E1 overlaps with the optical resonator LK in a plan view and also overlaps with the second portion B2 of the base semiconductor portion 8. The length of the first and second electrodes E1 and E2 in the Y direction may be smaller than the resonance length K1. In this way, when the compound semiconductor portion 9 is cleaved, the first and second electrodes E1 and E2 do not interfere.

[0027] The optical resonator LK includes a part of each of the first-type semiconductor layer 9N, the active layer 9K, and the second-type semiconductor layer 9P (the part overlapping the first electrode E1 in plan view). For example, the optical resonator LK is composed of including a part of each of the first cladding layer 9B, the first optical guide layer 9C, the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F (the part overlapping the first electrode E1 in plan view).

[0028] In the optical resonator LK, the refractive index (optical refractive index) decreases in the order of the active layer 9K, the first optical guide layer 9C, and the first cladding layer 9B, and also decreases in the order of the active layer 9K, the second optical guide layer 9E, and the second cladding layer 9F. Therefore, the light generated by the recombination of the holes supplied from the first electrode E1 and the electrons supplied from the second electrode E2 in the active layer 9K is confined within the optical resonator LK (especially in the active layer 9K), and laser oscillation occurs due to the stimulated emission and feedback effects in the active layer 9K. The laser light generated by the laser oscillation exits from the light emission region EA of the resonance end face F1 on the emission surface side.

[0029] Since the resonance end faces F1·F2 are formed by m-plane cleavage, they are excellent in flatness and perpendicularity to the c-plane (parallelism of the resonance end faces F1·F2) and have a high light reflectivity. For this reason, mirror loss can be reduced, and stable laser oscillation is possible even at a short resonance length of 200 μm or less where it is difficult to reduce the mirror loss. Since the resonance end faces F1·F2 are formed on the second part B2 which is a low dislocation part, the flatness of the cleavage surface is excellent and a high light reflectivity is realized.

[0030] The compound semiconductor part 9 includes a ridge part (current constriction part) RJ overlapping the first electrode E1 in plan view. The ridge part RJ includes a part of the second cladding layer 9F and the second optical guide layer 9E (the part overlapping the first electrode E1 in plan view). Also, insulating films DF are provided on both sides of the ridge part RJ. The refractive index of the insulating film DF may be smaller than the refractive indices of the second optical guide layer 9E and the second cladding layer 9F. By providing the ridge part RJ and the insulating films DF, the current path between the first electrode E1 and the first-type semiconductor layer 9N is constricted on the anode side, and efficient light emission can be achieved within the resonator LK.

[0031] In plan view, the entire ridge portion RJ overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the ridge portion RJ does not overlap with the first portion B1). In this way, the current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in a portion (low dislocation portion) that overlaps with the second portion B2 in plan view, and the light emission efficiency in the active layer 9K is enhanced. This is because through dislocations inhibit the movement of charges and cause a decrease in light emission efficiency.

[0032] In Example 1, the sum T1 of the thickness of the base semiconductor portion 8 and the thickness of the compound semiconductor portion 9 can be 50 [μm] or less. If this sum of thicknesses T1 is too large, it becomes difficult to cleave so that the resonance length becomes 200 μm or less.

[0033] The base semiconductor portion 8 includes a base end face (cleavage face of the base semiconductor portion 8) that is flush with the resonance end face F1, and the density of dislocations (dislocations measured by CL at the cleavage face, mainly basal plane dislocations) at the base end face may be equal to or greater than the density of through dislocations in the second portion B2. Also, the surface roughness of at least one of the pair of resonance end faces F1 and F2 (for example, the resonance end face F2 on the reflection surface side) can be made smaller than the surface roughness of the side face 9S (see FIG. 6) which is the a-plane of the compound semiconductor portion 9. The a-plane is the (11-20) plane of the compound semiconductor portion 9 which is a nitride semiconductor layer.

[0034] In Example 1, power of, for example, 200 [mW] or less is supplied between the first and second electrodes E1 and E2, and a light emitter with low power consumption and low output due to a short resonance length of 200 μm or less can be realized. The configuration in which the first and second electrodes E1 and E2 are provided on one side of the chip generally has the demerit that the current path becomes long and the electrical resistance becomes large, but in the case of a short resonance length (low output) as in Example 1, this point hardly becomes a problem. And the merit that it is easy to mount on a submount or the like (flip chip mounting) is obtained.

[0035] The lower surface (back surface) of the base semiconductor portion 8 may include a region 8C where the surface roughness is locally increased (a surface roughened region where the surface is rougher than the surroundings). In the region 8C, at least one of convex portions and concave portions may be formed. For example, a plurality of raised portions having a random shape and a plurality of recesses having a random shape may be formed. The region 8C may be a region corresponding to the first portion B1 (for example, the central region). The region 8C may be formed so as not to overlap with the ridge portion RJ in plan view. The heat dissipation property may be enhanced by the region 8C. A dielectric film made of the same material as the mirror film UF may be formed on at least a part of the region 8C.

[0036] FIG. 8 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 8, for the first electrode E1, a region other than the first region L1 may overlap with the first portion B1 in plan view. Also, a region other than the first region L1 may be located on the insulating film DF.

[0037] FIGS. 9 and 10 are cross-sectional views showing another configuration of the light-emitting body of Example 1. As shown in FIGS. 9 and 10, the second electrode E2 located in the dug-out portion 9Q of the compound semiconductor portion may overlap with the first portion B1 of the base semiconductor portion 8 in plan view.

[0038] FIG. 11 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 11, the thickness of the second electrode E2 is larger than the thickness of the first electrode E1, and the upper surface levels of the first electrode E1 and the second electrode E2 may be aligned. The first electrode E1 and the second electrode E2 may be made of conductive materials having different materials.

[0039] FIG. 12 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 12, the compound semiconductor portion 9 has a bank portion BK, the ridge portion RJ and the bank portion BK have aligned upper surface levels, and a part of the second electrode E2 may be located on the bank portion BK. In plan view, the bank portion BK may overlap with the first portion B1 of the base semiconductor portion 8. In this way, mounting (flip chip mounting) on a submount or the like becomes easy. The structures (layer configurations) of the ridge portion RJ and the bank portion BK may be the same.

[0040] As shown in FIG. 12, the second electrode E2 may have a second region L2 located on the first-type semiconductor layer 9N and a third region L3 located on the second-type semiconductor layer 9P. The third region L3 may overlap with the first part B1 of the base semiconductor part 8 in a plan view.

[0041] FIG. 13 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 13, at least a part of the second electrode E2 may be located on the compound semiconductor part 9, specifically, on the first-type (n-type) semiconductor layer 9N of the compound semiconductor part 9.

[0042] FIG. 14 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 14, the entire second electrode E2 may be configured to overlap with the first part B1 in a plan view. Also, above each of the second part B2 and the third part B3 of the base semiconductor part 8, a first-type semiconductor layer 9N, an active layer 9K, a second-type semiconductor layer 9P (including the ridge part RJ), and a first electrode E1 may be provided. By providing ridge parts on both the second part B2 and the third part B3 in this way, the number of light-emitting bodies that can be taken out can be increased, or when made into one chip, the distance between the light-emitting points of the two can be reduced, the light integration density can be increased, and the optical design can be facilitated, or measures against speckle noise can be taken due to the difference in the wavelengths of the two.

[0043] FIG. 15 is a cross-sectional view showing another configuration of the light-emitting body of Example 1. As shown in FIG. 15, the first electrode E1 may be located on the semi-polar plane PJ of the second-type semiconductor layer 9P, and the second electrode E2 may be located on the semi-polar plane NJ of the first-type semiconductor layer 9N. The semi-polar plane is, for example, the r plane, which is inclined with respect to the polar plane, the c plane. Note that the first and second electrodes E1 and E2 may be provided on a non-polar plane (a plane, m plane) perpendicular to the c plane.

[0044] FIG. 16 is a perspective view showing another configuration of the light-emitting body of Example 1. FIG. 17 is a top view and a cross-sectional view of FIG. 16. In the example shown in FIGS. 16 and 17, the second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the second-type semiconductor layer 9P. In this way, the difference in the top surface level between the first electrode E1 and the third region L3 becomes small, making it easier to mount. In this case, the second electrode E2 may have a recess UB on its surface.

[0045] FIG. 18 is a perspective view showing another configuration of the light-emitting body of Example 1. FIG. 19 is a top view and a cross-sectional view of FIG. 18. In the example shown in FIGS. 18 and 19, the compound semiconductor portion 9 has a bank portion BK, and the ridge portion RJ and the bank portion BK have the same top surface level. The second electrode E2 has a second region L2 located on the first contact layer 9A and a third region L3 located on the bank BK. In this way, the top surface levels of the first electrode E1 and the third region L3 coincide, making it easier to mount. In this case, the second electrode E2 has a recess UB on its surface.

[0046] FIG. 18 shows a case where the removal of the second-type (p-type) semiconductor layer during ridge formation is performed only in the vicinity of the ridge. The second electrode E2 is made larger than the first electrode E1, and in particular, the area of the third region L3 is increased. The larger the area of the third region L3 (the larger the bonding area), the more firmly it can be bonded to the support substrate, and handling in subsequent processes becomes easier. Although an insulating film (such as silicon oxide or silicon nitride) exists beside the ridge portion RJ in contact with the first electrode E1, since the adhesive force between the metal and the insulating film is generally weak, electrode peeling may occur at that location during peeling from the growth substrate (described later). Therefore, it is better to increase the area of the third region L3 (the second electrode E2 at the location without the insulating film) rather than increasing the area of the first electrode E1. The shape of the first electrode E1 or the second electrode E2 may be a shape that can be used for alignment (positioning) during bonding (for example, a shape having an alignment mark).

[0047] Regarding the third region L3, since the contact resistance between the second electrode E2, which is the cathode, and the p-type semiconductor layer 9P is sufficiently high, no current flows and the two do not short-circuit.

[0048] FIG. 20 is a cross-sectional view showing the configuration of the light-emitting element according to the first embodiment. The light-emitting element 23 includes a light-emitting body 21 including a base semiconductor portion 8 and a compound semiconductor portion 9, and a support ST that holds the light-emitting body 21. Examples of the material of the support ST include Si, SiC, and AlN. The support ST is arranged such that the compound semiconductor portion 9 and the first and second electrodes E1 and E2 are positioned between the support ST and the base semiconductor portion 8. That is, the light-emitting body 21 is mounted on the support ST in a junction-down type.

[0049] The support ST includes a conductive first pad P1 and a second pad P2. The first electrode E1 is connected to the first pad P1 via a first junction A1, and the second electrode E2 is connected to the second pad P2 via a second junction A2. The second junction A2 is thicker than the first junction A1, and the difference in thickness between the first and second junctions A1 and A2 is equal to or greater than the thickness of the compound semiconductor portion 9. Thereby, the first and second electrodes E1 and E2 can be connected to the first and second pads P1 and P2 located in the same plane. That is, the light-emitting element 23 functions as a COS (Chip on Submount).

[0050] FIG. 21 is a perspective view showing the configuration of the light-emitting element according to Example 1. As shown in FIG. 21, the light-emitting element 23 includes a light-emitting body 21 and a support ST. The support ST has two wide portions SH having a width larger than the resonance length of the light-emitting body 21, and a mounting portion SB located between the two wide portions SH and having a width smaller than the resonance length. The light-emitting body 21 is located above the mounting portion SB such that the width direction (Y direction) of the mounting portion SB coincides with the direction of the resonance length, and in a plan view, a pair of resonance end faces F1 and F2 protrude from the mounting portion SB. In other words, the mounting portion SB is formed between two notch portions C1 and C2 facing each other in the direction (Y direction) defining the resonance length, the resonance end face F1 is located on the notch portion C1, and the resonance end face F2 is located on the notch portion C2. The shapes of the notch portions C1 and C2 can be, for example, rectangular in a plan view when viewed in the Z direction.

[0051] The support ST includes a T-shaped first pad P1 and a second pad P2. The first pad P1 includes a mounting portion J1 located on the wide portion SH and having a length in the Y direction larger than the resonance length K1, and a contact portion Q1 located on the mounting portion SB and having a length in the Y direction smaller than the resonance length K1. The second pad P2 includes a mounting portion J2 located on the wide portion SH and having a length in the Y direction larger than the resonance length K1, and a contact portion Q2 located on the mounting portion SB and having a length in the Y direction smaller than the resonance length K1. The contact portions Q1 and Q2 are arranged in the X direction on the upper surface of the mounting portion SB, a first bonding portion A1 is formed on the contact portion Q1, and a second bonding portion A2 is formed on the contact portion Q2. The first bonding portion A1 contacts the first electrode E1 of the light-emitting body 21, and the second bonding portion A2 contacts the second electrode E2 of the light-emitting body 21. As the materials of the first and second bonding portions A1 and A2, solders such as AuSi and AuSn can be used.

[0052] The resonance end faces F1 and F2 of the light-emitting body 21 are covered with a mirror film UF, but a dielectric film SF made of the same material as the mirror film UF may be formed on a surface (for example, the side surface of the mounting portion SB) of the support ST that is parallel to the resonance end faces F1 and F2.

[0053] FIG. 22 is a cross-sectional view showing another configuration of the light-emitting element according to Example 1. In FIG. 21, the cutout portions C1 and C2 are rectangular in a plan view when viewed in the Z direction, but the present invention is not limited to this. As shown in FIG. 22, the cutout portions C1 and C2 may be trapezoidal with the mounting portion SB side as the short side.

[0054] FIGS. 23 and 24 are cross-sectional views showing another configuration of the light-emitting element according to Example 1. In the light-emitting element 23 of FIG. 23, a plurality of light-emitting bodies 21 are arranged on a support ST in a direction (X direction) orthogonal to the direction defining the resonance length so that the directions of the resonance lengths are aligned, and first and second pads P1 and P2 may be provided corresponding to each light-emitting body 21. As shown in FIG. 24, an optical device such as a photodiode PD may be provided in the cutout portion C1 of the support ST. In this way, the light emission intensity of the light-emitting body 21 can be feedback-controlled.

[0055] FIG. 25 is a perspective view showing the configuration of a light-emitting substrate (semiconductor laser array) according to Example 1. The light-emitting substrate 22 includes a support substrate SK and a plurality of light-emitting bodies 21. In the light-emitting substrate 22, a plurality of light-emitting bodies 21 are arranged in a matrix in the direction (Y direction) defining the resonance length and the direction (X direction) orthogonal thereto so that the directions of the resonance lengths are aligned, and first and second pads P1 and P2 and first and second bonding portions A1 and A2 may be provided corresponding to each light-emitting body 21.

[0056] The support substrate SK can be formed, for example, by providing a plurality of recesses HL (rectangular in plan view) in a matrix on a Si substrate, a SiC substrate, etc., and providing a plurality of first pads P1, a plurality of second pads P2, a plurality of first bonding portions A1, and a plurality of second bonding portions A2 in the non-recessed portions.

[0057] FIG. 26 is a perspective view showing another configuration of the light-emitting substrate according to Example 1. A two-dimensional arrangement type light-emitting substrate in which a plurality of light-emitting bodies 21 are arranged in a matrix as shown in FIG. 25 can be divided horizontally (divided row by row extending in the X direction) to form a one-dimensional arrangement type (bar-shaped) light-emitting substrate 22 as shown in FIG. 26. By adopting the one-dimensional arrangement type, it becomes easy to form the mirror film UF on the pair of resonant end faces F1 and F2.

[0058] (Manufacturing Method) FIG. 27 is a flowchart showing an example of a method for manufacturing a light-emitting device according to Example 1. FIG. 28 is a schematic cross-sectional view showing the manufacturing method of the light-emitting device of FIG. 27. FIG. 29 is a plan view showing the manufacturing method of the light-emitting device of FIG. 27. In the manufacturing method shown in FIGS. 27 to 29, a step of preparing a template substrate 7 including a lower base substrate UK and a mask layer 6, a step of forming a first semiconductor layer S1 (and a third semiconductor layer S3) that becomes the base semiconductor portion 8 by the ELO method (described later), a step of forming a second semiconductor layer S2 (and a fourth semiconductor layer S4) that becomes the compound semiconductor portion 9, a step of forming a laminate LB having the first semiconductor layer S1, the second semiconductor layer S2 including a ridge portion, and the first electrode E1 and the second electrode E2, etc., a step of bonding the laminate LB to a support substrate SK and separating the first semiconductor layer S1 from the template substrate 7, a step of cleaving the laminate LB on the support substrate SK to form a pair of resonant end faces F1·F2 (including an optical resonator LK), a step of forming a mirror film UF on each of the pair of resonant end faces F1·F2, and a step of dividing the support substrate SK into a plurality of supports ST.

[0059] After forming the laminate LB, the mask layer 6 is etched away, and the laminate LB is bonded to the support substrate SK in a state where the first and second joints A1 and A2 (e.g., solder) of the support substrate SK are heated and melted. As a result, the joint (lower protruding portion) of the back surface of the first semiconductor layer S1 with the underlying substrate UK breaks, and the first semiconductor layer S1 separates from the template substrate 7. Thereafter, on the support substrate SK, cleavage of the laminate LB (m-plane cleavage of the first and second semiconductor layers S1 and S2 which are nitride semiconductor layers) is performed to form a pair of resonant end faces F1 and F2. Thereby, a two-dimensional arrangement type light-emitting substrate 22 (see FIG. 25) is formed. Next, the two-dimensional arrangement type light-emitting substrate is divided row by row to form a one-dimensional arrangement type (rod-shaped) light-emitting substrate 22 (see FIG. 26). Next, a mirror film UF is formed on the resonant end faces F1 and F2 of the one-dimensional arrangement type light-emitting substrate 22. Thereafter, the support substrate SK is divided into a plurality of supports ST, and one or more light emitters 21 are held on each support ST to form a plurality of light-emitting elements 23. The mirror film UF (e.g., a dielectric film) may be formed not only on the cleavage planes (m-planes) of the base semiconductor portion 8 and the compound semiconductor portion 9 but also on the surfaces of the side faces of the support ST that are parallel to the resonant end faces F1 and F2 (including the side faces of the mounting portion SB).

[0060] FIGS. 30 and 31 are schematic cross-sectional views showing another example of a method for manufacturing a light-emitting device according to Example 1. As shown in FIG. 30, a plurality of one-dimensional arrangement type light-emitting substrates 22 (see FIG. 26) can be stacked in the Z direction such that the back surfaces of the base semiconductor portions 8 face each other, and a mirror film UF can be simultaneously formed on the resonant end faces F1 and F2 of each light-emitting substrate 22. Also, as shown in FIG. 31, when the support substrate SK is divided into a plurality of supports ST, the light-emitting elements 23 shown in FIG. 23 and the like can be formed by holding a plurality of light emitters 21 on each support ST.

[0061] (Base semiconductor portion) FIG. 32 is a cross-sectional view showing an example of the lateral growth of the base semiconductor part (ELO semiconductor layer) in Example 1. As shown in FIG. 32, the lower base substrate UK includes the main substrate 1 and the underlying layer 4 on the main substrate 1, and the seed layer 3, which is the surface layer of the underlying layer 4, is exposed from the opening K of the mask part 5. In the ELO method, first, an initial growth layer SL is formed on the seed layer 3, and then the first semiconductor layer S1 can be laterally grown from the initial growth layer SL. The initial growth layer SL is the starting point of the lateral growth of the first semiconductor layer S1 and is a part of the first part B1 of the base semiconductor part 8. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first semiconductor layer S1 in the Z direction (c-axis direction) or in the X direction (a-axis direction).

[0062] Here, the film formation of the initial growth layer SL can be stopped at the timing immediately before the edge of the initial growth layer SL rides on the upper surface of the mask part 5 (the stage in contact with the upper end of the side surface of the mask part 5) or immediately after riding on the upper surface of the mask part 5 (that is, at this timing, the ELO film formation conditions are switched from the c-axis direction film formation conditions to the a-axis direction film formation conditions). In this way, since the lateral film formation is performed from the state where the initial growth layer SL slightly protrudes from the mask part 5, it becomes difficult for the material to be consumed in the growth in the thickness direction of the first semiconductor layer S1, and the first semiconductor layer S1 can be laterally grown at high speed. The initial growth layer SL may be formed, for example, to have a thickness of 2.0 μm or more and 3.0 μm or less.

[0063] In Example 1, the first semiconductor layer S1 that becomes the base semiconductor part 8 was an n-type GaN layer, and ELO film formation of Si-doped GaN (gallium nitride) was performed on the template substrate 7 using an MOCVD apparatus. As an example of the ELO film formation conditions, a substrate temperature of 1120°C, a growth pressure of 50 kPa, TMG (trimethylgallium) of 22 sccm, NH3 of 15 slm, and V / III = 6000 (the ratio of the supply amount of group V raw materials to the supply amount of group III raw materials) can be adopted. Note that the lateral growth of the first and third semiconductor layers S1 and S3 that laterally grow from both sides on the mask part 5 was stopped before they met.

[0064] The width of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the lateral width of the first semiconductor layer S1 was 53 μm, the widths (X-direction sizes) of the low-defect portions B2 and B3 were 24 μm, and the layer thickness of the first semiconductor layer S1 was 5 μm. The aspect ratio of the first semiconductor layer S1 was 53 μm / 5 μm = 10.6, achieving a high aspect ratio.

[0065] For the main substrate 1 in FIG. 32, a different substrate having a lattice constant different from that of the nitride semiconductor can be used. Examples of the different substrate include a single-crystalline silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The plane orientation of the main substrate 1 is, for example, the (111) plane of the silicon substrate, the (0001) plane of the sapphire substrate, or the 6H-SiC(0001) plane of the SiC substrate.

[0066] As the underlying layer 4 in FIG. 32, a buffer layer 2 and a seed layer 3 can be provided in this order from the main substrate 1 side. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed layer 3, since both (the main substrate and the seed layer) melt together, for example, by providing a buffer layer 2 including at least one of an AlN layer and a SiC (silicon carbide) layer, the melting is reduced. The buffer layer 2 may have at least one of the effect of enhancing the crystallinity of the seed layer 3 and the effect of relaxing the internal stress of the first semiconductor layer S1. When a main substrate 1 that does not melt with the seed layer 3 is used, a configuration without providing the buffer layer 2 is also possible. Note that, as shown in FIG. 32, the configuration is not limited to the case where the seed layer 3 overlaps the entire mask portion 5. Since the seed layer 3 only needs to be exposed from the opening K, the seed layer 3 may be locally formed so as not to overlap a part or all of the mask portion 5.

[0067] The opening K of the mask layer 6 has the function of a growth start hole that exposes the seed layer 3 and starts the growth of the first semiconductor layer S1, and the mask portion 5 of the mask layer 6 has the function of a selective growth mask that laterally grows the first semiconductor layer S1. The mask layer 6 may be a mask pattern including the mask portion 5 and the opening K.

[0068] As the mask layer 6, for example, a single-layer film including any one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (for example, 1000 °C or higher), or a laminated film including at least two of these can be used.

[0069] For example, on the underlying layer 4, a silicon oxide film with a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed over the entire surface using a sputtering method, and a resist is applied over the entire surface of the silicon oxide film. Then, the resist is patterned using a photolithography method to form a resist having a plurality of stripe-shaped openings. Then, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to form the mask layer 6.

[0070] The openings K are in a longitudinal shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor layer S1. The width of the openings K is set to about 0.1 μm to 20 μm. The smaller the width of each opening, the smaller the number of through dislocations propagating from each opening to the first semiconductor layer S1. Also, the width (size in the X direction) of the low defect portions B2 and B3 can be increased.

[0071] Although the silicon oxide film may decompose and evaporate slightly during the formation of the ELO semiconductor layer and be incorporated into the ELO semiconductor layer, silicon nitride films and silicon oxynitride films have the advantage of being difficult to decompose and evaporate at high temperatures.

[0072] Therefore, the mask layer 6 may be a single-layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film formed by sequentially forming a silicon oxide film and a silicon nitride film on the underlying layer 4, or may be a laminated body film formed by sequentially forming a silicon nitride film and a silicon oxide film on the underlying layer 4, or may be a laminated film formed by sequentially forming a silicon nitride film, a silicon oxide film, and a silicon nitride film on the underlying layer.

[0073] When forming the base semiconductor part 8 using the ELO method, a template substrate 7 including the main substrate 1 and the mask layer 6 (mask pattern) on the main substrate 1 may be used. The template substrate 7 may have a growth suppression region corresponding to the mask part 5 (for example, a region that suppresses crystal growth in the Z direction) and a seed region corresponding to the opening K. For example, a growth suppression region and a seed region may be formed on the main substrate 1, and the base semiconductor part 8 may be formed on the growth suppression region and the seed region using the ELO method.

[0074] (Compound semiconductor part, etc.) The compound semiconductor part 9 can be formed, for example, using a MOCVD apparatus. For the first contact layer 9A, for example, an n-type GaN layer can be used, for the first cladding layer 9B, for example, an n-type AlGaN layer can be used, for the first optical guide layer 9C, for example, an n-type GaN layer can be used, for the active layer 9K, for example, a MQW (Multi-Quantum Well) structure including an InGaN layer can be used, for the electron blocking layer 9D, for example, a p-type AlGaN layer can be used, for the second optical guide layer 9E, for example, a p-type GaN layer can be used, for the second cladding layer 9F, for example, a p-type AlGaN layer can be used, and for the second contact layer 9G, for example, a p-type GaN layer can be used.

[0075] Regarding the thickness of each layer of the light emitter 21, it can be such that the base semiconductor part 8 > the first cladding layer 9B > the first optical guide layer 9C > the active layer 9K, and the base semiconductor part 8 > the second cladding layer 9F > the second optical guide layer 9E > the active layer 9K. Also, regarding the refractive index of each layer of the compound semiconductor part 9 (the refractive index of the light generated in the active layer 9K), it can be such that the first cladding layer 9B < the first optical guide layer 9C < the active layer 9K, and the insulating film DF < the second cladding layer 9F < the second optical guide layer 9E < the active layer 9K.

[0076] For the first and second electrodes E1 and E2 and the first and second pads P1 and P2, a single-layer film or a multilayer film including at least one of metal films (which may be alloy films) containing at least one of Ni, Rh, Pd, Cr, Au, W, Pt, Ti, and Al and at least one of conductive oxide films containing at least one of Zn, In, and Sn can be used. For the insulating film DF covering the ridge portion RJ, a single-layer film or a laminated film including, for example, oxides or nitrides of Si, Al, Zr, Ti, Nb, and Ta can be used.

[0077] The first semiconductor layer S1 (ELO semiconductor layer) that forms the base semiconductor portion 8 and the second semiconductor layer S2 that forms the compound semiconductor portion 9 can also be continuously formed using the same film-forming apparatus (for example, an MOCVD apparatus). The intermediate substrate in the state where the first semiconductor layer S1 is formed can be taken out of the film-forming apparatus once, and the second semiconductor layer S2 can be formed on the first semiconductor layer S1 by another apparatus. In this case, an n-type GaN layer (for example, about 0.1 μm to about 3 μm thick) serving as a buffer during regrowth may be formed on the first semiconductor layer S1, and then the second semiconductor layer S2 may be formed.

[0078] Examples of the material for the mirror film UF covering the resonant end faces F1 and F2 include dielectrics such as SiO2, Al2O3, AlN, AlON, Nb2O5, Ta2O5, and ZrO2. The mirror film UF may be a multilayer film. The mirror film UF can be formed by electron beam evaporation, electron cyclotron resonance sputtering, chemical vapor deposition, or the like.

[0079] In Example 1, silicon substrates can be used for the main substrate 1 used for the ELO of the base semiconductor portion 8, and the support substrate SK and the support ST, respectively. By doing so, it is difficult for bonding defects to occur due to the difference in thermal expansion coefficient during bonding, and there are also advantages in terms of large diameter, heat dissipation, workability, and cost.

[0080] Since the light-emitting body 21 has a structure in which the first and second electrodes E1 and E2 are provided on one side (one-sided electrode structure), the surface of the first-type semiconductor layer 9N connected to the second electrode E2 and the surface of the second-type semiconductor layer 9P connected to the first electrode E1 can both be the (0001) plane (c-plane) of the GaN-based semiconductor. In a GaN-based semiconductor laser, when the crystal growth substrate (for example, a GaN substrate) is conductive, the semiconductor layer is fabricated such that the surface is the (0001) plane, and the contact surface of the anode is the (0001) plane and the contact surface of the cathode is the back surface of the crystal growth substrate, that is, a double-sided electrode structure with the (000-1) plane is generally adopted. With a one-sided electrode structure, current flows horizontally between the anode and the cathode, and the current becomes non-uniform within the ridge portion (ridge waveguide), causing the threshold current to increase, or the current path becomes longer than that of the double-sided electrode structure, causing the driving voltage to increase. Therefore, the one-sided electrode structure of the GaN-based semiconductor laser has conventionally been used only when the crystal growth substrate is insulating and an electrode cannot be formed on the back surface side (for example, a sapphire substrate). It is known that the contact resistance becomes higher when the (000-1) plane is used as the connection surface of the cathode compared to when the (0001) plane is used as the connection surface of the cathode. Therefore, a process such as etching the (000-1) plane of the crystal growth substrate is added to expose various planes on the surface.

[0081] In Example 1, even when the crystal growth substrate (main substrate) is conductive or the main substrate is removed and the conductive base semiconductor portion is located on the back surface side, enabling a double-sided electrode structure, there are merits to using a one-sided electrode structure. At short resonance lengths, the driving current is originally small, and in applications such as AR (augmented reality) glasses that do not require high optical output and operate near the threshold current, the increase in series resistance that causes a voltage increase according to the current value is not a major problem. On the other hand, by using the (0001) plane as the connection surface of the cathode, the merit of reduced contact resistance (lower power consumption) is obtained, and furthermore, mounting on the submount (support substrate SK, etc.) becomes easier.

[0082] 〔Example 2〕 FIG. 33 is a cross-sectional view showing the configuration of the light-emitting body according to Example 2. The light-emitting body 21 includes a base semiconductor portion 8, a compound semiconductor portion 9 located on the base semiconductor portion 8, a first electrode E1 that is an anode, and a second electrode E2 that is a cathode. The light-emitting body 21 can also be referred to as an LED (light-emitting diode) chip. The compound semiconductor portion 9 is formed by sequentially forming a first-type (n-type) semiconductor layer 9N having a donor, an active layer 9K, and a second-type (p-type) semiconductor layer 9P having an acceptor. At least a part of the first electrode E1 is located on the (0001) plane of the second-type semiconductor layer 9P, and at least a part of the second electrode E2 is located on the (0001) plane of the first-type semiconductor layer 9N.

[0083] In a plan view, the entire first electrode E1 overlaps with the second portion B2 (low dislocation portion) of the base semiconductor portion 8 (the first electrode E1 does not overlap with the first portion B1). In this way, the current path from the first electrode E1 through the active layer 9K to the first-type semiconductor layer 9N is formed in a portion (low dislocation portion) that overlaps with the second portion B2 in a plan view, and the light emission efficiency in the active layer 9K is increased.

[0084] 〔Example 3〕 In Examples 1 and 2, the base semiconductor portion 8 (ELO semiconductor layer) can be a GaN layer, but it is not limited thereto. As the ELO semiconductor layer, an InGaN layer which is a GaN-based semiconductor layer can also be formed. The lateral film formation of the InGaN layer is performed at a low temperature, for example, below 1000 °C. This is because the vapor pressure of indium becomes high at high temperatures and it cannot be effectively incorporated into the film. By reducing the film formation temperature to a low temperature, there is an effect of reducing the interaction between the mask portion 5 and the InGaN layer. Also, the InGaN layer has an effect that its reactivity with the mask portion 5 is lower than that of the GaN layer. When indium is incorporated into the InGaN layer at an In composition level of 1% or more, the reactivity with the mask portion 5 further decreases. As the gallium source gas, triethylgallium (TEG) can be used.

[0085] 〔Example 4〕 FIG. 34 is a perspective view showing the configuration of the light-emitting module of Example 4. The light-emitting module 24 (light-emitting device) in FIG. 34 is a surface-mount type package, and includes a housing 35 and a light-emitting element 23 (see, for example, FIG. 23). The light-emitting element 23 includes a plurality of light emitters 21, and is provided such that the side surface of the support ST (a plane parallel to the resonant end face) faces the bottom surface 37 of the housing 35. For this reason, the emission surface (the resonant end face on the emission side) of each light emitter 21 faces the top surface 34 (transparent plate) of the housing 35, and laser light is emitted from the top surface 34 of the housing 35. The light-emitting element 23 is connected to an external connection pin 33 via a wire 31.

[0086] FIG. 35 is a perspective view showing another configuration of the light-emitting module of Example 4. The light-emitting module 24 in FIG. 35 is a TO-CAN mount type package, and includes a stem 38 and a light-emitting element 23 (see, for example, FIG. 21). The light-emitting element 23 is disposed on a heat block 36 protruding from the base of the stem 38. The first and second pads P1 and P2 of the light-emitting element 23 are connected to an external connection pin 33 via a wire 31.

[0087] In the prior art, it was necessary to individually die-bond a semiconductor laser chip to a submount to fabricate a CoS (Chip on Submount). However, in Examples 1 to 4, since the support ST of the light-emitting element 23 functions as a submount and the light-emitting element 23 itself has a CoS structure, die-bonding to the submount becomes unnecessary. Thereby, it is possible to solve the problem of the difficulty of handling when the resonance length is short or the chip width is narrow. Specifically, the light-emitting element 23 has first and second pads P1 and P2 that satisfy the size conditions required for wire bonding on the support ST. Since these first and second pads P1 and P2 are electrically connected to the first and second electrodes (anode and cathode) of the light emitter 21 (semiconductor laser chip), it is sufficient to electrically connect the external connection pin 33 of the package and the first and second pads P1 and P2 with a wire 31.

[0088] 〔Example 5〕 FIG. 36 is a schematic diagram showing the configuration of the electronic device according to Example 5. The electronic device 50 in FIG. 36 includes the light-emitting devices GD (21 to 24) described in Examples 1 to 4 and a control unit 80 that includes a processor and controls the light-emitting devices GD. Examples of the electronic device 50 include a lighting device, a display device, a communication device, an information processing device, a medical device, an electric vehicle (EV), and the like.

[0089] The above technical forms are for illustrative and explanatory purposes and not for limiting purposes. Based on these illustrations and explanations, it is obvious to those skilled in the art that many variations are possible.

[0090] 〔Supplementary Notes〕 As described above, the invention according to the present disclosure has been described based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments. That is, the invention according to the present disclosure can be variously modified within the scope shown in the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that those skilled in the art can easily make various modifications or corrections based on the present disclosure. Also, note that these modifications or corrections are included in the scope of the present disclosure.

Explanation of Reference Numerals

[0091] 7 Template substrate 8 Base semiconductor part 9 Compound semiconductor part 21 Light emitter (light-emitting device) 22 Light-emitting substrate (light-emitting device) 23 Light-emitting element (light-emitting device) 24 Light-emitting module (light-emitting device) S1 First semiconductor layer S2 Second semiconductor layer LK Optical resonator RJ Ridge part B1 First part B2 Second part (low dislocation part) B2 Third part (low dislocation part) A pair of resonant end faces F1·F2 Pad P1 Pad P2 Electrode E1 Electrode E2 Reflection mirror film UF Support ST Mounting portion SB Support substrate SK

Claims

1. A step of preparing a semiconductor substrate comprising: an underlying substrate; a plurality of mask portions located on the underlying substrate; and a base semiconductor portion extending from a region of an upper surface of the underlying substrate that is exposed between the plurality of mask portions, the base semiconductor portion comprising a first portion extending upward from the exposed region and a second portion extending from the first portion onto one or more of the plurality of mask portions; forming a compound semiconductor portion on the base semiconductor portion; forming a first electrode and a second electrode above the base semiconductor portion such that at least a portion of the first electrode is located above the second portion; Providing a support substrate having a first pad and a second pad; bonding a stack including the base semiconductor portion, the compound semiconductor portion, the first electrode, and the second electrode to a support substrate while connecting the first electrode and the first pad and while connecting the second electrode and the second pad, and isolating the base semiconductor portion from the underlying substrate.

2. The method of claim 1 , wherein the threading dislocation density of the second portion is equal to or less than ⅕ of the threading dislocation density of the first portion.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion.

4. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion on the base substrate prior to the step of isolating.

5. The method for manufacturing a semiconductor device according to claim 3 , further comprising the steps of: dividing the base semiconductor portion and the compound semiconductor portion to form resonator facets of the semiconductor device.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the base semiconductor portion includes a nitride semiconductor, and the base semiconductor portion has an elongated shape whose longitudinal direction is in a <1-100> direction of the nitride semiconductor.

7. the base semiconductor portion and the compound semiconductor portion include nitride semiconductors, 6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion so as to produce a cross section along an m-plane of the nitride semiconductor.

8. the base semiconductor portion and the compound semiconductor portion include nitride semiconductors, 6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of dividing the base semiconductor portion and the compound semiconductor portion on the base substrate so as to produce a cross section along an m-plane of the nitride semiconductor, prior to the step of separating.

9. 9. The method for manufacturing a semiconductor element according to claim 1, wherein the first electrode and the second electrode are formed such that at least a portion of the first electrode and at least a portion of the second electrode are located on a (0001) plane of the compound semiconductor portion.

10. The plurality of mask portions are arranged in a first direction, The method for manufacturing a semiconductor element according to claim 1 , wherein the first electrode and the second electrode are aligned in the first direction in a plan view.

11. The plurality of mask portions are arranged in a first direction, 9. The method for manufacturing a semiconductor element according to claim 1, wherein the first electrode has a longitudinal direction in a second direction perpendicular to the first direction.

12. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in this order.

13. the first electrode is in contact with a (0001) plane of the p-type semiconductor layer; The method for manufacturing a semiconductor device according to claim 12 , wherein the second electrode is in contact with a (0001) plane of the n-type semiconductor layer.

14. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the first electrode is an anode and the second electrode is a cathode.

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