Semiconductor Devices

Abstract

To reduce power consumption in a driving circuit by reducing a driving voltage of the driving circuit.SOLUTION: An amplitude voltage of a signal IN1 can be increased and output by a level shifter circuit. Specifically, the amplitude voltage of the signal IN1 can be made high and output. Thus, an amplitude voltage of a circuit (shift register circuit, decoder circuit, etc.) outputting the signal IN can be reduced. Therefore, power consumption of the circuit can be reduced. In addition, a voltage applied to a transistor included in the circuit can be reduced, which can thus inhibit the transistor from deteriorating or be broken.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to semiconductor devices and methods for driving them. In particular, a semiconductor device having a drive circuit formed on the same substrate as a pixel portion, a display device, a liquid crystal display device, a light-emitting device, or a method for driving them. Or an electronic device having the semiconductor device, the display device, the liquid crystal display device, or the light-emitting device.

Background Art

[0002] In recent years, the development of large display devices such as liquid crystal televisions has been actively promoted. In particular, a technique of forming a drive circuit such as a gate driver circuit on the same substrate as a pixel portion using a transistor having a non-single crystal semiconductor greatly contributes to cost reduction and reliability improvement in manufacturing, and thus development has been actively promoted (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004]

[0005] In view of the above problems, one aspect of the present invention aims to reduce the driving voltage of the driving circuit and achieve low power consumption of the driving circuit. This is the problem to be solved.

Means for Solving the Problems

[0006] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the first transistor is electrically connected to the first wiring, the second terminal of the first transistor is electrically connected to the second wiring, the first terminal of the second transistor is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to the first wiring, the second terminal of the third transistor is electrically connected to the gate of the first transistor, the gate of the third transistor is electrically connected to the fourth wiring, the first terminal of the fourth transistor is electrically connected to the third wiring, the second terminal of the fourth transistor is electrically connected to the gate of the first transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, the first terminal of the fifth transistor is electrically connected to the fifth wiring, the second terminal of the fifth transistor is electrically connected to the gate of the second transistor, the gate of the fifth transistor is electrically connected to the sixth wiring, the first terminal of the sixth transistor is electrically connected to the third wiring, the second terminal of the sixth transistor is electrically connected to the gate of the second transistor, and the gate of the sixth transistor is electrically connected to the fourth wiring.

[0007] In one aspect of the present invention, a first signal is input to the fourth wiring, and from the second wiring, a second signal is output, and the amplitude voltage of the second signal is greater than half of the amplitude voltage of the first signal and it may be a semiconductor device.

[0008] In one aspect of the present invention, the first signal is a digital signal, the second signal is a digital signal and when the first signal is at the H level, the second signal becomes the H level, and when the first signal is at the L level, the second signal may be a semiconductor device that becomes the L level.

[0009] In one aspect of the present invention, the fourth wiring may be a semiconductor device electrically connected to a shift register circuit.

[0010] Note that in the figures, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0011] Note that the figures schematically show ideal examples and are not limited to the shapes or values shown in the figures. For example, it may include variations in shape due to manufacturing technology, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0012] Note that technical terms are often used for the purpose of describing specific embodiments. However, one aspect of the present invention is not limitedly interpreted by technical terms.

[0013] Note that terms not defined (including scientific and technical terms such as technical terms or academic terms) are ​​​It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. Dictionaries, etc. The words defined by are preferably interpreted in a meaning that does not conflict with the background of the related art.

Advantages of the Invention

[0014] One aspect of the present invention can reduce the driving voltage of the drive circuit and achieve low power consumption.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the description of the embodiments of the present invention should not be construed as being limited to the described content. In the configurations described below, the same parts or parts having the same functions are denoted by common reference numerals in different drawings, and detailed descriptions of the same parts or parts having the same functions are omitted.

[0017] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with the content described in another embodiment (even part of the content) described in that embodiment and / or the content described in one or more other embodiments (even part of the content). Note that the terms such as first, second, and third are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, the terms first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc. Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with the content described in another embodiment (even part of the content) described in that embodiment and / or the content described in one or more other embodiments (even part of the content). Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with the content described in another embodiment (even part of the content) described in that embodiment and / or the content described in one or more other embodiments (even part of the content).

[0018] Note that the terms such as first, second, third, etc. are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, the terms first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc. Note that the terms such as first, second, third, etc. are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, the terms first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc. Note that the terms such as first, second, third, etc. are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, the terms first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc. Note that the terms such as first, second, third, etc. are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, the terms first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc.

[0019] (Embodiment 1) In this embodiment, an example of a semiconductor device and an example of a driving method for the semiconductor device will be described. In particular, an example of a level shifter circuit and an example of a driving method for the level shifter circuit will be described. In this embodiment, an example of a semiconductor device and an example of a driving method for the semiconductor device will be described. In particular, an example of a level shifter circuit and an example of a driving method for the level shifter circuit will be described. In this embodiment, an example of a semiconductor device and an example of a driving method for the semiconductor device will be described. In particular, an example of a level shifter circuit and an example of a driving method for the level shifter circuit will be described.

[0020] First, an example of the semiconductor device of this embodiment will be described.

[0021] FIG. 1 shows an example of a semiconductor device. Assume that circuit 100 has circuits 110 and 120. Circuit 110 is connected to wiring 11, wiring 13, wiring 14, wiring 16, and circuit 120. Circuit 120 is connected to wiring 11, wiring 12, wiring 15, wiring 16, and circuit 110. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations. FIG. 1 shows an example of a semiconductor device. Assume that circuit 100 has circuits 110 and 120. Circuit 110 is connected to wiring 11, wiring 13, wiring 14, wiring 16, and circuit 120. Circuit 120 is connected to wiring 11, wiring 12, wiring 15, wiring 16, and circuit 110. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations. FIG. 1 shows an example of a semiconductor device. Assume that circuit 100 has circuits 110 and 120. Circuit 110 is connected to wiring 11, wiring 13, wiring 14, wiring 16, and circuit 120. Circuit 120 is connected to wiring 11, wiring 12, wiring 15, wiring 16, and circuit 110. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations. However, an example of this embodiment is not limited to this. For example, circuit 100, circuit 110, and circuit 120 can be connected to various wirings according to their configurations.

[0022] The circuit 110 is assumed to include a transistor 111 and a transistor 112. Circuit 1 20 is assumed to include a transistor 121, a transistor 122, a transistor 123, and a transistor 124. The first terminal of the transistor 121 is connected to the wiring 15 , and the second terminal of the transistor 121 is connected to the wiring 12. The first terminal of the transistor 122 is connected to the wiring 16, and the second terminal of the transistor 122 is connected to the wiring 12 . The first terminal of the transistor 123 is connected to the wiring 15, and the second terminal of the transistor 123 is connected to the gate of the transistor 121, and the gate of the transistor 123 is connected to the wiring 11. The first terminal of the transistor 124 is connected to the wiring 16, and the second terminal of the transistor 124 is connected to the gate of the transistor 121, and the gate of the transistor 124 is connected to the gate of the transistor 122. The first terminal of the transistor 111 is connected to the wiring 14, and the second terminal of the transistor 111 is connected to the gate of the transistor 122, and the gate of the transistor 111 is connected to the wiring 13. The first terminal of the transistor 112 is connected to the wiring 16, and the second terminal of the transistor 112 is connected to the gate of the transistor 122, and the gate of the transistor 112 is connected to the wiring 11.

[0023] Note that the connection point of the second terminal of the transistor 111, the second terminal of the transistor 112, the gate of the transistor 122, and the gate of the transistor 124 is denoted as node A. The connection point of the gate of the transistor 121, the second terminal of the transistor 123, and the second terminal of the transistor 124 is denoted as node B. ​​

[0024] The transistors 111, 112, and 121 to 124 are The N-channel transistor has a potential between the gate and the source. When the difference becomes larger than the threshold voltage, the transistor is turned on. The device is a transistor using an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, or the like. In particular, the transistor can be formed using an oxide semiconductor. It is preferable to configure the semiconductor device of the present embodiment because the semiconductor layer is made of an oxide. This is because the mobility of the transistor can be increased by using a compound semiconductor. Therefore, the semiconductor device of this embodiment can be used for a display device with high resolution or a large display device. However, the present embodiment is not limited to this. The transistor 111, the transistor 112, and the transistors 121 to 124 are all P-channel A P-channel transistor can have a negative charge between the gate and source. It is assumed that the transistor turns on when the potential difference falls below the threshold voltage.

[0025] A transistor is defined as an element having at least three terminals including a gate, a drain, and a source. The drain (drain region or drain electrode) and the source ( The drain and the channel region are connected to each other. A current can flow through the source and the drain. Since it depends on the transistor structure or operating conditions, it is unclear which is the source or drain. Therefore, it is difficult to determine whether the source is a A portion that functions as a drain may not be referred to as a source or a drain. In that case, as an example, one of the source and the drain may be denoted as a first terminal, a first electrode, or a first region, and the other of the source and the drain may be denoted as a second terminal, a second electrode, or a second region.

[0026] Note that when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and includes those other than the connection relationship shown in the figure or the text.

[0027] It is assumed that a voltage VDD1 is input to the wiring 14. The voltage VDD1 is a constant voltage and has a value greater than the ground voltage. Therefore, the wiring 14 is assumed to have a function as a power supply line or a positive power supply line. It is assumed that a voltage VDD2 is input to the wiring 15. The voltage VDD2 is a constant voltage and has a value greater than the voltage VDD1. Therefore, the wiring 15 is assumed to have a function as a power supply line or a positive power supply line. It is assumed that a voltage VSS is supplied to the wiring 16. The voltage VSS is a constant voltage and has a value smaller than the voltage VDD1. Therefore, the wiring 16 is assumed to have a function as a power supply line or a negative power supply line. However, an example of this embodiment is not limited to this. For example, a signal can be input to the wiring 14, the wiring 15, and / or the wiring 16. In such a case, the wiring 14, ​​​​​​​​​ Wiring 15 and / or wiring 16 can function as signal lines. Another example is that the voltage VSS can be approximately equal to the ground voltage. Therefore, the wiring 16 can function as a ground line or an earth, etc.

[0028] Assume that a signal IN1 is input to the wiring 11. The signal IN1 is a digital signal . The potential of the H level of the signal IN1 is approximately VDD1, and the potential of the L level of the signal IN1 is approximately VSS. Therefore, the wiring 11 is assumed to have a function as a signal line . Assume that a signal IN2 is input to the wiring 13. The signal IN2 is a digital signal . The potential of the H level of the signal IN2 is approximately VDD1, and the signal The potential of the L level of IN2 is approximately VSS. Therefore, the wiring 13 is assumed to have a function as a signal line when considered. However, an example of this embodiment is not limited to this. For example , a voltage (for example, voltage VDD1 or voltage VDD2) can be input to the wiring 13. As a result, the signal IN2 can be omitted, so that the number of signals and the number of wirings can be reduced. Furthermore, power consumption can be reduced.

[0029] Assume that a signal OUT is output from the wiring 12. The signal OUT is a digital signal and is the output signal of the circuit 100. The potential of the H level of the signal OUT is approximately VD D2, and the potential of the L level of the signal OUT is approximately VSS. That is, it is assumed that the amplitude voltage of the signal OU T is larger than the amplitude voltage of the signal IN1. Therefore, the wiring 12 is assumed to have a function as a signal line .

[0030] Next, an example of the operation of the semiconductor device according to this embodiment will be described.

[0031] FIG. 2 is an example of a diagram for explaining the operation of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment can realize the first to fourth operations by combining the H level and L level of signal IN1 and signal IN2. The first to fourth operations will be described. However, an example of this embodiment is not limited thereto. For example, by changing the potential of wiring 14, wiring 15, and / or wiring 16, the semiconductor device according to this embodiment can perform more operations.

[0032] First, the first operation will be described (see FIG. 3(A)). In the first operation, signal IN1 becomes the H level, and signal IN2 becomes the L level. Therefore, transistor 111 turns off, and transistor 112 turns on, so that node A is in conduction with wiring 16. Then, since the potential of wiring 16 (voltage VSS) is supplied to node A, the potential of node A (denoted as potential Va) is approximately VSS. Therefore, transistor 124 turns off. At this time, since transistor 123 turns on, node B is in conduction with wiring 15. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to node B, the potential of node B (denoted as potential Vb) starts to rise. After that, when the potential of node B becomes VSS + Vth121 (Vth121: threshold voltage of transistor 121), transistor 121 turns on. At this time, since transistor 122 turns off, wiring 12 is in conduction with wiring 15. Then, the potential of wiring 15 (for example, voltage VDD2) is supplied to wiring 12, so that the potential of wiring 12 becomes the potential of wiring 15. Since the voltage VDD2 is supplied, the potential of wiring 12 (signal OUT) starts to rise. Then after that, the potentials of node B and wiring 12 continue to rise. Eventually, the potential of node B becomes a value obtained by subtracting the threshold voltage (Vth123) of transistor 123 from the potential (voltage VDD1) of the gate of transistor 123. Then, transistor 123 turns off so that wiring 15 and node B become non-conductive. Therefore, node B becomes a floating state . At this time, the potential of wiring 12 continues to rise. Therefore, due to the parasitic capacitance between the gate and the second terminal of transistor 121, the potential of node B further rises from VDD1 - Vth123 . Eventually, the potential of node B becomes VDD2 + Vth121 + V1 (V1 : a positive number). This is a so-called bootstrap operation. Therefore, the potential of wiring 12 can rise to VDD2. In this way, signal OUT becomes the H level . Next, the second operation will be described (see Fig. 3(B)). In the second operation, signal IN1 becomes the L level and signal IN2 becomes the H level. Therefore, transistor 111 turns on

[0033] and transistor 112 turns off, so that node A becomes conductive with wiring 14. Then, since the potential (voltage VDD1) of wiring 14 is supplied to node A, the potential of node A rises. After that, the potential of node A becomes a value obtained by subtracting the threshold voltage (Vth111) of transistor 111 from the potential (H-level signal IN2) of the gate of transistor 111 (VD D1 - Vth111). Then, transistor 111 turns off and wiring 14 and node A become non-conductive. Therefore, node A becomes a floating state, and the potential of node A is ​​, is generally maintained at VDD1 - Vth111. As a result, transistor 124 turns on. At this time, since transistor 123 turns off, node B becomes conductive with wiring 16. Then, the potential (voltage VSS) of wiring 16 is supplied to node B, so the potential of node B generally becomes VSS. Therefore, transistor 121 turns off. At this time, since transistor 122 turns on, wiring 12 becomes conductive with wiring 16. Then, the potential (voltage VSS) of wiring 16 is supplied to wiring 12, so the potential (signal OUT) of wiring 12 generally becomes VSS. In this way, signal OUT becomes the L level. Next, the third operation will be described (see Fig. 4(A)). In the third operation, signal IN1 becomes the H level and signal IN2 becomes the H level. Therefore, transistor 111 turns on and transistor 112 turns on, so node A becomes conductive with wiring 14 and wiring 16. Then, the potential (voltage VDD1) of wiring 14 and the potential (voltage VSS) of wiring 16 are supplied to node A, so the potential of node A becomes a value between VSS and VDD1. This potential of node A is determined by the current supply capabilities of transistor 111 and transistor 112. Here, it is assumed that the current supply capability of transistor 112 is greater than that of transistor 111. Therefore, preferably, the potential of node A is a value closer to VSS than VDD1. More preferably, the potential of node A is lower than VSS + Vth124 (Vth124: the threshold voltage of transistor 124) or VSS + Vth122 (Vth122: the threshold voltage of transistor 122).

[0034] ​​​​​​​​​​​​​​​​​Therefore, transistor 124 turns off. At this time, transistor 123 is on, so node B becomes conductive with wiring 15. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to node B, the potential of node B (denoted as potential Vb) starts to rise. After that, when the potential of node B reaches VSS + Vth121 (Vth121: the threshold voltage of transistor 121), transistor 121 turns on. At this time, since transistor 122 turns off, wiring 12 becomes conductive with wiring 15. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to wiring 12, the potential of wiring 12 (signal OUT) starts to rise. After that, the potential of node B and the potential of wiring 12 continue to rise. Eventually, the potential of node B becomes the value obtained by subtracting the threshold voltage (Vth123) of transistor 123 from the potential (voltage VDD1) of the gate of transistor 123. Then, since transistor 123 turns off, wiring 15 and node B become non-conductive. Therefore, node B becomes a floating state. At this time, the potential of wiring 12 continues to rise. Therefore, due to the parasitic capacitance between the gate and the second terminal of transistor 121, the potential of node B rises further from VDD1 - Vth123. Eventually, the potential of node B becomes VDD2 + Vth121 + V1 (V1: a positive number). This is a so-called bootstrap operation. Therefore, the potential of wiring 12 can rise to VDD2. In this way, signal OUT becomes the H level. Since it is on, node B becomes conductive with wiring 15. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to node B, the potential of node B (denoted as potential Vb) starts to rise. Therefore, the potential of node B (denoted as potential Vb) starts to rise. After that, when the potential of node B reaches VSS + Vth121 (Vth121: the threshold voltage of transistor 121), transistor 121 turns on. At this time, since transistor 122 turns off, wiring 12 becomes conductive with wiring 15. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to wiring 12, the potential of wiring 12 (signal OUT) starts to rise. Then, since the potential of wiring 15 (for example, voltage VDD2) is supplied to wiring 12, the potential of wiring 12 (signal OUT) starts to rise. After that, the potential of node B and the potential of wiring 12 continue to rise. Eventually, the potential of node B becomes the value obtained by subtracting the threshold voltage (Vth123) of transistor 123 from the potential (voltage VDD1) of the gate of transistor 123. Eventually, the potential of node B becomes the value obtained by subtracting the threshold voltage (Vth123) of transistor 123 from the potential (voltage VDD1) of the gate of transistor 123. Then, since transistor 123 turns off, wiring 15 and node B become non-conductive. Therefore, node B becomes a floating state. At this time, the potential of wiring 12 continues to rise. Therefore, due to the parasitic capacitance between the gate and the second terminal of transistor 121, the potential of node B rises further from VDD1 - Vth123. Eventually, the potential of node B becomes VDD2 + Vth121 + V1 (V1: a positive number). This is a so-called bootstrap operation. Eventually, the potential of node B becomes VDD2 + Vth121 + V1 (V1: a positive number). This is a so-called bootstrap operation. Therefore, the potential of wiring 12 can rise to VDD2. In this way, signal OUT becomes the H level.

[0035] Next, the fourth operation will be described (see Fig. 4(B)). In the fourth operation, signal IN1 is It becomes the L level and the signal IN2 becomes the L level. Therefore, the transistor 111 turns off and the transistor 112 turns off, so the node A becomes floating. Then, the potential of node A remains in the state before the fourth operation. For example, before the fourth operation, it is assumed that the first operation or the third operation is performed. In this case, the potential of node A is approximately VSS . On the other hand, it is assumed that the second operation is performed before the fourth operation. In this case, the potential of node A is approximately VDD1 - Vth111. Here, it is assumed that the second operation is performed before the fourth operation. Therefore, the potential of node A is maintained at approximately VDD1 - Vth111. As a result, the transistor 124 turns on. At this time, since the transistor 123 turns off, the node B becomes conductive with the wiring 16. Then, since the potential (voltage VSS) of the wiring 16 is supplied to the node B, the potential of the node B is approximately VSS. Therefore, the transistor 121 turns off. At this time, since the transistor 122 turns on, the wiring 12 becomes conductive with the wiring 16. Then, since the potential (voltage VSS) of the wiring 16 is supplied to the wiring 12, the potential (signal OUT) of the wiring 12 is approximately VSS. In this way, the signal OUT becomes the L level. As described above, the semiconductor device of the present embodiment can increase the amplitude voltage of the signal IN1 and output . Specifically, the amplitude voltage of the signal IN1 can be increased and output . Thereby, the amplitude voltage of a circuit (such as a shift register circuit or a decoder circuit) that outputs the signal IN1 to the semiconductor device of the present embodiment can be reduced. Therefore, the circuit

[0036] As described above, the semiconductor device of the present embodiment can increase the amplitude voltage of the signal IN1 and output . Specifically, the amplitude voltage of the signal IN1 can be increased and output . Thereby, the amplitude voltage of a circuit (such as a shift register circuit or a decoder circuit) that outputs the signal IN1 to the semiconductor device of the present embodiment can be reduced. Therefore, the circuit can have its amplitude voltage reduced. Therefore, the circuit The power consumption can be reduced. Or, the voltage applied to the transistor constituting the circuit can be reduced. Therefore, deterioration or destruction of the transistor can be suppressed. Or, the timing at which the signal OUT is inverted can be made substantially equal to the timing at which the signal IN1 is inverted. As a result, it is not necessary to provide an inverter circuit or the like in the wiring 12. Therefore, reduction of power consumption, reduction of circuit scale, or reduction of layout area can be achieved.

[0037]

[0038] Or, in the first operation, when the signal IN1 is at the H level, if the signal IN2 becomes the L level, the through current between the wiring 14 and the wiring 16 can be prevented. As a result, the power consumption can be reduced.

[0039] Note that although the first to fourth operations have been described, it is noted that the semiconductor device of the present embodiment does not necessarily perform all of these operations. The semiconductor device of the present embodiment can select only the necessary operations from these multiple operations and perform the selected operations.

[0040] Next, in the semiconductor device of the present embodiment, a configuration different from that in FIG. 1 will be described.

[0041] First, as shown in FIGS. 5(A) and 5(B), in the semiconductor device shown in FIG. 1, the first terminal of the transistor 111 can be connected to a wiring different from the wiring 14. FIG. 5(A) shows the semiconductor device when the first terminal of the transistor 111 is connected to the wiring 15. ​​​​​​​​​​​​An example is shown. Thereby, the voltage VDD1 can be omitted. Or, since the potential difference (Vds) between the source and the drain of the transistor 111 can be increased, the rise of the potential at node A can be shortened. FIG. 5(B) shows an example of a semiconductor device when the first terminal of the transistor 11 is connected to the wiring 13. Therefore, the voltage VDD1 can be omitted. Or, since a reverse bias can be applied to the transistor 111, the deterioration of the transistor 111 can be suppressed. However, an example of this embodiment is not limited to this. For example, the first terminal of the transistor 111 can be connected to a wiring to which the inverted signal of the signal IN1 is input.

[0042] Next, as shown in FIGS. 6(A) and 6(B), in the semiconductor devices shown in FIGS. 1 and 5(A) to (B), the gate of the transistor 111 can be connected to a wiring different from the wiring 13. FIG. 6(A) shows an example of a semiconductor device when the gate of the transistor 111 is connected to the wiring 15. Thereby, the signal IN2 can be omitted. Therefore, power consumption can be reduced. FIG. 6(B) shows an example of a semiconductor device when the gate of the transistor 111 is connected to the wiring 14. Thereby, the signal IN2 can be omitted. Therefore, power consumption can be reduced. However, an example of this embodiment is not limited to this. For example, the gate of the transistor 111 can be connected to a wiring to which the inverted signal of the signal IN1 is input. Next, as shown in FIG. 7(A), in FIGS. 1, 5(A) to (B), and 6(A) to (B),

[0043] Next, as shown in FIG. 7(A), as shown in FIGS. 1, 5(A) to (B), and 6(A) to (B), In a semiconductor device, the first terminal of transistor 111 is connected to a wiring different from wiring 14 and it is possible that the gate of transistor 111 is connected to a wiring different from wiring 13. FIG. 7(A) shows an example of a semiconductor device in which the first terminal of transistor 111 is connected to wiring 13 and the gate of transistor 111 is connected to wiring 14. Accordingly, in the second operation, the potential of node A can be increased, and in the fourth operation, the potential of node A can be decreased. Therefore, in the second operation, transistors 122 and 124 are turned on, and in the fourth operation, transistors 122 and 124 are turned off. Thus, the time during which transistors 122 and 124 are turned on can be shortened. Therefore, deterioration of transistors 122 and 124 can be suppressed.

[0044] Next, as shown in FIGS. 7(B) and 8(A), in the semiconductor devices shown in FIGS. 1, 5(A)-(B), 6(A)-(B), and 7(A), the first terminal of transistor 123 can be connected to a wiring different from wiring 15. FIG. 7(B) shows an example of a semiconductor device in which the first terminal of transistor 123 is connected to wiring 13B. It is assumed that signal IN2B is input to wiring 13B. Signal IN2B is an inverted signal of signal IN2. Accordingly, a reverse bias can be applied to transistor 123, so that deterioration of the transistor can be suppressed. FIG. 8(A) shows an example of a semiconductor device in which the first terminal of transistor 123 is connected to wiring 11. Accordingly, in the second operation and the fourth operation, the potential difference between the source and the drain applied to transistor 123 ​ (Vds) can be reduced. Therefore, deterioration of the transistor 123 can be suppressed. Or, the off-current of the transistor 123 can be reduced, and power consumption can be reduced. However, an example of this embodiment is not limited to this. For example, the first terminal of the transistor 123 can be connected to the wiring 14.

[0045] As shown in FIG. 8(B), when the first terminal of the transistor 123 is connected to the wiring 11, the gate of the transistor 123 can be connected to a wiring different from the wiring 11. FIG. 8(B) shows an example of a semiconductor device in the case where the gate of the transistor 123 is connected to the wiring 14. However, an example of this embodiment is not limited to this. The gate of the transistor 123 can be connected to the wiring 15, the wiring to which the inverted signal of the signal IN2 is input, or the wiring to which a signal having a different phase from the signal IN 2 is input.

[0046] Next, as shown in FIG. 9(A), in the semiconductor devices shown in FIGS. 1, 5(A) to (B), 6(A) to (B), 7 (A) to (B), and 8(A) to (B), a capacitive element 125 can be provided between the gate and the second terminal of the transistor 12 1. Thereby, in the first operation and the second operation, the potential of the node B can be further increased. Therefore, the potential difference (Vgs) between the gate and the source of the transistor 121 can be increased, so that the rising time of the signal OUT can be shortened.

[0047] Next, as shown in FIG. 9(B), in the semiconductor devices shown in FIGS. 1, 5(A) to (B), 6(A) to (B), 7 (A) to (B), in the semiconductor devices shown in FIGS. 8(A) to (B) and FIG. 9(A), a capacitor element 126 can be provided between node A and wiring 16. Thereby, in the fourth operation , fluctuations in the potential of node A, noise in node A, etc. can be suppressed, so , it becomes easier to maintain the potential of node A. However, an example of this embodiment is not limited thereto. For example, the capacitor element 126 can be connected between node A and a wiring different from wiring 16 (for example, wiring 1 3, wiring 14, or wiring 15, etc.). In particular, when the capacitor element 126 is connected between node A and wiring 13, the potential of node A can be varied in synchronization with signal I N2. Therefore, the time during which transistors 122 and trans istors 124 are turned on can be shortened.

[0048] Next, as shown in FIG. 10(A), in the semiconductor devices shown in FIGS. 1, 5(A) to (B), 6(A) to (B), FIGS. 7(A) to (B), 8(A) to (B), and 9(A) to (B), each transistor, etc. can be connected to a separate wiring. FIG. 10(A) shows an example of a semiconductor device when the first terminal of transistor 112, the second terminal of transistor 124, and the second terminal of trans istor 122 are connected to separate wirings. Wiring 16 is divided into a plurality of wirings such as wiring 16A to 16C. And the first terminal of transistor 1 12, the second terminal of transistor 124, and the second terminal of transistor 122 are connected to wiring 16A, wiring 16B, and wiring 16C, respectively. However, an example of this embodiment is not limited thereto. For example, the first terminal of transistor 121 and the trans istor 124's second terminal and transistor 122's second terminal are each connected to wiring 16A, wiring 16B, and wiring 16C. However, an example of this embodiment is not limited to this. For example, the first terminal of transistor 121 and the trans istor 124's second terminal and transistor 122's second terminal are each connected to wiring 16A, wiring 16B, and wiring 16C. However, an example of this embodiment The first terminal of the stud 123 can also be connected to a separate wiring. In this case, wiring 1 5 can be split into two wirings.

[0049] Next, as shown in FIG. 10(B), in the semiconductor devices shown in FIGS. 1, 5(A)-(B), 6(A)-(B), FIGS. 7(A)-(B), 8(A)-(B), 9(A)-(B), and 10(A), the transistor can be replaced with a resistive element, a diode, a capacitive element, etc. FIG. 10(B) shows a semiconductor device when the transistor 111 is replaced with a diode 111d. One electrode (e.g., the anode) of the diode 111d is connected to the wiring 13, and the other electrode (e.g., the cathode) is connected to the node A. However, an example of this embodiment is not limited to this. For example, the transistor 111 can be replaced with a resistive element. The resistive element can be connected between any one of the wirings 13-15 and the node A. As another example, the transistor 123 can be replaced with a diode whose one electrode ( e.g., the anode) is connected to the wiring 11 and the other electrode (e.g., the cathode) is connected to the node B. As another example, the diode can be a transistor connected in diode connection. However, an example of this embodiment is not limited to this. For example, the transistor 111 can be replaced with a resistive element. The resistive element can be connected between any one of the wirings 13-15 and the node A. As another example, the transistor 123 can be replaced with a diode whose one electrode ( e.g., the anode) is connected to the wiring 11 and the other electrode (e.g., the cathode) is connected to the node B. As another example, the diode can be a transistor connected in diode connection. e.g., the anode) is connected to the wiring 11 and the other electrode (e.g., the cathode) is connected to the node B. As another example, the diode can be a transistor connected in diode connection. Next, an example of the function of each circuit and an example of the function of each transistor will be described. First, assume that the circuit 100 has a function of increasing the amplitude voltage of the signal IN1. Also has a function of raising the potential of the H level of the signal IN1 of the circuit 100. Or, the circuit 1 00 has a function of inverting the signal OUT when the signal IN1 is inverted. Or, the circuit

[0050] Next, an example of the function of each circuit and an example of the function of each transistor will be described.

[0051] First, assume that the circuit 100 has a function of increasing the amplitude voltage of the signal IN1. Also has a function of raising the potential of the H level of the signal IN1 of the circuit 100. Or, the circuit 1 00 has a function of inverting the signal OUT when the signal IN1 is inverted. Or, the circuit When signal IN1 goes to the H level, 100 has the function of setting signal OUT to the H level. Alternatively, when signal IN1 goes to the L level, circuit 100 has the function of setting signal OUT to the L level. In this way, circuit 100 has the function as a level shifter circuit.

[0052] Note that by making voltage VDD2 smaller than voltage VDD1, the potential of the H level of signal OUT can be made lower than the potential of the H level of signal IN1 or signal IN2. In this case, circuit 100 has the function of reducing the amplitude voltage of signal IN1. In this case, circuit 100 has the function of reducing the amplitude voltage of signal IN1. In this case, circuit 100 has the function of reducing the amplitude voltage of signal IN1.

[0053] Next, circuit 110 has the function of inverting signal IN1. Alternatively, when signal IN1 goes to the H level, circuit 110 has the function of decreasing the potential of node A. Alternatively, when signal IN1 goes to the L level, circuit 110 has the function of increasing the potential of node A. Alternatively, circuit 110 has the function of floating node A. In this way, circuit 110 has the function as an inverter circuit. Next, circuit 110 has the function of inverting signal IN1. Alternatively, when signal IN1 goes to the H level, circuit 110 has the function of decreasing the potential of node A. Alternatively, when signal IN1 goes to the L level, circuit 110 has the function of increasing the potential of node A. Alternatively, circuit 110 has the function of floating node A. In this way, circuit 110 has the function as an inverter circuit. In this way, circuit 110 has the function as an inverter circuit.

[0054] Next, circuit 120 has the function of increasing the amplitude voltage of signal IN1. Alternatively, circuit 120 has the function of increasing the potential of the H level of signal IN1. Alternatively, when signal IN1 is inverted, circuit 120 has the function of inverting signal OUT. Alternatively, when signal IN1 goes to the H level, circuit 120 has the function of setting signal OUT to the H level. Alternatively, when signal IN1 goes to the L level, circuit 120 has the function of setting signal OUT to the L level. In this way, circuit 120 has the function as a level shifter circuit. Next, circuit 120 has the function of increasing the amplitude voltage of signal IN1. Alternatively, circuit 120 has the function of increasing the potential of the H level of signal IN1. Alternatively, when signal IN1 is inverted, circuit 120 has the function of inverting signal OUT. Alternatively, when signal IN1 goes to the H level, circuit 120 has the function of setting signal OUT to the H level. Alternatively, when signal IN1 goes to the L level, circuit 120 has the function of setting signal OUT to the L level. In this way, circuit 120 has the function as a level shifter circuit.

[0055] Next, the transistor 111 has a function of controlling the conduction state between the wiring 14 and the node A. Or, the transistor 111 has a function of controlling the timing of supplying the potential of the wiring 14 to the node A. Or, the transistor 111 has a function of controlling the timing of raising the potential of the node A. Or, the transistor 111 has a function of controlling the timing of floating the node A. In this way, the transistor 111 has a function as a switch.

[0056] Next, the transistor 112 has a function of controlling the conduction state between the wiring 16 and the node A. Or, the transistor 112 has a function of controlling the timing of supplying the potential of the wiring 16 to the node A. Or, the transistor 112 has a function of controlling the timing of decreasing the potential of the node A. In this way, the transistor 112 has a function as a switch.

[0057] Next, the transistor 121 has a function of controlling the conduction state between the wiring 15 and the wiring 12. Or, the transistor 121 has a function of controlling the timing of supplying the potential of the wiring 15 to the wiring 12. Or, the transistor 121 has a function of controlling the timing of raising the potential of the wiring 12. Or, the transistor 121 has a function of controlling the timing of performing a bootstrap operation. Or, the transistor 121 has a function of controlling the timing of raising the potential of the node B. In this way, the transistor 121 has a function as a switch.

[0058] Next, the transistor 122 has a function of controlling the conduction state between the wiring 16 and the wiring 12. ​​​Or, transistor 122 has a function of controlling the timing of supplying the potential of wiring 16 to wiring 12. Or, transistor 122 has a function of controlling the timing of reducing the potential of wiring 12. Thus, transistor 122 has a function as a switch. Next, transistor 123 has a function of controlling the conduction state between wiring 15 and node B. Or, transistor 123 has a function of controlling the timing of supplying the potential of wiring 14 to node B. Or, transistor 123 has a function of controlling the timing of increasing the potential of node B. Or, transistor 123 has a function of controlling the timing of floating node B. Thus, transistor 123 has a function as a switch. Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, an example of the channel width of each transistor will be described.

[0059] First, the channel width of transistor 121 is preferably larger than the channel widths of transistor 111, transistor 112, and transistors 122 to 124. That is, it is preferably the largest among the transistors included in circuit 100. This is because the transistor Next, transistor 123 has a function of controlling the conduction state between wiring 15 and node B. Or, transistor 123 has a function of controlling the timing of supplying the potential of wiring 14 to node B. Or, transistor 123 has a function of controlling the timing of increasing the potential of node B. Or, transistor 123 has a function of controlling the timing of floating node B. Thus, transistor 123 has a function as a switch. Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, an example of the channel width of each transistor will be described. First, the channel width of transistor 121 is preferably larger than the channel widths of transistor 111, transistor 112, and transistors 122 to 124. That is, it is preferably the largest among the transistors included in circuit 100. This is because the transistor

[0060] Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, transistor 124 has a function of controlling the conduction state between wiring 16 and node B. Or, transistor 124 has a function of controlling the timing of supplying the potential of wiring 16 to node B. Or, transistor 124 has a function of controlling the timing of reducing the potential of node B. Thus, transistor 124 has a function as a switch. Next, an example of the channel width of each transistor will be described. First, the channel width of transistor 121 is preferably larger than the channel widths of transistor 111, transistor 112, and transistors 122 to 124. That is, it is preferably the largest among the transistors included in circuit 100. This is because the transistor

[0061] Next, an example of the channel width of each transistor will be described.

[0062] First, the channel width of transistor 121 is preferably larger than the channel widths of transistor 111, transistor 112, and transistors 122 to 124. That is, it is preferably the largest among the transistors included in circuit 100. This is because the transistor Next, transistor 123 has a function of controlling the conduction state between wiring 15 and node B. Or, transistor 123 has a function of controlling the timing of supplying the potential of wiring 14 to node B. Or, transistor 123 has a function of controlling the timing of increasing the potential of node B. Or, transistor 123 has a function of controlling the timing of floating node B. Thus, transistor 123 has a function as a switch. 100 has the largest transistor among them. Because the transistor Since 121 has the role of driving wiring 12, it requires a large driving ability. The channel width of transistor 121 is preferably 2 times or more and 10 times or less that of transistor 123. More preferably, it is 3 times or more and 8 times or less. Even more preferably, it is 4 times or more and 6 times or less.

[0063] Next, the channel width of transistor 122 is preferably larger than the channel widths of transistors 111, 112, transistor 123, and transistor 124. This is because transistor 122 has the role of driving wiring 12 and thus requires a large driving ability. The channel width of transistor 122 is preferably 2 times or more and 30 times or less that of transistor 124. More preferably, it is 4 times or more and 15 times or less. Even more preferably, it is 6 times or more and 10 times or less.

[0064] Note that the channel width of transistor 122 can be larger than the channel width of transistor 121.

[0065] The channel width of transistor 123 is preferably larger than the channel width of transistor 124. This is because in the first operation and the third operation, due to the timing shift, even if transistors 123 and 124 are turned on simultaneously, the potential of node B can be increased. The channel width of transistor 123 is preferably 1.5 times or more and 10 times or less that of transistor 124. More preferably, it is 2 times or more and 8 times or less. Even more preferably, it is 2.5 times or more and 5 times or less.

[0066] Note that the current supply capacity of a transistor can be controlled by the channel width of the transistor. Specifically, the larger the channel width of the transistor, the higher the current supply capacity of the transistor. However, the factor for controlling the current supply capacity of the transistor is not limited to the channel width of the transistor. For example, the current supply capacity can be controlled by the channel length of the transistor or the potential difference (Vgs) between the gate and the source of the transistor. Specifically, the smaller the channel length of the transistor, the higher the current supply capacity of the transistor. And the larger the potential difference (Vgs) between the gate and the source of the transistor, the higher the current supply capacity of the transistor. In addition, by making the transistor into a multi-gate structure, the current supply capacity can be reduced.

[0067] As described above, there are multiple methods for controlling the current supply capacity of a transistor. Therefore, when, in the following, a method of controlling the channel width is exemplified as a method of controlling the current supply capacity of a transistor, the channel width can be rephrased as the channel length or the potential difference (Vgs) between the gate and the source of the transistor, etc.

[0068]

[0069] (Embodiment 2) In this embodiment, an example of a semiconductor device and an example of a driving method of the semiconductor device will be described. The semiconductor device of this embodiment is assumed to have the semiconductor device of Embodiment 1.

[0069] First, an example of the semiconductor device of this embodiment will be described.

[0070] ​FIG. 11 shows an example of a semiconductor device according to this embodiment. The semiconductor device shown in FIG. 11 is assumed to have a circuit 3 00, a circuit 400, and a circuit 500. The circuit 400 is assumed to have circuits 401_1~ 401_m (m is a natural number). And, as the circuits 401_1~401_m, the semiconductor devices described in Embodiment 1 can be used respectively. In FIG. 11, it is assumed that the semiconductor devices shown in FIG. 1 are used as the circuits 401_1~401_m, respectively. The circuit 500 is assumed to have a circuit 501 and a circuit 502.

[0071] The circuit 300 is connected to wirings 21_1~21_m, a wiring 23, wirings 24_1~24_4, a wiring 25 and a wiring 27. The circuit 400 is connected to wirings 21_1~21_m, wirings 22_1~2 2_m, wirings 24_1~24_4, a wiring 25, a wiring 26, and a wiring 27. The circuit 401_i (i is any one of 1~m) is connected to a wiring 21_i, a wiring 22_i, one of the wirings 24_ 1~24_4, a wiring 25, a wiring 26, and a wiring 27. And, in the circuit 401_i, wirings 11, 12, 13, 14, 15, and 1 6 are respectively connected to a wiring 21_i, a wiring 22_i, one of the wirings 24_1~24_4, a wiring 25, a wiring 26, and a wiring 27. The circuit 500 is connected to a wiring 23, wirings 24 _1~24_4, a wiring 25, a wiring 26, and a wiring 27. The circuit 501 is connected to a wiring 2 3 and wirings 24_1~24_4, and the circuit 502 is connected to a wiring 25, a wiring 26, and a wiring 27.

[0072] Note that it is assumed that the circuit 401_i is connected to the wiring 24_1. In this case, the circuit 401_ i + 1, circuit 401_i + 2, and circuit 401_i + 3 are each often connected to wiring 24_2, wiring 24_ 3, and wiring 24_4. Or, circuit 401_i - 3, circuit 401_ i - 2, and circuit 401_i - 1 are each often connected to wiring 24_2, wiring 24_3, and wiring 24_4.

[0073] Note that circuit 401_i is preferably connected to the wiring whose potential becomes L level during the period when signal SOUTi is at H level among wirings 24_1 to 24_4. Thereby, the period during which transistor 111 and transistor 112 are simultaneously turned on can be omitted. As a result, power consumption can be reduced.

[0074] Circuit 500 has a function of controlling the timing for supplying signals or voltages to circuit 300 and circuit 400. And circuit 500 has a function of controlling the timing when circuit 300 and circuit 400 operate. That is, circuit 500 is assumed to have a function as a controller.

[0075] Circuit 501 has a function of controlling the timing for outputting signals SP, signal CK1, signal CK2, signal CK3, and signal CK4 to wiring 23, wiring 24_1, wiring 24_2, wiring 24_3, and wiring 24_4, respectively. That is, circuit 501 is assumed to have a function as a signal generation circuit (or also called a timing generator). Therefore, circuit 501 can include switches, diodes, transistors, oscillation circuits, clock generators, PLL circuits and / or frequency division circuits, etc.

[0076] ​​​​As shown in FIG. 12, the signal SP, signal CK1, signal CK2, signal CK3, and signal CK4 are often digital signals. The potential of the H level of these signals is generally set to VDD1, and the potential of the L level is generally set to VSS. And the signal SP is assumed to have a function as a start pulse (or also referred to as a horizontal synchronization signal or a vertical synchronization signal). Therefore, the wiring 23 is assumed to have a function as a signal line (or also referred to as a start signal line). The signals CK1 to CK4 are each assumed to have a function as a clock signal. The signals CK1 to CK4 are assumed to have a phase shift of 1 / 4 cycle (90°) each. Therefore, the wirings 24_1 to 24_4 are assumed to have a function as clock signal lines (or also referred to as signal lines). , and are often digital signals. The potential of the H level of these signals is generally set to VDD1 , and the potential of the L level is generally set to VSS. And the signal SP is assumed to have a function as a start pulse (or also referred to as a horizontal synchronization signal or a vertical synchronization signal). Therefore , the wiring 23 is assumed to have a function as a signal line (or also referred to as a start signal line). The signals CK1 to CK4 are each assumed to have a function as a clock signal. The signals CK1 to CK4 are assumed to have a phase shift of 1 / 4 cycle (90°) each. Therefore , the wirings 24_1 to 24_4 are assumed to have a function as clock signal lines (or also referred to as signal lines). The signals CK1 to CK4 are assumed to have a phase shift of 1 / 4 cycle (90°) each. Therefore , the wirings 24_1 to 24_4 are assumed to have a function as clock signal lines (or also referred to as signal lines).

[0077] Note that, as shown in FIG. 12, the signals CK1 to CK4 are assumed to be balanced. By balanced, it means that the period of being at the H level and the period of being at the L level are generally equal within one cycle . However, an example of this embodiment is not limited to this. For example, as shown in FIG. 13(A), the signals CK1 to CK4 can be unbalanced. By unbalanced, it means that the period of being at the H level and the period of being at the L level are different. Here, different means outside the range of being approximately equal . For example, as shown in FIG. 13(A), the signals CK1 to CK4 can be unbalanced. By unbalanced, it means that the period of being at the H level and the period of being at the L level are different. Here, different means outside the range of being approximately equal .

[0078] Note that, as shown in FIGS. 13(B) and 13(C), in the semiconductor device of this embodiment, it is possible to use a single-phase clock signal. Even in this case, the clock signal can be balanced as shown in FIG. 13(B), or can be unbalanced as shown in FIG. 13(C). However, an example of this embodiment is not limited to this. For example, in this case, the clock signal can be balanced as shown in FIG. 13(B), or can be unbalanced as shown in FIG. 13(C). However, an example of this embodiment is not limited to this. For example, in this case, the clock signal can be balanced as shown in FIG. 13(B), or can be unbalanced as shown in FIG. 13(C). However, an example of this embodiment is not limited to this. For example, in this case, the clock signal can be balanced as shown in FIG. 13(B), or can be unbalanced as shown in FIG. 13(C). However, an example of this embodiment is not limited to this. For example, in this​​ The semiconductor device of the embodiment uses a three-phase clock signal or a five or more phase clock signal. It is possible.

[0079] The circuit 502 supplies a voltage VDD1, a voltage VDD2 to the wiring 25, the wiring 26, and the wiring 27, respectively. In other words, the circuit 502 functions as a power supply circuit (or The wiring 25 has a function as a power supply. The wiring 27 functions as a power line, a negative power line, a ground line, or a positive power line. The circuit 502 has a function as a land line or a ground. Switches, transistors, capacitors, coils, diodes, regulators, DCDC converters The input / output terminal may include a boost circuit and / or a step-up circuit.

[0080] Note that the circuits 500, 501, and 502 are different in configuration from the circuits 300 and 400. Therefore, it is possible to provide different signals or different voltages to the circuits 300 and 400. do.

[0081] The circuit 300 receives signals and voltages (e.g., signal SP, signal CK1 1 to CK4, voltage VDD1 and voltage VSS) to output signals SOUT1 to SOUTm. The signals SOUT1 to SOUTm are digital signals. The H level potential is generally VDD1, and the L level potential is The circuit 300 sets the signals SOUT1 to SOUTm to H in order. In other words, the circuit 300 functions as a shift register circuit. However, the present embodiment is not limited to this example. For example, circuit 300 has the function of setting signals SOUT1 to SOUTm to the H level in any order. Therefore, circuit 300 can function as a decoder circuit.

[0082] Note that signals SOUT1 to SOUTm are each input to circuit 400 via wirings 21_1 to 21_m. For example, signal SOUTi is input to circuit 401_i via wiring 21_i. Therefore, wirings 21_1 to 21_m each have the function of a signal line.

[0083] Note that in the timing chart shown in FIG. 12, a part of the period during which signal SOUTi becomes the H level overlaps with a part of the period during which signal SOUTi - 1 becomes the H level. And a part of the period during which signal SOUTi becomes the H level overlaps with a part of the period during which signal SOUTi + 1 becomes the H level. As a result, the period during which signals SOUT1 to SOUTm become the H level can be lengthened. Therefore, the driving frequency of circuit 300 can be lowered, and power consumption can be reduced. However, an example of this embodiment is not limited to this. For example, as shown in FIGS. 13(A) to (C), the periods during which signals SOUT1 to SOUTm become the H level can be non - overlapping.

[0084] Circuit 400 outputs signals BOUT1 to BOUTm according to signals (for example, signals SOUT1 to SOUTm) supplied from circuit 300, signals and voltages (for example, signals CK1 to CK4, voltage VDD1, voltage VDD2, and voltage VSS) supplied from circuit 500. ​​​​​​​​​​It has a function of controlling imaging. The signals BOUT1 to BOUTm are digital signals This is often the case, and the potential of its H level is generally VDD2, and the potential of its L level is generally VSS. And the timing at which the signals BOUT1 to BOUTm invert is assumed to be approximately equal to the timing at which the signals S OUT1 to SOUTm invert. That is, the circuit 400 is assumed to have a function of increasing the amplitude voltage of the signals SOUT1 to SOUTm .

[0085] Next, an example of the operation of the semiconductor device of the present embodiment will be described.

[0086] FIG. 14 is an example of a timing chart of the circuit 401_i. In FIG. 14, the signal SOU Ti, the signal CK, the potential of node A of the circuit 401_i, the potential of node B of the circuit 401_i, and the signal BOUTi are shown. The signal CK is one of the signals CK1 to CK4. The signal CK is a signal that becomes L level when the signal SOUTi becomes H level among the signals CK1 to CK4 . And the timing chart shown in FIG. 14 has a period Ta, a period Tb, and a period Tc. Among the timing charts shown in FIG. 14, except for the period Ta, the periods Tb and Tc are arranged in order.

[0087] Note that the signal SOUTi corresponds to the signal IN1 shown in FIG. 2. The signal CK corresponds to the signal IN2 shown in FIG 2. The signal BOUTi corresponds to the signal OUT shown in FIG. 2 .

[0088] First, in the period Ta, the signal SOUTi becomes H level and the signal CK becomes L level . Then, the circuit 400_i performs the first operation. Therefore, the signal BOUTi is H level It becomes. Thus, the potential of the H level of the signal SOUTi is raised from VDD1 to VDD2 can be.

[0089] Next, in the period Tb, the signal SOUTi becomes the L level and the signal CK becomes the H level . Then, the circuit 400_i performs the second operation. Therefore, the signal BOUTi becomes the L level becomes.

[0090] Next, in the period Tc, the signal SOUTi remains at the L level and the signal CK becomes the L level . Then, the circuit 400_i performs the fourth operation. Furthermore, before the period Tc, since it is the period Tb, the potential Va is VDD1 - Vth111 is maintained. Therefore, the signal BOUTi remains at the L level.

[0091] As described above, the semiconductor device of the present embodiment can output after increasing the amplitude voltage of the output signal of the circuit 300 . Thereby, the amplitude voltage of the circuit 300 can be reduced . Therefore, the power consumption of the circuit 300 can be reduced.

[0092] Alternatively, the circuits 401_1 to 401_m often perform any one of the first operation, the second operation, and the fourth operation . Therefore, since there is no period in which the transistor 111 and the transistor 112 are simultaneously turned on, power consumption can be reduced.

[0093] Next, an example of the circuit 300 will be described.

[0094] FIG. 15 shows an example of the circuit 300. The circuit 300 is assumed to have circuits 310_1 to 310_m . The circuit 310_i includes wiring 21_i, wiring 21_i - 1, and wiring 21_i + 2 , any three of the wirings 24_1 to 24_4, are connected to the wiring 25 and the wiring 27. However, the circuit 310_1 is often connected to the wiring 23 instead of the wiring 21_i-1.

[0095] The circuits 310_1 to 310_m each have a transistor 311, a transistor 312, a transistor 313, a transistor 314, a transistor 315, a transistor 316, a transistor 317, a transistor 318, and a transistor 319. The first terminal of the transistor 311 is connected to the wiring 33, and the second terminal of the transistor 311 is connected to the wiring 32. The first terminal of the transistor 312 is connected to the wiring 37, the second terminal of the transistor 312 is connected to the wiring 32, and the gate of the transistor 312 is connected to the wiring 35. The first terminal of the transistor 313 is connected to the wiring 37, the second terminal of the transistor 313 is connected to the wiring 32. The first terminal of the transistor 314 is connected to the wiring 37, the second terminal of the transistor 314 is connected to the gate of the transistor 311, and the gate of the transistor 314 is connected to the gate of the transistor 313. The first terminal of the transistor 315 is connected to the wiring 36, the second terminal of the transistor 315 is connected to the gate of the transistor 311, and the gate of the transistor 315 is connected to the wiring 31. The first terminal of the transistor 316 is connected to the wiring 36, the second terminal of the transistor 316 is connected to the gate of the transistor 313, and the gate of the transistor 316 is connected to the wiring 38. The first terminal of the transistor 317 is connected to the wiring 36, and the gate of the transistor 317 is connected to the wiring 35. The first terminal of the transistor 318 is connected to the second terminal of the transistor 317, and the second terminal of the transistor 318 is connected to the gate of the transistor 313, and the gate of the transistor 318 is connected to the wiring 34. The first terminal of the transistor 319 is connected to the wiring 37, and the second terminal of the transistor 319 is connected to the gate of the transistor 313, and the gate of the transistor 319 is connected to the wiring 31.

[0096] Note that the connection point between the gate of the transistor 311, the second terminal of the transistor 314, and the second terminal of the transistor 315 is indicated as node C. The connection point between the gate of the transistor 313, the gate of the transistor 314, the second terminal of the transistor 316, the second terminal of the transistor 31 8, and the second terminal of the transistor 319 is indicated as node D.

[0097] Note that the transistors 311 to 319 are assumed to be N-channel type. Therefore, all of the semiconductor devices of this embodiment can be configured by N-channel type transistors. However, an example of this embodiment is not limited thereto. For example, all of the transistors 311 to 3 19 can be P-channel type.

[0098] Note that in the circuit 310_i, the wiring 31 is connected to the wiring 21_i-1. The wiring 32 is connected to the wiring 21_i. The wirings 33 to 35 are connected to three selected wirings among the wirings 24_1 to 24_4. For example, if the wiring 33 is connected to the wiring 24_1, then the wiring 34 is connected to the wiring 24_2, and the wiring 35 is connected to the wiring 24_3. The wiring 36 is connected to the wiring 25. The wiring 37 is connected to the wiring 27. The wiring 38 is connected to the wiring 21_ It is connected to i + 2. However, in circuit 310_1, wiring 31 is connected to wiring 23 .

[0099] Next, an example of the operation of circuit 300 will be described.

[0100] FIG. 16 shows an example of a timing chart that can be used for circuit 310_i. The timing chart shown in FIG 16 shows signal IN33, signal IN34, signal IN35, signal SO UTi-1, signal SOUTi+1, the potential of node C (potential Vc), the potential of node D (potential Vd) and signal SOUTi. And the timing chart shown in FIG. 16 has periods T 1 to T9. It is assumed that periods T5 to T9 are arranged in order, and periods T 1 to T4 are repeatedly arranged in order in the other periods.

[0101] First, in period T1, signal SOUTi becomes the L level, signal SOUTi+2 becomes the L level, signal IN33 becomes the L level, signal IN34 becomes the H level, signal IN 35 becomes the H level. Therefore, transistor 316 turns off, transistor 31 7 turns on, transistor 318 turns on, and transistor 319 turns off. As a result, node D becomes conductive with wiring 36. Then, the potential of wiring 36 ( for example, voltage VDD) is supplied to node D, so the potential of node D rises. Therefore, the transistor 3 14 turns on. At this time, since transistor 315 turns off, node C becomes conductive with wiring 37. Then, the potential of wiring 37 (voltage VSS) is supplied to node C, so the potential of node C becomes approximately VSS. Therefore, transistor 3 11 turns off. At this time, transistors 312 and 313 turn on. Therefore, wiring 32 becomes conductive with wiring 37. Then, the potential (voltage VSS) of wiring 37 is supplied to wiring 32, so the potential of wiring 32 becomes approximately VSS. Thus, signal SOUTi becomes an L level.

[0102] Next, in period T2, compared with period T1, the difference is that signal IN34 becomes an L level. Therefore, since transistor 318 turns off, wiring 36 and node D become non-conductive. Then, since node D becomes a floating state, the potential of node D maintains the potential in period T1.

[0103] Next, in period T3, compared with period T2, the differences are that signal IN33 becomes an H level and signal IN3 5 becomes an L level. Therefore, transistors 317 and transistor 312 turn off.

[0104] Next, in period T4, compared with period T3, the difference is that signal IN34 becomes an H level. Therefore, transistor 318 turns on.

[0105] Next, in period T5, signal SOUTi becomes an H level, signal SOUTi+2 becomes an L level signal IN33 becomes an L level, signal IN34 becomes an L level, and signal IN35 becomes an H level. Therefore, transistor 316 turns off, transistor 317 turns on, transistor 318 turns off, and transistor 319 turns on. Thus, wiring 37 and node D become conductive. Then, the potential (voltage VSS) of wiring 37 is supplied to node D, so the potential of node D becomes approximately VSS. Therefore, the transistor Distorter 314 turns off. At this time, since transistor 315 turns on, node C becomes conductive with wiring 36. Then, the potential of wiring 36 is supplied to node C, and the potential of node C starts to rise. Eventually, the potential of node C becomes the sum of the potential of wiring 32 (VSS ) and the threshold voltage (Vth311) of transistor 311 (VSS + Vth311), and then transistor 311 turns on. At this time, transistor 312 turns on while transistor 313 turns off, so that wiring 32 becomes conductive with wiring 37 and wiring 33. Then, the potential of wiring 37 (voltage VSS) and the potential of wiring 33 (signal IN33 at L level) are supplied to wiring 32, so that the potential of wiring 37 becomes approximately VSS. Thus, signal SOUTi becomes L level. After that, the potential of node C continues to rise. Eventually, the potential of node C becomes VDD1 - Vth315 (Vth315 is the threshold voltage of transistor 3 15). Then, transistor 315 turns off and node C becomes floating. Therefore, the potential of node C is maintained at VDD1 - Vth315.

[0106] Next, in period T6, signal SOUTi - 1 remains at H level, signal SOUTi + 2 remains at L level, signal IN33 becomes H level, signal IN34 remains at L level, and signal IN35 becomes L level. Therefore, transistor 316 remains off, transistor 317 turns off, transistor 318 remains off, and transistor 3 19 remains on, so that node D remains conductive with wiring 37. Then, the potential of wiring 37 (voltage VSS) is continuously supplied to node D. , the potential of node D generally remains at VSS. Therefore, transistor 314 turns off. and remains off. At this time, transistor 315 remains off. Then, node C becomes floating, so the potential of node C remains at VDD1 - Vth315. Therefore , transistor 311 remains on. And transistors 312 and 313 turn off, so wiring 32 becomes conductive with wiring 33. At this time, since signal I N33 becomes high level, the potential of wiring 32 starts to rise. At the same time, the potential of node C also rises due to the bootstrap operation. As a result, the potential of node C rises to VDD1 + Vth311 (Vth311 is the threshold voltage of transistor 311) + V1. So , the potential of wiring 32 generally rises to VDD1. Thus, signal SOUTi becomes high level.

[0107] Next, in period T7, signal SOUTi - 1 becomes low level and signal IN34 becomes high level, which is different from period T6. Therefore, transistor 318 turns on and transistor 319 turns off. Then, node D becomes floating, so the potential of node D is generally maintained at VSS.

[0108] Next, in period T8, signal SOUTi - 1 remains low level, signal SOUTi + 2 becomes high level, signal IN33 becomes low level, signal IN34 remains high level, signal IN35 becomes high level, so transistor 316 turns on, transistor 317 turns on, transistor 318 turns on, and transistor 319 remains off, so node D becomes conductive with wiring 36. Then, at node D, there is wiring Since a potential of 36 (voltage VDD1) is supplied, the potential of node D rises. Therefore, transistor 314 turns on. At this time, transistor 315 remains off, and node C becomes conductive with wiring 37. Then, the potential of wiring 37 ( voltage VSS) is supplied to node C, so the potential of node C becomes approximately VSS. Therefore, transistor 311 turns off. At this time, since transistors 312 and 313 turn on, wiring 32 becomes conductive with wiring 33 and wiring 37. Then, since the potential of wiring 37 (voltage VSS) is supplied to wiring 32, the potential of wiring 32 becomes approximately VSS. Thus, signal SOUTi becomes the L level.

[0109] Next, in period T9, compared with period T8, the difference is that signal IN34 becomes the L level. Therefore, transistor 318 turns off.

[0110] The above is an example of circuit 300.

[0111] Note that the gate of transistor 317 can be connected to wiring 34, and the gate of transistor 318 can be connected to wiring 35.

[0112] Note that transistor 319 can be omitted.

[0113] Note that transistor 312 can be omitted.

[0114] (Embodiment 3) In this embodiment, an example of a display device and an example of a pixel included in the display device will be described. In particular, an example of a liquid crystal display device and an example of a pixel included in the liquid crystal display device will be described. Note that in this The drive circuit of the display device according to the embodiment has the semiconductor devices of Embodiments 1 to 2. This is possible.

[0115] First, an example of the display device according to the present embodiment will be described.

[0116] FIG. 17(A) shows an example of the display device according to the present embodiment. The display device shown in FIG. 17(A) includes a circuit 1001, a circuit 1002, a circuit 1003_1, a pixel portion 1004, and a terminal 1005. A plurality of wirings extend from the circuit 1003_1 and are arranged in the pixel portion 1004. It is assumed that the plurality of wirings function as gate signal lines (also referred to as scanning lines). Alternatively, a plurality of wirings extend from the circuit 1002 and are arranged in the pixel portion 1004. It is assumed that the plurality of wirings function as video signal lines (also referred to as data lines). And a plurality of pixels are arranged corresponding to the plurality of wirings extending from the circuit 1003_1 and the plurality of wirings extending from the circuit 1002. However, an example of the present embodiment is not limited to this. For example, various other wirings can be arranged in the pixel portion 1004. The wiring can function as a gate signal line, a data line, a power supply line, a capacitance line, or the like. In the display device shown in FIG. 17(A), the circuit 1003_1 is formed on the same substrate 100 6 as the pixel portion 1004, and the circuits 1001 and 1002 are formed on a substrate different from the pixel portion 1004. The drive frequency of the circuit 1003_1 is often slower compared to the circuit 1001 or the circuit 1002.

[0117] Therefore, as the semiconductor layer of the transistor, an amorphous semiconductor, an amorphous is often used. When compared with the circuit 1001 or the circuit 1002, the drive frequency of the circuit 1003_1 is often slow. Therefore, as the semiconductor layer of the transistor, an amorphous semiconductor, an amorphous It becomes easy to use a compound semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. This results in the ability to increase the size of the display device. Or, the display device can be manufactured at low cost.

[0118] Circuit 1001 has a function of controlling the timing for supplying a signal, voltage, current, etc. to circuit 1002 and circuit 1003_1. Or, circuit 1001 has a function of controlling circuit 1002 and circuit 1003_1. Thus, circuit 1001 shall have a function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, etc.

[0119] Circuit 1002 has a function of controlling the timing for supplying a video signal to pixel section 1004. Or, circuit 1002 has a function of controlling the luminance, transmittance, etc. of the pixels that pixel section 1004 has. Thus, circuit 1002 shall have a function as a drive circuit, a source driver circuit, a signal line drive circuit, etc.

[0120] Circuit 1003_1 has a function of controlling the timing for supplying a gate signal to pixel section 1004. Or, circuit 1003_1 has a function of controlling the timing for selecting pixels. Thus, circuit 1003_1 shall have a function as a gate driver (or also referred to as a scan line drive circuit).

[0121] Note that, as shown in Fig. 17(B), the display device of this embodiment can have circuit 1003_2. Circuit 1003_2 shall have the same function as circuit 1003_1. And, circuits 1003_1 and 1003_2 drive the same wiring. ​​​​​​​​​​​​​ As a result, the loads on circuit 1003_1 and circuit 1003_2 can be reduced. However, an example of this embodiment is not limited thereto. For example, circuit 1003_1 may drive the gate signal lines of the odd-numbered stages, and circuit 1003_2 may drive the gate signal lines of the even-numbered stages. Thereby, the driving frequencies of circuit 1003_1 and circuit 1003_2 can be reduced. As another example, the display device of this embodiment may have three or more circuits having the same functions

[0122] In the display device shown in FIG. 17(B), circuit 1003_1 and circuit 1003_2 are formed on the same substrate 1006 as pixel section 1004, and circuit 1001 and circuit 1002 are formed on a substrate different from pixel section 1004. The driving frequencies of circuit 1003_1 and circuit 1003_2 are often slower than those of circuit 1001 or circuit 1002. Therefore, it becomes easy to use an amorphous semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of

[0123] the thin-film transistor. As a result, the display device can be made larger. Or, the display device can be manufactured at a lower cost. As shown in FIG. 17(C), circuit 1002, circuit 1003_1, and circuit 1003_2 may be formed on the same substrate 1006 as pixel section 1004, and circuit 1001 may be

[0124] Note that, as shown in FIG. 17(D), a part of circuit 1002, circuit 1002a, circuit 1003 _1 and circuit 1003_2 are formed on the same substrate 1006 as the pixel portion 1004, and another part of circuit 100 1, circuit 1002b, can be formed on a substrate different from the pixel portion 1004. As circuit 1002a, it is possible to use a circuit with a relatively low driving frequency, such as a switch, a shift register, and / or a selector. As a result, it becomes easy to use an amorphous semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, an organic semiconductor, etc. as the semiconductor layer of the transistor. As a result, the display device can be made larger. Or, the display device can be manufactured at low cost. Note that, as a part of circuit 1003_1, circuit 1003_2, circuit 1002, and / or circuit 1002a, it is possible to use the semiconductor device of Embodiments 1 to 2. As a result, the driving voltage can be reduced, so that power consumption can be reduced. Next, an example of a pixel included in the pixel portion 1004 will be described. FIG. 17(E) shows an example of a pixel. Pixel 3020 includes a transistor 3021, a liquid crystal element 3022, and a capacitor element 3023. The first terminal of transistor 3021 is connected to wiring 3 031, the second terminal of transistor 3021 is connected to one electrode of liquid crystal element 3022 and one electrode of capacitor element 3023, and the gate of transistor 3021 is connected to wiring

[0125] 3032. The other electrode of liquid crystal element 3022 is connected to electrode 3034, and the other electrode of capacitor element 3023 is connected to wiring 3033.

[0126]

[0127]

[0128] ​​​​​​​​​ It is assumed that a video signal is input to the wiring 3031 from the circuit 1002 shown in FIGS. 17(A) to (D). Therefore, the wiring 3031 shall have a function as a video signal line (or also referred to as a source signal line). A gate signal is input to the wiring 3032 from the circuit 1 003_1 and / or the circuit 1003_2 shown in FIGS. 17(A) to (D). Therefore, the wiring 3032 shall have a function as a gate signal line. A constant voltage is supplied to the wiring 3033 and the electrode 3034 from the circuit 1001 shown in FIGS. 17(A) to (D). Therefore, the wiring 3033 shall have a function as a power supply line or a capacitance line. Or, the electrode 3034 shall have a function as a common electrode or a counter electrode. However, an example of this embodiment is not limited thereto. For example, a precharge voltage can be supplied to the wiring 3031. The precharge voltage is often approximately equal to the voltage supplied to the electrode 3034. As another example, a signal can be input to the wiring 3033. Thus, since the voltage applied to the liquid crystal element 3022 can be controlled, the amplitude of the video signal can be reduced or inversion driving can be realized. As another example, a signal can be input to the electrode 3034. Thus, frame inversion driving can be realized. The transistor 3021 shall have a function of controlling the conduction state between the wiring 3031 and one electrode of the liquid crystal element 3022. Or, it shall have a function of controlling the timing for writing a video signal to the pixel. Thus, the transistor 3021 serves as a switch. As another example, a signal can be input to the wiring 3033. Thus, since the voltage applied to the liquid crystal element 3022 can be controlled, the amplitude of the video signal can be reduced or inversion driving can be realized. As another example, a signal can be input to the electrode 3034. Thus, frame inversion driving can be realized. The transistor 3021 shall have a function of controlling the conduction state between the wiring 3031 and one electrode of the liquid crystal element 3022. Or, it shall have a function of controlling the timing for writing a video signal to the pixel. Thus, the transistor 3021 serves as a switch. As another example, a signal can be input to the electrode 3034. Thus, frame inversion driving can be realized.

[0129] The transistor 3021 shall have a function of controlling the conduction state between the wiring 3031 and one electrode of the liquid crystal element 3022. Or, it shall have a function of controlling the timing for writing a video signal to the pixel. Thus, the transistor 3021 serves as a switch. In this way, the transistor 3021 serves as a switch. It shall have such a function. The capacitive element 3023 shall have a function of holding the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Alternatively, it shall have a function of holding the voltage applied to the liquid crystal element 3022 to be constant. As such, the capacitive element 3023 shall have a function as a holding capacitor. The potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033 is held. Or, it has a function of holding the voltage applied to the liquid crystal element 3022 to be constant. In this way, the capacitive element 3023 has a function as a holding capacitor.

[0130] (Embodiment 4) In this embodiment, an example of a semiconductor device and an example of the operation of the semiconductor device will be described. In particular, an example of a signal line driving circuit and an example of the operation of the signal line driving circuit will be described.

[0131] First, an example of the signal line driving circuit of this embodiment will be described.

[0132] FIG. 18(A) shows an example of the signal line driving circuit of this embodiment. The signal line driving circuit shown in FIG. 18(A) shall have the circuit 2001 and the circuit 2002. The circuit 2002 shall have a plurality of circuits called circuits 2002_1 to 2002_N (N is a natural number). The circuits 2002_1 to 2002_N each shall have a plurality of transistors called transistors 2003_1 to 2003_k (k is a natural number). Regarding the connection relationship of the signal line driving circuit of this embodiment, the circuit 2002_1 will be described as an example. The first terminals of the transistors 2003_1 to 2003_k are each connected to the wirings 2004_1 to 2004_k. The second terminals of the transistors 2003_1 to 2003_k are each connected to the wirings S1 to Sk. The gates of the transistors 2003_1 to 2003_k are each connected to the wiring 2005_1. Continue. 1 to 2003_k are each connected to the wirings 2004_1 to 2004_k. The second terminals of the transistors 2003_1 to 2003_k are each connected to the wirings S1 to Sk. The gates of the transistors 2003_1 to 2003_k are each connected to the wiring 2005_1. Continue.

[0133] Note that transistors 2003_1 to 2003_k are of the N-channel type. However, an example of this embodiment is not limited to this. For example, all of transistors 2003_1 to 2003_k can be of the P-channel type. An example of this embodiment is not limited to this. For example, all of transistors 2003_1 to 2003 _k can be of the P-channel type.

[0134] Circuit 2001 has a function of controlling the timing to output H-level signals to wirings 2005_1 to 2005_N in order. Or, it has a function of selecting circuits 2002_1 to 2002_N in order. In this way, circuit 2001 has a function as a shift register. However, an example of this embodiment is not limited to this. For example, circuit 2001 can output H-level signals to wirings 2005_1 to 2005_N in various orders. Or, it can select circuits 2002_1 to 2002_N in various orders. In this way, circuit 2001 can have a function as a decoder. Circuit 2001 has a function as a shift register. However, an example of this embodiment is not limited to this. For example, circuit 2001 can output H-level signals to wirings 2005_1 to 2005_N in various orders. Or, it can select circuits 2002_1 to 2002_N in various orders. In this way, circuit 2001 can have a function as a decoder. Circuit 2001 can output H-level signals to wirings 2005_1 to 2005_N in various orders. Or, it can select circuits 2002_1 to 2002_N in various orders. In this way, circuit 2001 can have a function as a decoder.

[0135] Circuit 2002_1 has a function of controlling the timing when wirings 2004_1 to 2004_k and wirings S1 to Sk are conducting. Or, circuit 2002_1 has a function of controlling the timing to supply the potentials of wirings 2004_1 to 2004_k to wirings S1 to Sk. In this way, circuit 2002_1 can have a function as a selector. Circuit 2002_1 has a function of controlling the timing when wirings 2004_1 to 2 004_k and wirings S1 to Sk are conducting. Or, circuit 2002_1 has a function of controlling the timing to supply the potentials of wirings 2004_1 to 2004_k to wirings S1 to Sk. In this way, circuit 2002_1 can have a function as a selector.

[0136] Note that circuits 2002_2 to 2002_N have the same functions as circuit 2002_1. Let it be so.

[0137] Next, transistors 2003_1 to 2003_N each have a function of controlling the timing when wirings 2004_1 to 2004 _k and wirings S1 to Sk are conducting. Or, the transistor The distributors 2003_1 to 2003_N each have a function of controlling the timing of supplying the potentials of the wirings 2004_1 to 2004_k. For example, the transistor 2 003_1 has a function of controlling the timing when the wiring 2004_1 and the wiring S1 are electrically connected. Alternatively, the transistor 2003_1 has a function of controlling the timing of supplying the potential of the wiring 2004_1 to the wiring S1. In this way, the transistors 2003_1 to 20 03_N can each have a function as a switch.

[0138] Note that signals are often input to the wirings 2004_1 to 2004_k respectively. In particular , the signal is often an analog signal corresponding to image information (also referred to as an image signal). In this way, the signal can have a function as a video signal. Therefore, the wirings 2004_1 to 2004_k can have a function as signal lines. However , an example of this embodiment is not limited to this. For example, depending on the pixel configuration, it can be a digital signal, it can be an analog voltage, or it can be an analog current.

[0139] Next, an example of the operation of the signal line driving circuit shown in FIG. 18(A) will be described.

[0140] FIG. 18(B) shows an example of a timing chart that can be used in the signal line driving circuit of this embodiment. In the timing chart shown in FIG. 18(B), examples of signals 2015_1 to 20 15_N and signals 2014_1 to 2014_k are shown. The signals 2015_1 to 201 5_N are each an example of the output signal of the circuit 2001, and the signals 2014_1 to 2014_ ​k is an example of the signals input to wirings 2004_1 to 2004_k. Note that the operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into a period T0 and periods T1 to TN. The period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row, and is assumed to have a function as a precharge period. Periods T1 to TN are each a period for writing a video signal to the pixels belonging to the selected row, and are assumed to have a function as a writing period.

[0141] First, in period T0, circuit 2001 supplies signals of H level to wirings 2005_1 to 2005_N. Then, for example, in circuit 2002_1, transistors 200 3_1 to 2003_k turn on, so that wirings 2004_1 to 2004_k and wirings S1 to Sk become conductive. At this time, a precharge voltage Vp is supplied to wirings 2004_1 to 2004_k. Thus, the precharge voltage Vp is output to wirings S1 to Sk via transistors 2003_ 1 to 2003_k, respectively. Therefore, the precharge voltage Vp is written to the pixels belonging to the selected row, so that the pixels belonging to the selected row are precharged.

[0142] In periods T1 to TN, circuit 2001 outputs signals of H level to wirings 2005_1 to 2 005_N in order. For example, in period T1, circuit 2001 outputs a signal of H level to wiring 2005_1. Then, transistors 2003_1 to 2003_k turn on, so that wirings 2004_1 to 2004_k and wirings S1 to Sk become conductive. This occurs. At this time, Data(S1) to Data( Sk) are input to the wirings 2004_1 to 2004_k. Data(S1) to Data(Sk) are each, via the transistors 20 03_1 to 2003_k, among the pixels belonging to the selected row, written to the pixels in the 1st column to the k-th column . Thus, in the periods T1 to TN, the video signal is written to the pixels belonging to the selected row , k columns at a time in order.

[0143] As described above, by writing the video signal to the pixels in multiple columns at a time, the number of the video signal or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced, so that the yield can be improved, the reliability can be improved, the number of components can be reduced, and / or the cost can be reduced. Alternatively, by writing the video signal to the pixels in multiple columns at a time, the writing time can be lengthened. Therefore, insufficient writing of the video signal can be prevented, so that the display quality can be improved.

[0144] Note that by increasing k, the number of connections to the external circuit can be reduced. However, if k is too large, the writing time to the pixel becomes short. Therefore, it is preferable that k ≤ 6. More preferably, it is preferable that k ≤ 3. Even more preferably, it is preferable that k = 2. However, an example of this embodiment is not limited thereto.

[0145] In particular, when the number of color elements of the pixel is n (n is a natural number), it is preferable that k = n or k = n × d (d is a natural number). For example, when the color elements of the pixel are divided into three of red (R), green (G), and blue (B), it is preferable that k = 3 or k = 3 × d. However, this embodiment An example of the form is not limited to this. For example, when a pixel is divided into m (m is a natural number) sub-pixels (sub-pixels are also referred to as sub-pixels or auxiliary pixels), it is preferable that k = m or k = m ×d. For example, when a pixel is divided into two sub-pixels, it is preferable that k = 2 . Or, when the color elements of a pixel are n, it is preferable that k = m×n or k = m× n×d. However, an example of this embodiment is not limited to this.

[0146] Note that all of the signal line drive circuits of this embodiment can be formed on the same substrate as the pixel portion, or all of the signal line drive circuits of this embodiment can be formed on a substrate different from the pixel portion (for example, a silicon substrate or an SOI substrate, etc.). Or, a part of the signal line drive circuit of this embodiment (for example, circuit 2002) is formed on the same substrate as the pixel portion, and another part of the signal line drive circuit of this embodiment (for example, circuit 2001) is formed on a substrate different from the pixel portion is possible.

[0147] FIG. 18(C) shows an example of a configuration in the case where circuit 2001 and circuit 2002 are formed on the same substrate as pixel portion 2007. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved, the reliability can be improved, the number of components can be reduced, or the cost can be reduced, etc. In particular, by forming scan line drive circuit 2006A and scan line drive circuit 2 006B also on the same substrate as pixel portion 2007, the number of subsequent connections to the external circuit can be further reduced.

[0148] FIG. 18(D) shows a case where circuit 2002 is formed on the same substrate as pixel portion 2007, and pixel portion 2007 ​​​​​​2 shows an example of a configuration in which the circuit 2001 is formed on a different substrate. This reduces the number of connections between the substrate on which the semiconductor device is formed and the external circuit, improving yields. It is possible to improve reliability, reduce the number of parts, or reduce costs. Since fewer circuits are formed on the same board as the 2007, the frame can be made smaller.

[0149] As the circuit 2001, the semiconductor device of the first or second embodiment can be used. This allows the drive voltage to be reduced, leading to a reduction in power consumption. Alternatively, the polarity of all the transistors can be N-channel, so that the manufacturing process This can lead to improved yields, reduced manufacturing costs, and improved reliability. It is possible to aim higher.

[0150] (Embodiment 5) In this embodiment, an example of a structure of a semiconductor device will be described. An example of the structure will be described.

[0151] First, the structure of a transistor of this embodiment will be described.

[0152] FIG. 19A shows an example of a top-gate transistor and a display element formed thereon. The transistor shown in FIG. 19A includes a substrate 5260 and an insulating layer 5261. and regions 5262a, 5262b, 5262c, 5262d, and 5262 a semiconductor layer 5262 having an opening 5264; an insulating layer 5263; a conductive layer 5264; The insulating layer 5261 is disposed on the substrate 5260. The semiconductor layer 5262 is formed on the insulating layer 5261. The insulating layer 5263 is is formed to cover the semiconductor layer 5262. The conductive layer 5264 is formed on the semiconductor layer 5262 and the insulating layer 5263. The insulating layer 5265 is formed on the insulating layer 5263 and the conductive layer 526 4. The conductive layer 5266 is formed on the insulating layer 5265 and in the opening of the insulating layer 5265 . Thus, a top-gate type transistor is formed.

[0153] FIG. 19(B) shows an example of a bottom-gate type transistor and an example of a display element formed thereon. The transistor shown in FIG. 19(B) includes a substrate 5300, a conductive layer 5301, an insulating layer 5302, a semiconductor layer 5303a, a semiconductor layer 5303b, a conductive layer 5304, an insulating layer 5305 having an opening, and a conductive layer 5306. The conductive layer 5301 is formed on the substrate 5300. The insulating layer 5302 is formed to cover the conductive layer 5301. The semiconductor layer 5303a is formed on the conductive layer 5301 and the insulating layer 5302. The semi- conductor layer 5303b is formed on the semiconductor layer 5303a. The conductive layer 5304 is formed on the semiconductor layer 5303b and on the insulating layer 5302. The insulating layer 5305 is formed on the insulating layer 5302 and on the conductive layer 5304. The conductive layer 5306 is formed on the insulating layer 5305 and in the opening of the insulating layer 5305. Thus, a bottom-gate type transistor is formed.

[0154] FIG. 19(C) shows an example of a transistor formed on a semiconductor substrate. The transistor shown in FIG. 19(C) includes a semiconductor substrate 5352 having regions 5353 and 5355, an insulating layer 5356, an insulating layer 5354, a conductive layer 5357, and an insulating layer 5358 having an opening. and a conductive layer 5359. The insulating layer 5356 is formed on the semiconductor substrate 5352. The ins ulating layer 5354 is formed on the semiconductor substrate 5352. The conductive layer 5357 is formed on the insulating layer 53 56. The insulating layer 5358 is formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357. The conductive layer 5359 is formed on the insulating layer 5358 and in the opening of the insulating layer 5358 . In this way, transistors are fabricated in the regions 5350 and 5351, respectively.

[0155] In addition, in the transistor shown in FIGS. 19(A) to (C), as shown in FIG. 19(A), an insulating layer 5267 having an opening, a conductive layer 5268, an insulating layer 5269 having an opening, a light-emitting layer 5270, and a conductive layer 5271 can be formed on the transistor. The insulating layer 5267 is formed on the conductive layer 5266 and on the insulating layer 5265. The conductive layer 5268 is formed on the insulating layer 5267 and in the opening of the insulating layer 5267. The insulating layer 5 269 is formed on the insulating layer 5267 and on the conductive layer 5268. The light-emitting layer 5270 is formed on the insulating layer 5269 and in the opening of the insulating layer 5269. The conductive layer 5271 is formed on the insulating layer 5269 and on the light-emitting layer 5270.

[0156] In addition, in the transistor shown in FIGS. 19(A) to (C), as shown in FIG. 19(B), a liquid crystal layer 5307 and a conductive layer 5308 can be formed on the transistor. The liquid crystal layer 5307 is disposed on the insulating layer 5305 and on the conductive layer 5306. The conductive layer 5308 is formed on the liquid crystal layer 5307.

[0157] In addition to the layers shown in FIGS. 19(A) to (C), various other layers can be formed. For example, on the insulating layer 5305 and on the conductive layer 5306, an insulating layer having a function as an alignment film and / or an insulating layer having a function as a protrusion can be formed. As another example, on the conductive layer 5308, an insulating layer functioning as a protrusion, a color filter and / or a black matrix can be formed. As another example, under the conductive layer 5308, an insulating layer having a function as an alignment film can be formed.

[0158] Note that the regions 5262c and 5262e are regions where impurities are added and are assumed to function as a source region or a drain region. The regions 5262b and 5262 d are regions where impurities are added at a lower concentration than in the region 5262c or the region 5262e and are assumed to function as a lightly doped drain (LDD) region. The region 5262a is a region where no impurities are added and has a function as a channel region. However, an example of this embodiment is not limited to this. For example, it is possible to add impurities to the region 5262 a. In this way, the characteristics of the transistor can be improved and the control of the threshold voltage and the like can be performed. However, the concentration of the impurities added to the region 5262a is preferably lower than the concentration of the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e . As another example, it is possible to omit the region 5262e from the region 5262c. Or, it is possible to provide only the region 5262c or the region 5262e in an N-channel type transistor.

[0159] ​Note that the semiconductor layer 5303b is a semiconductor layer doped with impurity elements such as phosphorus, and is assumed to have an n-type conductivity type. However, when an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, the semiconductor layer 5303b can be omitted.

[0160] As an example of the semiconductor substrate (for example, the semiconductor substrate 5352), a single crystal Si substrate having an n-type or p-type conductivity type can be used. And the region 5353 is a region where impurities are added to the semiconductor substrate 5352 and is assumed to have a function as a well. For example, when the semiconductor substrate 5352 has a p-type conductivity type, the region 5353 has an n-type conductivity type On the other hand, for example, when the semiconductor substrate 5352 has an n-type conductivity type , the region 5353 has a p-type conductivity type. The region 5355 is a region where impurities are added to the semiconductor substrate 5352 and is assumed to have a function as a source region or a drain region. Note that an LDD region can be formed on the semiconductor substrate 5352.

[0161] Next, an example of the function of each layer will be described.

[0162] The insulating layer 5261 is assumed to have a function as an underlayer film. The insulating layer 5354 is assumed to have a function as an element isolation layer (for example, a field oxide film). The insulating layers 5263, the insulating layer 5302, and the insulating layer 5356 are assumed to have a function as a gate insulating film. The conductive layers 5264, 5301, and 5357 are assumed to have a function as gate electrodes. The insulating layers 5265, 5267, 5305, and 5358 have a function as an interlayer film or a planarization film. The conductive layers 5266, 530 4 and the conductive layer 5359 shall have functions such as wiring, electrodes of transistors, or electrodes of capacitor elements. The conductive layer 5268 and the conductive layer 5306 shall have functions as pixel electrodes or reflective electrodes. The insulating layer 5269 shall have a function as a partition wall. The conductive layer 5271 and the conductive layer 5308 shall have functions as counter electrodes or common electrodes. However, an example of this embodiment is not limited thereto.

[0163] Next, materials, structures, or features of each layer will be described.

[0164] First, as an example of the substrate (for example, substrate 5260 or substrate 5300), there are a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. As an example of the glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or synthetic resins having flexibility such as acrylic. As an example of the laminated film, there are polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride. As an example of the base film, there are polyester, polyamide, polyimide, an inorganic vapor deposition film, or papers. In particular, a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc. ​​​​​​​​​​​By manufacturing transistors using [a certain method], variations such as in characteristics, size, or shape can be reduced, and transistors with high current capacity and small size can be manufactured. When circuits are configured using such transistors, power consumption of the circuits can be reduced, or high integration of the circuits can be achieved.

[0165] Note that it is possible to form transistors on a certain substrate and then transfer the transistors to another substrate. Examples of such another substrate include, in addition to the above-mentioned substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrate, or rubber substrate. By using these substrates, formation of transistors with good characteristics, formation of transistors with low power consumption, manufacture of a device that is difficult to break, imparting heat resistance, weight reduction, or thickness reduction can be achieved.

[0166] Note that it is possible to form all the circuits necessary to realize a predetermined function on the same substrate (for example, glass substrate, plastic substrate, single crystal substrate, or SOI substrate, etc.). In this way, cost reduction by reducing the number of parts, or improvement of

[0167] reliability by reducing the number of connection points with circuit components can be achieved. Note that it is also possible not to form all the circuits necessary to realize a predetermined function on the same substrate. That is, a part of the circuits necessary to realize a This is possible. For example, a part of the circuit necessary to realize a predetermined function is formed on a glass substrate, and another part of the circuit necessary to realize a predetermined function can be formed on a single crystal substrate (or an SOI substrate). Then, a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary to realize a predetermined function is formed is connected to the glass substrate by COG (Chip On Glass), and the IC chip can be arranged on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board, etc. A part of the circuit necessary to realize a predetermined function is formed on a glass substrate, and another part of the circuit necessary to realize a predetermined function can be formed on a single crystal substrate (or an SOI substrate). (or an SOI substrate). And, a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary to realize a predetermined function is formed is connected to the glass substrate by COG ( Chip On Glass), and the IC chip can be arranged on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Aut omated Bonding), COF (Chip On Film), SMT (Su rface Mount Technology), or a printed circuit board, etc. omated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board, etc. rface Mount Technology), or a printed circuit board, etc. rface Mount Technology), or a printed circuit board, etc.

[0168] Next, as an example of an insulating layer (for example, insulating layer 5261, insulating layer 5263, insulating layer 5265, insulating layer 526 7, insulating layer 5269, insulating layer 5305, insulating layer 5356, and insulating layer 5358), there are single-layer structures such as films containing oxygen or nitrogen (for example, silicon oxide (SiOx), silicon nitride (SiNx) , silicon oxynitride (SiOxNy) (x > y > 0), silicon nitride oxide (SiNxOy) (x > y > 0), etc.), films containing carbon (for example, DLC (diamond-like carbon), etc.), organic materials (for example, siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol ol, benzocyclobutene, or acrylic, etc.), or laminated structures of these, etc. However, an example of this embodiment is not limited to this. ol, benzocyclobutene, or acrylic, etc.), or laminated structures of these, etc. However, an example of this embodiment is not limited to this. ol, benzocyclobutene, or acrylic, etc.), or laminated structures of these, etc. However, an example of this embodiment is not limited to this.

[0169] When the insulating layer has a two-layer structure, a silicon nitride film is provided as the first insulating layer, and the second It is preferable to provide a silicon oxide film as the insulating layer. When the insulating layer has a three-layer structure, a silicon oxide film is provided as the first insulating layer and a silicon nitride film is provided as the second insulating layer, and a silicon oxide film is provided as the third insulating layer.

[0170] Next, as an example of the semiconductor layer (for example, semiconductor layer 5262, semiconductor layer 5303a, and semiconductor layer 5303b etc.), there are non-crystalline semiconductors (for example, amorphous silicon, poly crystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconduct uctors (for example, ZnO, InGaZnO, SiGe, GaAs, IZO (indium zinc oxide ide), ITO (indium tin oxide), SnO, TiO, AlZnSnO (AZTO) etc.), organic semiconductors, or carbon nanotubes.

[0171] When manufacturing polycrystalline silicon or microcrystalline silicon, by using a catalyst (such as nickel) the crystallinity can be further improved, and a transistor with good electrical characteristics can be manufactured. Therefore, a gate driver circuit (scan line driving circuit), a source driver circuit (signal line driving circuit), a part of the source driver circuit (for example, a switch for video signal splitting, etc. ) and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on a substrate. In particular, when manufacturing microcrystalline silicon using a catalyst (such as nickel) it is possible to improve the crystallinity only by applying heat treatment without performing laser irradiation. Therefore, unevenness in the crystallinity of silicon can be suppressed, and an image with improved image quality can be displayed. However, it is possible to manufacture polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel). ​​

[0172] Note that improving the crystallinity of silicon to polycrystalline or microcrystalline, etc., is preferably done for the entire panel, but is not limited thereto. The crystallinity of silicon may be improved only in a partial region of the panel. Selectively improving the crystallinity can be achieved by selectively irradiating with laser light, etc. For example, in regions other than pixels such as the peripheral circuit region, regions such as the gate driver circuit and the source driver circuit, or a part of the source driver circuit (e.g., analog switch), etc., laser light can be irradiated to regions where it is necessary to operate the circuit at high speed. On the other hand, since the pixel region has little need to operate at high speed, the pixel circuit can operate without problems even if the crystallinity is not improved. In this way, since the region where the crystallinity needs to be improved can be reduced, the manufacturing process can also be shortened. Therefore, the throughput can be improved and the manufacturing cost can be reduced. Or, since the number of manufacturing apparatuses required can also be reduced to a small number, the manufacturing cost can be reduced. Next, as an example of the conductive layer (e.g., conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 527 1, conductive layer 5301, conductive layer 5304, conductive layer 5306, and conductive layer 5308, conductive layer 5 357, and conductive layer 5359, etc.), there is a single-layer film or its laminated structure, etc.

[0173] As an example of the single-layer film, there is aluminum (Al), tantalum (Ta), titanium (Ti) , molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn) . , etc. , cobalt (Co), niobium (Nb), silicon (Si), iron (Fe), palladium (P d), carbon (C), scandium (Sc), zinc (Zn), gallium (Ga), indium ium (In), tin (Sn), zirconium (Zr), cerium (Ce) and the like. There are also compounds containing one element selected from this group, one or more elements selected from this group, etc. As another example of the single-element film, there are nanotube materials (such as carbon nanotubes, organic nanotubes, inorganic nanotubes or metal nanotubes), films including high molecular films, or conductive plastics (such as polyethylene dioxythiophene (P EDOT), etc.). Note that the single-element film may contain phosphorus (P), boron (B), arsenic (A s), and / or oxygen (O), etc. In addition, as an example of the compound, there are compounds containing one element or a plurality of elements selected from the above group (such as alloys), compounds of one element or a plurality of elements selected from the above group and nitrogen (such as nitride films), or compounds of one element or a plurality of elements selected from the above group and silicon (such as silicide films), etc. As an example of the alloy, there are indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-

[0174] W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum nickel um (Mo-Ni), etc. As an example of the alloy, there are indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al- W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum nickel um (Mo-Ni), etc. aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum nickel B (Mo-Nb), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo- Ta), etc. Examples of nitride films include titanium nitride, tantalum nitride, molybdenum nitride , etc. Examples of silicide films include tungsten silicide, titanium silicide , nickel silicide, aluminum silicon, molybdenum silicon, etc.

[0175] Next, as an example of the light-emitting layer (e.g., 5270), there are an organic EL element, an inorganic EL element, etc. Examples of organic EL elements include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed , or a laminated structure of these, etc.

[0176] Next, as an example of the liquid crystal layer 5307, there is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be structured by a pair of electrodes and a liquid crystal layer . Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field or an oblique electric field). Specifically, examples of liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal , thermotropic liquid crystal, lyotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main-chain liquid crystal, side-chain high-molecular liquid crystal, plasma addressed liquid crystal (PALC), banana-type liquid crystal, etc. Also, as the driving method of liquid crystal, there are TN (Twisted Nematic) mode, STN (Super Twisted Nematic mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axially Symmetrically aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, FLCD (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, Blue Phase mode, etc. ng) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (A dvanced Super View) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB (Opticall y Compensated Birefringence) mode, ECB (Elec trically Controlled Birefringence) mode, FL CD (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, P NLC (Polymer Network Liquid Crystal) mode, gel host mode, Blue Phase mode, etc.

[0177] Each layer constituting the above transistor can be formed using an inkjet method or a printing method. Thus, it can be manufactured at room temperature, at low vacuum, or on a large substrate. Therefore, it is possible to manufacture without using a mask (reticle), so that the layout of the transistor can be easily changed. Or, since it is possible to manufacture without using a resist, the material cost can be reduced and the number of processes can be reduced. Or, since it is possible to attach a film only to the necessary parts, it can be made at a lower cost without wasting materials compared to the manufacturing method of etching after forming a film over the entire surface.

[0178] Above, an example of the structure of a transistor has been described. However, the structure of the transistor is not limited to the above-described structure, and various other structures are possible.

[0179] For example, as the transistor, a MOS transistor, a junction transistor, a bipolar transistor, etc. can be used. In particular, by using a MOS transistor as the transistor, the size of the transistor can be reduced. In particular, by using a bipolar transistor as the transistor, a large current can be passed. Therefore, the circuit can operate at high speed.

[0180] As another example, the transistor can have a structure in which gate electrodes are disposed above and below the channel. By adopting a structure in which gate electrodes are disposed above and below the channel, a circuit configuration is formed in which a plurality of transistors are connected in parallel. Therefore, since the channel area increases, an increase in the current value can be achieved. Or, by adopting a structure in which gate electrodes are disposed above and below the channel, since a depletion layer is likely to be formed, an improvement in the S value can be achieved.

[0181] As another example, the transistor has a structure in which a gate electrode is disposed above the channel region, a structure in which a gate electrode is disposed below the channel region, a normal stagger structure, an inverse stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a channel The structure can be such that the Ru regions are connected in series.

[0182] As another example, the transistor can have a structure in which a source electrode and a drain electrode overlap with the channel region (or a part thereof). By adopting a structure in which a source electrode and a drain electrode overlap with the channel region (or a part thereof), it is possible to prevent the operation from becoming unstable due to the accumulation of charges in a part of the channel region. )

[0183] The transistor of the present embodiment can be used in the semiconductor device or the display device of Embodiments 1 to 4.

[0184] (Embodiment 6) In the present embodiment, an example of the cross-sectional structure of the display device will be described.

[0185] FIG. 20(A) shows an example of a top view of the display device. A driving circuit 5392 and a pixel portion 5393 are formed on a substrate 5391. As an example of the driving circuit 5392, there is a scanning line driving circuit or a signal line driving circuit.

[0186] FIG. 20(B) shows an example of the A - B cross-section of the display device shown in FIG. 20(A). The display device is assumed to include a substrate 5400, a conductive layer 5401, an insulating layer 5402, a semiconductor layer 5403a, a semiconductor layer 540 3b, a conductive layer 5404, an insulating layer 5405, a conductive layer 5406, an insulating layer 5408, a liquid crystal layer 54 07, a conductive layer 5409, and a substrate 5410. The conductive layer 5401 is formed on the substrate 54 00. The insulating layer 5402 is formed so as to cover the conductive layer 5401. The semiconductor layer 5403a is formed on the conductive layer 5401 and the insulating layer 5402. It is assumed to be formed. The semiconductor layer 5403b is formed on the semiconductor layer 5403a It is assumed to be formed on the semiconductor layer 5403b and on the insulating layer 5402 The insulating layer 5405 is formed on the insulating layer 5402 and on the conductive layer 5404 It is assumed to have an opening. The conductive layer 5406 is formed on the insulating layer 5405 and in the opening of the insulating layer 5405 The liquid crystal layer 5407 is formed on the insulating layer 5405 The insulating layer 5408 is formed on the insulating layer 5405 and on the conductive layer 5406 The conductive layer 5409 is formed on the liquid crystal layer 5407 and on the insulating layer 5405 It is assumed to be formed.

[0187] The conductive layer 5401 is assumed to have a function as a gate electrode. The insulating layer 5402 is assumed to have a function as a gate insulating film. The conductive layer 5404 is assumed to have a function as a wiring, an electrode of a transistor, or an electrode of a capacitor element. The insulating layer 5405 is assumed to have a function as an interlayer film or a planarization film. The conductive layer 5406 is assumed to have a function as a wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 is assumed to have a function as a sealing material. The conductive layer 5409 is assumed to have a function as a counter electrode or a common electrode. Here, a parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409 As a result, a distortion or a delay may occur in the output signal of the drive circuit 5392 or the potential of each node. Therefore, the power consumption may increase. However, as shown in Fig. 20(B), an insulating layer having a function as a sealing material is formed on the drive circuit 5392 The insulating layer 5405 is assumed to have a function as an interlayer film or a planarization film. The conductive layer 5406 is assumed to have a function as a wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 is assumed to have a function as a sealing material. The conductive layer 5409 is assumed to have a function as a counter electrode or a common electrode. Here, a parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409 As a result, a distortion or a delay may occur in the output signal of the drive circuit 5392 or the potential of each node. Therefore, the power consumption may increase. However, as shown in Fig. 20(B), an insulating layer having a function as a sealing material is formed on the drive circuit 5392 It is assumed to be formed.

[0188] Here, a parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409 As a result, a distortion or a delay may occur in the output signal of the drive circuit 5392 or the potential of each node. Therefore, the power consumption may increase. However, as shown in Fig. 20(B), an insulating layer having a function as a sealing material is formed on the drive circuit 5392 Here, a parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409 As a result, a distortion or a delay may occur in the output signal of the drive circuit 5392 or the potential of each node. Therefore, the power consumption may increase. However, as shown in Fig. 20(B), an insulating layer having a function as a sealing material is formed on the drive circuit 5392 By forming 5408, the parasitic capacitance generated between the drive circuit 5392 and the conductive layer 5409 can be reduced. This is because the dielectric constant of the sealing material is often lower than that of the liquid crystal layer. Therefore, the smear or delay of the output signal of the drive circuit 5392 or the potential of each node can be reduced. As a result, the power consumption can be reduced. In addition, as shown in FIG. 20(C), an insulating layer 5408 that can function as a sealing material can be formed on a part of the drive circuit 5392. Even in such a case, the parasitic capacitance generated between the drive circuit 5392 and the conductive layer 5409 can be reduced, and the smear or delay of the output signal of the drive circuit 5392 or the potential of each node can be reduced. It should be noted that the display element is not limited to a liquid crystal element, and various display elements such as an EL element or an electrophoretic element can be used. It should be noted that the structure of the display device according to the present embodiment can be applied to the semiconductor device or the display device of Embodiments 1 to 5. For example, when using a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer of the transistor, the channel width of the transistor often becomes large. However, if the parasitic capacitance of the drive circuit can be reduced as in the present embodiment, the channel width of the transistor can be reduced. Therefore, the layout area can be reduced, and the display device can be made into a narrow bezel. Or the display device can be made into high definition.

[0189]

[0190]

[0191]

[0192] (Embodiment 7) In this embodiment, an example of a semiconductor device and an example of a manufacturing process of the semiconductor device will be described. . In particular, an example of a manufacturing process of a transistor and an example of a manufacturing process of a capacitive element will be described. In particular, a manufacturing process in the case where an oxide semiconductor is used as the semiconductor layer will be described.

[0193] FIGS. 21(A) to (C) show an example of a manufacturing process of a transistor and a capacitive element. The trans istor 5441 is a reverse staggered thin film transistor, and wiring is provided on the oxide semiconductor layer via a source electrode or a drain electrode.

[0194] First, a first conductive layer is formed over the entire surface of the substrate 5420 by sputtering. Next, using a resist mask formed by a photolithography process using a first photomask, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 5422 can function as one electrode of the capacitive element. However, it is not limited thereto. The conductive layer 5421 and the conductive layer 5422 can have portions that function as wiring, a gate electrode, or an electrode of the capacitive element. After that, the resist mask is removed.

[0195] Next, an insulating layer 5423 is formed over the entire surface using plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer and is formed to cover the conductive layer 5421 and the conductive layer 5422. Note that the film thickness of the insulating layer 5423 is often 50 nm to 250 nm.

[0196] Next, a resist mask formed by a photolithography process using a second photomask is used to selectively etch the insulating layer 5423 to reach the conductive layer 5421 and form a contact hole 5424. After that, the resist mask is removed. However, it is not limited to this, and the contact hole 5424 can be omitted. Alternatively, the contact hole 5424 can be formed after the formation of the oxide semiconductor layer. The cross-sectional view up to this stage corresponds to FIG. 21(A).

[0197] Next, an oxide semiconductor layer is formed over the entire surface by a sputtering method. However, it is not limited to this, and an oxide semiconductor layer can be formed by a sputtering method, and further a buffer layer (e.g., an n + layer) can be formed thereon. Note that the film thickness of the oxide semiconductor layer is often 5 nm to 2 00 nm.

[0198] Next, the oxide semiconductor layer is selectively etched using a third photomask. After that the resist mask is removed.

[0199] Next, a second conductive layer is formed over the entire surface by a sputtering method. Next, a resist mask formed by a photolithography process using a fourth photomask is used to selectively etch the second conductive layer to form a conductive layer 5429, a conductive layer 5430, and a conductive layer 5431 . The conductive layer 5429 is connected to the conductive layer 5421 through the contact hole 5424 . The conductive layers 5429 and 5430 can function as a source electrode or a drain electrode , and the conductive layer 5431 can function as the other electrode of the capacitive element . However, it is not limited to this, and the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 may include portions that function as wiring, source or drain electrodes, or electrodes of a capacitor element. The cross-sectional view at this stage corresponds to FIG. 21(B).

[0200] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. This heat treatment rearranges the atoms of the In-Ga-Zn-O-based amorphous layer at the atomic level. In this way, strains that inhibit the movement of carriers are released by the heat treatment (including photo annealing). Note that the timing of performing this heat treatment is not limited, and it can be performed at various timings as long as it is after the formation of the oxide semiconductor.

[0201] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 can be a single-layer structure or a laminated structure. For example, when an organic insulating layer is used as the insulating layer 5432, a composition that is a material of the organic insulating layer is applied, and a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere to form the organic insulating layer. In this way, by forming an organic insulating layer in contact with the oxide semiconductor layer, a thin-film transistor with high electrical property reliability can be fabricated. Note that when an organic insulating layer is used as the insulating layer 5432, it is possible to provide a silicon nitride film or a silicon oxide film under the organic insulating layer.

[0202] Next, a third conductive layer is formed over the entire surface. Next, the third conductive layer is selectively etched using a resist mask formed by a photolithography process using a fifth photomask to form a conductive layer 5433 and a conductive layer 5434. The cross-sectional view at this stage corresponds to FIG. 21(C). corresponds to. The conductive layer 5433 and the conductive layer 5434 can function as wiring, a pixel electrode, a reflective electrode, a translucent electrode, or an electrode of a capacitive element. In particular, since the conductive layer 5434 is connected to the conductive layer 5422, it can function as an electrode of the capacitive element 5442. However, it is not limited to this, and it is possible to have a function of connecting the first conductive layer and the second conductive layer. For example, by connecting the conductive layer 5433 and the conductive layer 5434, the conductive layer 5422 and the conductive layer 5430 can be connected via a third conductive layer (the conductive layer 5433 and the conductive layer 5434).

[0203] Through the above steps, the transistor 5441 and the capacitive element 5442 can be fabricated. The transistor of this embodiment can be used in the semiconductor device or display device of Embodiments 1 to 8.

[0204] Note that, as shown in FIG. 21(D), an insulating layer 5435 can be formed over the oxide semiconductor layer 5425.

[0205] Note that, as shown in FIG. 21(E), the oxide semiconductor layer 5425 can be formed after patterning the second conductive layer.

[0206] Note that as the substrate, insulating layer, conductive layer, and semiconductor layer of this embodiment, the materials described in other embodiments or this specification can be used.

[0207] (Embodiment 8) In this embodiment, an example of an electronic device will be described.

[0208] FIGS. 22(A) to 22(H) and FIGS. 23(A) to 23(D) are diagrams showing an electronic device. ​​​​Yes. These electronic devices can have a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, a sensor 5007 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 5008, etc.

[0209] Figure 22(A) is a mobile computer and, in addition to the above-described components, can have a switch 5009, an infrared port 5010, etc. Figure 22(B) is a portable image playback device equipped with a recording medium (for example, a DVD playback device) and, in addition to the above-described components, can have a second display unit 5002, a recording medium reading unit 5011, etc. Figure 22(C) is a goggle type display and, in addition to the above-described components, can have a second display unit 5002, a support unit 5012, earphones 5013, etc. Figure 22(D) is a portable game machine and, in addition to the above described components, can have a recording medium reading unit 5011, etc. Figure 22(E) is a digital camera with a television reception function and, in addition to the above-described components, can have an antenna 5014, a shutter button 5015, an image receiving unit 5016, etc. Figure 22(F) is a portable game machine and, in addition to the above-described components, can have a second display unit 5002, a recording medium reading unit 5011, etc. Figure 22(G) is a television receiver and, in addition to the above-described components, can have a tuner, an image processing unit, etc. Figure 22(H) is a portable television receiver and, in addition to the above-described components, can have a charger 5017 capable of transmitting and receiving signals, etc. ​​​ It can be. Figure 23(A) is a display, and in addition to what has been described above, it can have a support base 5018, etc. It can be. Figure 23(B) is a camera, and in addition to what has been described above, it can have an external connection port 5019, a shutter button 5015, an imaging unit 5016, etc. Figure 23(C) is a computer, and in addition to what has been described above, it can have a pointing device 5020, an external connection port 5019, a reader / writer 5021, etc. Figure 23(D) is a mobile phone, and in addition to what has been described above, it can have a transmission unit, a reception unit, a tuner for a one-segment partial reception service for mobile phones / mobile terminals, etc.

[0210] The electronic devices shown in FIGS. 22(A) to 22(H) and FIGS. 23(A) to 23(D) can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be provided. Further, in an electronic device having a plurality of display units, a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or a function of displaying a three-dimensional image by displaying an image considering parallax on a plurality of display units, etc. can be provided. Further, in an electronic device having an imaging unit, functions such as a function of taking a still image, a function of taking a moving image, taking A function to automatically or manually correct the captured image, a function to save the captured image to a recording medium (external or built-in to the camera), a function to display the captured image on a display unit, etc. can be provided. Note that the functions that the electronic device can have are not limited to these, and it can have various functions. In addition, the electronic device shown in FIGS. 22(A) to 22(H) and FIGS. 23(A) to 23(D) Note that the functions that the electronic device can have are not limited to these, and it can have various functions.

[0211] The electronic device described in this embodiment is characterized by having a display unit for displaying some information. By using the semiconductor device or display device described in Embodiments 1 to 9 as this display unit, it is possible to achieve cost reduction in manufacturing, improvement in reliability, or improvement in yield. By using the semiconductor device or display device described in Embodiments 1 to 9 as this display unit, it is possible to achieve cost reduction in manufacturing, improvement in reliability, or improvement in yield. etc.

[0212] Next, application examples of the semiconductor device will be described.

[0213] FIG. 23(E) shows an example in which the semiconductor device is provided integrally with a building. FIG. 23(E) includes a housing 5022, a display unit 5023, a remote control device 5024 which is an operation unit, a speaker 5 025, etc. The semiconductor device is wall-mounted and integrated with the building, and can be installed without requiring a large installation space. without requiring a large installation space.

[0214] FIG. 23(F) shows another example in which the semiconductor device is provided integrally with a building inside the building. The display panel 5026 is attached integrally with the unit bus 5027, and a bather can view the display panel 5026.

[0215] In this embodiment, a wall and a unit bus are taken as examples of the building, but this embodiment is not limited to this, and the semiconductor device can be installed in various buildings. In this embodiment, a wall and a unit bus are taken as examples of the building, but this embodiment is not limited to this, and the semiconductor device can be installed in various buildings.

[0216] Next, an example in which the semiconductor device is provided integrally with a moving body will be described.

[0217] FIG. 23(G) is a diagram showing an example in which the semiconductor device is provided in an automobile. Display panel 5028 is attached to the vehicle body 5029 of the automobile, and can display on demand the operation of the vehicle body or information input from inside and outside the vehicle body. Note that it may have a navigation function.

[0218] FIG. 23(H) is a diagram showing an example in which the semiconductor device is provided integrally with a passenger airplane. FIG. 23(H) is a diagram showing the shape during use when the display panel 5031 is provided on the ceiling 5030 above the seat of the passenger airplane. The display panel 5031 is integrally attached to the ceiling 5030 via the hinge portion 5032, and the passenger can view the display panel 5031 by the expansion and contraction of the hinge portion 5032. The display panel 5031 has a function of displaying information by being operated by the passenger.

[0219] In the present embodiment, examples of the moving body include an automobile body and an airplane fuselage, but the present invention is not limited thereto, and it can be installed on various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, and the like.

Description of Reference Numerals

[0220] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring ​​​​​​​​​25 Wiring 26 Wiring 27 Wiring 31 Wiring 32 Wiring 33 Wiring 34 Wiring 35 Wiring 36 Wiring 37 Wiring 38 Wiring 100 Circuit 110 Circuit 111 Transistor 112 Transistor 120 Circuit 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Capacitor Element 126 Capacitor Element 13B Wiring 16A Wiring 16B Wiring 16C Wiring 300 Circuit 310 Circuit 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Transistor 316 Transistor 317 Transistor 318 Transistor 319 Transistor 400 Circuit 401 Circuit 500 Circuit 501 Circuit 502 Circuit 1001 Circuit 1002 Circuit 1003 Circuit 1004 Pixel Section 1005 Terminal 1006 Substrate 111d Diode 2001 Circuit 2002 Circuit 2003 Transistor 2004 Wiring 2005 Wiring 2007 Pixel Section 2014 Signal 2015 Signal 3020 Pixel 3021 Transistor 3022 Liquid Crystal Element 3023 Capacitive Element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 5000 Housing 5001 Display Section 5002 Display Section 5003 Speaker 5004 LED Lamp 5005 Operation Key 5006 Connection Terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording Medium Reader 5012 Support Section 5013 Earphone 5014 Antenna 5015 Shutter Button 5016 Image Receiving Section 5017 Charger 5018 Support Stand 5019 External Connection Port 5020 Pointing Device 5021 Reader / Writer 5022 Housing 5023 Display Section 5024 Remote Control Device 5025 Speaker 5026 Display Panel 5027 Unit Bus 5028 Display Panel 5029 Vehicle Body 5030 Ceiling 5031 Display panel 5032 Hinge part 5260 Substrate 5261 Insulating layer 5262 Semiconductor layer 5263 Insulating layer 5264 Conductive layer 5265 Insulating layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulating layer 5270 Light-emitting layer 5271 Conductive layer 5300 Substrate 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulating layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 Region 5351 Region 5352 Semiconductor substrate 5353 Region 5354 Insulating layer 5355 Region 5356 Insulating layer 5357 Conductive layer 5358 Insulating layer 5359 Conductive layer 5391 Substrate 5392 Driving circuit 5393 Pixel part 5400 Substrate 5401 Conductive layer 5402 Insulating layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulating layer 5409 Conductive layer 5410 Substrate 5420 Substrate 5421 Conductive layer 5422 Conductive layer 5423 Insulating layer 5424 Contact hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulating layer 5433 Conductive layer 5434 Conductive layer 5435 Insulating layer 5441 Transistor 5442 Capacitor element 1002a Circuit 1002b Circuit 2006A Scanning line drive circuit 2006B Scanning line drive circuit 5262a Region 5262b Region 5262c Region 5262d Region 5262e Region 5303a Semiconductor layer 5303b Semiconductor layer 5403a Semiconductor layer 5403b Semiconductor layer

Claims

1. A semiconductor device comprising first to sixth transistors and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; the gate of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the first wiring outputs a first signal; the second wiring has a function as a power supply line or a signal line, a first potential is supplied to the third wiring; a second signal is supplied to the fourth wiring; a second potential higher than the first potential is supplied to the fifth wiring; a third signal is supplied to the sixth wiring; when the third wiring is electrically connected to the gate of the first transistor via at least a channel formation region of the fourth transistor, the first potential is supplied to the gate of the first transistor via at least a channel formation region of the fourth transistor; when a potential of the second signal is supplied to a gate of the sixth transistor, the sixth transistor is brought into a conductive state or a non-conductive state according to the potential of the second signal; the fifth transistor has a function of controlling timing for increasing the potential of the gate of the second transistor and the potential of the gate of the fourth transistor; Semiconductor device.

2. A semiconductor device comprising first to sixth transistors and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; the gate of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the first wiring outputs a first signal; the second wiring has a function as a power supply line or a signal line, a first potential is supplied to the third wiring; a second signal is supplied to the fourth wiring; a second potential higher than the first potential is supplied to the fifth wiring; a third signal is supplied to the sixth wiring; when the third wiring is electrically connected to the gate of the first transistor via at least a channel formation region of the fourth transistor, the first potential is supplied to the gate of the first transistor via at least a channel formation region of the fourth transistor; when a potential of the second signal is supplied to a gate of the sixth transistor, the sixth transistor is brought into a conductive state or a non-conductive state according to the potential of the second signal; the fifth transistor has a function of controlling timing for increasing potentials of the gates of the second transistor and the fourth transistor; When the second transistor, the third transistor, and the fourth transistor are in a non-conductive state, the first transistor is in a conductive state, thereby increasing the potential of the first wiring. Semiconductor device.

3. A semiconductor device comprising first to sixth transistors and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; the gate of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the first wiring outputs a first signal; the second wiring has a function as a power supply line or a signal line, a first potential is supplied to the third wiring; a second signal is supplied to the fourth wiring; a second potential higher than the first potential is supplied to the fifth wiring; a third signal is supplied to the sixth wiring; when the third wiring is electrically connected to the gate of the first transistor via at least a channel formation region of the fourth transistor, the first potential is supplied to the gate of the first transistor via at least a channel formation region of the fourth transistor; when a potential of the second signal is supplied to a gate of the sixth transistor, the sixth transistor is brought into a conductive state or a non-conductive state according to the potential of the second signal; the fifth transistor has a function of controlling timing for increasing potentials of the gates of the second transistor and the fourth transistor; a period in which the level of the potential supplied to the fourth wiring and the level of the potential supplied to the sixth wiring are inverted to each other; Semiconductor device.

4. A semiconductor device comprising first to sixth transistors and first to sixth wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the third wiring; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; the gate of the third transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the third wiring; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the first wiring outputs a first signal; the second wiring has a function as a power supply line or a signal line, a first potential is supplied to the third wiring; a second signal is supplied to the fourth wiring; a second potential higher than the first potential is supplied to the fifth wiring; a third signal is supplied to the sixth wiring; when the third wiring is electrically connected to the gate of the first transistor via at least a channel formation region of the fourth transistor, the first potential is supplied to the gate of the first transistor via at least a channel formation region of the fourth transistor; when a potential of the second signal is supplied to a gate of the sixth transistor, the sixth transistor is brought into a conductive state or a non-conductive state according to the potential of the second signal; the fifth transistor has a function of controlling timing for increasing potentials of the gates of the second transistor and the fourth transistor; When the second transistor, the third transistor, and the fourth transistor are in a non-conductive state, the first transistor is in a conductive state, thereby increasing the potential of the first wiring; a period in which the level of the potential supplied to the fourth wiring and the level of the potential supplied to the sixth wiring are inverted to each other; Semiconductor device.

5. In any one of claims 1 to 4, the first to sixth transistors have the same polarity; Semiconductor device.

Images