Gate drive circuit, gate drive device, high frequency power supply device and system

Abstract

Provided is a gate drive circuit (100) for driving a switching element having a first drain, a first source, and a first gate. The gate drive circuit (100) is provided with a first terminal (T1) into which a gate control signal is input, a gate signal line connecting the first terminal (T1) and the first gate, a resistance element (R1) inserted into the gate signal line, a capacitance element (C1) connected in parallel with the resistance element (R1), a clamping circuit (101) that clamps a voltage between the first gate and the first source to a voltage that is smaller than a threshold voltage of the switching element when the gate control signal indicates an off-period of the switching element, and a clamping control circuit (102) that controls whether or not to prohibit the clamping operation of the clamping circuit (101) in the off-period.

Description

[Technical Field]

[0001] The present disclosure relates to a gate drive circuit, a gate drive device, a high frequency power supply device and a system. [Background technology]

[0002] Patent Document 1 discloses a technique for short-circuiting the gate and source in a gate drive circuit of a wide bandgap semiconductor switch such as GaN while a control signal indicates off, thereby preventing malfunctions in the off state of the semiconductor switch.

[0003] Patent Document 2 relates to a high-frequency power supply device equipped with a switch that performs DC / RF conversion to convert direct current power to high-frequency power, and discloses a switch driver that detects the impedance on the load side and optimizes the peak value of the drive signal applied to the switch based on the detected impedance, thereby reducing power loss in the high-frequency power supply device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-199763 [Patent Document 2] Patent No. 6313080 Summary of the Invention [Problem to be solved by the invention]

[0005] However, according to Patent Document 1, since the gate and source are short-circuited during the period indicating off, there is a problem that power consumption increases because a speed-up capacitor is charged and discharged every switching cycle. According to Patent Document 2, there is a problem that false firing may occur during the response time from when the load side impedance is detected until the peak value of the drive signal is changed to the optimal value.

[0006] Therefore, the present disclosure provides a gate drive circuit, a gate drive device, a high frequency power supply device, and a system that achieve both low power consumption and prevention of false firing. [Means for solving the problem]

[0007] A gate drive circuit according to one embodiment of the present disclosure is a gate drive circuit that drives a switching element having a first drain, a first source, and a first gate, and includes: a first terminal to which a gate control signal is input; a gate signal line that connects the first terminal and the first gate; a resistive element inserted in the gate signal line; a capacitive element connected in parallel to the resistive element; a clamp circuit that clamps the voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether or not to prohibit the clamping operation of the clamp circuit during the off period.

[0008] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0009] Here, the gate drive circuit may include a diode connected in parallel to the resistive element and having an anode connected to the first gate.

[0010] With this, even if the first gate voltage of the switching element rises due to reflected power caused by a load mismatch, the rise in the gate voltage is suppressed to below the forward drop voltage VF of the diode, thereby further suppressing false firing.

[0011] Here, the clamp circuit may include a first transistor switch connected between the first gate and the first source, and a second transistor switch connected in parallel with the first transistor switch.

[0012] With this, the clamp voltage between the first gate and the first source becomes substantially 0 V when the transistor switch is turned on, and can be made a voltage lower than the threshold voltage of the switching element. Moreover, because the clamp is performed by two transistor switches connected in parallel, the impedance between the gate and source during clamping is further reduced, making it possible to more effectively suppress false firing.

[0013] Here, the gate drive circuit may include an inverter that inverts a signal input to a gate of one of the first transistor switch and the second transistor switch and outputs the inverted signal to a gate of the other of the first transistor switch and the second transistor switch, and the channel of the first transistor switch and the channel of the second transistor switch may have different polarities.

[0014] According to this, clamping is performed by two transistor switches connected in parallel in a CMOS configuration, so that the impedance between the gate and source during clamping can be further lowered, and false firing can be further suppressed.

[0015] Here, the clamp control circuit may include a delay circuit that delays the gate control signal from the first terminal, and a logic circuit that generates a timing signal indicating the timing of the off period of the switching element based on a logical product or logical sum of the gate control signal before the delay and the gate control signal after the delay, and the clamp circuit may perform a clamping operation in accordance with the timing signal.

[0016] This makes it possible to prevent the clamping period of the clamp circuit from exceeding the range of the off-period of the switching element, thereby preventing the clamping operation from affecting the on-period of the switching element.

[0017] Here, the delay amount of the delay circuit may be variable.

[0018] According to this, since the amount of delay can be adjusted, the clamping operation can be performed effectively without affecting the ON period of the switching element.

[0019] Here, the logic circuit may receive an output state signal indicating a state of output power due to switching of the switching element, and inhibit the clamping operation of the clamp circuit in accordance with the output state signal.

[0020] This allows dynamic control of whether or not to inhibit clamping depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0021] Here, the clamp control circuit may inhibit the clamping operation of the clamp circuit in accordance with an output state signal indicating the state of the output power due to switching of the switching element.

[0022] This allows dynamic control of whether or not to inhibit clamping depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0023] Here, the output state signal may be based on at least one of information indicating reflected power of the output power and information indicating forward power of the output power.

[0024] In this way, since the output state signal indicates whether or not false firing is likely to occur, it is possible to dynamically control whether or not to inhibit clamp operation depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0025] Here, the gate drive circuit may include a test circuit that inhibits the clamping operation by forcibly setting the output state signal to a predetermined level in accordance with an externally input test signal.

[0026] This makes it possible to compare, test, and evaluate the operation when the clamp operation is disabled with the operation when it is enabled. As a result, the clamp control circuit can perform well-balanced clamp control that suppresses false firing and enables low-power consumption operation.

[0027] Here, the connection point of the clamp circuit in the gate signal line and the first gate The distance of the gate signal line between the connection point on the gate signal line and the resistor element may be smaller than the distance of the gate signal line between the connection point on the gate signal line and the resistor element.

[0028] This reduces the influence of the wiring capacitance of the gate signal line near the gate, enabling a more effective clamping operation.

[0029] A gate drive device according to one aspect of the present disclosure includes the gate drive circuit and a state detection circuit that generates the output state signal, wherein the state detection circuit detects at least one parameter that indicates the state of the output power from the switching element, converts each of the at least one parameter into at least one binary parameter that indicates the presence or absence of a possibility of false firing by threshold judgment, judges whether the at least one binary parameter satisfies a predetermined condition, and generates the judgment result as the binary output state signal.

[0030] This allows the clamp control circuit to dynamically control whether to disable clamp operation depending on the load operating state, since the output power state, which changes depending on the load operating state, is detected. As a result, it is possible to achieve both low power consumption and prevention of false firing, and further, to dynamically optimize the balance between the two.

[0031] Here, the at least one parameter may include a parameter indicating a forward wave power of the output power and a parameter indicating a reflected wave power.

[0032] This allows the impedance mismatch to be estimated, or in other words, the possibility of false firing, from the detection results of at least one of the forward power and the reflected power. As a result of the threshold determination, the output status signal indicates whether false firing is likely to occur. As a result, the clamp control circuit can inhibit clamping operation when false firing is likely to occur, and can continue clamping operation without inhibiting it when false firing is not highly likely.

[0033] Here, the at least one parameter may include a parameter indicating a voltage value of the output power, a parameter indicating a current value, and a parameter indicating a power value.

[0034] This allows the detection result to be used to estimate an impedance mismatch, or in other words, the possibility of false firing. As a result of the threshold determination, the output status signal indicates whether false firing is likely to occur. As a result, the clamp control circuit can inhibit clamping operation when false firing is likely to occur, and can continue clamping operation without inhibiting it when false firing is not highly likely.

[0035] Here, the predetermined condition may be an AND condition of one or more binarization parameters selected from the at least one binarization parameter.

[0036] A high frequency power supply device according to an aspect of the present disclosure includes the gate drive device and the switching element.

[0037] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0038] Here, the high frequency power supply device may include a positive power supply terminal, a negative power supply terminal, and a load inductor having a first end connected to the positive power supply terminal and a second end connected to the drain of the switching element, and the source of the switching element may be connected to the negative power supply terminal.

[0039] This allows the high frequency power supply device to be configured as a class E high frequency power supply equipped with the gate drive circuit described above, thereby achieving both low power consumption and prevention of false firing, and further enabling the balance between the two to be dynamically optimized.

[0040] Here, the high frequency power supply device may include a positive power supply terminal, a negative power supply terminal, two switching elements connected in series between the positive power supply terminal and the negative power supply terminal, and two gate drive circuits corresponding to the two switching elements, and the two gate drive circuits may exclusively conduct the two switching elements.

[0041] This allows the high frequency power supply device to be configured as a class D half-ridge high frequency power supply equipped with the gate driver described above, thereby achieving both low power consumption and prevention of false turn-on, and further enabling the balance between the two to be dynamically optimized.

[0042] Here, the high-frequency power supply device may include a positive power supply terminal, a negative power supply terminal, a first leg consisting of two of the switching elements connected in series between the positive power supply terminal and the negative power supply terminal, a second leg consisting of other two of the switching elements connected in series between the positive power supply terminal and the negative power supply terminal, and four gate drive circuits corresponding to the four switching elements, wherein the four gate drive circuits exclusively conduct two of the switching elements in the first leg, exclusively conduct two of the switching elements in the second leg, simultaneously conduct the switching element serving as a high-side switch in the first leg and the switching element serving as a low-side switch in the second leg, and simultaneously conduct the switching element serving as a high-side switch in the second leg and the switching element serving as a low-side switch in the first leg.

[0043] This allows the high frequency power supply device to be configured as a class D full-bridge high frequency power supply equipped with the gate driver described above, thereby achieving both low power consumption and prevention of false firing, and further enabling the balance between the two to be dynamically optimized.

[0044] A system according to one aspect of the present disclosure includes the high-frequency power supply device and a load connected to the high-frequency power supply device.

[0045] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0046] These general or specific aspects may be realized as a system, a method, or an integrated circuit, or may be realized as any combination of a system, a method, or an integrated circuit. [Effects of the Invention]

[0047] The gate drive circuit, gate drive device, high frequency power supply device, and system disclosed herein can achieve both low power consumption and prevention of false firing. [Brief explanation of the drawings]

[0048] [Figure 1A] FIG. 1A is a diagram showing an example of the configuration of a gate drive circuit according to the first embodiment. [Figure 1B] FIG. 1B is a diagram showing a specific example of the gate drive circuit according to the first embodiment. [Figure 2] FIG. 2 is a time chart showing an example of the operation of the gate drive circuit according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a gate drive circuit according to the second embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a gate driving device according to the third embodiment. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a system including a high-frequency power supply device according to the third embodiment. [Figure 6]FIG. 6 is a diagram illustrating a configuration example of a DC / RF conversion unit included in a high frequency power supply device according to the third embodiment. [Figure 7] FIG. 7 is a flowchart showing an example of the operation of the gate driving device according to the third embodiment. [Figure 8] FIG. 8 is a time chart showing an example of the operation of the gate driving device according to the third embodiment. [Figure 9] FIG. 9 is a diagram showing an example of an output waveform of the high frequency power supply device according to the third embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a system including a high-frequency power supply device according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram showing an example of the configuration of a gate drive circuit and a switching circuit included in a high frequency power supply device according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a DC / RF conversion unit included in the high frequency power supply device according to the fourth embodiment. [Figure 13] FIG. 13 is a time chart showing an example of the operation of the high frequency power supply device according to the fourth embodiment. [Figure 14] FIG. 14 is a diagram showing the relationship between loss and temperature depending on whether or not the clamping operation is prohibited in the high frequency power supply device according to the fourth embodiment. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a DC / RF conversion unit included in a high frequency power supply device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0049] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0050] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0051] (Embodiment 1) The gate drive circuit according to this embodiment drives a switching element provided in a high frequency power supply device that supplies high frequency power to a load such as a plasma generator, for example.

[0052] [1.1 Gate drive circuit configuration] 1A is a diagram showing an example of the configuration of a gate drive circuit 100 according to embodiment 1. In addition to the gate drive circuit 100, the diagram also shows a switching element Q1 to be driven.

[0053] The switching element Q1 is a power semiconductor element such as a GaN FET, and has a first drain, a first source, and a first gate. The first drain is connected to a DC power supply terminal DC1 and is supplied with a positive DC voltage. The first source is connected to ground or a negative terminal. A gate control signal is supplied to the first gate via a gate signal line. Cdg in the figure indicates the parasitic capacitance between the drain and gate.

[0054] The gate signal line refers to the line from the first terminal T1 to the first gate, and in the figure, a resistive element R1 and a capacitive element C1 are inserted in the gate signal line. The gate control signal input to the first terminal T1 is denoted as Sp1, and the gate control signal input to the first gate is denoted as S1.

[0055] The gate drive circuit 100 shown in the figure includes a resistive element R1, a capacitive element C1, a clamp circuit 101, and a clamp control circuit .

[0056] The resistive element R1 is inserted in the gate signal line and has a resistance value for regulating the value of the current flowing through the gate to an appropriate value in response to the gate control signal Sp1 input to the first terminal T1.

[0057] The capacitive element C1 is a speed-up capacitor.

[0058] When the gate control signal Sp1 indicates the off period of the switching element Q1, the clamp circuit 101 clamps the voltage between the first gate and the first source to a voltage lower than the threshold voltage of the switching element Q1 in order to suppress noise generated at the gate when the switching element Q1 is off.

[0059] Here, we will explain the noise generated at the first gate. The greater the impedance mismatch between the load and a high-frequency power supply device equipped with the gate drive circuit 100, the greater the reflected wave component of the high-frequency power from the load. A portion of the reflected wave component travels from the load through the parasitic capacitance Cdg between the drain and gate of the switching element Q1 in the high-frequency power supply device and appears as noise at the first gate. If the reflected wave component is large, the noise component at the first gate may exceed the threshold voltage of the switching element Q1. Such noise component can cause false firing of the switching element Q1. Conversely, if the impedance is matched between the high-frequency power supply device and the load, the reflected wave component and noise component are small, making false firing less likely to occur.

[0060] The clamp control circuit 102 controls whether or not to inhibit the clamp operation of the clamp circuit 101 during the off period indicated by the gate control signal Sp1. For example, in the impedance matched state described above, the noise component is small, so even if the clamp operation is inhibited, the possibility of false firing is small. In the impedance mismatched state described above, the noise component is large, so the clamp operation is not inhibited and is performed to suppress false firing.

[0061] For example, the clamp control circuit 102 controls whether to inhibit the clamp operation in accordance with the state determination signal S-jdg, regardless of the off-period and on-period. The state determination signal S-jdg is an example of an output state signal that indicates the state of the output power due to the switching of the switching element Q1, and is a signal that indicates whether the impedance is matched or mismatched. In other words, the state determination signal S-jdg is a signal that indicates whether false ignition is unlikely or likely. The clamp control circuit 102 inhibits the clamp operation when the state determination signal S-jdg indicates an impedance matched state, i.e., when false ignition is unlikely. Conversely, the clamp control circuit 102 does not inhibit the clamp operation but allows the clamp circuit 101 to perform the clamp operation when the state determination signal S-jdg indicates an impedance mismatched state, i.e., when false ignition is likely.

[0062] The distance between the connection point of the gate signal line to the clamp circuit 101 and the first gate may be shorter than the distance between the connection point and the resistive element R1, thereby reducing the influence of the wiring capacitance of the gate signal line near the gate and enabling more effective clamping operation.

[0063] Next, a more specific circuit example of the gate drive circuit 100 will be described.

[0064] Figure 1B is a diagram showing a specific example of a gate drive circuit according to embodiment 1. This figure differs from gate drive circuit 100 in Figure 1A in that it includes clamp circuit 101a and clamp control circuit 102a instead of clamp circuit 101 and clamp control circuit 102. The following will focus on the differences between Figure 1B and Figure 1A, avoiding redundant explanation of the same points.

[0065] The clamp circuit 101a is composed of a transistor switch n0 connected between the first gate and first source of the switching element Q1. The transistor switch n0 is, for example, an N-type MOSFET, and is turned on when a clamp control signal Con1 input to the gate is at a high level, shorting the first gate and the first source with low impedance. The low impedance is the on-resistance of the transistor switch n0.

[0066] The clamp control circuit 102a includes two inverters and an AND circuit.

[0067] The two inverters are inserted in the gate signal line between the first terminal T1 and the resistive element, and invert the gate control signal Sp1 twice.

[0068] The AND circuit performs a logical AND operation on the inverted gate control signal Sp1 and the state determination signal S-jdg.

[0069] [1.2 Gate drive circuit operation] FIG. 2 is a time chart showing an example of the operation of the gate drive circuit 100 of FIG. 1B according to the first embodiment.

[0070] In the figure, the gate control signal Sp1 indicates that the switching element Q1 is turned on at a high level and that the switching element Q1 is turned off at a low level.

[0071] The state determination signal S-jdg indicates a state where false firing is unlikely at a low level and a state where false firing is likely at a high level. In other words, the state determination signal S-jdg indicates a state where impedance is matched and clamping operation should be prohibited at a low level, and indicates a state where impedance is mismatched and clamping operation should be performed at a high level.

[0072] The clamp control signal Con1 is a signal obtained by logically ANDing the gate control signal Sp1 and the state determination signal S-jdg. When the state determination signal S-jdg is at a low level indicating that clamp operation is prohibited, the clamp control signal Con1 goes low, and the clamp circuit 101 goes into a disabled state where it cannot clamp.

[0073] When the state determination signal S-jdg is at a low level, the clamp circuit 101a is in a disabled state where clamping operation is prohibited, and when it is at a high level, the clamp circuit 101a is in an enabled state where clamping operation is not prohibited. Specifically, the transistor switch n0 of the clamp circuit 101a is in an off state when the clamp control signal Con1 is at a low level, and in an on state when it is at a high level.

[0074] The gate control signal S1 becomes a negative voltage during the off period when the clamping operation of the clamp circuit 101 is disabled, because the charge stored in the capacitive element C1 during the on period is retained without being discharged during the off period.

[0075] Furthermore, when the clamping operation of the clamp circuit 101 is enabled, the gate control signal S1 becomes approximately ground level during the off period. This is because the charge stored in the capacitive element C1 during the on period is discharged by the clamping operation during the off period.

[0076] The advantages and disadvantages of when the clamping operation of clamp circuit 101 is disabled and when it is enabled will be described below.

[0077] When the clamp operation is disabled, the first gate is more susceptible to noise and false firing than when it is enabled. This is because the impedance of the first gate is relatively high when the clamp operation of clamp circuit 101 is disabled, making it more susceptible to noise components.

[0078] Furthermore, when the clamp operation is disabled, the amount of charge charged and discharged to the capacitance element C1 is smaller than when the clamp operation is enabled, thereby reducing power consumption.

[0079] 2, the gate drive circuit 100 performs clamping when false firing is likely to occur, and does not perform clamping when false firing is unlikely to occur, thereby achieving both low power consumption and prevention of false firing.

[0080] As described above, the gate drive circuit 100 according to the first embodiment is a gate drive circuit 100 that drives a switching element Q1 having a first drain, a first source, and a first gate, and includes: a first terminal T1 to which a gate control signal is input; a gate signal line that connects the first terminal T1 to the first gate; a resistive element R1 inserted in the gate signal line; a capacitive element C1 connected in parallel with the resistive element R1; a clamp circuit 101 that clamps the voltage between the first gate and the first source to a voltage lower than the threshold voltage of the switching element Q1 when the gate control signal indicates an off period of the switching element Q1; and a clamp control circuit 102 that controls whether or not to prohibit the clamping operation of the clamp circuit 101 during the off period.

[0081] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0082] Here, the distance of the gate signal line between the connection point of the clamp circuit 101 on the gate signal line and the first gate may be shorter than the distance of the gate signal line between the connection point and the resistive element R1.

[0083] This reduces the influence of the wiring inductor of the gate signal line near the gate, enabling a more effective clamping operation.

[0084] (Embodiment 2) [2.1 Gate drive circuit configuration] In this embodiment, a configuration example will be described in which a diode is added to the gate signal line and clamp switches are connected in parallel, thereby enhancing the effect of suppressing erroneous firing.

[0085] FIG. 3 is a diagram illustrating an example of the configuration of a gate drive circuit according to the second embodiment.

[0086] 3 differs from gate drive circuit 100 in FIG. 1A in that diode D1 is added and that clamp circuit 101b and clamp control circuit 102b are provided instead of clamp circuit 101 and clamp control circuit 102. The following explanation will focus on the differences between FIG. 3 and FIG. 1A, avoiding duplication of explanations of the same points.

[0087] The diode D1 is connected in parallel to the resistor R1. The anode of the diode D1 is connected to the first gate. The diode D1 is, for example, a Zener diode with a forward drop voltage VF that is smaller than the threshold voltage of the switching element Q1. If the voltage at the first gate of the switching element Q1 increases due to a reflected power component caused by a load mismatch, the diode D1 suppresses the increase in the gate voltage to be equal to or less than the forward drop voltage VF of the diode D1, thereby further suppressing false firing.

[0088] The clamp circuit 101b includes a first clamp switch N1, a second clamp switch P1, and an inverter INV3.

[0089] The first clamp switch N1 is an NMOS type first transistor switch connected between the first gate and the first source.

[0090] The second clamp switch P1 is a PMOS-type second transistor switch connected in parallel with the first clamp switch N1, and the channels of the first and second transistor switches have different polarities.

[0091] Inverter INV3 inverts a signal input to the gate of one of the first clamp switch N1 and second clamp switch P1, and outputs the inverted signal to the gate of the other of the first clamp switch N1 and second clamp switch P1.

[0092] With this, the clamp voltage between the first gate and the first source becomes substantially 0 V when the two transistor switches are turned on, and can be made a voltage smaller than the threshold voltage of the switching element Q1. Furthermore, because the voltage is clamped by two transistor switches connected in parallel, the impedance between the gate and source during clamping is lowered, further suppressing false firing.

[0093] The clamp control circuit 102b includes an inverter INV1, an inverter INV2, a delay circuit DL1, and a combinational logic circuit LG1.

[0094] The inverter INV1 judges the inverted gate control signal output from the delay circuit DL1, and outputs a non-inverted gate control signal to the resistance element R1.

[0095] The inverter INV2 inverts the gate control signal from the first terminal T1 and outputs the inverted gate control signal to the delay circuit DL1.

[0096] The delay circuit DL1 delays the inverted gate signal output from the inverter INV2 and outputs the delayed signal to the inverter INV1. The delay amount of the delay circuit DL1 is variable.

[0097] The combinational logic circuit LG1 generates the clamp control signal Con1 as a timing signal indicating the timing of the OFF period of the switching element Q1 based on the logical product of the inverted gate control signal before the delay and the inverted gate control signal after the delay.

[0098] This clamp control signal Con1 can prevent the clamping period of the clamp circuit 101b from exceeding the range of the off-period of the switching element, thereby preventing the clamping operation from affecting the on-period of the switching element.

[0099] Furthermore, since the delay amount is adjustable, the clamping operation can be performed effectively without affecting the ON period of the switching element Q1.

[0100] Next, the operation of the gate drive circuit 100 in the second embodiment will be described.

[0101] The clamp control circuit 102b outputs a high level to the clamp control signal Con1 to turn on the clamp circuit 101b when the switching element Q1 is off (i.e., when the gate control signal Sp1 is low level) and the state determination signal S-jdg is high level (i.e., when a false ignition is likely to occur).

[0102] At this time, in a state where the impedance is mismatched, the reflected wave component flows from the drain of the switching element Q1 through the parasitic capacitance Cdg to the first gate as a current Icg, which is converted into a voltage by the on-resistance of the clamp circuit 101b, causing the gate-source potential to rise. If this rising voltage does not exceed the threshold voltage of the switching element Q1 (approximately 1.2 V in the case of a GaN switch), false firing will not occur. 2 The forward drop voltage VF of the diode D1 (for example, about 0.2 V) is smaller than the threshold voltage of the switching element Q1. Therefore, in order to reduce the potential rise between the first gate and the first source that cannot be absorbed by the on-resistance of the clamp circuit 101 alone, a shunt path for Icg can be provided from the anode of the diode D1 via the cathode to the sink transistor (usually an N-channel transistor) of the inverter INV1.

[0103] As described above, the gate drive circuit 100 according to the second embodiment includes the diode D1 connected in parallel to the resistance element R1 and having the anode connected to the first gate.

[0104] With this, even if the first gate voltage of the switching element Q1 rises due to reflected power caused by a load mismatch, the rise in the gate voltage is suppressed to be equal to or less than the forward drop voltage VF of the diode, thereby further suppressing false ignition.

[0105] Here, the clamp circuit 101 may include a first transistor switch N1 connected between the first gate and the first source, and a second transistor switch P1 connected in parallel with the first transistor switch.

[0106] With this, the clamp voltage between the first gate and the first source becomes substantially 0 V when the transistor switch is turned on, and can be made a voltage smaller than the threshold voltage of the switching element Q1. Furthermore, because the voltage is clamped by two transistor switches connected in parallel, the impedance between the gate and source during clamping is lowered, further suppressing false firing.

[0107] Here, an inverter may be provided that inverts a signal input to the gate of one of the first transistor switch N1 and the second transistor switch P1 and outputs the inverted signal to the gate of the other of the first transistor switch N1 and the second transistor switch P1, and the channel of the first transistor switch and the channel of the second transistor switch may have different polarities.

[0108] According to this, clamping is performed by two transistor switches connected in parallel in a CMOS configuration, so that the impedance between the gate and source during clamping can be further lowered, and false firing can be further suppressed.

[0109] Here, the clamp control circuit 102 includes a delay circuit DL1 that delays the gate control signal from the first terminal T1, and a combinational logic circuit LG1 that generates a timing signal indicating the timing of the off period of the switching element Q1 based on the logical product or logical sum of the gate control signal before the delay and the gate control signal after the delay, and the clamp circuit 101 may perform clamping operation in accordance with the timing signal.

[0110] This makes it possible to prevent the clamping period of the clamp circuit 101 from exceeding the range of the off-period of the switching element Q1, thereby preventing the clamping operation from affecting the on-period of the switching element Q1.

[0111] Here, the delay amount of the delay circuit may be variable.

[0112] According to this, the amount of delay can be adjusted, so that the clamping operation can be performed effectively without affecting the ON period of the switching element Q1.

[0113] Here, the combinational logic circuit LG1 may receive an output state signal indicating the state of the output power due to the switching of the switching element Q1, and inhibit the clamping operation of the clamp circuit 101 in accordance with the output state signal.

[0114] This allows dynamic control of whether or not to inhibit clamping depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0115] Here, the clamp control circuit 102 may prohibit the clamping operation of the clamp circuit 101 in accordance with an output state signal that indicates the state of the output power due to the switching of the switching element Q1.

[0116] This allows dynamic control of whether or not to inhibit clamping depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0117] (Embodiment 3) [3.1 Gate driver configuration] In this embodiment, an example of a configuration including a state detection circuit that detects a state where erroneous firing is likely to occur will be described.

[0118] FIG. 4 is a diagram showing an example of the configuration of a gate driving device according to the third embodiment.

[0119] The gate driver 110 in the figure includes a gate driver circuit 100 and a state detection circuit 105. The figure also shows a switching element Q1.

[0120] Gate drive circuit 100 may be the same as that shown in FIG. 1A of the first embodiment, and therefore description thereof will not be repeated here.

[0121] The state detection circuit 105 detects at least one parameter indicating the state of the output power from the switching element Q1, converts each of the at least one parameter into at least one binary parameter indicating the possibility of erroneous firing by threshold determination, and further determines whether the at least one binary parameter satisfies a predetermined condition and generates the determination result as a binary output state signal.

[0122] Here, the at least one parameter is (A) a parameter indicating the forward wave power of the output power, (B) a parameter indicating the reflected wave power, (C) a parameter indicating the voltage value of the output power, (D) a parameter indicating the current value, (E) a parameter indicating the power value, (F) a parameter indicating the complex impedance of the load, (G) a parameter indicating the temperature of the switching element Q1, etc.

[0123] The predetermined condition is, for example, an AND condition of one or more binarization parameters selected from at least one binarization parameter. The predetermined condition may be an AND condition of all parameters (A) to (G) above. Alternatively, the predetermined condition may be an AND condition of one or more parameters selected from (A) to (G) above. The predetermined condition may be an OR condition of one or more parameters selected from (A) to (G) above. The predetermined condition may be determined based on the operating conditions of the load, environmental conditions, etc. The predetermined condition may also be determined experimentally or empirically.

[0124] [3.2 Configuration of power supply including gate driver] 5 is a diagram showing an example of the configuration of a system including a high-frequency power supply device according to embodiment 3. Note that a load 2 is also shown in the drawing.

[0125] The high-frequency power supply device 120 shown in the figure includes an impedance matching device 3, a variable DC power supply unit 4, a DC / RF conversion unit 5, a low-pass filter 6, a power detector 7, a drive signal generation unit 86, a gate drive circuit 100, a state detection circuit 105, a combinational logic circuit LG2, an inverter INV4, and a power supply E1.

[0126] The load 2 is, for example, a plasma generator. The plasma generator is a device that generates plasma using high-frequency power provided by the high-frequency power supply device 120, and is a plasma processing device that performs processes such as etching by irradiating a workpiece such as a semiconductor with plasma. The plasma load typically has a plasma generation electrode provided in the chamber, and generates plasma when high-frequency power is provided to the electrode. The impedance of the plasma load varies depending on various conditions, such as the magnitude of the power provided between the electrodes, the pressure of the gas in the chamber, the flow rate of the gas supplied to the chamber, and the time for generating plasma.

[0127] The impedance matching device 3 includes a variable capacitor or variable inductor, which is a variable impedance element, and an operating mechanism that operates the variable impedance element using a motor as a drive source. To maximize the high-frequency power consumed by the load 2, the impedance matching device 3 adjusts the output impedance of the high-frequency power supply 120 and the impedance seen from the high-frequency power supply 120 to form a conjugate relationship. Because the output impedance of the high-frequency power supply 120 is typically designed to be 50 Ω, the impedance matching device 3 operates to equalize the impedance seen from the high-frequency power supply 120 to the load 2 with 50 Ω. Impedance matching typically takes 100 milliseconds to several seconds. Because reflections occur at the load until impedance matching is achieved, the reflected wave power returning to the DC / RF conversion unit 5 increases, resulting in increased loss in the DC / RF conversion unit.

[0128] The variable DC power supply 4 may be any device that has the function of adjusting the DC power to be output. For example, the variable DC power supply may include a DC-DC converter that includes an inverter that converts input DC power into AC power, a transformer that transforms the output of the inverter, a rectifier circuit that rectifies the output of the transformer, and a smoothing circuit that smoothes the output of the rectifier circuit, and is configured to obtain DC power at any level by PWM-controlling the output of the inverter in response to an output control signal (PWM control signal).

[0129] The DC / RF conversion unit 5 includes a switching circuit 51, a series resonant circuit 52 to which the output of the variable DC power supply unit 4 is supplied through the switching circuit 51, and a transformer 53 whose primary coil is connected in series with the series resonant circuit 52, and the switching circuit 51 and the series resonant circuit 52 work together to convert the DC output of the variable DC power supply unit 4 into a high-frequency AC output.

[0130] The low-pass filter 6 removes harmonic components from the output of the DC / RF conversion unit 5 .

[0131] The power detector 7 includes a directional coupler and is located upstream of the output terminal of the high frequency power supply device 120. It detects the traveling wave component of the high frequency power provided to the load 2 from the DC / RF conversion unit 5 through the low pass filter 6 and the reflected wave component of the high frequency power reflected back from the load, and outputs (A) a traveling wave component detection signal Pf and (B) a reflected wave component detection signal Pr having magnitudes proportional to the detected traveling wave component and reflected wave component. Furthermore, the power detector 7 detects the (F) complex impedance Z of the load 2. The complex impedance Z is expressed as R+jX.

[0132] The drive signal generating unit 86 generates the gate control signal Sp1. For example, the drive signal generating unit 86 can be configured by a DDS (Direct Digital Synthesizer) that outputs a signal having a pulse waveform at a desired frequency.

[0133] The gate drive circuit 100 may be the same as that shown in FIG. 3 of the second embodiment.

[0134] State detection circuit 105 may be the same as that shown in Fig. 4 of embodiment 3. However, state detection circuit 105 in Fig. 5 shows a more specific configuration example than that shown in Fig. 4. This state detection circuit 105 includes a power supply analyzer 81, a TEMP sensor 82, a binary conversion circuit 83, and an output state determination circuit 84.

[0135] The power analyzer 81 detects (C) the voltage value Vin, (D) the current value Iin, and (E) the power value Pin from the variable DC power supply unit 4 to the DC / RF conversion unit 5.

[0136] The TEMP sensor 82 is disposed as close as possible to the switching element Q1 and detects the (G) temperature Temp of the switching element Q1.

[0137] The binary conversion circuit 83 stores thresholds corresponding to the parameters (A) to (F) in advance, and converts each parameter into a binary parameter indicating whether or not a false firing is likely to occur based on threshold judgment. As a result, (A) the forward power Pf is converted into a forward power judgment code signal Pf-jdg. (B) the reflected power Pr is converted into a reflected power judgment code signal Pr-jdg. (C) the voltage value Vin is converted into a voltage value judgment code signal Vin-jdg. (D) the current value Iin is converted into a current value judgment code signal Iin-jdg. (E) the power value Pin is converted into a power value judgment code signal Pin-jdg. (F) the impedance Z is converted into an impedance judgment code signal Z-jdg. (G) the temperature Temp is converted into a temperature judgment code signal Temp-jdg. A high level of any of the judgment code signals (A) to (G) indicates a false firing is likely to occur, and a low level indicates that a false firing is not likely to occur.

[0138] The output state determination circuit 84 determines whether the binary parameters output from the binary conversion circuit 83, i.e., the determination code signals (A) to (G), satisfy a predetermined condition, and outputs the determination result as a binary state determination signal S-jdg. For example, the predetermined condition is an AND condition of one or more determination code signals selected from the determination code signals (A) to (G). Note that the predetermined condition may also be an OR condition of one or more determination code signals selected from the determination code signals (A) to (G). In FIG. 5, the state determination signal S-jdg is at a high level indicating that a false firing is likely, and at a low level indicating that a false firing is not likely.

[0139] The combinational logic circuit LG2 is a test circuit that prohibits clamping by forcibly setting the state determination signal S-jdg to a predetermined level in accordance with an externally input test signal TS1.

[0140] The inverter INV4 receives the test signal TS1 of positive logic and outputs the test signal TS1 of negative logic.

[0141] The power supply E1 supplies the gate drive circuit 100 with power supply voltages Vdd+ and Vdd− (i.e., GND).

[0142] 6 is a diagram showing a configuration example of a DC / RF conversion unit included in a high-frequency power supply device according to embodiment 3. The DC / RF conversion unit 5 in the diagram shows a configuration example of a class E DC / RF conversion unit, and includes a switching circuit 51, a series resonant circuit 52, and a transformer 53.

[0143] The switching circuit 51 includes a positive power supply terminal PVDD+, a negative power supply terminal PVDD-, a load inductor (Lr) having a first end connected to the positive power supply terminal PVDD+ and a second end connected to the drain of the switching element Q1, and a switching element Q1. A series resonant circuit 52, which connects the first source of the switching element Q1 and the negative power supply terminal PVDD-, is composed of an inductor Lr and a capacitor Cr connected in series.

[0144] The transformer 53 has a primary winding W1 and a secondary winding W2. The primary winding W1 is connected to the series resonant circuit 52. The secondary winding W2 is connected to a circuit on the load 2 side. In FIG. 5, the circuit on the load 2 side is a low-pass filter 6.

[0145] [3.3 Example of gate driver operation] 7 is a flowchart showing an example of the operation of the gate driving device according to embodiment 3. Steps S11 to S13 in the figure show a threshold determination process in which the binary conversion circuit 83 converts (B) the reflected power Pr into a reflected power determination code signal Pr-jdg. The threshold th1 is predetermined for the reflected power Pr.

[0146] Steps S21 to S23 represent a threshold determination process for converting (A) the forward power Pf into a forward power determination code signal Pf-jdg in the binary conversion circuit 83. The threshold th2 is predetermined for the forward power Pf.

[0147] Steps S31 to S33 represent a threshold determination process for converting the (F) impedance Z into an impedance determination code signal Z-jdg in the binary conversion circuit 83. The threshold th3 is determined in advance for the impedance Z.

[0148] Steps S41 to S43 represent a threshold value determination process for converting the (G) temperature Temp into a temperature determination code signal Temp-jdg in the binary conversion circuit 83. The threshold value th4 is predetermined for the temperature Temp.

[0149] Steps S51 to S53 represent threshold determination processing in which the binary conversion circuit 83 converts the voltage value Vin, the current value Iin, and the power value Pin into binary parameters X-jdg as parameters X.

[0150] Specifically, this shows a threshold determination process in which (C) the voltage value Vin is converted into a voltage value determination code signal Vin-jdg in the binary conversion circuit 83. The threshold is determined in advance for the voltage value Vin.

[0151] Also shown is a threshold value determination process in which (D) the current value Iin is converted into a current value determination code signal Iin-jdg in the binary conversion circuit 83. The threshold value is determined in advance for the current value Iin.

[0152] Also shown is a threshold value determination process in which (E) the power value Pin is converted into a power value determination code signal Pin-jdg in the binary conversion circuit 83. The threshold value is determined in advance for the power value Pin.

[0153] After conversion into binary parameters, the output state determination circuit 84 determines whether the (A) to (G) binary parameters output from the binary conversion circuit 83, i.e., the (A) to (G) determination code signals, satisfy a predetermined condition (S60). If the predetermined condition is satisfied (yes in S60), the output state determination circuit 84 outputs the state determination signal S-jdg at a high level. If the predetermined condition is not satisfied (no in S60), the output state determination circuit 84 outputs the state determination signal S-jdg at a low level. The predetermined condition may be an AND condition of one or more determination code signals selected from the (A) to (G) determination code signals. Note that the predetermined condition may also be an OR condition of one or more determination code signals selected from the (A) to (G) determination code signals. In FIG. 7, the state determination signal S-jdg is at a high level indicating that a false firing is likely, and at a low level indicating that a false firing is not likely.

[0154] 8 is a time chart showing an example of the operation of the gate driver according to the third embodiment. (a) in the figure schematically shows the waveform of the gate control signal S1 when the impedance is matched. (b) in the figure shows the jagged waveform of the gate control signal S1 when the clamp operation is prohibited due to impedance mismatch. The waveform in (b) in the figure has reflected wave components of high-frequency power from the load 2 superimposed as noise.

[0155] The dashed circle e0 in the figure indicates the timing when the output state determination circuit 84 determines that false firing is imminent, even though the noise peak does not exceed the threshold voltage Vth of the switching element Q1. This determination causes the state determination signal S-jdg to go high. As a result, at time e0, the clamp circuit 101 transitions from disabled to enabled. After time e0, the gate control signal S1 is clamped to the GND level while the switching element Q1 is off, as shown by the thick solid line. For example, even if a noise peak exceeds the threshold voltage Vth of the switching element Q1, as shown by the dashed circle e1 and e2, false firing can be prevented by the clamp operation.

[0156] 9 is a diagram showing an example of an output waveform of the high frequency power supply device according to embodiment 3. "RFOUT" in the upper part of the diagram is the final stage output of the high frequency power supply device 120, and shows the waveform of the high frequency power supplied to the load 2. "SWOUT" in the lower part of the diagram is the output of the switching circuit 51, and shows the waveform of the high frequency power output from the switching circuit 51.

[0157] The left side of the figure shows a waveform of high-frequency power that contains many reflected wave components due to impedance mismatch. The right side of the figure shows a waveform of high-frequency power that contains few reflected wave components due to impedance matching. The gate control signal S1 with little noise in (a) of Figure 8 corresponds to the state on the right side of Figure 9. The gate control signal S1 with noise superimposed in (b) of Figure 8 corresponds to the state on the left side of Figure 9.

[0158] As described above, in the gate drive circuit 100 according to the third embodiment, the output state signal may be based on at least one of information indicating the reflected power of the output power and information indicating the forward power of the output power.

[0159] In this way, since the output state signal indicates whether or not false firing is likely to occur, it is possible to dynamically control whether or not to inhibit clamp operation depending on the state of the output power to the load, thereby achieving a good balance between low power consumption and prevention of false firing.

[0160] Here, a test circuit may be provided that inhibits the clamping operation by forcibly setting the output state signal to a predetermined level in accordance with an externally input test signal.

[0161] This allows comparison, testing, and evaluation of the operation when clamp operation is disabled and the operation when it is not disabled. As a result, clamp control circuit 102 can perform well-balanced clamp control that suppresses false firing and enables low-power consumption operation.

[0162] Furthermore, the gate drive device 110 according to the third embodiment includes the gate drive circuit 100 and a state detection circuit 105 that generates an output state signal. The state detection circuit 105 detects at least one parameter that indicates the state of the output power from the switching element Q1, converts each of the at least one parameter into at least one binary parameter that indicates the possibility of erroneous firing by threshold judgment, judges whether the at least one binary parameter satisfies a predetermined condition, and generates the judgment result as a binary output state signal.

[0163] This allows the clamp control circuit to dynamically control whether to disable clamp operation depending on the load operating state, since the output power state, which changes depending on the load operating state, is detected. As a result, it is possible to achieve both low power consumption and prevention of false firing, and further, to dynamically optimize the balance between the two.

[0164] Here, the at least one parameter may include a parameter indicating a forward wave power of the output power and a parameter indicating a reflected wave power.

[0165] This allows the impedance mismatch to be estimated, or in other words, the possibility of false firing, from the detection results of at least one of the forward power and the reflected power. As a result of the threshold determination, the output status signal indicates whether false firing is likely to occur. As a result, the clamp control circuit can inhibit clamping operation when false firing is likely to occur, and can continue clamping operation without inhibiting it when false firing is not highly likely.

[0166] Here, the at least one parameter may include a parameter indicating a voltage value of the output power, a parameter indicating a current value, and a parameter indicating a power value.

[0167] This allows the detection result to be used to estimate an impedance mismatch, or in other words, the possibility of false firing. As a result of the threshold determination, the output status signal indicates whether false firing is likely to occur. As a result, the clamp control circuit can inhibit clamping operation when false firing is likely to occur, and can continue clamping operation without inhibiting it when false firing is not highly likely.

[0168] Here, the predetermined condition may be an AND condition of one or more binarization parameters selected from at least one binarization parameter.

[0169] According to this, the clamp control circuit inhibits the clamp operation when the AND condition of at least one binary parameter is satisfied, and as a result, the clamp operation can be inhibited when false firing is likely to occur, and can be performed without inhibition when the likelihood of false firing is low.

[0170] Moreover, the high frequency power supply device 120 according to the third embodiment includes a gate driver 110 and a switching element Q1.

[0171] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0172] Here, the high frequency power supply device 120 includes a positive power supply terminal PVDD+, a negative power supply terminal PVDD-, and a load inductor L1 having a first end connected to the positive power supply terminal and a second end connected to a first drain of the switching element Q1, and the first source of the switching element Q1 may be connected to the negative power supply terminal.

[0173] This allows the high frequency power supply device to be configured as a class E high frequency power supply including the above-described gate drive circuit 100. As a result, it is possible to achieve both low power consumption and prevention of false firing, and further, to dynamically optimize the balance between the two.

[0174] The system according to the third embodiment also includes a high frequency power supply device 120 and a load connected to the high frequency power supply device 120.

[0175] This makes it possible to achieve both low power consumption and prevention of erroneous firing.

[0176] (Fourth embodiment) In this embodiment, a high frequency power supply device 120 having a class D half-ridge configuration will be described.

[0177] [4.1 Gate driver configuration] Fig. 10 is a diagram showing an example of the configuration of a system including a high-frequency power supply device according to embodiment 4. The main differences from Fig. 5 are that two switching elements Q1 of a switching circuit 51 are provided and that another gate drive circuit 100 is added. The following mainly describes the differences.

[0178] The switching circuit 51 includes two switching elements connected in series between a positive power supply terminal PVDD+ and a negative power supply terminal PVDD-. When distinguishing between the two switching elements, the two switching elements are referred to as a first high-side switching element Q1 and a first low-side switching element Q2.

[0179] The two gate drive circuits 100 exclusively turn on the two switching elements in the switching circuit 51 .

[0180] 11 is a diagram showing an example of the configuration of a gate drive circuit and a switching circuit included in a high-frequency power supply device according to embodiment 4. As shown in the diagram, two gate drive circuits 100 correspond to a first high-side switch device Q1 and a first low-side switch device Q2. A drive signal generating unit 86 generates gate control signals Sp1 and Sp2. The gate control signals Sp1 and Sp2 have opposite phases.

[0181] 12 is a diagram showing a configuration example of a DC / RF conversion unit included in a high-frequency power supply device according to embodiment 4. As shown in the diagram, the DC / RF conversion unit 5 has a class D half-ridge configuration and includes a first high-side switching device Q1 and a first low-side switching device Q2.

[0182] [4.2 Gate driver operation] FIG. 13 is a time chart showing an example of the operation of the high frequency power supply device according to the fourth embodiment.

[0183] As shown in the figure, the two gate drive circuits 100 exclusively turn on the two switching elements.

[0184] FIG. 14 is a diagram showing the relationship between loss and temperature depending on whether or not the clamping operation is prohibited in the high frequency power supply device according to the fourth embodiment.

[0185] The (a1) and (a2) in the upper part of the figure show the power loss versus the voltage of the variable DC power supply unit 4. The (b1) and (b2) in the lower part of the figure show the temperature versus the voltage of the variable DC power supply unit 4. The (a1) and (b2) in the left part of the figure show the temperature versus the voltage of the variable DC power supply unit 4. b1 ) shows the graph when false firing occurs. (a2) and (b2) on the right side of the figure show the graph when false firing is avoided.

[0186] As shown on the right side of the figure, by avoiding false firing, power loss can be reduced compared to when false firing occurs, and temperature rise can also be reduced.

[0187] As described above, the high-frequency power supply device 120 according to the fourth embodiment includes a positive power supply terminal PVDD+, a negative power supply terminal PVDD-, two switching elements Q1 connected in series between the positive power supply terminal PVDD+ and the negative power supply terminal PVDD-, and two gate drive circuits corresponding to the two switching elements Q1, and the two gate drive circuits exclusively bring the two switching elements Q1 into conduction.

[0188] This allows the high frequency power supply device to be configured as a class D half-ridge high frequency power supply including the above gate driver 110. As a result, it is possible to achieve both low power consumption and prevention of false firing, and further, to dynamically optimize the balance between the two.

[0189] (Embodiment 5) [5.1 Gate driver configuration] In this embodiment, a high frequency power supply device 120 having a class D full bridge configuration will be described.

[0190] FIG. 15 is a diagram illustrating a configuration example of a DC / RF conversion unit included in a high frequency power supply device according to the fifth embodiment.

[0191] The DC / RF conversion unit 5 in the figure includes four switching elements Q1 to Q4, forming a class-D full-bridge circuit. That is, the switching circuit 51 includes a first leg consisting of two switching elements connected in series between the positive power supply terminal PVDD+ and the negative power supply terminal PVDD-, and a second leg consisting of two other switching elements connected in series between the positive power supply terminal PVDD+ and the negative power supply terminal PVDD-. The first leg consists of a first high-side switching element Q1 and a first low-side switching element Q2. The second leg consists of a second high-side switching element Q3 and a second low-side switching element Q4.

[0192] The four gate drive circuits control the following: two switching elements in the first leg are exclusively conductive; two switching elements in the second leg are exclusively conductive; a switching element serving as a high-side switch in the first leg and a switching element serving as a low-side switch in the second leg are simultaneously conductive; and a switching element serving as a high-side switch in the second leg and a switching element serving as a low-side switch in the first leg are simultaneously conductive.

[0193] As described above, the high-frequency power supply device 120 according to the fifth embodiment includes a positive power supply terminal PVDD+, a negative power supply terminal PVDD-, a first leg consisting of two switching elements Q1 and Q2 connected in series between the positive power supply terminal PVDD+ and the negative power supply terminal PVDD-, a second leg consisting of two other switching elements Q3 and Q4 connected in series between the positive power supply terminal PVDD+ and the negative power supply terminal PVDD-, and four gate drive circuits corresponding to the four switching elements Q1 to Q4. The four gate drive circuits exclusively conduct the two switching elements Q1 and Q2 in the first leg, exclusively conduct the two switching elements Q3 and Q4 in the second leg, simultaneously conduct the switching element Q1 as a high-side switch in the first leg and the switching element Q4 as a low-side switch in the second leg, and simultaneously conduct the switching element Q3 as a high-side switch in the second leg and the switching element Q2 as a low-side switch in the first leg.

[0194] According to this, the high frequency power supply device can be configured as a high frequency power supply with a class D full bridge configuration including the above-described gate driver 110. As a result, it is possible to achieve both low power consumption and prevention of false firing, and further, to dynamically optimize the balance between the two.

[0195] While the gate drive circuit, gate drive device, high-frequency power supply device, and system according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0196] The gate drive circuit, gate drive device, high frequency power supply device and system disclosed herein can be used, for example, in semiconductor manufacturing equipment equipped with a plasma generator, CO2 laser equipment, and the like. [Explanation of symbols]

[0197] 2. Load 3 Impedance matching box 4 Variable DC power supply 5 DC / RF conversion section 51 Switching Circuit 52 Series resonant circuit 53 Trans 6 Low-pass filter 7 Power Detector 81 Power Analyzer 82 TEMP sensor 83 Binary conversion circuit 84 Output status determination circuit 86 Drive signal generator 100 Gate drive circuit 101, 101a, 101b clamp circuits 102, 102a, 102b Clamp control circuit 105 Status detection circuit 110 Gate driver 120 High frequency power supply equipment AC1 AC power terminal C1 Capacitor element Con1 Clamp control signal DL1 delay circuit D1 Diode DC1 DC power supply terminal Iin current value Iin-jdg status determination signal INV1, INV2, INV3 inverters L1 Load inductor LG1, LG2 combinational logic circuits n0 Clamp switch N1 First clamp switch P1 Second clamp switch Pr reflected wave power Pf traveling wave power PVDD+ Positive power supply terminal PVDD- Negative power supply terminal Q1 First high-side switch element (switching element) Q2 First low-side switch element Q3 Second high-side switch element Q4 Second low-side switch element R1 Resistor element S-jdg Status determination signal T1 Terminal 1 TS1 Test Signal Temp Temperature Temp-jdg Temperature judgment code signal Vin voltage value Vin-jdg voltage determination code

Claims

1. A gate drive circuit for driving a switching element having a first drain, a first source, and a first gate, a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistive element inserted in the gate signal line; a capacitance element connected in parallel to the resistance element; a clamp circuit that clamps the voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; a clamp control circuit that controls whether or not to prohibit the clamping operation of the clamp circuit during the off period. Gate drive circuit.

2. a diode connected in parallel to the resistive element and having an anode connected to the first gate; 2. The gate drive circuit of claim 1.

3. the clamp circuit includes a first transistor switch connected between the first gate and the first source; a second transistor switch connected in parallel with the first transistor switch; 3. The gate drive circuit according to claim 1.

4. an inverter that inverts a signal input to a gate of one of the first transistor switch and the second transistor switch and outputs the inverted signal to a gate of the other of the first transistor switch and the second transistor switch; The channel of the first transistor switch and the channel of the second transistor switch have different polarities.

4. The gate drive circuit according to claim 3.

5. The clamp control circuit a delay circuit that delays the gate control signal from the first terminal; a logic circuit that generates a timing signal indicating a timing of an off period of the switching element based on a logical product or logical sum of the gate control signal before the delay and the gate control signal after the delay, The clamp circuit performs a clamping operation in accordance with a timing signal.

5. The gate drive circuit according to claim 1.

6. The delay amount of the delay circuit is variable.

6. The gate drive circuit according to claim 5.

7. The logic circuit receives an output state signal indicating the state of the output power due to switching of the switching element, and inhibits the clamping operation of the clamp circuit in accordance with the output state signal.

7. The gate drive circuit according to claim 5 or 6.

8. The clamp control circuit inhibits the clamping operation of the clamp circuit in accordance with an output state signal indicating the state of the output power due to switching of the switching element.

5. The gate drive circuit according to claim 1.

9. The output state signal is based on at least one of information indicating a reflected wave power of the output power and information indicating a forward wave power of the output power.

9. The gate drive circuit according to claim 7 or 8.

10. A test circuit is provided which inhibits the clamping operation by forcibly setting the output state signal to a predetermined level in accordance with an externally input test signal.

10. The gate drive circuit according to claim 7.

11. The distance of the gate signal line between the connection point of the clamp circuit on the gate signal line and the first gate is smaller than the distance of the gate signal line between the connection point of the gate signal line and the resistive element. The gate drive circuit according to any one of claims 1 to 10.

12. A gate drive circuit according to any one of claims 8 to 10; a state detection circuit that generates the output state signal; The state detection circuit Detecting at least one parameter indicative of a state of output power from the switching element; converting each of the at least one parameter into at least one binary parameter indicating the presence or absence of a possibility of false firing by threshold determination; determining whether the at least one binarization parameter satisfies a predetermined condition; The determination result is generated as the binary output state signal. Gate drive device.

13. The at least one parameter includes a parameter indicating a forward power of the output power and a parameter indicating a reflected power of the output power.

13. The gate driver of claim 12.

14. The at least one parameter includes a parameter indicating a voltage value, a parameter indicating a current value, and a parameter indicating a power value of the output power.

14. The gate driver according to claim 12 or 13.

15. The predetermined condition is an AND condition of one or more binarization parameters selected from the at least one binarization parameter.

15. The gate driver of claim 12, 13 or 14.

16. A gate driver according to any one of claims 12 to 15; The switching element High frequency power supply.

17. The positive power terminal, The negative power terminal, a load inductor having a first end connected to the positive power supply terminal and a second end connected to the first drain; The first source and the negative power supply terminal are connected.

17. The high frequency power supply device according to claim 16.

18. The positive power terminal, The negative power terminal, two of the switching elements connected in series between the positive power supply terminal and the negative power supply terminal; two gate drive circuits corresponding to the two switching elements; The two gate drive circuits exclusively turn on the two switching elements.

17. The high frequency power supply device according to claim 16.

19. The positive power terminal, The negative power terminal, a first leg consisting of two of the switching elements connected in series between the positive power supply terminal and the negative power supply terminal; a second leg consisting of two other switching elements connected in series between the positive power supply terminal and the negative power supply terminal; four gate drive circuits corresponding to the four switching elements; The four gate drive circuits are: two of the switching elements in the first leg are exclusively conductive; two of the switching elements in the second leg are exclusively conductive; simultaneously conducting the switching element serving as a high-side switch in the first leg and the switching element serving as a low-side switch in the second leg; The switching element serving as a high-side switch in the second leg and the switching element serving as a low-side switch in the first leg are simultaneously made conductive.

17. The high frequency power supply device according to claim 16.

20. The high frequency power supply device according to any one of claims 16 to 19, a load connected to the high frequency power supply device; system.

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