Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a technique capable of enhancing the reliability of a semiconductor device.SOLUTION: A semiconductor device comprises an insulation film provided along the top surface of a semiconductor substrate, a first surface electrode provided selectively on the insulation film, and a passivation film covering the insulation film and first surface electrode. A cover part of the passivation film which covers the first surface electrode is tapered increasing in width toward the semiconductor substrate in cross-sectional view with at least one of a first structure and a second structure.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Various techniques have been proposed for semiconductor devices. For example, Patent Document 1 proposes a technique of covering a surface electrode connected to a guard ring with a passivation film such as an interlayer film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the prior art, the side surface of the surface electrode rises vertically with respect to the upper surface of the semiconductor substrate. Along with this, the side surface of the portion of the passivation film that covers the surface electrode also rises vertically with respect to the upper surface of the semiconductor substrate. In such a configuration, cracks are likely to occur in the vertically rising portion of the passivation film due to the concentration of stresses such as thermal stress. Therefore, moisture may enter from the cracks to the chip end portion during a high temperature and high humidity bias (THB) reliability test, and the surface electrode may be corroded. As a result, there has been a problem that the reliability of the semiconductor device may decrease.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of enhancing the reliability of a semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate having an end portion, an insulating film provided along the upper surface of the semiconductor substrate, a first surface electrode selectively provided on the insulating film, and a passivation film covering the insulating film and the first surface electrode. A cover portion of the passivation film that covers the first surface electrode has a tapered shape in which the width increases as it approaches the semiconductor substrate in a cross-sectional view by at least one of a first structure and a second structure. In the first structure, the first surface electrode includes a first metal portion and a second metal portion made of a metal having higher corrosion resistance than the first metal portion, and the second metal portion is provided in contact with a side surface of the first metal portion on the same side as the end portion of the semiconductor substrate in a plan view and has a tapered shape in which the width increases as it approaches the semiconductor substrate in a cross-sectional view. In the second structure, a first angle on the cover portion side formed by the side surface of the cover portion and the upper surface of the semiconductor substrate in a cross-sectional view is smaller than a second angle on the first surface electrode side formed by the side surface of the first surface electrode and the upper surface of the semiconductor substrate in a cross-sectional view.

Advantages of the Invention

[0007] According to the present disclosure, a cover portion of the passivation film that covers the first surface electrode has a tapered shape in which the width increases as it approaches the semiconductor substrate in a cross-sectional view by at least one of a first structure and a second structure. With such a configuration, the reliability of the semiconductor device can be improved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are examples, and not all features are necessarily essential. Also, in the descriptions given below, the same or similar reference numerals are assigned to similar components in a plurality of embodiments, and different components will be mainly described. Further, in the descriptions given below, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily have to match the positions and directions during actual implementation. Also, in the following description, n-type and p-type may be replaced with p-type and n-type, respectively.

[0010] <Embodiment 1> FIG. 1 is a plan view showing the configuration of a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, in the semiconductor device according to Embodiment 1, a cell region 81, a pad region 82, and a termination region 83 are defined.

[0011] The cell region 81 is a region where a plurality of semiconductor elements are provided. The plurality of semiconductor elements include, for example, at least any one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting - IGBT), an SBD (Schottky Barrier Diode), and a PND (PN junction diode). In this specification, for example, at least any one of A, B, C,..., and Z means any one of all combinations selected from one or more types from the group of A, B, C,..., and Z.

[0012] The pad region 82 is a region where control pads for controlling the semiconductor elements in the cell region 81 are provided. The control pads may be, for example, current sense pads, Kelvin emitter pads, gate pads, and temperature sense diode pads.

[0013] The current sense pad is a control pad for detecting the current flowing in the cell region 81 of the semiconductor device. This current sense pad is a control pad electrically connected to a part of the cell region 81 such that when a current flows in the cell region 81 of the semiconductor device, a current of one fraction to one ten-thousandth of the current flowing through the entire cell region 81 flows. The Kelvin emitter pad and the gate pad are control pads to which a gate drive voltage for on / off control of the semiconductor device is applied. The Kelvin emitter pad is electrically connected to the p-type base layer of the cell region 81, and the gate pad is electrically connected to the gate electrode of the cell region 81. The temperature sense diode pad is a control pad electrically connected to the anode and cathode of the temperature sense diode provided in the semiconductor device. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region 81 is measured, and the temperature of the semiconductor device is measured based on the voltage.

[0014] Around the combined region of the cell region 81 and the pad region 82, a termination region 83 for maintaining the breakdown voltage of the semiconductor device is provided. In the termination region 83, a breakdown voltage maintaining structure is appropriately provided. As the breakdown voltage maintaining structure, for example, on the first main surface side which is the front surface side of the semiconductor device, an FLR (Field Limiting Ring) surrounding the cell region 81 with a p-type terminal well layer of a p-type semiconductor, or a VLD (Variation of Lateral Doping) surrounding the cell region 81 with a p-type terminal well layer having a concentration gradient may be provided. The number of the ring-shaped p-type terminal well layers used for the FLR and the concentration distribution used for the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device. Also, a p-type terminal well layer may be provided over substantially the entire pad region 82, or a part of the cell region 81 may be provided in the pad region 82.

[0015] Figure 2 is a cross-sectional view showing the configuration of the termination region 83 of the semiconductor device according to Embodiment 1, specifically, a cross-sectional view taken along line A-A' of Figure 1. As shown in Figure 2, the semiconductor device according to Embodiment 1 includes a semiconductor substrate 1, an insulating film 2, a first surface electrode 3, a glass coat 4 which is a passivation film, and a polyimide film 5.

[0016] The end of the semiconductor substrate 1 corresponds to the outer peripheral portion of the terminal region 83 in FIG. 1. In the cross-sectional views after FIG. 2, the right side in FIG. 2 corresponds to the end side of the semiconductor substrate 1, and the left side in FIG. 2 corresponds to the cell region 81 side of the semiconductor substrate 1. For the sake of convenience, in the cross-sectional views after FIG. 2, the illustration of the lower part of the semiconductor substrate 1 and the like is omitted.

[0017] The semiconductor substrate 1 may be made of silicon (Si) or may be made of a wide-bandgap semiconductor. The wide-bandgap semiconductor includes, for example, at least any one of silicon carbide (SiC), silicon nitride (SiN), gallium oxide (Ga2O3), gallium nitride (GaN), and diamond. In particular, the semiconductor substrate 1 made of SiC can apply a higher electric field to the terminal region 83 than a semiconductor substrate made of Si. Further, the semiconductor substrate 1 may be composed of a normal semiconductor wafer or may be composed of an epitaxial growth layer.

[0018] The semiconductor substrate 1 includes a guard ring region 1a which is a p-type terminal well layer. The guard ring region 1a has an annular shape in plan view similar to the terminal region 83. The number of the guard ring regions 1a in FIG. 2 is one, but may be plural. The region in contact with the guard ring region 1a in the semiconductor substrate 1 has, for example, an n-type.

[0019] The insulating film 2 is, for example, an oxide film and is provided along the upper surface of the semiconductor substrate 1. In FIG. 2, the insulating film 2 is directly provided on the semiconductor substrate 1, but may be indirectly provided on the semiconductor substrate 1.

[0020] The first surface electrode 3 is selectively provided on the insulating film 2. In the first embodiment, the first surface electrode 3 is electrically connected to the guard ring region 1a through the contact hole of the insulating film 2 and functions as a field plate for providing breakdown voltage. Generally, the electric field during the driving of a semiconductor element tends to concentrate at the interface between the guard ring region 1a directly under the contact hole of the insulating film 2 and the insulating film 2. The first surface electrode 3 that functions as a field plate can relieve such electric field concentration, so the breakdown voltage can be increased. Note that although the first surface electrode 3 according to the first embodiment functions as a field plate, the first surface electrode 3 does not necessarily have to function as a field plate.

[0021] The first surface electrode 3 according to the first embodiment includes a first metal portion 3a and a second metal portion 3b. The first metal portion 3a is made of, for example, AlSi. Note that the first metal portion 3a may have a laminated structure composed of multiple layers.

[0022] The second metal portion 3b is made of a metal with higher corrosion resistance than the first metal portion 3a, for example, tungsten. The second metal portion 3b is provided in contact with the side surface of the first metal portion 3a on the same side as the end of the semiconductor substrate 1 in plan view. That is, the second metal portion 3b is provided in contact with the right side surface of the first metal portion 3a in FIG. 2. As in the example of FIG. 2, the second metal portion 3b may be provided in contact with not only the right side surface of the first metal portion 3a but also the left side surface of the first metal portion 3a. The second metal portion 3b has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate 1 in cross-sectional view, that is, as it goes downward in FIG. 2.

[0023] The glass coat 4 continuously covers the insulating film 2 and the first surface electrode 3. Due to the first structure in which the first surface electrode 3 includes the first metal part 3a and the second metal part 3b as described above, the cover part 4a of the glass coat 4 that covers the first surface electrode 3 has a tapered shape that widens as it approaches the semiconductor substrate 1 in a cross-sectional view. The glass coat 4 may have, for example, a laminated structure of an SInSiN film and a SiN film. The SInSiN film can stabilize the breakdown voltage at the end by correcting the electric field non-uniformity caused by the fluctuating interface charge Qss and mobile ions from the outside (e.g., mold resin), and the SiN film can serve as a protective film to prevent moisture intrusion.

[0024] The polyimide film 5 covers the glass coat 4. With such a configuration of overcoating with the polyimide film 5, the influence from the outside can be suppressed. In the cross-sectional views after FIG. 2, the illustration of the polyimide film 5 may be omitted.

[0025] FIGS. 3 and 4 are cross-sectional views showing the manufacturing process of the semiconductor device according to Embodiment 1. First, as shown in FIG. 3, an insulating film 2 is formed on the upper surface of the semiconductor substrate 1 provided with the guard ring region 1a by performing a film-forming process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or thermal oxidation. Then, a contact hole is formed in the insulating film 2 by performing patterning by an exposure process, a development process, and an etching process.

[0026] Next, a conductive member made of, for example, AlSi is formed on the guard ring region 1a and the insulating film 2 by performing a film-forming process, and the first metal part 3a is formed by patterning the conductive member. Then, a conductive member 31 made of, for example, tungsten is formed on the insulating film 2 and the first metal part 3a by performing a film-forming process.

[0027] Then, as shown in FIG. 4, by performing patterning such as etch-back on the conductive member 31, a second metal portion 3b having a tapered shape in a cross-sectional view is formed. As a result, the first surface electrode 3 having a tapered shape in a cross-sectional view as a whole is formed.

[0028] And a glass coat 4 that continuously covers the insulating film 2 and the first surface electrode 3 is formed. The cover portion 4a of the glass coat 4 has a tapered shape in a cross-sectional view due to the first structure in which the first surface electrode 3 has a tapered shape. Thereafter, by forming a polyimide film 5 that covers the glass coat 4, the semiconductor device of FIG. 2 is obtained.

[0029] <Summary of Embodiment 1> According to the semiconductor device according to the first embodiment as described above, the cover portion 4a of the glass coat 4 that covers the first surface electrode 3 has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate 1 in a cross-sectional view. Such a configuration in which the side surface of the cover portion 4a rises obliquely with respect to the upper surface of the semiconductor substrate 1 can suppress the generation of cracks due to stress concentration such as thermal stress more effectively than a configuration in which it rises vertically. Therefore, it is possible to suppress moisture from entering the chip end from the crack and corroding the first surface electrode 3 during the high-temperature and high-humidity bias (THB) reliability test, thereby enhancing the reliability of the semiconductor device.

[0030] Also, in the first embodiment, the second metal portion 3b made of a metal having higher corrosion resistance than the first metal portion 3a is provided in contact with the side surface of the first metal portion 3a on the same side as the end of the semiconductor substrate 1 in a plan view. According to such a configuration, even if a crack occurs, it is possible to suppress moisture from entering the chip end and corroding the first surface electrode 3.

[0031] <Embodiment 2> FIG. 5 is a cross-sectional view showing the configuration of the terminal region 83 in FIG. 1 of the semiconductor device according to Embodiment 2. The first surface electrode 3 is made of, for example, AlSi. Note that the first surface electrode 3 in FIG. 5 substantially corresponds to only the first metal portion 3a described in Embodiment 1, but the first surface electrode 3 according to Embodiment 2 may also include the second metal portion 3b described in Embodiment 1.

[0032] In Embodiment 2, a first angle θ1 on the cover portion 4a side formed by the side surface of the cover portion 4a and the upper surface of the semiconductor substrate 1 in a cross-sectional view is smaller than a second angle θ2 on the first surface electrode 3 side formed by the side surface of the first surface electrode 3 and the upper surface of the semiconductor substrate 1 in a cross-sectional view. Due to the second structure in which the first angle θ1 is smaller than the second angle θ2, the cover portion 4a covering the first surface electrode 3 in the glass coat 4 has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate 1 in a cross-sectional view.

[0033] FIGS. 6 and 7 are cross-sectional views showing the manufacturing process of the semiconductor device according to Embodiment 2. First, as shown in FIG. 6, an insulating film 2 having contact holes is formed on the upper surface of the semiconductor substrate 1. Then, by performing a film formation process and patterning, a first surface electrode 3 made of, for example, AlSi is formed on the guard ring region 1a and the insulating film 2. Next, by performing a film formation process, an SInSiN film 41 that continuously covers the insulating film 2 and the first surface electrode 3 is formed.

[0034] Then, as shown in FIG. 7, an anisotropic half-etching process is performed on the SInSiN film 41 so that the SInSiN film 41 has a target film thickness and a tapered shape. Then, by performing a film formation process, a SiN film is formed on the SInSiN film 41. Thereby, the glass coat 4 including the SInSiN film 41 and the SiN film is completed. Note that the glass coat 4 in FIG. 5 is thicker than the SInSiN film 41 in FIG. 7 by the thickness of the SiN film.

[0035] The cover portion 4a of the glass coat 4 has a tapered shape in a cross-sectional view by a second structure in which the first angle θ1 is smaller than the second angle θ2. Then, by forming the polyimide film 5 that covers the glass coat 4, the semiconductor device of FIG. 5 is obtained.

[0036] <Summary of Embodiment 2> According to the semiconductor device according to Embodiment 2 as described above, the cover portion 4a that covers the first surface electrode 3 of the glass coat 4 has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate 1 in a cross-sectional view. According to such a configuration, similarly to Embodiment 1, it is possible to suppress the occurrence of cracks, and thus the reliability of the semiconductor device can be improved.

[0037] <Embodiment 3> FIG. 8 is a cross-sectional view showing the configuration of the end region 83 of FIG. 1 of the semiconductor device according to Embodiment 3. The tapered shape of the cover portion 4a described in Embodiments 1 and 2 can be more easily formed as the height of the insulating film 2 of the first surface electrode 3 is lower. However, when the height of the surface electrode such as the first surface electrode 3 is low, there is a possibility that cracks may occur in the surface electrode when wire bonding is performed on the surface electrode in a later process.

[0038] Therefore, in Embodiment 3, as shown in FIG. 8, a plurality of annular guard ring regions 1a are provided on the semiconductor substrate 1, and the height of the surface electrode connected to the outermost peripheral guard ring region 1a is lower than the height of the other surface electrodes. Hereinafter, the configuration of the semiconductor device according to Embodiment 3 will be described in detail.

[0039] The configuration of Embodiment 3 is the same as the configuration in which the second surface electrode 7 is added to the configuration of Embodiment 2, and the second surface electrode 7 is farther from the first surface electrode 3 with respect to the end of the semiconductor substrate 1. That is, the second surface electrode 7 is provided on the cell region 81 side with respect to the first surface electrode 3.

[0040] The outermost guard ring region 1a is electrically connected to the first surface electrode 3 through the contact hole of the insulating film 2, and the other guard ring regions 1a are electrically connected to the second surface electrode 7 through the contact hole of the insulating film 2. And the height of the first surface electrode 3 with respect to the upper surface of the insulating film 2 is lower than the height of the second surface electrode 7 with respect to the upper surface of the insulating film 2. Note that the glass coat 4 may cover the second surface electrode 7, or the cover portion of the glass coat 4 that covers the second surface electrode 7 may have a tapered shape in which the width becomes wider as it approaches the semiconductor substrate 1 in a cross-sectional view.

[0041] FIGS. 9 and 10 are cross-sectional views showing the manufacturing process of the semiconductor device according to Embodiment 3. First, as shown in FIG. 9, an insulating film 2 having contact holes is formed on the upper surface of the semiconductor substrate 1. Then, by performing a film forming process, a conductive member 32 made of, for example, AlSi is formed on the guard ring region 1a and the insulating film 2. Next, formation of a resist 21, a half etching process of the conductive member 32, and removal of the resist 21 are performed so that the upper part of the conductive member 32 corresponding to the first surface electrode 3 is removed.

[0042] Then, as shown in FIG. 10, formation of a resist 22, an etching process of the conductive member 32, and removal of the resist 22 are performed so that the first surface electrode 3 is formed on the outermost guard ring region 1a and the second surface electrode 7 is formed on the other guard ring regions 1a. Note that since the upper part of the conductive member 32 corresponding to the first surface electrode 3 has already been removed, the height of the first surface electrode 3 with respect to the upper surface of the insulating film 2 is lower than the height of the second surface electrode 7 with respect to the upper surface of the insulating film 2.

[0043] Then, by forming the glass coat 4 in the same manner as in Embodiment 2, the cover portion 4a of the glass coat 4 that covers the first surface electrode 3 has a tapered shape in a cross-sectional view. After that, by forming a polyimide film 5 that covers the glass coat 4, the semiconductor device of FIG. 8 is obtained.

[0044] <Summary of Embodiment 3> According to the semiconductor device according to the third embodiment as described above, the height of the first surface electrode 3 with respect to the upper surface of the insulating film 2 is lower than the height of the second surface electrode 7 with respect to the upper surface of the insulating film 2, which is farther from the first surface electrode 3 with respect to the end portion of the semiconductor substrate 1. According to such a configuration, the tapered shape of the cover portion 4a covering the first surface electrode 3 can be easily formed, and the occurrence of cracks in the second surface electrode 7 due to wire bonding or the like can be suppressed.

[0045] In the above description, the number of the first surface electrodes 3 was one, but if the second surface electrode 7 exists, the number of the first surface electrodes 3 may be plural. Also, in the above, the case where the third embodiment is applied to the second embodiment has been described, but the third embodiment may be applied to the first embodiment. The same applies to the fourth and subsequent embodiments.

[0046] <Embodiment 4> The configuration of the termination region 83 of the semiconductor device according to the fourth embodiment is the same as the configuration of the termination region 83 of the semiconductor device according to the third embodiment shown in FIG. 8. In the third embodiment, the first surface electrode 3 and the second surface electrode 7 are formed by performing two etching steps (etching step and half-etching step) on the conductive member 32. On the other hand, in the fourth embodiment, the first surface electrode 3 and the second surface electrode 7 can be formed by performing one etching step on the conductive member 32.

[0047] FIGS. 11 to 14 are cross-sectional views showing the manufacturing process of the semiconductor device according to the fourth embodiment. First, a preparation step of preparing a semiconductor substrate 1 having an upper surface provided with a conductive member 32 made of AlSi via an insulating film 2 is performed.

[0048] Next, a resist is applied on the conductive member 32 and an exposure step is performed. The exposure step according to the fourth embodiment includes a first exposure step and a second exposure step that are performed individually.

[0049] In the first exposure process, as shown in FIG. 11, using mask A, the upper part of the resist 23b in the second region corresponding to the first surface electrode 3 is exposed without exposing the lower part of the resist 23b. In the first exposure process, the upper part of the resist 23c in the third region may also be exposed together with the upper part of the resist 23b in the second region.

[0050] In the second exposure process, as shown in FIG. 12, using mask B, the resist 23c in the third region is exposed without exposing the resist 23a in the first region corresponding to the second surface electrode 7 and the resist 23b in the second region. In the description here, the second exposure process is performed after the first exposure process, but the first exposure process may also be performed after the second exposure process.

[0051] As described above, as shown in FIG. 12, an exposure process is performed in which the upper part of the resist 23b in the second region and the resist 23c in the third region are exposed without exposing the resist 23a in the first region.

[0052] Then, as shown in FIG. 13, a development process is performed to remove the upper part of the exposed resist 23b in the second region and the exposed resist 23c in the third region. As a result, the lower part of the resist 23b in the second region and the resist 23a in the first region remain.

[0053] Then, an etching process is performed to selectively etch the conductive member 32 using the lower part of the resist 23b in the second region and the resist 23a in the first region. As a result, the conductive member 32 in the first region where the resist 23a is provided is not etched, and the conductive member 32 in the third region where the resists 23a and 23b are not provided is etched. Also, the thin resist 23b in the second region disappears during the etching process, and the conductive member 32 in the second region is half-etched. As a result, as shown in FIG. 14, the first surface electrode 3 having a height lower than that of the second surface electrode 7 is formed in the second region, and the second surface electrode 7 is formed in the first region farther from the second region with respect to the end of the semiconductor substrate 1.

[0054] Next, the resist 23a is removed. Thereafter, in the same manner as in Embodiment 3, a glass coat 4 that continuously covers the insulating film 2 and the first surface electrode 3 is formed, and a polyimide film 5 that covers the glass coat 4 is formed, whereby the semiconductor device of FIG. 8 is obtained.

[0055] <Summary of Embodiment 4> According to the method for manufacturing a semiconductor device according to Embodiment 4 as described above, the number of times of the etching process of the conductive member 32 can be reduced as compared with the method for manufacturing a semiconductor device according to Embodiment 3.

[0056] <Embodiment 5> The configuration of the termination region 83 of the semiconductor device according to Embodiment 5 is the same as the configuration of the termination region 83 of the semiconductor device according to Embodiment 3 shown in FIG. 8. In Embodiment 4, in the exposure process, two exposure processes (the first exposure process and the second exposure process performed individually) were performed. In contrast, in Embodiment 5, one exposure process is performed. Note that the method for manufacturing a semiconductor device according to Embodiment 5 is the same as the method for manufacturing a semiconductor device according to Embodiment 4 except for the exposure process. Therefore, the exposure process will be mainly described below.

[0057] FIG. 15 is a cross-sectional view showing the exposure process among the manufacturing processes of the semiconductor device according to Embodiment 5. In Embodiment 5, in the exposure process, the upper part of the resist 23b in the second region is exposed using the semi-transmissive mask C, and the resist 23c in the third region is exposed using the transmissive mask D without exposing the resist 23a in the first region, simultaneously. Note that the semi-transmissive mask C is made of, for example, a non-transmissive material, a transmissive material, and a semi-transmissive material, and the transmissive mask D is made of, for example, a non-transmissive material and a transmissive material.

[0058] <Summary of Embodiment 5> According to the method for manufacturing a semiconductor device according to Embodiment 5 as described above, the number of times of the exposure process can be reduced as compared with the method for manufacturing a semiconductor device according to Embodiment 4.

[0059] <Embodiment 6> FIG. 16 is a cross-sectional view showing the configuration of the terminal region 83 in FIG. 1 of the semiconductor device according to Embodiment 6. In Embodiment 6, a trench 1b is provided in a non-implanted region between the outermost guard ring region 1a of the semiconductor substrate 1 and the end of the semiconductor substrate 1. When the semiconductor element in the cell region 81 has an electrode such as a gate electrode provided in a trench, the trench 1b may be formed together with the trench of the semiconductor element.

[0060] As shown in FIG. 16, the trench 1b in the semiconductor substrate 1 houses at least the lower part of the first surface electrode 3. The height of the first surface electrode with respect to the upper surface of the insulating film 2 is, for example, about 1 μm and may be equal to the thickness of the glass coat 4.

[0061] <Summary of Embodiment 6> According to the semiconductor device according to Embodiment 6 as described above, since the height of the first surface electrode 3 with respect to the upper surface of the insulating film 2 can be lowered, the tapered shape of the cover portion 4a covering the first surface electrode 3 can be easily formed. Although not described above, the second surface electrode 7 described in Embodiment 3 etc. may be added. This is the same in the next Embodiment 7.

[0062] <Embodiment 7> FIG. 17 is a cross-sectional view showing the configuration of the terminal region 83 in FIG. 1 of the semiconductor device according to Embodiment 7. In Embodiment 7, a pattern portion 8 is added. The pattern portion 8 is provided between the semiconductor substrate 1 and the insulating film 9 which is an interlayer film in a cross-sectional view. Further, the pattern portion 8 is provided, for example, on both sides of the first surface electrode 3 connected to the outermost guard ring region 1a through the contact hole of the insulating film 9.

[0063] The pattern portion 8 includes an oxide film 8a and a polyimide layer 8b. The oxide film 8a is provided on the semiconductor substrate 1 in the same manner as the insulating film 2 described in Embodiment 1. The polyimide layer 8b is provided on the oxide film 8a and is provided inside the outer contour line of the oxide film 8a in a plan view.

[0064] In a cross-sectional view, the shape of the pattern portion 8 is reflected in the shape of the insulating film 9, whereby the recessed portion 9a is provided in the insulating film 9. The recessed portion 9a of the insulating film 9 houses at least the lower portion of the first surface electrode 3. The height of the first surface electrode 3 with respect to the upper surface of the insulating film 9 is, for example, about 1 μm and may be equivalent to the thickness of the glass coat 4.

[0065] Figs. 18 to 20 are cross-sectional views showing the manufacturing process of the semiconductor device according to Embodiment 7. First, as shown in Fig. 18, by performing a film forming process and patterning, an oxide film 8a, a polyimide layer 8b, and an insulating film 9 are formed on the semiconductor substrate 1 in this order. In a cross-sectional view, the shape of the pattern portion 8 is reflected in the shape of the insulating film 9, whereby the recessed portion 9a is provided in the insulating film 9.

[0066] Then, as shown in Fig. 19, by performing a film forming process, a conductive member 32 made of, for example, AlSi is formed on the guard ring region 1a and the interlayer film. Then, as shown in Fig. 20, by patterning the conductive member 32, the first surface electrode 3 whose at least the lower portion is housed in the recessed portion 9a is formed. Thereafter, in the same manner as in Embodiment 1, a glass coat 4 that continuously covers the insulating film 9 and the first surface electrode 3 is formed, and a polyimide film 5 that covers the glass coat 4 is formed, whereby the semiconductor device of Fig. 17 is obtained.

[0067] <Summary of Embodiment 7> According to the semiconductor device according to Embodiment 7 as described above, since the height of the first surface electrode 3 with respect to the upper surface of the insulating film 9 can be lowered, the tapered shape of the cover portion 4a that covers the first surface electrode 3 can be easily formed. Further, even in a region of the semiconductor substrate 1 where the trench 1b described in Embodiment 6 cannot be provided due to design constraints or the like, the height of the first surface electrode 3 can be lowered.

[0068] It should be noted that each embodiment and each modification can be freely combined, or each embodiment and each modification can be appropriately modified or omitted.

[0069] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0070] (Appendix 1) A semiconductor substrate having an end, An insulating film provided along the upper surface of the semiconductor substrate, A first surface electrode selectively provided on the insulating film, A passivation film covering the insulating film and the first surface electrode And comprising A cover portion of the passivation film that covers the first surface electrode has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate in a cross-sectional view by at least one of a first structure and a second structure, In the first structure, the first surface electrode is composed of a first metal portion and a metal having higher corrosion resistance than the first metal portion, and is provided in contact with a side surface of the first metal portion on the same side as the end of the semiconductor substrate in a plan view, and has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate in a cross-sectional view, and includes a second metal portion, In the second structure, a semiconductor device in which a first angle on the cover portion side formed by a side surface of the cover portion and the upper surface of the semiconductor substrate in a cross-sectional view is smaller than a second angle on the first surface electrode side formed by a side surface of the first surface electrode and the upper surface of the semiconductor substrate in a cross-sectional view.

[0071] (Appendix 2) The semiconductor device according to Appendix 1, Further comprising a second surface electrode provided on the insulating film farther from the first surface electrode with respect to the end of the semiconductor substrate, The semiconductor substrate Includes a plurality of annular guard ring regions each electrically connected to either the first surface electrode or the second surface electrode through a contact hole in the insulating film, A semiconductor device in which a height of the first surface electrode with respect to the upper surface of the insulating film is lower than a height of the second surface electrode with respect to the upper surface of the insulating film.

[0072] (Appendix 3) The semiconductor device according to Appendix 1 or Appendix 2, wherein a trench that houses at least a lower portion of the first surface electrode is provided in the semiconductor substrate.

[0073] (Appendix 4) The semiconductor device according to Appendix 1 or Appendix 2, wherein in a cross-sectional view, a pattern portion is further provided between the semiconductor substrate and the insulating film and on both sides of the first surface electrode, in the cross-sectional view, a concave portion that houses at least a lower portion of the first surface electrode is provided in the insulating film by reflecting the shape of the pattern portion in the shape of the insulating film.

[0074] (Appendix 5) A preparation step of preparing a semiconductor substrate having an upper surface provided with a conductive member via an insulating film; An exposure step of applying a resist on the conductive member and exposing an upper portion of the resist in a second region and the resist in a third region without exposing the resist in a first region; A development step of removing the exposed upper portion of the resist in the second region and the exposed resist in the third region; An etching step of selectively etching the conductive member using the lower portion of the resist in the second region and the resist in the first region to form a first surface electrode and a second surface electrode that is farther from the first surface electrode with respect to an end portion of the semiconductor substrate, and the height of the first surface electrode with respect to the upper surface of the insulating film is lower than the height of the second surface electrode with respect to the upper surface of the insulating film; A film formation step of forming a passivation film that covers the insulating film and the first surface electrode, and a cover portion of the passivation film that covers the first surface electrode has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate in a cross-sectional view A method for manufacturing a semiconductor device, comprising

[0075] (Appendix 6) A method for manufacturing a semiconductor device according to Appendix 5, wherein A method of manufacturing a semiconductor device, comprising separately performing, in the exposure process, exposing the upper portion of the resist in the second region and exposing the resist in the third region.

[0076] (Appendix 7) A method of manufacturing a semiconductor device according to Appendix 5, In the exposure process, simultaneously performing exposing the upper portion of the resist in the second region using a semi-transmissive mask and exposing the resist in the third region using a transmissive mask.

Explanation of Reference Numerals

[0077] 1 Semiconductor substrate, 1a Guard ring region, 1b Trench, 2, 9 Insulating film, 3 First surface electrode, 3a First metal portion, 3b Second metal portion, 4 Glass coat, 4a Cover portion, 7 Second surface electrode, 8 Pattern portion, 9a Concave portion, 23a, 23b, 23c Resist, 32 Conductive member, C Semi-transmissive mask, D Transmissive mask, θ1 First angle, θ2 Second angle.

Claims

1. A semiconductor substrate having an end portion, An insulating film provided along the upper surface of the semiconductor substrate, A first surface electrode selectively provided on the insulating film, A passivation film covering the insulating film and the first surface electrode, and comprising: A cover portion of the passivation film covering the first surface electrode has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate in a cross-sectional view by at least one of a first structure and a second structure, In the first structure, the first surface electrode is made of a first metal portion and a metal having higher corrosion resistance than the first metal portion, and is provided in contact with a side surface of the first metal portion on the same side as the end portion of the semiconductor substrate in a plan view, and has a tapered shape in which the width becomes wider as it approaches the semiconductor substrate in a cross-sectional view, and includes a second metal portion, In the second structure, a first angle on the cover portion side formed by the side surface of the cover portion and the upper surface of the semiconductor substrate in a cross-sectional view is smaller than a second angle on the first surface electrode side formed by the side surface of the first surface electrode and the upper surface of the semiconductor substrate in a cross-sectional view. A semiconductor device.

2. The semiconductor device according to claim 1, further comprising a second surface electrode provided on the insulating film farther from the first surface electrode with respect to the end portion of the semiconductor substrate, The semiconductor substrate, includes a plurality of annular guard ring regions each electrically connected to either the first surface electrode or the second surface electrode through a contact hole in the insulating film, The height of the first surface electrode with respect to the upper surface of the insulating film is lower than the height of the second surface electrode with respect to the upper surface of the insulating film. A semiconductor device.

3. The semiconductor device according to claim 1 or claim 2, A trench for accommodating at least a lower portion of the first surface electrode is provided in the semiconductor substrate. A semiconductor device.

4. The semiconductor device according to claim 1 or claim 2, further comprising, in a cross-sectional view, a pattern portion provided between the semiconductor substrate and the insulating film and on both sides of the first surface electrode, A semiconductor device, wherein a recess for accommodating at least a lower portion of the first surface electrode is provided in the insulating film by reflecting the shape of the pattern portion in the cross-sectional view in the shape of the insulating film.

5. A preparation step of preparing a semiconductor substrate having an upper surface provided with a conductive member via an insulating film, An exposure step of applying a resist on the conductive member and exposing an upper portion of the resist in a second region and the resist in a third region without exposing the resist in a first region, A development step of removing the upper portion of the resist in the exposed second region and the resist in the exposed third region, An etching step of selectively etching the conductive member using the lower portion of the resist in the second region and the resist in the first region to form a first surface electrode and a second surface electrode farther from the first surface electrode with respect to an end of the semiconductor substrate, and a height of the first surface electrode with respect to the upper surface of the insulating film being lower than a height of the second surface electrode with respect to the upper surface of the insulating film, A film formation step of forming a passivation film covering the insulating film and the first surface electrode, wherein a cover portion of the passivation film covering the first surface electrode has a tapered shape in which a width becomes wider as it approaches the semiconductor substrate in a cross-sectional view A method of manufacturing a semiconductor device, comprising:

6. A method of manufacturing a semiconductor device according to claim 5, In the exposure step, exposing the upper portion of the resist in the second region and exposing the resist in the third region are performed separately. A method of manufacturing a semiconductor device.

7. A method of manufacturing a semiconductor device according to claim 5, A method of manufacturing a semiconductor device, comprising simultaneously exposing an upper portion of the resist in the second region using a semi-transmissive mask and exposing the resist in the third region using a transmissive mask in the exposure step.

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