Amplifier and driver amplifier circuit

Abstract

To provide an amplifier capable of improving characteristics.SOLUTION: An amplifier includes a first amplifier circuit that includes a first distributor 14 for distributing an input signal into a first signal and a second signal, a control amplifier 10 for amplifying the first signal and outputting the amplified signal as a third signal, a second distributor 16 for distributing the second signal into a fourth signal and a fifth signal having different phases at the center frequency of an operating band, a first auxiliary amplifier 12a for amplifying the fourth signal and outputting the amplified signal as a sixth signal, a second auxiliary amplifier 12b for amplifying the fifth signal and outputting the amplified signal as a seventh signal, and a hybrid coupler having a first end to which the sixth signal is input, a second end to which the seventh signal is input, a third end to which the third signal is input, and a fourth end to which an output signal is output, and a second amplifier circuit for amplifying the output signal of the first amplifier circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier and a driver amplifier circuit.

Background Art

[0002] It is known to use an LMBA (Load Modulated Balanced Amplifier) for the final-stage power amplifier in mobile communication transmission (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the output power of the final-stage power amplifier changes, the load of the driver amplifier fluctuates. For this reason, the characteristics of the driver amplifier deteriorate.

[0005] The present disclosure has been made in view of the above problems, and aims to improve characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal, and a hybrid coupler; a first amplifier circuit including the hybrid coupler; and a second amplifier circuit that amplifies the output signal of the first amplifier circuit.

[0007] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal to an amplifier circuit in a subsequent stage, and a hybrid coupler; a driver amplifier circuit including the hybrid coupler.

Advantages of the Invention

[0008] According to the present disclosure, the characteristics can be improved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal, and a hybrid coupler. By using the hybrid coupler, the resistance to load fluctuations when viewing the second amplifier circuit from the first amplifier circuit can be increased. Also, the efficiency can be increased. Therefore, the characteristics can be improved. (2) In (1) above, the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier may be amplifiers operating in class A or class AB. Thereby, linearity and efficiency can be improved. (3) In the above (1) or (2), the input bias voltages of the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier may be the same as each other. Thereby, the number of bias voltages can be reduced. (4) In any one of the above (1) to (3), the second amplifier circuit may include a first amplifier operating in class A or class AB, and a second amplifier operating in class C connected in parallel with the first amplifier. Thereby, although the load variation seen from the first amplifier circuit to the second amplifier circuit increases, the tolerance to load variation can be improved. (5) In any one of the above (1) to (3), the second amplifier circuit may be an LMBA or Doherty amplifier circuit. Thereby, although the load variation seen from the first amplifier circuit to the second amplifier circuit increases, the tolerance to load variation can be improved. (6) In the above (1), the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier may be amplifiers operating in class A or class AB, and the second amplifier circuit may be an LMBA or Doherty amplifier circuit. Thereby, although the load variation seen from the first amplifier circuit to the second amplifier circuit increases, the tolerance to load variation can be improved. (7) In the above (1) to (6), the hybrid coupler may be a branch line coupler. Thereby, the tolerance to load variation can be improved. (8) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal to an amplification circuit in a subsequent stage, and a hybrid coupler. By using the hybrid coupler, the resistance to load fluctuations when viewing the amplification circuit in the subsequent stage from the driver amplification circuit can be increased. Also, the efficiency can be increased. Therefore, the characteristics can be improved. (9) In the above (8), the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier may be amplifiers operating in class A or class AB. Thereby, linearity and efficiency can be improved. (10) In the above (8) or (9), the input bias voltages of the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier may be the same as each other. Thereby, the number of bias voltages can be reduced.

[0011] [Details of Embodiments of the Present Disclosure] Specific examples of the amplifier and the driver amplification circuit according to the embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is intended to be indicated by the claims and to include all modifications within the meaning and scope equivalent to the claims.

[0012] [Example 1] Example 1 is an example using an LMBA as a driver amplifier circuit and a power amplifier circuit. FIG. 1 is a circuit diagram of the amplifier according to Example 1. As shown in FIG. 1, in the amplifier 100 of Example 1, a driver amplifier circuit 50 is connected between an input terminal Tin and an intermediate terminal Tm, and a power amplifier circuit 52 is connected between the intermediate terminal Tm and an output terminal Tout. The driver amplifier circuit 50 (first amplifier circuit) amplifies an input signal Sin, which is a high-frequency signal input to the input terminal Tin, and outputs the amplified signal as an intermediate signal Sm to the intermediate terminal Tm. The power amplifier circuit 52 (second amplifier circuit, subsequent-stage amplifier circuit) amplifies the intermediate signal Sm input to the intermediate terminal Tm, and outputs the amplified signal as an output signal Sout to the output terminal Tout.

[0013] When the amplifier 100 is used in a base station for mobile communication, the frequencies of the input signal Sin, the intermediate signal Sm, and the output signal Sout are, for example, 0.5 GHz or higher and 20 GHz or lower. The output signal Sout is radiated into space from, for example, an antenna.

[0014] In the driver amplifier circuit 50, a control amplifier 10 and a balun 15 are connected in parallel between the input terminal Tin and the intermediate terminal Tm. A high-frequency signal is input to the input terminal Tin as the input signal Sin. A distributor 14 (first distributor) distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal). The control amplifier 10 amplifies the signal S1 and outputs the amplified signal as a signal S3 (third signal) to an end T23 of a synthesizer 18.

[0015] The signal S2 distributed by the distributor 14 is input to the balun 15. The balun 15 includes a distributor 16, auxiliary amplifiers 12a and 12b, and a synthesizer 18. The distributor 16 (second distributor) distributes the signal S2 input to an end T11 into a signal S4 (fourth signal) and a signal S5 (fifth signal), and outputs them from ends T13 and T14, respectively. An end T12 of the distributor 16 is grounded via a resistor R0 (for example, 50 Ω).

[0016] The auxiliary amplifier 12a (first auxiliary amplifier) amplifies the signal S4 and outputs the amplified signal as the signal S6 (sixth signal) to the terminal T21 of the synthesizer 18. The auxiliary amplifier 12b (second auxiliary amplifier) amplifies the signal S5 and outputs the amplified signal as the signal S7 (seventh signal) to the terminal T22 of the synthesizer 18. The synthesizer 18 synthesizes the signals S3, S6, and S7, and outputs the synthesized signal as the intermediate signal Sm from the terminal T24 of the synthesizer 18 to the intermediate terminal Tm.

[0017] In the power amplification circuit 52, a control amplifier 20 and a balance amplifier 25 are connected in parallel between the intermediate terminal Tm and the output terminal Tout. The distributor 24 distributes the intermediate signal Sm input to the intermediate terminal Tm into signals S11 and S12. The control amplifier 20 amplifies the signal S11 and outputs the amplified signal as the signal S13 to the terminal T23 of the synthesizer 28.

[0018] The signal S12 distributed by the distributor 24 is input to the balance amplifier 25. The balance amplifier 25 includes a distributor 26, auxiliary amplifiers 22a and 22b, and a synthesizer 28. The distributor 26 distributes the signal S12 input to the terminal T11 into signals S14 and S15, and outputs them from the terminals T13 and T14, respectively. The terminal T12 of the distributor 26 is grounded via a resistor R0.

[0019] The auxiliary amplifier 22a amplifies the signal S14 and outputs the amplified signal as the signal S16 to the terminal T21 of the synthesizer 28. The auxiliary amplifier 22b amplifies the signal S15 and outputs the amplified signal as the signal S17 to the terminal T22 of the synthesizer 28. The synthesizer 28 synthesizes the signals S13, S16, and S17, and outputs the synthesized signal as the output signal Sout from the terminal T24 of the synthesizer 28 to the output terminal Tout.

[0020] [Detailed description of the driver amplification circuit] Figure 2 is a block diagram showing details of the driver amplifier circuit in Example 1. As shown in Figure 2, the signal S1 distributed by the distributor 14 passes through the matching circuit (MN: Matching Network) 30 and is input to the control amplifier 10. The matching circuit 30 matches the impedance seen from the distributor 14 to the matching circuit 30 and the impedance seen from the matching circuit 30 to the control amplifier 10. A bias circuit (BC: Bias Circuit) 34 is connected to a node in the line between the distributor 14 and the control amplifier 10. The bias circuit 34 supplies the input bias voltage VG1 to the control amplifier 10 and suppresses leakage of the signal S1 to the power supply that supplies the input bias voltage VG1.

[0021] The signal S3 amplified by the control amplifier 10 passes through the matching circuit 33 and is input to the terminal T23 of the synthesizer 18. The matching circuit 33 matches the impedance seen from the control amplifier 10 to the matching circuit 33 and the impedance seen from the matching circuit 33 to the synthesizer 18. A bias circuit 37 is connected to a node in the line between the control amplifier 10 and the synthesizer 18. The bias circuit 37 supplies the output bias voltage VD to the control amplifier 10 and suppresses leakage of the signal S3 to the power supply that supplies the output bias voltage VD.

[0022] The signal S2 distributed by the distributor 14 is input to the balanced amplifier 15. The balanced amplifier 15 includes a distributor 16, auxiliary amplifiers 12a and 12b, and a synthesizer 18. The distributor 16 distributes the signal S2 input to the terminal T11 into signals S4 and S5 and outputs them from the terminals T13 and T14, respectively. At the center frequency of the operating band, the phase of the signal S4 lags behind the phase of the signal S3 by, for example, about 90°. The amplitudes of the signals S3 and S4 are, for example, substantially the same. The 90° in the present disclosure does not have to be exactly 90°, and may be, for example, greater than 85° and less than 95°, or greater than or equal to 88° and less than or equal to 92°. The same applies to the following examples.

[0023] The signal S4 passes through the matching circuit 31 and is input to the auxiliary amplifier 12a. The matching circuit 31 matches the impedance seen from the distributor 16 to the matching circuit 31 and the impedance seen from the matching circuit 31 to the auxiliary amplifier 12a. A bias circuit 35 is connected to the node in the line between the distributor 16 and the auxiliary amplifier 12a. The bias circuit 35 supplies the input bias voltage VG2 to the auxiliary amplifier 12a and suppresses the leakage of the signal S4 to the power supply that supplies the input bias voltage VG2. The signal S6 amplified by the auxiliary amplifier 12a is input to the terminal T21 of the synthesizer 18.

[0024] The signal S5 passes through the matching circuit 32 and is input to the auxiliary amplifier 12b. The matching circuit 32 matches the impedance seen from the distributor 16 to the matching circuit 32 and the impedance seen from the matching circuit 32 to the auxiliary amplifier 12b. A bias circuit 36 is connected to the node in the line between the distributor 16 and the auxiliary amplifier 12b. The bias circuit 36 supplies the input bias voltage VG3 to the auxiliary amplifier 12b and suppresses the leakage of the signal S5 to the power supply that supplies the input bias voltage VG3. The signal S7 amplified by the auxiliary amplifier 12b is input to the terminal T22 of the synthesizer 18.

[0025] A matching circuit for impedance matching may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the synthesizer 18 adjusts the loads of the auxiliary amplifiers 12a and 12b. Therefore, a matching circuit may not be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. A harmonic processing circuit that reflects the harmonic signals in the signals S6 and S7 may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. The harmonic signals are, for example, the second harmonic or the third harmonic when the operating frequency of the amplifier circuit is taken as the fundamental wave. A bias circuit that supplies an output bias voltage to the auxiliary amplifiers 12a and 12b may be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the output bias voltages of the auxiliary amplifiers 12a and 12b are supplied from the bias circuit 37 through the synthesizer 18 to the auxiliary amplifiers 12a and 12b.

[0026] The control amplifier 10, auxiliary amplifiers 12a and 12b are transistors such as FETs (Field Effect Transistors), for example. The source is grounded, a high-frequency signal is input to the gate, and a high-frequency signal is output from the drain. The FET is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The control amplifier 10, auxiliary amplifiers 12a and 12b may each be provided with a multi-stage FET. When the control amplifier 10, auxiliary amplifiers 12a and 12b are FETs, the input bias voltages VG1, VG2, and VG3 are gate bias voltages, and the output bias voltage VD is a drain bias voltage.

[0027] The control amplifier 10, auxiliary amplifiers 12a and 12b are class AB or class B amplifiers. The input bias voltages VG1, VG2, and VG3 are the same bias voltage. As a result, the operating points when the input power in the control amplifier 10, auxiliary amplifiers 12a and 12b is small are substantially the same. Thus, in the driver amplifier circuit 50, from when the input power of the input signal Sin is small, the control amplifier 10, auxiliary amplifiers 12a and 12b amplify the input signal Sin in parallel.

[0028] [Explanation of Branch Line Coupler] FIG. 3 is a circuit diagram of a branch line coupler used in the distributor and the synthesizer in Embodiment 1. As shown in FIG. 3, a distributed constant type branch line coupler is used as the distributor 16 and the synthesizer 18. Transmission lines TL1, TL2, TL3, and TL4 are respectively connected between node N11 and N12, between node N11 and N13, between node N13 and N14, and between node N12 and N14. Transmission lines TL1 to TL4 are λ / 4 transmission lines. The electrical length of the λ / 4 transmission line is, for example, approximately λ / 4. Here, λ is the wavelength of the center frequency fo of the operating band of the amplifier 100. The electrical length of the λ / 4 transmission line in the present disclosure does not have to be exactly λ / 4, and may be, for example, 3λ / 16 or more and 5λ / 16 or less, 7λ / 32 or more and 9λ / 32 or less, or 15λ / 64 or more and 17λ / 64 or less. Between end T11 or T21 and node N11, between end T12 or T22 and node N12, between end T13 or T23 and node N13, and between end T14 or T24 and node N14 are connected by transmission line TL0.

[0029] In the distributor 16 in the driver amplifier circuit 50, the signal S2 input to end T11 is distributed to signals S4 and S5 and output from ends T13 and T14, respectively. The phase of the signal S6 at the center frequency fo lags behind the phase of the signal S5 at the center frequency fo by approximately 90°. End T12 is connected to the reference potential via resistor R0. The resistance value of resistor R0 is, for example, the reference impedance (for example, 50Ω). As the distributor 16, for example, a coupler combining a Wilkinson type distributor and a λ / 4 transmission line, a lumped multiplier type branch line coupler using an inductor and a capacitor, a distributed coupling type coupler in which two transmission lines are electromagnetically coupled, or a closely wound coil coupler in which two inductors are electromagnetically coupled may be used.

[0030] [Description of the synthesizer] Figure 4 is a block diagram near the synthesizer in Example 1. As shown in Figure 4, in the synthesizer 18 of the driver amplifier circuit 50, the signal S3 input to the synthesizer 18 from the terminal T23 is split into signals S3a and S3b at the terminals T21 and T22. The ratio of the power amplitudes of the signals S3a and S3b is approximately 1:1. The phase of the signal S3b at the terminal T22 lags behind the phase of the signal S3a at the terminal T21 by approximately 90°. The signals S3a and S3b are reflected at the terminals T21 and T22 respectively. The phase of the signal S7 lags behind the phase of the signal S6 by approximately 90°. The phase of the signal S3b at the terminal T22 lags behind the phase of the signal S3a at the terminal T21 by approximately 90°. Thus, by appropriately adjusting the phase difference between the signals S1 and S2, the phases of the signals S6 and S3a at the terminal T21 are aligned, and the phases of the signals S7 and S3b at the terminal T22 are aligned. The signal S6+S3a synthesized at the terminal T21 and the signal S7+S3b synthesized at the terminal T22 are synthesized at the terminal T24. The path from the terminal T21 to the terminal T24 is λ / 4 longer than the path from the terminal T22 to the terminal T24. Thus, at the terminal T24, the phases of the signals S6+S3a and S7+S3b are aligned. The synthesized signal S3+S6+S7 is output as an intermediate signal Sm to the intermediate terminal Tm.

[0031] The signals incident on terminals T21 and T22 from auxiliary amplifiers 12a and 12b are substantially S6 + S3a and S7 + S3b respectively, and the signals reflected at terminals T21 and T22 are substantially S3a and S3b respectively. Therefore, the reflection coefficients (i.e., the absolute values of impedances Z3a and Z3b) seen from terminals T21 and T22 to auxiliary amplifiers 12a and 12b are less than 1, and become smaller as the power amplitudes of signals S6 and S7 are larger. The impedances Z3a and Z3b that are the loads of auxiliary amplifiers 12a and 12b become substantially lower as the power amplitudes of signals S6 and S7 are larger. Thus, synthesizer 18 modulates the impedances Z3a and Z3b that are the loads seen from auxiliary amplifiers 12a and 12b to synthesizer 18 depending on the amplitudes of signals S6 and S7. On the other hand, since signals S6 and S7 are not output from terminal T23, the impedance Z2 seen from terminal T23 to matching circuit 33 is the reference impedance (e.g., 50 Ω, which is the characteristic impedance of transmission line TL0) regardless of the amplitudes of signals S6 and S7. Although an example of a distributed constant type branch line coupler has been described as synthesizer 18, synthesizer 18 may be a lumped parameter type branch line coupler using inductors and capacitors.

[0032] [Description of Power Amplification Circuit] In power amplification circuit 52, control amplifier 20 is a class A amplifier or a class AB amplifier, and auxiliary amplifiers 22a and 22b are class C amplifiers. Input bias voltages VG2 and VG3 are larger negatively compared to input bias voltage VG1. Thereby, the power of intermediate signal Sm when auxiliary amplifiers 22a and 22b are on is larger than the power of the intermediate signal when control amplifier 20 is on. The output power of power amplification circuit 52 is larger than the output power of driver amplification circuit 50. Therefore, the saturation powers of control amplifier 20, auxiliary amplifiers 22a and 22b are larger than the saturation powers of control amplifier 10, auxiliary amplifiers 12a and 12b of driver amplification circuit 50.

[0033] In the power amplifier circuit 52, when the power of the intermediate signal Sm is low, the control amplifier 20 operates, and the auxiliary amplifiers 22a and 22b do not operate. The signal S13 input from the terminal T23 to the synthesizer 28 is divided into two at the terminals T21 and T22, and the divided signals are reflected at the terminals T21 and T22. The reflected signals are combined at the terminal T24, and the combined signal S13 is output as the output signal Sout to the output terminal Tout. At this time, the impedance seen from the terminal T23 to the synthesizer 28 is the reference impedance.

[0034] When the power of the intermediate signal Sm is high, in addition to the control amplifier 20, the auxiliary amplifiers 22a and 22b operate. The operation of the synthesizer 28 at this time is the same as that of the synthesizer 18 in the driver amplifier circuit 50. A signal obtained by combining the signals S13, S16, and S17 is output as the output signal Sout to the terminal T24. The impedance seen from the terminal T23 to the synthesizer 28 is substantially the reference impedance regardless of the power of the intermediate signal Sm. The impedance seen from the auxiliary amplifiers 22a and 22b to the synthesizer 28 depends on the magnitudes of the powers of the signals S16 and S17. Thus, the synthesizer 28 modulates the impedance that becomes the load seen from the auxiliary amplifiers 22a and 22b to the synthesizer 18 depending on the amplitudes of the signals S16 and S17.

[0035] [Modification Example 1 of Embodiment 1] FIG. 5 is a block diagram of an amplifier according to Modification Example 1 of Embodiment 1. As shown in FIG. 5, in the amplifier 102 of Modification Example 1 of Embodiment 1, a Doherty amplifier circuit is used as the power amplifier circuit 52a. In the power amplifier circuit 52a, the distributor 24 distributes the intermediate signal Sm into signals S11 and S12. The main amplifier 21 amplifies the signal S11 and outputs the amplified signal as the signal S13. The peak amplifier 23 amplifies the signal S12 that has passed through the phase adjuster 27 and outputs the amplified signal as the signal S14. The synthesizer 28 combines the signal S13 and the signal S14 that have passed through the impedance converter 29, and outputs the combined signal as the output signal Sout to the output terminal Tout.

[0036] The main amplifier 21 is a class-A amplifier or a class-AB amplifier. The peak amplifier 23 is a class-C amplifier. When the power of the intermediate signal Sm is small, the main amplifier 21 operates and the peak amplifier 23 does not operate. When the power of the intermediate signal Sm is large, both the main amplifier 21 and the peak amplifier 23 operate. By providing the impedance converter 29, the load impedance seen from the synthesizer 28 to the output terminal Tout can be made the same both when the peak amplifier 23 is operating and when it is not operating.

[0037] As in the first embodiment and its first modification, the power amplifier circuit 52 or 52a uses a control amplifier 20 or a main amplifier 21 that operates in class-A or class-AB, and a balance amplifier 25 or a peak amplifier 23 that operates in class-C. Thereby, the efficiency in the power range from the power of the intermediate signal Sm at which the control amplifier 20 or the main amplifier 21 reaches the saturation power to the power of the intermediate signal Sm at which the balance amplifier 25 or the peak amplifier 23 reaches the saturation power can be increased.

[0038] [Comparative Example 1] FIG. 6 is a block diagram of the amplifier according to Comparative Example 1. As shown in FIG. 6, in the amplifier 110 of Comparative Example 1, the driver amplifier circuit 50a is a single amplifier 11 without a balance amplifier. The other configurations are the same as those in the first embodiment.

[0039] When the balance amplifier 25 or the peak amplifier 23 operates or does not operate depending on the magnitude of the intermediate signal Sm, as in the power amplifier circuits 52 and 52a, the impedance seen from the intermediate terminal Tm to the power amplifier circuits 52 and 52a changes. As a result, the load impedance of the driver amplifier circuit 50a changes. For this reason, when the power of the input signal Sin changes, the load impedance of the amplifier 11 changes from the optimal impedance matching condition. When the operating bandwidth is narrow, the impedance matching condition may be maintained even if the load impedance of the amplifier 11 fluctuates. However, when the operating bandwidth is broadened, it becomes difficult to prevent the characteristics from deteriorating over a wide band when the load impedance of the amplifier 11 fluctuates. Also, when the amplifier 11 is operated in class A to improve linearity, the efficiency decreases.

[0040] [Comparative Example 2] FIG. 7 is a block diagram of the amplifier according to Comparative Example 2. As shown in FIG. 7, in the amplifier 112 of Comparative Example 2, the driver amplifier circuit 50b is a balance amplifier 15a. The balance amplifier 15a includes a distributor 17, a combiner 19, and amplifiers 13a and 13b. The distributor 17 and the combiner 19 are, for example, the branch line couplers shown in FIG. 3. In the branch line coupler, the impedance seen from the amplifiers 13a to 13b to the combiner 19 changes gently even if the impedance seen from the intermediate terminal Tm to the power amplifier circuit 52 changes. For example, it can be set to a value close to the characteristic impedance of the transmission line TL0 in FIG. 3. For this reason, even if the power of the input signal Sin changes, the load impedances of the amplifiers 13a and 13b can be set to values close to the optimal impedance matching condition.

[0041] However, when the amplifiers 13a and 13b are operated in class A to improve linearity, the efficiency decreases.

[0042] [Description of Example 1 and its Modification 1] According to Example 1 and its Modification 1, the driver amplifier circuit 50 is an LMBA, and as the synthesizer 18, for example, a branch line coupler as shown in FIG. 3 is used. The branch line coupler includes an end T21 (first end) to which the signal S6 is input, an end T22 (second end) to which the signal S7 is input, an end T23 (third end) to which the signal S3 is input, and an end T24 (fourth end) that outputs the output signal Sout. Thereby, the load impedances of the auxiliary amplifiers 12a and 12b (the impedances Z3a and Z3b in FIG. 4) change gently even when the impedance seen from the intermediate terminal Tm to the power amplifier circuit 52 changes. Also, the load impedance of the control amplifier 10 (the impedance Z2 in FIG. 4) becomes the characteristic impedance of the transmission line TL0 of the branch line coupler and does not fluctuate due to the impedance seen from the intermediate terminal Tm to the power amplifier circuit 52. In this way, the resistance to load fluctuations seen from the driver amplifier circuit 50 to the power amplifier circuit 52 can be increased.

[0043] Since the load impedance of the control amplifier 10 does not change with the power of the input signal Sin, the efficiency of the control amplifier 10 can be increased by making the matching circuit 33 (see FIG. 2) an efficient match. Also, the load impedances of the auxiliary amplifiers 12a and 12b can be modulated by the power of the signal S3. Thereby, even when the powers of the signals S6 and S7 change, the load impedances of the auxiliary amplifiers 12a and 12b can be maintained near the efficient match. Thereby, the efficiency can be increased compared to Comparative Examples 1 and 2.

[0044] The control amplifier 10 may be an amplifier operating in class A or AB, and the auxiliary amplifiers 12a and 12b may be amplifiers operating in class C. Thereby, the efficiency can be increased. However, since a class C amplifier is used, the linearity and gain deteriorate. Therefore, the control amplifier 10, the auxiliary amplifiers 12a and 12b are made into amplifiers operating in class A or AB. Thereby, the linearity and gain are improved.

[0045] In order to operate as the balance amplifier 15, the input bias voltage VG2 and the input bias voltage VG3 of the auxiliary amplifier 12b are the same as each other. The input bias voltage VG1 of the control amplifier 10 and the input bias voltages VG2 and VG3 of the auxiliary amplifiers 12a and 12b may be different. By making the input bias voltage VG1 of the control amplifier 10, and the input bias voltages VG2 and VG3 of the auxiliary amplifiers 12a and 12b the same, the number of bias voltages can be reduced. The input bias voltages VG1, VG2, and VG3 being the same as each other does not necessarily mean they are exactly the same. For example, when the maximum value of the input bias voltages VG1, VG2, and VG3 is Vmax and the minimum value is Vmin, (Vmax - Vmin) / (Vmax + Vmin) ≤ 0.05 can be satisfied.

[0046] The power amplifier circuits 52 and 52a do not have to be LMBA or Doherty amplifier circuits, and any amplifier circuit can be used as long as the impedance seen from the intermediate terminal Tm to the power amplifier circuits 52 and 52a varies depending on the power of the intermediate signal Sm. Thus, as the amplifier circuit, an amplifier circuit including a first amplifier operating in class A or AB and a second amplifier operating in class C connected in parallel with the first amplifier can be used. In the first embodiment and its first modification, even if the impedance seen from the intermediate terminal Tm to the power amplifier circuits 52 and 52a varies, the resistance to load variation can be improved.

[0047] Also, in the first embodiment and its first modification, there are four matching circuits 30 to 33. Also in the second comparative example, there are four input matching circuits and output matching circuits for each of the amplifiers 13a and 13b. Since the area of the matching circuits is large, in the first comparative example, the first embodiment, and its first modification, the area does not change much, and miniaturization to about the level of the second comparative example is possible.

[0048] Table 1 shows the characteristics and sizes of driver amplifier circuits 50a (Comparative Example 1), 50b (Comparative Example 2), and 50 (Example 1). For the class C of driver amplifier circuit 50, it shows the case where auxiliary amplifiers 12a and 12b are of class C, and for the class AB, it shows the case where auxiliary amplifiers 12a and 12b are of class C. The control amplifier 10 is of class AB in all cases. The characteristics are load fluctuation tolerance, efficiency, and linearity / gain. The load fluctuation tolerance indicates whether the characteristics are difficult to change when the impedance seen from the intermediate terminal Tm to the power amplifier circuit 52 fluctuates. For each characteristic and size, A indicates the best characteristics, B indicates that the characteristics and size are good but worse than A, C indicates that the characteristics and size are better than D but worse than B, and D indicates that the characteristics and size are bad.

[0049]

Table 1

[0050] Referring to Table 1, in the driver amplifier circuit 50a of Comparative Example 1, one amplifier 11 is used. The linearity and gain are B, and the size is good at A, but the load fluctuation tolerance and efficiency are bad at C. In the driver amplifier circuit 50b of Comparative Example 2, a balanced amplifier 15a is used. For this reason, a hybrid coupler such as a branch-line coupler is used in the synthesizer 19. Thereby, the load fluctuation tolerance becomes good at B. The efficiency is C, which is the same as that of Comparative Example 1. Since amplifiers 13a, 13b, distributor 17, and synthesizer 19 are used, the size becomes larger than that of Comparative Example 1 and is B.

[0051] In the driver amplifier circuit 50 of Example 1, an LMBA is used. Since a hybrid coupler is used in the synthesizer 18, the load fluctuation tolerance is equivalent to that of Comparative Example 2 at B. The efficiency is very good at A. However, when the auxiliary amplifiers 12a and 12b are class C amplifiers, the linearity and gain deteriorate and become D. Since the number of matching circuits can be made the same as that of Comparative Example 2, the size is about the same as that of Comparative Example 2 at B.

[0052] In the driver amplifier circuit 50 of the first embodiment, when the auxiliary amplifiers 12a and 12b are class AB amplifiers, the efficiency is B, which is slightly inferior to the case where the auxiliary amplifiers 12a and 12b are class C amplifiers. However, the linearity and gain can be made as good as B.

[0053] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of reference numerals

[0054] 10 control amplifier 11, 13a, 13b amplifier 12a (first auxiliary amplifier), 12b (second auxiliary amplifier) auxiliary amplifier 14 (first distributor), 16 (second distributor), 17, 24, 26 distributor 15, 15a, 25 balun 18, 19, 28 combiner 20 control amplifier 22a, 22b auxiliary amplifier 23 peak amplifier 27 phase adjuster 29 impedance converter 30, 31, 32, 33 matching circuit 34, 35, 36, 37 bias circuit 50 (first amplifier circuit), 50a, 50b driver amplifier circuit 52 (second amplifier circuit), 52a power amplifier circuit 100, 102, 110, 112 amplifier S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal) Sin input signal Sm intermediate signal Sout output signal T21 (first terminal), T22 (second terminal), T23 (third terminal), T24 (fourth terminal) terminal Tin input terminal Tout output terminal

Claims

1. A first distributor that distributes an input signal into a first signal and a second signal; A control amplifier that amplifies the first signal and outputs the amplified signal as a third signal; A second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band; A first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal; A second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal; A hybrid coupler including a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal; A first amplification circuit comprising; A second amplification circuit that amplifies the output signal of the first amplification circuit; An amplifier comprising.

2. The amplifier according to claim 1, wherein the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier are amplifiers operating in class A or class AB.

3. The amplifier according to claim 1 or claim 2, wherein the input bias voltages of the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier are the same as each other.

4. The amplifier according to claim 1 or claim 2, wherein the second amplification circuit includes a first amplifier operating in class A or class AB and a second amplifier operating in class C connected in parallel with the first amplifier.

5. The amplifier according to claim 1 or claim 2, wherein the second amplification circuit is an LMBA or Doherty amplification circuit.

6. The control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier are amplifiers operating in class A or class AB, The amplifier according to claim 1, wherein the second amplification circuit is an LMBA or Doherty amplification circuit.

7. The amplifier according to claim 1 or claim 2, wherein the hybrid coupler is a branch-line coupler.

8. A first distributor that distributes an input signal into a first signal and a second signal, A control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, A second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, A first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, A second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, A hybrid coupler including a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal to an amplifier circuit in a subsequent stage, A driver amplifier circuit comprising the same.

9. The driver amplifier circuit according to claim 8, wherein the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier are amplifiers operating in class A or class AB.

10. The driver amplifier circuit according to claim 8 or claim 9, wherein the input bias voltages of the control amplifier, the first auxiliary amplifier, and the second auxiliary amplifier are the same as each other.

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