Printed circuit board and method of manufacturing the same

Abstract

To provide a printed circuit board including a cavity having a sufficient area for mounting an electronic component and capable of improving molding characteristics by increasing a bonding surface area between a molding material and the cavity, and a method of manufacturing the same.SOLUTION: A printed circuit board according to an embodiment includes a first insulating layer, a first wiring layer embedded in the first insulating layer, a first solder resist layer located on the first insulating layer, and a cavity formed by penetrating the first solder resist layer and a portion of the first insulating layer along a height direction, where a second depth of an edge portion of the cavity along the height direction may be greater than a first depth of a center portion of the cavity.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method for manufacturing the same.

Background Art

[0002] A printed circuit board is formed by forming a circuit pattern with a conductive material such as copper on an insulating material. As electronic devices in the IT field such as mobile phones have been miniaturized, a method has been proposed in which a cavity is formed in a printed circuit board and electronic components such as ICs, active elements, or passive elements are mounted in the cavity.

[0003] The deeper the cavity of the printed circuit board, the more parts of the electronic component can be mounted in the cavity, and the wider the cavity, the wider the bonding surface area between the molding material filled in the cavity to fix the electronic component and the cavity, the greater the adhesive force of the molding material, the easier the movement of the molding material during injection of the molding material, and the occurrence of voids and the like can be prevented.

[0004] However, when the width of the cavity is increased, the area occupied by wirings and the like formed in the printed circuit board may become narrow.

Summary of the Invention

Problems to be Solved by the Invention

[0005] An embodiment aims to provide a printed circuit board including a cavity that has an area sufficient for mounting an electronic component and can improve molding characteristics by widening the bonding surface area between the molding material and the cavity, and a method for manufacturing the same.

[0006] However, the problems to be solved by the embodiment are not limited to the above-described problems, and can be variously extended within the scope of the technical idea included in the embodiment.

[0007] The printed circuit board according to the embodiment includes a first insulating layer, a first wiring layer embedded in the first insulating layer, a first solder resist layer located on the first insulating layer, and a cavity formed by penetrating the first solder resist layer and a part of the first insulating layer along the height direction, and along the height direction, the second depth of the edge portion of the cavity can be greater than the first depth of the central portion of the cavity.

[0008] The cavity can include a first part formed in the part of the first insulating layer, a second part formed in the edge portion of the cavity, and a third part formed in the first solder resist layer.

[0009] The portion where the side wall and the bottom surface of the second part of the cavity meet can have a round shape.

[0010] Along the height direction, the side walls of the first part and the second part can be aligned with each other.

[0011] Along the direction perpendicular to the height direction, the first width of the first part, the second width of the second part, and the third width of the third part can be different from each other.

[0012] The second width of the second part may be smaller than the first width of the first part and the third width of the third part.

[0013] The third width of the third part can be greater than the first width of the first part.

[0014] The printed circuit board can further include a first via located in a first via hole in the first insulating layer and connected to the first wiring layer, the first depth of the first part is substantially equal to the first thickness of the first wiring layer, and the second depth of the second part may be smaller than the second thickness of the first via.

[0015] The third depth of the third part may be substantially the same as the third thickness of the first solder resist layer.

[0016] The method for manufacturing a printed circuit board according to an embodiment includes steps of forming a first wiring layer and a first sacrificial layer, laminating a first insulating layer that buries the first wiring layer and the first sacrificial layer on the first wiring layer and the first sacrificial layer, forming a first via hole overlapping with the first wiring layer in the first insulating layer, forming a first via in the first via hole of the first insulating layer, removing the first sacrificial layer by a first etching to form a preliminary cavity, and removing an edge portion at the bottom of the preliminary cavity by a second etching, and along the height direction, the second depth of the edge portion can be larger than the first depth of the central portion.

[0017] The method for manufacturing the printed circuit board may further include a step of forming a solder resist layer having an opening exposing the preliminary cavity on the first insulating layer.

[0018] According to an embodiment, it is possible to provide a printed circuit board including a cavity having an area sufficient for mounting an electronic component and capable of improving molding characteristics by widening a bonding surface area between a molding material and the cavity, and a method for manufacturing the same.

[0019] However, the effects of the embodiments are not limited to the above-described effects, and it is obvious that they can be variously extended without departing from the spirit and scope of the present invention.

Brief Description of the Drawings

[0020]

Figure 1

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Figure 14

Embodiments for Carrying Out the Invention

[0021] Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail so that those skilled in the art in the technical field to which the present invention pertains can easily implement them. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0022] To clearly explain the present invention, parts not related to the explanation are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

[0023] In addition, the attached drawings are provided to facilitate an easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings. It should be understood that the drawings include all modifications, equivalents, or alternatives included in the spirit and technical scope of the present invention.

[0024] In addition, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to what is shown in the drawings. In the drawings, the thickness is enlarged to clearly represent a plurality of layers and regions. And, in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

[0025] In addition, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is directly above the other part but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in the middle. Also, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being "on" or "above" in the direction opposite to gravity.

[0026] In addition, throughout the specification, a part "including" a certain component means that, unless otherwise stated to the contrary, it does not exclude other components but can further include other components.

[0027] In addition, throughout the specification, "on a plane" means when the target part is viewed from above, and "in a cross-section" means when a cross-section obtained by vertically cutting the target part is viewed from the side.

[0028] Also, throughout the specification, the term "connected" does not only mean that two or more components are directly connected, but can also mean that two or more components are indirectly connected via other components, not only physically connected but also electrically connected, or that they are integrated although they are called by different names according to their positions and functions.

[0029] Hereinafter, various embodiments and modifications will be described in detail with reference to the drawings.

[0030] Referring to FIGS. 1 and 2, a printed circuit board according to an embodiment will be described. FIG. 1 is a cross-sectional view of a printed circuit board according to an embodiment. FIG. 2 is an enlarged view of a part of a printed circuit board according to an embodiment.

[0031] Referring to FIG. 1, the printed circuit board 100 according to the present embodiment can include a plurality of stacked insulating layers (IL), a plurality of wiring layers (ML) embedded in the plurality of insulating layers (IL), a plurality of vias (MV) located in a plurality of via holes (VA) of the plurality of insulating layers (IL), a plurality of pad layers (MP), a solder resist layer (PL), and a cavity (CV) formed in a part of the plurality of insulating layers (IL).

[0032] The plurality of insulating layers (IL) can include a first insulating layer (IL1) and a second insulating layer (IL2) located below the first insulating layer (IL1) along the height direction (DRH).

[0033] The plurality of wiring layers (ML) can include a first wiring layer (ML1) embedded by the first insulating layer (IL1), and a second wiring layer (ML2) and a third wiring layer (ML22) embedded by the second insulating layer (IL2).

[0034] The plurality of vias (MV) can include a first via (MV1) located within a first via hole (VA1) formed in a first insulating layer (IL1), a second via (MV2) located within a second via hole (VA2) formed in a second insulating layer (IL2), and a third via (MV22) located within a third via hole (VA22) formed in the second insulating layer (IL2).

[0035] The plurality of pad layers (MP) can include a first pad layer (MP1) located above the first insulating layer (IL1), and a second pad layer (MP2) and a third pad layer (MP3) located below the second insulating layer (IL2).

[0036] A part of a first wiring layer (ML1) and a part of a second wiring layer (ML2) are connected via the first via (MV1), a part of the second wiring layer (ML2) and the second pad layer (MP2) are connected via the second via (MV2), the first pad layer (MP1) is connected to the first wiring layer (ML1), and a part of a third wiring layer (ML22) and the third pad layer (MP3) can be connected to each other via the third via (MV22).

[0037] The solder resist layer (PL) can include a first solder resist layer (PL1) located above the first insulating layer (IL1) and exposing a part of the first pad layer (MP1) through an opening (OP2), and a second solder resist layer (PL2) located below the second insulating layer (IL2) and exposing a part of the second pad layer (MP2) and the third pad layer (MP3) through openings (OP3A, OP3B).

[0038] The cavity (CV) can include a first part (CV1) and a second part (CV2) formed in the first insulating layer (IL1) and having different widths and heights from each other, and a third part (CV3) formed in the first solder resist layer (PL1).

[0039] The first part (CV1) of the cavity (CV) is located on the side surface of the first wiring layer (ML1), the second part (CV2) of the cavity (CV) is located on the side surface of the first via (MV1), and the third part (CV3) of the cavity (CV) is located on the side surface of the first solder resist layer (PL1).

[0040] Along the height direction (DRH), the first part (CV1) of the cavity (CV) can be located above the second part (CV2) of the cavity (CV), and the third part (CV3) of the cavity (CV) can be located above the first part (CV1) of the cavity (CV).

[0041] Along the direction (DRW) perpendicular to the height direction (DRH), the second part (CV2) of the cavity (CV) can be located at the edge portion of the bottom surface of the cavity (CV).

[0042] Along the height direction (DRH), the first part (CV1) of the cavity (CV) can have a depth substantially the same as the first thickness (D1) of the first wiring layer (ML1) embedded by the first insulating layer (IL1), the second part (CV2) of the cavity (CV) can have a depth smaller than the second thickness (D2) of the first via (MV1) located in the first via hole (VA1) formed in the first insulating layer (IL1), and the third part (CV3) of the cavity (CV) can have a depth substantially the same as the third thickness (D3) of the first solder resist layer (PL1).

[0043] Along the height direction (DRH), the central portion of the cavity (CV) includes the first part (CV1) and the third part (CV3), the central portion of the cavity (CV) can have a first depth (H1), the edge portion of the cavity (CV) further includes the second part (CV2) in addition to the first part (CV1) and the third part (CV3), and the edge portion of the cavity (CV) can have a second depth (H2). The second depth (H2) can be greater than the first depth (H1).

[0044] Referring to FIG. 2 together with FIG. 1, as described above, along the height direction (DRH), the central portion of the cavity (CV) includes a first portion (CV1) and a third portion (CV3). The central portion of the cavity (CV) can have a first depth (H1). The edge portion of the cavity (CV) further includes a second portion (CV2) in addition to the first portion (CV1) and the third portion (CV3). The edge portion of the cavity (CV) can have a second depth (H2). The second depth (H2) can be greater than the first depth (H1). Therefore, the surface of the bottom of the central portion of the cavity (CV) and the lowermost surface of the edge portion of the cavity (CV) can have a height difference (HD).

[0045] Along the direction (DRW) perpendicular to the height direction (DRH), the first portion (CV1) of the cavity (CV) formed in the first insulating layer (IL1) has a first width (W1). The second portion (CV2) of the cavity (CV) formed in the first insulating layer (IL1) can have a second width (W2). The third portion (CV3) of the cavity (CV) formed in a part of the first solder resist layer (PL1) can have a third width (W3).

[0046] The first width (W1) of the first portion (CV1) of the cavity (CV) and the second width (W2) of the second portion (CV2) of the cavity (CV) can be different from each other. The first width (W1) of the first portion (CV1) of the cavity (CV) can be wider than the second width (W2) of the second portion (CV2) of the cavity (CV).

[0047] Along the height direction (DRH), the second portion (CV2) of the cavity (CV) can overlap with the first portion (CV1) of the cavity (CV).

[0048] The third width (W3) of the third portion (CV3) of the cavity (CV) can be greater than the first width (W1) of the first portion (CV1) of the cavity (CV).

[0049] Along the height direction (DRH), the side walls of the first part (CV1) and the second part (CV2) of the cavity (CV) can be arranged in a row.

[0050] According to the printed circuit board according to the embodiment, by further including a second part (CV2) of the cavity (CV) that is formed in a part of the first insulating layer (IL1) and the second solder resist layer (PL2), is located in the etched part at the bottom of the cavity (CV), and is deeper than the first part (CV1) of the cavity (CV), a bottom surface sufficient for mounting electronic components can be maintained, and the surface area of the bottom of the cavity (CV) can be widened. Therefore, during the manufacturing process, by increasing the bonding surface area between the molding material inserted into the cavity (CV) and the cavity, the molding characteristics can be improved, the movement of the molding material to the edge part of the cavity is facilitated during the injection of the molding material, and the occurrence of voids and the like can be prevented.

[0051] Referring to FIG. 2, according to an embodiment, the bottom of the second part (CV2) of the cavity located in the etched part at the bottom of the cavity (CV) can include a corner part (CP) that is a part connected to the side wall of the cavity (CV) and has a curved round shape. When the corner part where the side wall and the bottom of the cavity (CV) meet has a folded form, when injecting the molding material into the cavity, the molding material may not be filled up to the corner part of the cavity, and defects such as voids may occur. However, according to the embodiment, since the corner part (CP) where the bottom surface and the side wall of the second part (CV2) of the cavity located in the etched part at the bottom of the cavity (CV) meet has a curved round shape, the molding material can be well filled up to the corner part, and the occurrence of defects such as voids can be prevented.

[0052] In the illustrated embodiment, the first part (CV1) of the cavity (CV) is located in a part of the first insulating layer (IL1). However, according to other embodiments, the first part (CV1) of the cavity (CV) can also be formed in an additional insulating layer other than the first insulating layer (IL1).

[0053] Hereinafter, with reference to FIGS. 3 to 13 together with FIG. 1, a method for manufacturing a printed circuit board according to an embodiment will be described. FIGS. 3 to 13 are cross-sectional views showing a method for manufacturing a printed circuit board according to an embodiment.

[0054] Referring to FIG. 3, a first copper foil layer (TC1) and a first wiring layer (ML1) can be formed on a carrier substrate (CS) including a core portion (CL) and thin film metal layers (MS) laminated on both sides of the core portion (CL). At this time, a first sacrificial layer (SF1) disposed at a position where a cavity (CV) is formed can be formed together. Since the first sacrificial layer (SF1) is formed together with the first wiring layer (ML1), it can be made of the same material as the first wiring layer (ML1) and have the same thickness as the first thickness (D1) of the first wiring layer (ML1).

[0055] As shown in FIG. 4, a first insulating layer (IL1) is formed on and embedded in the first wiring layer (ML1) and the first sacrificial layer (SF1), a first via hole (VA1) overlapping the first wiring layer (ML1) is formed in the first insulating layer (IL1), a first via (MV1) located in the first via hole (VA1) is formed, a second wiring layer (ML2) overlapping the first via (MV1) is formed on the first insulating layer (IL1), and a third wiring layer (ML22) can be formed on the first insulating layer (IL1).

[0056] Referring to FIG. 5, a second insulating layer (IL2) and a second copper foil layer (TC2) are formed on the second wiring layer (ML2) and the third wiring layer (ML22), and the second wiring layer (ML2) and the third wiring layer (ML22) are embedded with the second insulating layer (IL2).

[0057] Referring to FIG. 6, a second via hole (VA2) overlapping with the second wiring layer (ML2) and a third via hole (VA22) overlapping with the third wiring layer (ML22) are formed in the second insulating layer (IL2). A second via (VL2) is formed in the second via hole (VA2), and a third via (VL22) is formed in the third via hole (VA22). A second pad layer (MP2) located above the second insulating layer (IL2) and connected to the second wiring layer (ML2) via the second via (VL2), and a third pad layer (MP3) connected to the third wiring layer (ML22) via the third via (VL22) can be formed.

[0058] Next, as shown in FIG. 7, the substrate portion (SUB) is peeled off from both sides of the carrier substrate (CS).

[0059] Hereinafter, one substrate portion (SUB) peeled off from the carrier substrate (CS) will be described.

[0060] As shown in FIG. 8, the first copper foil layer (TC1) is removed from the substrate portion (SUB), and a first pad layer (MP1) is formed on the first wiring layer (ML1).

[0061] Referring to FIG. 9, a first solder resist layer (PL1) is formed on the first insulating layer (IL1), and a second solder resist layer (PL2) is formed under the second insulating layer (IL2).

[0062] The first solder resist layer (PL1) has a first opening (OP1) that exposes all of the first sacrificial layer (SF1) and a second opening (OP2) that overlaps at least a part of the first pad layer (MP1). The second solder resist layer (PL2) can have a third opening (OP3A) that overlaps with the second pad layer (MP2) and a fourth opening (OP3B) that overlaps with the third pad layer (MP3).

[0063] As shown in FIG. 10, a first mask layer (MSK1) is disposed to cover a second opening (OP2) of the first solder resist layer (PL1) and expose the first opening (OP1) on the first solder resist layer (PL1), and a second mask layer (MSK2) is disposed to cover a third opening (OP3A) and a fourth opening (OP3B) under the second solder resist layer (PL2). All portions except the region where the cavity (CV) is formed are covered by the first mask layer (MSK1) and the second mask layer (MSK2).

[0064] Using the first mask layer (MSK1) and the second mask layer (MSK2) as an etching mask, a first sacrificial layer (SF1) located in the region where the cavity (CV) is formed is first etched (ET) so that a preliminary cavity (CV11) can be formed in the portion where the first sacrificial layer (SF1) is located, as shown in FIG. 11.

[0065] Referring to FIG. 12, using the first mask layer (MSK1) and the second mask layer (MSK2) as an etching mask, a second etching (ET1) can be performed to remove a part (P1) of the side wall and the bottom of the preliminary cavity (CV11) located at the edge portion of the preliminary cavity (CV11). The second etching (ET1) can use a laser, but the embodiment is not limited thereto.

[0066] In FIG. 12, a part (P1) of the side wall and the bottom of the preliminary cavity (CV11) located at the edge portion of the preliminary cavity (CV11) removed through the second etching (ET1) is indicated by a substantially square dotted line.

[0067] By the second etching (ET1), a part (P1) of the side wall and the bottom of the preliminary cavity (CV11) located at the edge portion of the preliminary cavity (CV11) is removed, so that a first part (CV1) of the cavity (CV) located on the side surface of the first wiring layer (ML1) and a second part (CV2) of the cavity (CV) located on the side surface of the first via (MV1) can be formed, as shown in FIG. 13.

[0068] As described above with reference to FIG. 2, according to one embodiment, the corner portion (CP) where the bottom surface and the side wall of the second portion (CV2) of the cavity meet can be formed to have a curved round shape.

[0069] The first opening (OP1) that exposes all of the first sacrificial layer (SF1) of the first solder resist layer (PL1) can be the third portion (CV3) of the cavity (CV).

[0070] Thereafter, the first mask layer (MSK1) and the second mask layer (MSK2) can be removed to form the printed circuit board 100 of FIG. 1.

[0071] According to the method for manufacturing a printed circuit board according to this embodiment, a plurality of dummy patterns (DP) and a first sacrificial layer (SF1) are formed so as to be embedded in the first insulating layer (IL1), and the mask layers (MSK1, MSK2) are used as etching masks for first etching (ET) to remove the first sacrificial layer (SF1), and second etching (ET1) is performed to remove a part of the side wall and the bottom of the edge portion of the cavity (CV) of the first insulating layer (IL1) to form the second portion (CV2) of the cavity (CV). Thus, the cavity (CV) can be formed to have a wider width and a greater depth than the preliminary cavity (CV11). Therefore, a sufficient bottom surface for mounting electronic components can be maintained, the surface area of the bottom of the cavity (CV) can be increased, and when an electronic component is mounted on the printed circuit board to form a semiconductor device, the bonding surface area between the molding material inserted into the cavity (CV) and the cavity can be increased to improve the molding characteristics, and the movement of the molding material to the edge portion of the cavity can be facilitated during injection of the molding material, and the occurrence of voids and the like can be prevented.

[0072] Also, according to the embodiment, the corner portion (CP) where the bottom surface and the side wall of the second portion (CV2) of the cavity (CV) located at the edge portion of the bottom surface of the cavity (CV) meet can be formed to have a curved round shape. By forming the corner portion where the bottom surface and the side wall meet to have a curved round shape, the molding material can be well filled up to the corner portion, and it is possible to prevent defects such as voids from occurring.

[0073] In the illustrated embodiment, the first sacrificial layer (SF1) formed at the position where the preliminary cavity (CV11) of the cavity (CV) is formed is formed to be located within at least a part of the first insulating layer (IL1). However, according to other embodiments, the first sacrificial layer (SF1) formed at the position where the preliminary cavity (CV11) is formed can also be additionally formed within an additional insulating layer. In this case, the depth of the first portion (CV1) of the cavity (CV) can be made larger.

[0074] Hereinafter, with reference to FIG. 14, a semiconductor device including a printed circuit board according to an embodiment will be described. FIG. 14 is a cross-sectional view of a semiconductor device including a printed circuit board according to an embodiment.

[0075] Referring to FIG. 14, a semiconductor device 1000 according to an embodiment includes a printed circuit board 100 according to the embodiment described above with reference to FIGS. 1 to 3, a counter substrate (SUB1) facing the printed circuit board 100, a mounting chip (CHP) such as an electronic component located within the cavity (CV) of the printed circuit board 100 and electrically connected to the counter substrate (SUB1) via a connection portion (SP), and a molding layer (MDL) located between the printed circuit board 100 and the counter substrate (SUB1) and connecting the printed circuit board 100 and the counter substrate (SUB1) to each other.

[0076] According to the semiconductor device 1000 according to the present embodiment, the cavity (CV) of the printed circuit board 100 where the mounting chip (CHP) is located is formed in a part of the first insulating layer (IL1) and the second solder resist layer (PL2), located in the etched portion at the bottom of the cavity (CV), and further includes a second portion (CV2) of the cavity (CV) that is deeper than the first portion (CV1) of the cavity (CV), thereby maintaining a sufficient bottom surface for mounting electronic components and increasing the surface area of the bottom of the cavity (CV). Therefore, during the manufacturing process, the bonding surface area between the molding material that constitutes the molding layer (MDL) inserted into the cavity (CV) and the cavity can be widened, improving the molding characteristics, facilitating the movement of the molding material to the edge portion of the cavity during injection of the molding material, and preventing the occurrence of voids and the like.

[0077] Also, according to the embodiment, by forming the corner portion (CP) where the bottom surface and the side wall of the second portion (CV2) of the cavity (CV) located at the edge portion of the bottom surface of the cavity (CV) meet to have a curved round shape, the molding material can be well filled up to the corner portion, preventing the occurrence of defects such as voids.

[0078] Many features of the printed circuit board 100 and the method for manufacturing the printed circuit board according to the embodiments described above are all applicable to the semiconductor device 1000 according to the present embodiment.

[0079] As described above, the preferred embodiments of the present invention have been described, but the present invention is not limited thereto, and various modifications can be made within the scope of the claims, the detailed description of the invention, and the accompanying drawings, and it is natural that this also belongs to the scope of the present invention.

Explanation of Reference Numerals

[0080] CV, CV1, CV2, CV3 Cavity IL, IL1, IL2 Insulating Layer ML, ML1, ML2, ML22 Wiring Layer MP, MP1, MP2, MP3 pad layers VA, VA1, VA2, VA22 via holes MV, MV1, MV2, MV22 vias PL, PL1, PL2 solder resist layers SF1 sacrificial layer MSK1, MSK2 mask layers

Claims

1. A first insulating layer; a first wiring layer embedded in the first insulating layer; a first solder resist layer overlying the first insulating layer; and a cavity formed along a height direction, penetrating the first solder resist layer and a portion of the first insulating layer; Including, A printed circuit board, comprising: a first depth at a center portion of the cavity along the height direction; a second depth at an edge portion of the cavity that is greater than a first depth at a center portion of the cavity along the height direction;

2. the cavity includes a first portion formed in the portion of the first insulating layer, a second portion formed in the edge portion of the cavity, and a third portion formed in the first solder resist layer; The printed circuit board of claim 1 , wherein the sidewalls of the first portion and the sidewalls of the second portion are aligned with each other along the height direction.

3. The printed circuit board of claim 2 , wherein the portion where the sidewall and bottom surface of the second portion of the cavity meet has a rounded shape.

4. The printed circuit board according to claim 2 , wherein a first width of the first portion, a second width of the second portion, and a third width of the third portion are different from each other along a plane direction perpendicular to the height direction.

5. The printed circuit board of claim 4 , wherein the second width of the second portion is less than the first width of the first portion and the third width of the third portion.

6. 6. The printed circuit board of claim 5, wherein the third width of the third portion is greater than the first width of the first portion.

7. a first via located in a first via hole in the first insulating layer and connected to the first wiring layer; a first depth of the first portion is substantially equal to a first thickness of the first wiring layer; The printed circuit board of claim 6 , wherein the second depth of the second portion is less than the second thickness of the first via.

8. The printed circuit board of claim 7 , wherein a third depth of the third portion is substantially equal to a third thickness of the first solder resist layer.

9. a first via located in a first via hole in the first insulating layer and connected to the first wiring layer; a first depth of the first portion is substantially equal to a first thickness of the first wiring layer; The printed circuit board of claim 2 , wherein the second depth of the second portion is less than the second thickness of the first via.

10. The printed circuit board of claim 9 , wherein the third depth of the third portion is substantially equal to a third thickness of the first solder resist layer.

11. forming a first wiring layer and a first sacrificial layer; laminating a first insulating layer on the first wiring layer and the first sacrificial layer to embed the first wiring layer and the first sacrificial layer; forming a first via hole in the first insulating layer so as to overlap a first wiring layer; forming a first via in the first via hole of the first insulating layer; removing the first sacrificial layer by a first etch to form a pre-cavity; and removing an edge portion of a bottom of the preliminary cavity by a second etching to form a cavity having a second depth at an edge portion that is greater than a first depth at a center portion along a height direction; A method for manufacturing a printed circuit board comprising:

12. The method for manufacturing a printed circuit board according to claim 11, further comprising the step of forming a solder resist layer having an opening exposing the preliminary cavity on the first insulating layer.

13. the cavity includes a first portion formed in the portion of the first insulating layer, a second portion formed in the edge portion of the cavity, and a third portion formed in the first solder resist layer; The method of claim 12 , wherein the sidewalls of the first portion and the sidewalls of the second portion are aligned with each other along the height direction by the second etching.

14. The method of claim 13 , wherein a first width of the first portion, a second width of the second portion, and a third width of the third portion are different from each other along a plane direction perpendicular to the height direction.

15. The method of claim 14 , wherein the second width of the second portion is smaller than the first width of the first portion and the third width of the third portion.

16. The method of claim 15 , wherein the third width of the third portion is greater than the first width of the first portion.

17. a first depth of the first portion is substantially equal to a first thickness of the first wiring layer; The method of claim 16 , wherein the second depth of the second portion is less than the second thickness of the first via.

18. The method for manufacturing a printed circuit board according to claim 17 , wherein a third depth of the third portion is substantially equal to a third thickness of the first solder resist layer.

19. a first depth of the first portion is substantially equal to a first thickness of the first wiring layer; The method of claim 13 , wherein the second depth of the second portion is less than the second thickness of the first via.

20. The method for manufacturing a printed circuit board according to claim 19 , wherein a third depth of the third portion is substantially equal to a third thickness of the first solder resist layer.

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