Semiconductor device

Abstract

To improve driving capability of a semiconductor device.SOLUTION: A semiconductor device has a first transistor and a second transistor. A first terminal of the first transistor is electrically connected with first wiring, and a second terminal of the first transistor is electrically connected with second wiring. A gate of the second transistor is electrically connected with third wiring, a first terminal of the second transistor is electrically connected with the third wiring line, and a second terminal of the second transistor is electrically connected with a gate of the first transistor. In each of the first transistor and second transistor, a channel region is formed of an oxide semiconductor. An off-current of each of the first transistor and second transistor per channel width of 1 μm is 1aA or less.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field of the disclosed invention relates to semiconductor devices, display devices, liquid crystal display devices, and driving methods thereof.

Background Art

[0002] The development of semiconductor devices composed of only one type of transistor is in progress. In particular, the development of semiconductor devices composed of only N-channel transistors is in progress (for example, Patent Documents 1 to 3). (For example, Patent Documents 1 to 3).

[0003] Such a semiconductor device includes, for example, a first transistor having one of a source and a drain connected to a power line and the other connected to an output, and one or more second transistors connected between the gate of the first transistor and each wiring.

[0004] And, in order to make the amplitude voltage of the output signal of the semiconductor device equal to the power supply voltage, the potential of the gate of the first transistor is often made higher (or lower) than the power supply voltage by capacitive coupling. To achieve this, it is necessary to float the gate of the first transistor. Therefore, it is necessary to turn off all of the one or more second transistors connected to the gate of the first transistor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

[0006] However, in the conventional technology, even when the second transistor is turned off, The charge held by the gate of the first transistor is lost over time due to the off-current of the first transistor. This causes a decrease in the driving capability of the semiconductor device.

[0007] In view of the above problems, an object of one embodiment of the present invention is to achieve better operation. Another object of one embodiment of the present invention is to improve the driving capability of a semiconductor device. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to a third wiring. a first terminal of the second transistor is electrically connected to a third wiring; and a second terminal of the second transistor electrically connected to the gate of the first transistor; The first transistor and the second transistor each have a channel region formed of an oxide semiconductor. and the off-state current of the first transistor and the second transistor is 1 aA / μm or less. It is a semiconductor device.

[0009] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. It has a first transistor and a fourth transistor, and a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring and a gate of the second transistor is electrically connected to a third wiring, and a first terminal of the second transistor is electrically connected to the third wiring and a second terminal of the second transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is electrically connected to a fourth wiring and a first terminal of the third transistor is electrically connected to a fifth wiring, and a second terminal of the third transistor is electrically connected to the second wiring and a gate of the fourth transistor is electrically connected to the fourth wiring, and a first terminal of the fourth transistor is electrically connected to the fifth wiring and a second terminal of the fourth transistor is electrically connected to a gate of the first transistor, and the first transistor to the fourth transistor have a channel region formed of an oxide semiconductor, and the semiconductor device has an off-current of 1 aA / μm or less for the first transistor to the fourth transistor

[0010] Another aspect of the present invention has a first transistor and a second transistor, and a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring, and a gate of the second transistor is electrically connected to the first wiring and a first terminal of the second transistor is electrically connected to the first wiring and a second terminal of the second transistor is electrically connected to a gate of the first transistor, and the first transistor and the second transistor have a channel region formed of an oxide semiconductor ​​​​​​formed, the off-currents of the first transistor and the second transistor are 1 aA / μm or less is a semiconductor device.

[0011] Another aspect of the present invention includes a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor is electrically connected to a first wiring, and a second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring. A first terminal of the second transistor is electrically connected to the first wiring, and a second terminal of the second transistor is electrically connected to a gate of the first transistor. A gate of the third transistor is electrically connected to a third wiring. A first terminal of the third transistor is electrically connected to a fourth wiring, and a second terminal of the third transistor is electrically connected to the second wiring. A gate of the fourth transistor is electrically connected to the third wiring. A first terminal of the fourth transistor is electrically connected to the fourth wiring, and a second terminal of the fourth transistor is electrically connected to a gate of the first transistor. The first to fourth transistors are

[0012] Another aspect of the present invention includes a first transistor, a second transistor, and N (where N is a natural number) third transistors and N fourth transistors. A first terminal of the first transistor is electrically connected to a first wiring, and a second terminal is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the first wiring is connected, the first terminal of the second transistor is electrically connected to the first wiring, and the second terminal of the transistor is electrically connected to the gate of the first transistor, and N the gates of the third transistors are each electrically connected to N third wirings, and N all of the first terminals of the third transistors are electrically connected to the fourth wiring, and N all of the second terminals of the third transistors are electrically connected to the second wiring, and N the gates of the fourth transistors are each electrically connected to N third wirings, and N all of the first terminals of the fourth transistors are electrically connected to the fourth wiring, and N all of the second terminals of the fourth transistors are electrically connected to the gate of the first transistor, and the first transistor, the second transistor, N third transistors, and N fourth transistors have a channel region formed of an oxide semiconductor, and the off-currents of the first transistor, the second transistor, N third transistors, and N fourth transistors are 1 aA / μm or less, which is a semiconductor device.

[0013] In the above semiconductor device, the oxide semiconductor preferably has a structure having a non-single crystal region Or, in the above semiconductor device, it is preferable to have a non-single crystal region in which the c-axis is oriented in a direction perpendicular to the surface of the oxide semiconductor

[0014] Further, one aspect of the present invention is an electronic device having the above semiconductor device and an operation switch .

[0015] For example, in this specification and the like, when it is explicitly described that X and Y are connected​ When X and Y are electrically connected and when X and Y are functionally connected, including the case where X and Y are directly connected. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, but also includes those other than the connection relationship shown in the figure or text.

[0016] As an example of the case where X and Y are electrically connected, there is a configuration in which one or more elements (e.g., switches, transistors, capacitor elements, inductors, resistance elements, diodes, etc.) that enable electrical connection between X and Y are connected between X and Y. Note that the expression "electrically connected" may be used in the same meaning as "connected". In this case, "electrically connected" includes "functionally connected" and "directly connected".

[0017] As an example of the case where X and Y are functionally connected, there is a configuration in which one or more circuits (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) are connected between X and Y. Also, Even if another circuit is interposed between X and Y, the case where the signal output from X is transmitted to Y shall be regarded as X and Y being functionally connected. For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0018] For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). For example, in this specification etc., when it is explicitly described that Y is formed on X, or Y is formed above X, it is not limited to Y being formed in direct contact with X. The case where they are not in direct contact, that is, the case where another object is interposed between X and Y, shall also be included. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0019] Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Therefore, for example, when it is explicitly described that layer Y is formed on (or above) layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated).

[0020] Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated). Furthermore, the same applies to the case where it is explicitly described that Y is formed above X. It is not limited to Y being in direct contact with X, and the case where another object is interposed between X and Y shall also be included. Therefore, for example, when it is said that layer Y is formed above layer X, it includes the case where layer Y is formed in direct contact with layer X and the case where another layer (for example, layer Z) etc. is formed on layer X in direct contact and layer Y is formed in direct contact on it. Note that another layer (for example, layer Z) may be a single layer or a multi-layer (laminated).

[0021] In addition, when it is explicitly described that Y is formed on X, Y is formed above X, or Y is formed over X, it also includes the case where Y is formed obliquely above X.

[0022] The same applies to the case where Y is below X or Y is beneath X.

[0023] For example, in this specification and the like, for those explicitly described as singular, it is desirable that they be singular. However, it is not limited thereto, and they may also be plural. Similarly, for those explicitly described as plural, it is desirable that they be plural. However, it is not limited thereto, and they may also be singular.

[0024] For example, in this specification and the like, terms such as first, second, and third are used to describe various elements, members, regions, layers, and areas separately from others. Therefore, terms such as first, second, and third do not limit the number of elements, members, regions, layers, areas, etc. Furthermore, for example, it is possible to replace "first" with "second" or "third", etc.

[0025] For example, in this specification and the like, terms indicating spatial arrangements such as "on", "above", "under", "beneath", "sideways", "to the right", "to the left", "diagonally", "in the back", "in the front", "inside", "outside", or "in" are often used to simply show the connection between an element or feature and another element or feature by a figure. However, it is not limited thereto, and these terms indicating spatial arrangements can include other directions in addition to the directions depicted in the figure. ​​​​​​There is. For example, when it is explicitly shown as Y on X, it is not limited to Y being on X. Since the devices in the figure can be inverted or rotated 180°, it is possible to include Y being below X. Thus, the phrase "on" can include the direction of "below" in addition to the direction of "on". However, without being limited to this, since the devices in the figure can be rotated in various directions, the phrase "on" can include other directions such as "sideways", "to the right", "to the left", "diagonally", "inward", "forward", "inside", "outside", or "in the middle" in addition to the directions of "on" and "below". That is, it can be appropriately interpreted according to the situation.

[0026] Note that in the figure, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0027]

Advantages of the Invention

[0028]

Brief Description of the Drawings

[0029]

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Embodiments for Carrying Out the Invention

[0030] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the description of the embodiments should not be construed as being limited thereto. In the configurations described below, the same parts or parts having similar functions are denoted by common reference numerals in different drawings, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0031] Note that the content described in a certain embodiment (it may be part of the content) can be applied, combined, or replaced with respect to the content described in one or more embodiments (including that embodiment and other embodiments) (it may also be part of the content).

[0032] (Embodiment 1) In this embodiment, an example of a semiconductor device and an example of a driving method for the semiconductor device will be described. In particular, an example of a circuit using a bootstrap operation and an example of a driving method for the circuit will be described.

[0033] First, an example of the configuration of the semiconductor device of this embodiment will be described.

[0034] FIG. 1(A) shows an example of the semiconductor device of this embodiment. The semiconductor device shown in FIG. 1(A) has a transistor 101 and a transistor 102. The first terminal of the transistor 101 is connected to the wiring 111, and the second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 113, and the second terminal of the transistor 102 is connected to the gate of the transistor 101, and the gate of the transistor 102 is connected to the wiring 113. However, the semiconductor device of this embodiment is not limited to the configuration shown in FIG. 1(A), and can have various other configurations.

[0035] Note that the connection point between the gate of the transistor 101 and the second terminal of the transistor 102 is designated as node 11.

[0036] Note that the case where the transistor 101 and the transistor 102 are N-channel type will be described. is explained. An N-channel transistor turns on when the potential difference between the gate and the source is greater than the threshold voltage.

[0037] Note that as the semiconductor layer of the transistor constituting the semiconductor device of this embodiment, it is preferable to use an oxide semiconductor. By using an oxide semiconductor as the semiconductor layer, it is possible to improve the S value of the transistor, reduce the off-current of the transistor, and / or improve the breakdown voltage of the transistor.

[0038] Note that in this specification and the like, even if the locations where all terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are connected are not specified, those skilled in the art may be able to configure an aspect of the invention. In particular, when there are multiple cases where the location where a terminal is connected is considered, it is not necessary to limit the location where the terminal is connected to a specific location. Therefore, for some terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., it may be possible to configure an aspect of the invention by specifying the location where the terminal is connected.

[0039] Note that in this specification and the like, for a certain circuit, if at least the location where it is connected to a terminal is specified, those skilled in the art may be able to identify the invention. Or, for a certain circuit, if at least its function is specified, those skilled in the art may be able to identify the invention. Therefore, for a certain circuit, even if its function is not specified, as long as the location where it is connected to a terminal is specified, it is disclosed as an aspect of the invention and constitutes an aspect of the invention. ​​​​​​​​​​​​​​It is possible. Or, for a certain circuit, even if the location connected to the terminal is not specified, if the function is specified, it is disclosed as one aspect of the invention, and it is possible to constitute one aspect of the invention. and is possible.

[0040] Next, an example of the potential applied to each wiring will be described.

[0041] A potential V1 is applied to wiring 111. In other words, a constant voltage ( for example, voltage V1) is supplied to wiring 111. Or, potentials V1 and V2 (V 2 < V1) are selectively or alternately applied to wiring 111. In other words, a signal (for example, a clock signal) is input to wiring 111. When potential V1 is applied to wiring 111, wiring 111 has the function of a power supply line. On the other hand, when potentials V1 and V2 are selectively applied to wiring 111, wiring 111 has the function of a signal line (for example, a clock signal line). However, the potential applied to wiring 111 is not limited to potentials V1 and V2, and various other potentials can be applied.

[0042] Also, a signal is output from wiring 112. Therefore, wiring 112 has the function of a signal line. Note that the potential of wiring 112 is, for example, equal to or higher than V2 and equal to or lower than V1.

[0043] Potentials V1 and V2 (V2 < V1) are selectively applied to wiring 113. In other words, a signal is input to wiring 113. Therefore, wiring 113 has the function of a signal line. However, the potential applied to wiring 113 is not limited to potentials V1 and V2. For example, a constant voltage can be supplied to wiring 113. This is the case. As another example, the wiring 113 may receive an analog signal or a signal having three or more potentials. It is possible to input.

[0044] When the potential A is applied to a node, wiring, electrode, terminal, etc., these potentials will be described assuming that they are equal to the potential A. That is, it will be described on the assumption that they are equal.

[0045] In this specification, expressions such as "equal" or "the same" may include cases where there are differences within the range of errors. For example, when it is said that "the potential (or voltage) is equal", it may include at least a range of ±10% as an error. More preferably, it is ±5%. Even more preferably, it is ±3%. Or, the range of potential variation due to leakage current, etc., the range of potential variation due to feed-through, etc., the range of potential variation due to noise, etc., the range of measurement error due to a measuring device, etc., or the range of potential variation due to process variations, etc., shall be included as the range of errors.

[0046] Next, an example of the operation of the semiconductor device of this embodiment will be described. In the following, there are two cases of operation: when the potential V1 is applied to the wiring 111 and when the potential V1 and the potential V2 are selectively applied to the wiring 111. These two cases of operation will be described.

[0047] An example of the operation of the semiconductor device of this embodiment when the potential V1 is applied to the wiring 111 will be described.

[0048] Assume that the initial value of the potential of the node 11 and the initial value of the potential of the wiring 112 are equal to the potential V2. When the potential V1 is applied to the wiring 113, the transistor 102 turns on, so the wiring 113 and the node 11 are in a conductive state. Then, the potential of the wiring 113 is supplied to the node 11. ​​​​ Therefore, the potential of node 11 starts to rise. Eventually, when the potential of node 11 reaches V2 + Vt h101 (Vth101 is the threshold voltage of transistor 101), transistor 1 01 turns on, so wiring 111 and wiring 112 become conductive. Then, since the potential of wiring 11 1 is supplied to wiring 112, the potential of wiring 112 starts to rise (see Fig. 1(B) for reference).

[0049] After that, when the potential of node 11 reaches V1 - Vth102 (Vth102 is the threshold voltage of transistor 102: V2 + Vth101 < V1 - Vth102 is satisfied), transistor 102 turns off, so wiring 113 and node 11 become non-conductive. Then, node 11 becomes floating. After that, the potential of wiring 112 continues to rise and eventually rises to a value equal to potential V 1. As the potential of wiring 112 rises, the potential of node 11 reaches V1 + Vth101 + Va (Va is a positive number) due to the parasitic capacitance between the gate and the second terminal of transistor 101 (see Fig. 1(C)). This is the so-called bootstrap operation.

[0050] When potential V2 is applied to wiring 113, transistor 102 turns off, so wiring 113 and node 11 become non-conductive. That is, node 11 becomes floating. In this case, the operation of the semiconductor device shown in Fig. 1(A) depends on the potential of node 11 before potential V2 is applied to wiring 113. For example, assume that the potential of node 11 before potential V2 is applied to wiring 113 is less than V2 + Vth101. When potential V2 is applied to wiring 113 in this state is applied, transistor 101 turns off, so wiring 111 and wiring 112 become non-conductive ​It becomes like this. Therefore, the potential of wiring 112 remains the value before applying the potential V2 to wiring 113 and becomes. Also, for example, assume that the potential of node 11 before applying the potential V2 to wiring 113 is V2 + V exceeds th101. When the potential V2 is applied to wiring 113 in this state, the trans istor 101 turns on, so wiring 111 and wiring 112 become conductive. Therefore, the potential of wiring 112 becomes equal to the value of potential V1, and the potential of node 11 becomes boot strap operation, it becomes V1 + Vth101 + Va.

[0051] An example of the operation of the semiconductor device according to the present embodiment when selectively applying the potential V1 and the potential V2 to wiring 111 will be described. An example of the operation will be described.

[0052] Assume that the initial value of the potential of node 11 and the initial value of the potential of wiring 112 are equal to the potential V2. When the potential V1 is applied to wiring 113 and the potential V2 is applied to wiring 111, the trans istor 102 turns on, so wiring 113 and node 11 become conductive. Then, since the potential of wiring 113 is supplied to node 11, the potential of node 11 starts to rise. Eventually, when the potential of node 11 reaches V2 + Vth101, the transistor 101 turns on so that wiring 111 and wiring 112 become conductive. Then, the potential of wiring 111 is supplied to wiring 112, so the potential of wiring 112 becomes equal to the potential V2 (see Fig. 2(A)). (Refer to Fig. 2(A)).

[0053] After that, when the potential of node 11 reaches V1 - Vth102, the transistor 102 turns off so that wiring 113 and node 11 become non-conductive. Then, node 11 becomes in a floating state (see Fig. 2(B)).

[0054] ​ After that, a potential V1 is applied to the wiring 111. At this time, the node 11 remains in a floating state. Therefore, the potential of the node 11 remains at V1-Vth102. The starter 101 remains on, and the wiring 111 and the wiring 112 remain in a conductive state. That is, the potential of the wiring 111 continues to be supplied to the wiring 112. At the same time that voltage V1 is applied, the potential of the wiring 112 starts to rise, and the potential V As the potential of the wiring 112 rises, the potential of the node 11 Due to the parasitic capacitance between the gate and the second terminal of transistor 101, V1 + Vth101 + Va (Va is a positive number) (see Figure 2(C)). This is called bootstrap operation. be.

[0055] Note that when a potential V2 is applied to the wiring 113, the transistor 102 is turned off. There is no electrical continuity between the wiring 113 and the node 11. That is, the node 11 is in a floating state. In this case, the operation of the semiconductor device illustrated in FIG. 2A is performed in the state before the potential V2 is applied to the wiring 113. It depends on the potential of the node 11. For example, In this state, the potential V2 is applied to the wiring 113. When the transistor 101 is turned off, the wiring 111 and the wiring 112 are not electrically connected to each other. Therefore, the potential of the wiring 112 remains at the value before the potential V2 is applied to the wiring 113. In addition, for example, the potential of the node 11 before the potential V2 is applied to the wiring 113 is V2+ In this state, when a potential V2 is applied to the wiring 113, Since the transistor 101 is turned on, the wiring 111 and the wiring 112 are in a conductive state. Therefore, the potential of wiring 112 becomes equal to the potential of wiring 111. That is, when potential V1 is applied to wiring 111, the potential of wiring 112 becomes equal to potential V1, and when potential V2 is applied to wiring 111, the potential of wiring 112 becomes equal to potential V2.

[0056] As described above, in the semiconductor device of this embodiment, by using the bootstrap operation, the potential of wiring 112 can be made equal to the potential of wiring 111.

[0057] Also, in the conventional technology, the S value of the transistor was large. Therefore, the time from when potential V1 is applied to wiring 113 until transistor 102 turns off becomes long. Or, the timing at which the potential of node 11 starts to rise due to the bootstrap operation is delayed. Or, the potential of node 11 is low. Or, the potential difference between the gate and the second terminal of transistor 101 becomes small. Or, the rise time of the potential of wiring 112 is long. Or, the load that can be connected to wiring 112 is small. Or, the channel width of transistor 101 is large. Or, the layout area is large. On the other hand, in the semiconductor device of this embodiment, since an oxide semiconductor is used as the semiconductor layer of the transistor constituting the semiconductor device, the S value can be made small. Therefore, the driving ability of the semiconductor device can be improved. For example, if the S value of transistor 102 is small,

[0058] the time from when potential V1 is applied to wiring 113 until transistor 102 turns off can be shortened, so that the potential of node 11 rises due to the bootstrap operation. Since an oxide semiconductor is used as the semiconductor layer of the transistor constituting the semiconductor device, the S value can be made small. Therefore, the driving ability of the semiconductor device can be improved. For example, if the S value of transistor 102 is small, the time from when potential V1 is applied to wiring 113 until transistor 102 turns off can be shortened, so that the potential of node 11 rises due to the bootstrap operation. Since an oxide semiconductor is used as the semiconductor layer of the transistor constituting the semiconductor device, the S value can be made small. Therefore, The starting timing can be advanced. The timing when the potential of node 11 starts to rise becomes earlier, so that the potential of node 11 can be increased, and thus the potential difference between the gate of transistor 101 and the second terminal can be increased. As a result, the rising time of the potential of wiring 112 can be shortened. Or, even if a large load is connected to wiring 112 , the load can be driven. Or, since the channel width of transistor 101 can be reduced , the layout area can be reduced. As another example, when the S value of transistor 101 is small, the rising time of the potential of wiring 112 can be shortened .

[0059] Also, in the conventional technology, the off-current of the transistor was large. Therefore, the amount of charge lost from node 11 increased with the passage of time . Or, the potential of node 11 decreased . Or, the time during which the potential of node 11 could be maintained at a value higher than V1 + Vth101 was short . Or, it was difficult to lower the driving frequency. Or, the range of the driving frequency at which the semiconductor device could operate was narrow .

[0060] In contrast, in the semiconductor device of the present embodiment, the off-current of the transistor constituting the semiconductor device is small. Therefore, the driving ability of the semiconductor device can be improved. For example, when the off-current of transistor 102 is small, the amount of charge lost from node 11 can be reduced , so that the decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened . As a result, the driving frequency can be lowered, so that the semiconductor device of the present embodiment can operate .​​​​ The range of the drive frequency that can be achieved can be widened.

[0061] Also, when selectively applying the potential V1 and the potential V2 to the wiring 111, the potential of the node 11 rises up to V1 - Vth102 and then further rises by the bootstrap operation. That is, the potential difference between the gate of the transistor 101 and the second terminal can be increased. As a result, the rise time of the potential of the wiring 112 can be shortened. Or, even if a large load is connected to the wiring 112, the load can be driven. Or, since the channel width of the transistor 101 can be reduced, the layout area can be reduced.

[0062] Note that when selectively applying the potential V1 and the potential V2 to the wiring 111, after the potential V1 is applied to the wiring 113, simultaneously with the timing when the potential V1 is applied to the wiring 111, the potential of the wiring 112 rises. Therefore, the semiconductor device of the present embodiment can be used as part of a shift register circuit.

[0063] Next, an example of the function of each transistor will be described.

[0064] The transistor 101 has a function of controlling the conduction state between the wiring 111 and the wiring 112. That is, the transistor 101 has a function as a switch. Or, the transistor 101 has a function of controlling the timing of supplying the potential of the wiring 111 to the wiring 112. Or, the transistor 101 has a function of controlling the timing of raising the potential of the wiring 112. Or, the transistor 101 has a function of controlling the timing of raising the potential of the wiring 112. Or, the transistor 101 has a function of controlling the potential difference between the gate of the transistor 101 and the second It has a function of controlling the timing to raise the potential of node 11 due to the parasitic capacitance with the terminal. However, transistor 101 may have at least one of the functions described above. Transistor 102 has a function of controlling the conduction state between wiring 113 and node 11. That is, transistor 102 has a function as a switch. Or, when the potential of wiring 113 is higher than the potential of node 11, transistor 102 makes wiring 113 and node 11 in a conductive state, and when the potential of wiring 113 is lower than the potential of node 11, it has a function of making wiring 113 and node 11 in a non-conductive state. That is, transistor 102 has a function as a diode. Or, transistor 102 has a function of controlling the timing to supply the potential of wiring 113 to node 11. Or, transistor 102 has a function of controlling the timing to raise the potential of node 11. Or, transistor 102 has a function of controlling the timing to make node 11 in a floating state. However, transistor 102 may have at least one of the functions described above.

[0065] Next, an example of the potential applied to each wiring will be described. By appropriately controlling the potential applied to each wiring, various functions can be given to the semiconductor device of the present embodiment, or the driving ability of the semiconductor device can be improved. For example, when potential V1 and potential V2 are selectively applied to wiring 113, it is possible to apply a potential higher than potential V1 or a potential less than potential V1 to wiring 111.

[0066]

[0067] ​​​​​​​​​​​​​​By applying a potential higher than potential V1 or a potential lower than potential V1 to 111, the semiconductor device of the present embodiment can have a function as a level shift circuit.

[0068] In addition, when applying a potential higher than potential V1 to wiring 111, the potential applied to wiring 111 is preferably higher than 1 times of potential V1 and 4 times or less. More preferably, it is 1.2 times or more and 3 times or less. Even more preferably, it is 1.5 times or more and 2.3 times or less.

[0069] In addition, when applying a potential lower than potential V1 to wiring 111, the potential applied to wiring 111 is the potential preferably 0.2 times or more and less than 1 times of potential V1. More preferably, it is 0.3 times or more and 0.9 times or less. Even more preferably, it is 0.5 times or more and 0.7 times or less.

[0070] Also, for example, when potential V1 is applied to wiring 111, it is possible to apply a potential higher than potential V1 to wiring 113. Specifically, the potential applied to wiring 113 is preferably higher than 1 times of the potential applied to wiring 111 and 3 times or less. More preferably it is 1.3 times or more and 2.5 times or less. Even more preferably, it is 1.5 times or more and 2 times or less. When the potential applied to wiring 113 is high, the time from when potential V1 is applied to wiring 113 until transistor 102 turns off can be shortened, so the timing at which the potential of node 1 1 starts to rise by the bootstrap operation can be advanced. When the timing at which the potential of node 11 starts to rise is early, the potential of node 11 can be increased, so the potential difference between the gate of transistor 101 and the second terminal can be increased. This is possible. As a result, the rising time of the potential of wiring 112 can be shortened. Alternatively, even if a large load is connected to wiring 112, the load can be driven. Or since the channel width of transistor 101 can be reduced, the layout area can be made small er.

[0071] Next, an example of the threshold voltage of each transistor will be described. By setting the threshold voltage of each transistor to an appropriate value, the driving ability of the semiconductor device can be improved.

[0072] For example, the smaller the threshold voltage of transistor 102, the more preferable. Specifically, the threshold voltage of transistor 102 is preferably smaller than the threshold voltage of transistor 101. Preferably, the threshold voltage of transistor 102 is 0.1 times or more and less than 1 times the threshold voltage of transistor 101. More preferably, it is 0.3 times or more and 0.9 times or less. Further preferably, it is 0.5 times or more and 0.7 times or less. When the threshold voltage of transistor 102 is small er, the time from when potential V1 is applied to wiring 113 until transistor 102 turns off can be shortened, so the timing at which the potential of node 11 starts to rise due to the bootstrap operation can be advanced. When the timing at which the potential of node 11 starts to rise is early, the potential of node 11 can be increased, so the potential difference between the gate of transistor 101 and the second terminal can be increased. As a result, the rising time of the potential of wiring 112 can be shortened. Alternatively, even if a large load is connected to wiring 112 the load can be driven. Or, the channel width of transistor 101 can be reduced and the layout area can be made small. and the potential difference between the gate of transistor 101 and the second terminal can be increased. As a result, the rising time of the potential of wiring 112 can be shortened. Alternatively, even if a large load is connected to wiring 112 the load can be driven. Or since the channel width of transistor 101 can be reduced, the layout area can be made small Since it is possible, the layout area can be reduced.

[0073] Also, for example, the threshold voltage of the transistor 101 is preferably smaller than the driving voltage of the semiconductor device (for example, potential V 1 - potential V2). In particular, the threshold voltage of the transistor 101 is preferably not less than 1 / 50 times and not more than 1 / 2 times the driving voltage of the semiconductor device. More preferably it is not less than 1 / 40 times and not more than 1 / 7 times. Even more preferably, it is not less than 1 / 30 times and 1 / 10 times or less. By making the threshold voltage of the transistor 101 smaller than the driving voltage of the semiconductor device it is possible to prevent malfunction of the semiconductor device and make the semiconductor device operate normally.

[0074] Next, an example of the size of each transistor will be described. By setting the size of each transistor to an appropriate value, it is possible to improve the driving ability of the semiconductor device of the present embodiment.

[0075] For example, the channel width of the transistor 101 is preferably larger than the channel width of the transistor 102. Preferably, the channel width of the transistor 101 is not less than 2 times and not more than 100 times the channel width of the transistor 1 02. More preferably, it is not less than 5 times and not more than 50 times. Even more preferably, it is not less than 10 times and not more than 30 times.

[0076] Note that the current supply ability can be controlled by the channel width (W) of the transistor. Specifically, the larger the channel width of the transistor, the higher the current supply ability of the transistor. However, the factor that controls the current supply ability of the transistor is the channel of the transistor. ​​​It is not limited to the channel width. For example, the current supply ability of the transistor can also be controlled by the channel length (L) of the transistor, the W / L ratio of the transistor, the potential difference (Vgs) between the gate and the source of the transistor, etc. Specifically, the smaller the channel length of the transistor, the larger the W / L ratio of the transistor, or the larger the Vgs of the transistor, the more improved the current supply ability of the transistor. Therefore, in this specification, etc., the description "the channel width of the transistor is large" is equivalent to "the channel length of the transistor is small", "the W / L ratio of the transistor is large", or "the Vgs of the transistor is large", and it is noted that they are synonymous. Depending on the potential difference (Vgs) between the gate and the source of the transistor, etc., the current supply ability of the transistor can also be controlled. Specifically, the smaller the channel length of the transistor, the larger the W / L ratio of the transistor, or the larger the Vgs of the transistor, the more improved the current supply ability of the transistor. Therefore, the smaller the channel length of the transistor, the larger the W / L ratio of the transistor, or the larger the Vgs of the transistor, the more improved the current supply ability of the transistor. Therefore, in this specification, etc., the description "the channel width of the transistor is large" is equivalent to "the channel length of the transistor is small", "the W / L ratio of the transistor is large", or "the Vgs of the transistor is large", and it is noted that they are synonymous. Therefore, in this specification, etc., the description "the channel width of the transistor is large" is equivalent to "the channel length of the transistor is small", "the W / L ratio of the transistor is large", or "the Vgs of the transistor is large", and it is noted that they are synonymous. Therefore, in this specification, etc., the description "the channel width of the transistor is large" is equivalent to "the channel length of the transistor is small", "the W / L ratio of the transistor is large", or "the Vgs of the transistor is large", and it is noted that they are synonymous. Therefore, in this specification, etc., the description "the channel width of the transistor is large" is equivalent to "the channel length of the transistor is small", "the W / L ratio of the transistor is large", or "the Vgs of the transistor is large", and it is noted that they are synonymous.

[0077] Next, a semiconductor device having a configuration different from that of the semiconductor device shown in Fig. 1(A) will be described.

[0078] For example, in the semiconductor device shown in Fig. 1(A), the wiring to which the gate and / or the first terminal of the transistor 102 is connected is not limited to the wiring 113, and various other wirings can be used. For example, in the semiconductor device shown in Fig. 1(A), the wiring to which the gate and / or the first terminal of the transistor 102 is connected is not limited to the wiring 113, and various other wirings can be used. It is possible.

[0079] Fig. 3(A) shows an example in which the gate of the transistor 102 is connected to the wiring 111 in the semiconductor device shown in Fig. 1(A). In the semiconductor device shown in Fig. 3(A), when the potential V2 is applied to the wiring 113, the potential of the node 11 can be made equal to the value of the potential V2. In the semiconductor device shown in Fig. 3(A), when the potential V2 is applied to the wiring 113, the potential of the node 11 can be made equal to the value of the potential V2. In the semiconductor device shown in Fig. 3(A), when the potential V2 is applied to the wiring 113, the potential of the node 11 can be made equal to the value of the potential V2. It can be made equal to the value of the potential V2.

[0080] Fig. 3(B) shows an example in which the first terminal of the transistor 102 is connected to the wiring 111 in the semiconductor device shown in Fig. 1(A). In the semiconductor device shown in Fig. 3(B), the potential V1 can be supplied to the node 11 from the wiring 111 having a smaller wiring resistance than the wiring 113. In the semiconductor device shown in Fig. 3(B), the potential V1 can be supplied to the node 11 from the wiring 111 having a smaller wiring resistance than the wiring 113. In the semiconductor device shown in Fig. 3(B), the potential V1 can be supplied to the node 11 from the wiring 111 having a smaller wiring resistance than the wiring 113. Therefore, the potential of the node 11 can be increased quickly.

[0081] FIG. 3C shows a semiconductor device in which the gate of the transistor 102 is arranged in the semiconductor device shown in FIG. When the first terminal of the transistor 102 is connected to the wiring 111, In the semiconductor device shown in FIG. 3C, the wiring 113 can be omitted. The number of wires and signals can be reduced.

[0082] In addition, for example, in the semiconductor device shown in FIG. 1(A) and FIG. 3(A) to (C), By increasing the capacitance between the line 1 and the wiring 112, the This allows the potential of node 11 to be increased.

[0083] Specifically, for example, in the semiconductor device shown in FIG. 1(A) and FIG. 3(A) to (C), A capacitance element can be connected between the node 11 and the wiring 112. One electrode of the transistor 101 is made of the same material as the gate of the transistor 101, and is connected to the node 11. The other electrode of the capacitor 121 is preferably connected to the It is preferable that the second terminal of the first terminal 112 is connected to the wiring 112. In this way, contact holes and the like can be omitted, making it possible to reduce the layout area. Cut.

[0084] Alternatively, for example, in the semiconductor device shown in FIG. 1(A) and FIG. 3(A) to (C), The material constituting the gate of the transistor 101 and the material constituting the second terminal of the transistor 101 The area where the material constituting the gate of the transistor 101 and the material of the transistor 102 overlap is It is possible to make it larger than the area where the material constituting the first terminal of 01 overlaps. In particular the area where the material constituting the gate of the transistor 101 and the material constituting the second terminal of the transistor 101 overlap is larger than 1 times and at most 5 times the area where the material constituting the gate of the transistor 101 and the material constituting the first terminal of the transistor 101 overlap. More preferably, it is at least 1.5 times and at most 4 times. Even more preferably it is at least 2 times and at most 3 times.

[0085] FIG. 3(D) shows an example in the semiconductor device shown in FIG. 1(A) when a capacitor element 121 is connected between the gate of the transistor 101 and the second terminal.

[0086] Also, for example, in the semiconductor devices shown in FIGS. 3(A) to 3(D), the first terminal of the transistor 101 and the gate or the first terminal of the transistor 102 can be connected to different wirings.

[0087] FIG. 4(A) shows an example in the semiconductor device shown in FIG. 3(A) where the first terminal of the transistor 101 is connected to the wiring 111A and the gate of the transistor 102 is connected to the wiring 111B.

[0088] FIG. 4(B) shows an example in the semiconductor device shown in FIG. 3(B) where the first terminal of the transistor 101 is connected to the wiring 111A and the first terminal of the transistor 102 is connected to the wiring 111B.

[0089] FIG. 4(C) shows an example in the semiconductor device shown in FIG. 3(C) where the first terminal of the transistor 101 is connected to the wiring 111A, the gate of the transistor 102 is connected to the wiring 111B, and the t​​​​ An example in which the first terminal of the transistor 102 is connected to the wiring 111B is shown.

[0090] Note that the wirings 111A and 111B have the same functions as the wiring 111. Then, a potential V1 is supplied to the wirings 111A and 111B. However, the potentials applied to the wiring 111A and the wiring 111B can be different values. For example, by applying a potential higher than the potential V1 or a potential lower than the potential V1 to the wiring 111A, the semiconductor device shown in FIGS. 4(A) to (C) has a function as a level shift circuit. As another example, by applying a potential higher than the potential V1 to the wiring 111B, the rising time of the potential of the node 11 can be shortened. As another example, by applying a potential lower than the potential V1 to the wiring 111B, the timing at which the transistor 102 turns off can be advanced.

[0091] Note that in this specification and the like, as an example of the transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used. When a multi-gate structure is used, a plurality of channel regions corresponding to the plurality of gate electrodes are connected in series to each other, so that a structure in which a plurality of transistors are connected in series is formed. Therefore, with the multi-gate structure, it is possible to further reduce the off-current and improve the breakdown voltage (improve the reliability) of the transistor. Alternatively, with the multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and a voltage-current characteristic with a flat slope can be obtained. The voltage-current characteristic with a flat slope is utilized. ​​​​​​​​​​​​When used, an ideal current source circuit or an active load having a very high resistance value can be realized. As a result, a differential circuit, a current mirror circuit, etc. with good characteristics can be realized.

[0092] Note that as an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below the channel can be applied. By adopting a structure in which gate electrodes are arranged above and below the channel, a circuit configuration is formed in which a plurality of transistors are connected in parallel. Therefore, since the channel area increases, an increase in the current value can be achieved. Or, by adopting a structure in which gate electrodes are arranged above and below the channel, depletion layers are likely to be formed, so that the S value can be improved.

[0093] Note that as an example of a transistor, a transistor having a structure in which a gate electrode is arranged above the channel region, a structure in which a gate electrode is arranged below the channel region, a positive stagger structure, a negative stagger structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series can be used.

[0094] Note that as an example of a transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) can be used. By adopting a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof), it is possible to prevent charge from accumulating in a part of the channel region and the operation from becoming unstable.

[0095] Note that in this specification, etc., in a certain embodiment, in the figure or text described, ​​​​​​​​​​​​Therefore, it is possible to extract a part thereof to constitute an aspect of the invention. Thus, When a figure or text describing a certain part is provided, the figure or text of that part can be extracted, and the content thus extracted is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for example, in a drawing or text describing one or more active elements (such as transistors and diodes), wirings, passive elements (such as capacitive elements and resistive elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc., it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute an aspect of the invention.

[0096] In addition, in this specification, etc., when at least one specific example is described in the figure or text described in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, when at least one specific example is described in the figure or text described in a certain This is also disclosed as one aspect of the invention and can constitute one aspect of the invention. It is possible.

[0097] In addition, in this specification and the like, at least the content described in the figure (even a part in the figure) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, for a certain content, if it is described in the figure, even if it is not described in the text, that content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and can constitute one aspect of the invention.

[0098] (Embodiment 2) In this embodiment, an example of the configuration of a semiconductor device and an example of a method for driving the semiconductor device will be described. In particular, an example of an inverter circuit and a buffer circuit using the semiconductor device shown in Embodiment 1, and an example of a method for driving the inverter circuit and the buffer circuit will be described. First, an example of the configuration of the semiconductor device of this embodiment will be described.

[0099] First, an example of the configuration of the semiconductor device of this embodiment will be described.

[0100] FIG. 5(A) shows an example of the configuration of a semiconductor device. The semiconductor device shown in FIG. 5(A) includes transistor 101, transistor 102, transistor 103, transistor 104, and wirings 112, 113, 114, 115. Transistors 101 to 104 are formed using an oxide semiconductor material. Also, transistor 103 and transistor 104 are N-channel type.

[0101] ​ FIG. 5(A) shows a semiconductor device obtained by adding transistor 103 and transistor 1 04 to the semiconductor device shown in FIG. 1(A). The gate of transistor 103 is connected to wiring 11 4, the first terminal of transistor 103 is connected to wiring 115, and the second terminal of the transistor 103 is connected to wiring 112. Also, the gate of transistor 104 is connected to wiring 114, the first terminal of transistor 104 is connected to wiring 115, and the second terminal of transistor 104 is connected to the gate of transistor 101. However, the configuration of the semiconductor device of this embodiment is not limited to FIG. 5(A), and various other configurations are possible. Next, an example of the potential applied to each wiring will be described.

[0102]

[0103] Potential V1 and potential V2 are selectively applied to wiring 114. In other words, a signal is input to wiring 11 4. Therefore, wiring 114 has the function of a signal line. Here, it is assumed that an inverted signal of the signal input to wiring 113 is input to wiring 114. Thus, when potential V2 is applied to wiring 113, potential V1 is applied to wiring 114, and when potential V1 is applied to wiring 113, potential V2 is applied to wiring 114. However, it is not limited to this, and the same potential may be applied to wiring 113 and wiring 114.

[0104] Potential V2 is applied to wiring 115. In other words, a constant voltage (for example, voltage V2) is supplied to wiring 115. Therefore, wiring 115 has the function of a power supply line. It is assumed that. However, the potential applied to the wiring 115 is not limited to the potential V2, and various other potentials can be applied. For example, the wiring 115 can be selectively applied with the potential V1 and the potential V2. By applying the potential V1 to the wiring 115, a reverse bias can be applied to the transistor 103 and the transistor 104, so that the shift of the threshold voltage of these transistors can be suppressed. Various other potentials can be applied. For example, the wiring 115 can be selectively applied with the potential V1 and the potential V2. By applying the potential V1 to the wiring 115, a reverse bias can be applied to the transistor 103 and the transistor 104, so that the shift of the threshold voltage of these transistors can be suppressed.

[0105] Next, an example of the operation of the semiconductor device shown in Fig. 5(A) will be described. Hereinafter, two operations will be described: the case where the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114, and the case where the potential V1 is applied to the wiring 113 and the potential V2 is applied to the wiring 114. In the following, two operations will be described: the case where the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114, and the case where the potential V1 is applied to the wiring 113 and the potential V2 is applied to the wiring 114. will be described.

[0106] Note that Fig. 5(B) shows an example of a timing chart for explaining the operation of the semiconductor device shown in Fig. 5(A). Fig. 5(B) shows the potential of the wiring 113 (potential V113), the potential of the wiring 114 (potential V114), the potential of the node 11 (potential V11), and the potential of the wiring 112 (potential V112). Note that Fig. 5(B) shows an example of a timing chart for explaining the operation of the semiconductor device shown in Fig. 5(A). Fig. 5(B) shows the potential of the wiring 113 (potential V113), the potential of the wiring 114 (potential V114), the potential of the node 11 (potential V11), and the potential of the wiring 112 (potential V112). will be described.

[0107] The operation when the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114 will be described.

[0108] When the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114, the transistor 104 turns on, so that the wiring 115 and the node 11 are in a conductive state. At this time, the transistor 102 turns off, and the wiring 113 and the node 11 are in a non-conductive state. In this way, the potential of the wiring 115 is supplied to the node 11, so that the potential of the node 11 is the potential V2. When the potential V2 is applied to the wiring 113 and the potential V1 is applied to the wiring 114, the transistor 104 turns on, so that the wiring 115 and the node 11 are in a conductive state. At this time, the transistor 102 turns off, and the wiring 113 and the node 11 are in a non-conductive state. In this way, the potential of the wiring 115 is supplied to the node 11, so that the potential of the node 11 is the potential V2. At this time, the transistor 102 turns off, and the wiring 113 and the node 11 are in a non-conductive state. In this way, the potential of the wiring 115 is supplied to the node 11, so that the potential of the node 11 is the potential V2. ​​​It becomes a value equal to. Therefore, the transistor 101 turns off, and the wiring 111 and the wiring 11 2 are in a non-conductive state. At this time, the transistor 103 turns on, and the wiring 115 and the wiring 112 are in a conductive state. Thus, the potential of the wiring 115 is supplied to the wiring 112, so that the potential of the wiring 112 becomes a value equal to the potential V2 (see Fig. 6(A)).

[0109] The operation when the potential V1 is applied to the wiring 113 and the potential V2 is applied to the wiring 114 will be described.

[0110] When the potential V1 is applied to the wiring 113 and the potential V2 is applied to the wiring 114, the transistor 104 turns off, and the wiring 115 and the node 11 are in a non-conductive state. At this time, the transistor 102 turns on, and the wiring 113 and the node 11 are in a conductive state. Thus, the potential of the wiring 113 is supplied to the node 11, so that the potential of the node 11 begins to rise. Eventually, the potential of the node 11 rises to V2 + Vth101. Therefore, the transistor 101 turns on, and the wiring 111 and the wiring 112 are in a conductive state. At this time, since the transistor 103 is off, the wiring 115 and the wiring 112 are in a non-conductive state. Thus, the potential of the wiring 111 is supplied to the wiring 112, so that the potential of the wiring 112 begins to rise (see Fig. 6(B)).

[0111] After that, the potential of the node 11 rises to V1 - Vth102. Therefore, the transistor 102 turns off, so that the wiring 113 and the node 11 are in a non-conductive state. Then, the node 11 becomes a floating state. At this time, the potential of the wiring 112 continues to rise. Therefore, Thus, the potential of node 11 rises to V1 + Vth101 + Va due to the parasitic capacitance between the gate and the second terminal of transistor 101. This is the so-called bootstrap operation . As a result, the potential of wiring 112 rises to a value equal to the potential V1 (see Fig. 6(C)) . .

[0112] As described above, the semiconductor device of this embodiment can make the potential of wiring 112 equal to the potential of wiring 111 or the potential of wiring 115 by using the bootstrap operation . .

[0113] In the conventional technology, the S value of the transistor was large. Therefore, the time from when the potential V1 was applied to wiring 113 until transistor 102 turned off was long. Or, the timing at which the potential of node 11 started to rise due to the bootstrap operation was late. Or, the potential of node 11 was low. Or, the potential difference between the gate and the second terminal of transistor 101 was small. Or, the rise time of the potential of wiring 112 was long. Or, the load that could be connected to wiring 112 was small. Or, the channel width of transistor 101 was large. Or, the layout area was large. Or, the fall time of the potential of wiring 112 was long. Or, the time from when the potential V1 was applied to wiring 114 until transistor 101 turned off was long. Or, the time during which current flowed from wiring 111 through transistor 101 and transistor 103 to wiring 115 was long. Or, the power consumption increased . . . . . . . . . . .

[0114] On the other hand, in the semiconductor device of the present embodiment, since an oxide semiconductor is used as the semiconductor layer of the transistor constituting the semiconductor device, the S value can be reduced. Therefore, the driving ability of the semiconductor device can be improved. For example, if the S value of the transistor 102 is small, the time from when the potential V1 is applied to the wiring 113 until the transistor 102 turns off can be shortened, so the timing at which the potential of the node 11 starts to rise by the bootstrap operation can be advanced. When the timing at which the potential of the node 11 starts to rise becomes earlier, the potential of the node 11 can be increased, so the potential difference between the gate of the transistor 101 and the second terminal can be increased. As a result, the rising time of the potential of the wiring 112 can be shortened. Or, even if a large load is connected to the wiring 112, the load can be driven. Or, since the channel width of the transistor 101 can be reduced, the layout area can be reduced. As another example, if the S value of the transistor 101 is small, the rising time of the potential of the wiring 112 can be shortened. As another example, if the S value of the transistor 103 is small, the falling time of the potential of the wiring 112 can be shortened. As another example, due to the small S value of the transistor 104, the time from when the potential V1 is applied to the wiring 114 until the transistor 101 turns off can be shortened. Therefore, the flow of current from the wiring 111 through the transistor 101 and the transistor 103 to the wiring 115 can be suppressed. Thereby, power consumption can be reduced. Since an oxide semiconductor is used as the semiconductor layer of the transistor constituting the semiconductor device, the S value can be reduced. Therefore, the driving ability of the semiconductor device can be improved. For example, if the S value of the transistor 102 is small, the time from when the potential V1 is applied to the wiring 113 until the transistor 102 turns off can be shortened, so the timing at which the potential of the node 11 starts to rise by the bootstrap operation can be advanced. When the timing at which the potential of the node 11 starts to rise becomes earlier, the potential of the node 11 can be increased, so the potential difference between the gate of the transistor 101 and the second terminal can be increased. As a result, the rising time of the potential of the wiring 112 can be shortened. Or, even if a large load is connected to the wiring 112, the load can be driven. Or, since the channel width of the transistor 101 can be reduced, the layout area can be reduced. As another example, if the S value of the transistor 101 is small, the rising time of the potential of the wiring 112 can be shortened. As another example, if the S value of the transistor 103 is small, the falling time of the potential of the wiring 112 can be shortened. As another example, due to the small S value of the transistor 104, the time from when the potential V1 is applied to the wiring 114 until the transistor 101 turns off can be shortened. Therefore, the flow of current from the wiring 111 through the transistor 101 and the transistor 103 to the wiring 115 can be suppressed. Thereby, power consumption can be reduced.

[0115] In the prior art, the off-current of the transistor was large. Therefore, the amount of charge leaking from node 11 was large. Or, the potential of node 11 was decreasing. Or, the time during which the potential of node 11 could be maintained at a value higher than V1 + Vth101 was short. Or, it was difficult to lower the drive frequency. Or, the range of drive frequencies at which the semiconductor device could operate was narrow. Or, the amount of charge leaking from node 11 was large. Or, the potential of node 11 was decreasing. Or, the time during which the potential of node 11 could be maintained at a value higher than V1 + Vth101 was short. Or, it was difficult to lower the drive frequency. Or, the range of drive frequencies at which the semiconductor device could operate was narrow. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened.

[0116] In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened. In contrast, the off-current of the transistor constituting the semiconductor device of the present embodiment is small. Therefore, the driving ability of the semiconductor device can be improved. For example, since the off-currents of transistor 102 and transistor 104 are small, the amount of charge leaking from node 11 can be reduced. Therefore, a decrease in the potential of node 11 can be suppressed. That is, the time during which the potential of node 11 can be maintained at a value higher than V1 + Vth101 can be lengthened. As a result, the drive frequency can be lowered, and the range of drive frequencies at which the semiconductor device of the present embodiment can operate can be widened.

[0117] Note that the signal output from wiring 112 becomes the inverted signal of the signal input to wiring 114. That is, the semiconductor device of the present embodiment can function as an inverter circuit. Or, the signal output from wiring 112 becomes the non-inverted signal of the signal input to wiring 113. That is, the semiconductor device of the present embodiment can function as a buffer circuit. Note that the signal output from wiring 112 becomes the inverted signal of the signal input to wiring 114. That is, the semiconductor device of the present embodiment can function as an inverter circuit. Or, the signal output from wiring 112 becomes the non-inverted signal of the signal input to wiring 113. That is, the semiconductor device of the present embodiment can function as a buffer circuit. Note that the signal output from wiring 112 becomes the inverted signal of the signal input to wiring 114. That is, the semiconductor device of the present embodiment can function as an inverter circuit. Or, the signal output from wiring 112 becomes the non-inverted signal of the signal input to wiring 113. That is, the semiconductor device of the present embodiment can function as a buffer circuit. Note that the signal output from wiring 112 becomes the inverted signal of the signal input to wiring 114. That is, the semiconductor device of the present embodiment can function as an inverter circuit. Or, the signal output from wiring 112 becomes the non-inverted signal of the signal input to wiring 113. That is, the semiconductor device of the present embodiment can function as a buffer circuit. Note that the signal output from wiring 112 becomes the inverted signal of the signal input to wiring 114. That is, the semiconductor device of the present embodiment can function as an inverter circuit. Or, the signal output from wiring 112 becomes the non-inverted signal of the signal input to wiring 113. That is, the semiconductor device of the present embodiment can function as a buffer circuit.

[0118] Next, an example of the function of each transistor will be described.

[0119] Transistor 103 has a function of controlling the conduction state between wiring 115 and wiring 112. That is, transistor 103 has a function as a switch. Or, transistor 103 has a function of controlling the timing of supplying the potential of wiring 115 to wiring 112. Or, transistor 103 has a function of controlling the timing of reducing the potential of wiring 112. However, transistor 103 only needs to have at least one of the functions described above.

[0120] Transistor 104 has a function of controlling the conduction state between wiring 115 and node 11. That is, transistor 104 has a function as a switch. Or, transistor 104 has a function of controlling the timing of supplying the potential of wiring 115 to node 11. Or, transistor 104 has a function of controlling the timing of reducing the potential of node 11. However, transistor 104 only needs to have at least one of the functions described above.

[0121] Next, variations in the potential applied to each wiring will be described. By appropriately controlling the potential applied to each wiring, the semiconductor device of the present embodiment can be provided with various functions, or the driving ability of the semiconductor device can be improved.

[0122] For example, when potential V1 and potential V2 are selectively applied to wiring 113 or wiring 114, it is possible to apply a potential higher than potential V1 or a potential less than potential V1 to wiring 111. Thereby, the semiconductor device of the present embodiment can have a function as a level shift circuit.

[0123] ​​​ Assume that a potential higher than the potential V1 is applied to the wiring 111. In this case, the potential is preferably higher than 1 times and not more than 4 times the potential V1. More preferably, it is 1.2 times or more and not more than 3 times. Even more preferably, it is 1.5 times or more and not more than 2.3 times.

[0124] Assume that a potential lower than the potential V1 is applied to the wiring 111. In this case, the potential is preferably 0.2 times or more and less than 1 times the potential V1. More preferably, it is 0.3 times or more and not more than 0.9 times. Even more preferably, it is 0.5 times or more and not more than 0.7 times.

[0125] Also, for example, when the potentials V1 and V2 are selectively applied to the wiring 114, it is possible to selectively apply a potential lower than the potential V1 and a potential higher than the potential V2 to the wiring 1 13. In this case, the rise time of the potential of the wiring 114 is often shorter than the rise time of the potential of the wiring 113. Or, the fall time of the potential of the wiring 114 is often shorter than the fall time of the potential of the wiring 1 13. Or, the wiring 114 is often connected to the wiring 1 13 via an inverter circuit.

[0126] Also, for example, when the potentials V1 and V2 are selectively applied to the wiring 113, it is possible to selectively apply a potential lower than the potential V1 and a potential higher than the potential V2 to the wiring 1 14. In this case, the rise time of the potential of the wiring 113 is often shorter than the rise time of the potential of the wiring 114. Or, the fall time of the potential of the wiring 113 is often shorter than the fall time of the potential of the wiring 1 14. Or, the wiring 113 is often connected to the wiring 1 14 via an inverter circuit. ​​​​​​

[0127] Next, an example of the threshold voltage of each transistor will be described. By setting the threshold voltage of each transistor to an appropriate value, the driving ability of the semiconductor device can be improved.

[0128] For example, the threshold voltage of transistor 103 is preferably greater than the threshold voltage of transistor 101 and / or the threshold voltage of transistor 102. In particular, the threshold voltage of transistor 103 is preferably higher than 1 times and not more than 3 times the threshold voltage of transistor 101. More preferably, it is not less than 1.2 times and not more than 2.5 times. Even more preferably, it is not less than 1.5 times and not more than 2 times.

[0129] Also, for example, the threshold voltage of transistor 104 is preferably greater than the threshold voltage of transistor 101 and / or the threshold voltage of transistor 102. In particular, the threshold voltage of transistor 1 04 is preferably greater than 1 times and not more than 3 times the threshold voltage of transistor 101. More preferably, it is not less than 1.2 times and not more than 2.5 times. Even more preferably, it is not less than 1. 5 times and not more than 2 times.

[0130] Also, for example, the sum of the threshold voltage of transistor 101 and the threshold voltage of transistor 103 is preferably smaller than the driving voltage of the semiconductor device (for example, potential V1 - potential V2). In particular, the sum of the threshold voltage of transistor 101 and the threshold voltage of transistor 103 is preferably not less than 1 / 100 times and not more than 1 / 2 times the driving voltage of the semiconductor device. More preferably it is not less than 1 / 50 times and not more than 1 / 5 times. Even more preferably, it is not less than 1 / 30 times and not more than 1 / 10 times. The sum of the threshold voltage of transistor 101 and the threshold voltage of transistor 103 being By being smaller than the driving voltage of the semiconductor device, malfunction of the semiconductor device can be prevented and the semiconductor device can operate normally.

[0131] Next, an example of the size of each transistor will be described. By setting the size of each transistor to an appropriate value, the driving ability of the semiconductor device according to the present embodiment can be improved .

[0132] For example, the potential difference between the gate and the source when the transistor 101 is turned on is often smaller than the potential difference between the gate and the source when the transistor 103 is turned on. Therefore, it is preferable that the channel width of the transistor 101 is larger than the channel width of the transistor 103. In particular, the channel width of the transistor 101 is preferably larger than 1 times and equal to or less than 10 times the channel width of the transistor 103. More preferably, it is 1.3 times or more and 5 times or less. Even more preferably, it is 1.5 times or more and 3 times or less.

[0133] Also, for example, the load of the wiring 112 is often larger than the load of the node 11. Therefore, it is preferable that the channel width of the transistor 103 is larger than the channel width of the transistor 104. In particular, the channel width of the transistor 103 is preferably larger than 1 times and equal to or less than 10 times the channel width of the transistor 104. More preferably, it is 1.5 times or more and 7 times or less. Even more preferably, it is 2 times or more and 5 times or less.

[0134] Also, for example, it is preferable that the channel length of the transistor 103 and / or the channel length of the transistor 104 is large. Specifically, the channel length of the transistor 103 is the channel length of the It is preferably larger than the channel length of transistor 101 and / or the channel length of transistor 102. Or, the channel length of transistor 104 is preferably larger than the channel length of transistor 101 and / or the channel length of transistor 102. By increasing the channel length of transistor 103 and / or the channel length of transistor 104, the shift amount of the threshold voltage of transistor 103 and / or transistor 104 can be reduced. Therefore, the reliability of the semiconductor device can be improved. Next, a semiconductor device having a configuration different from that of the semiconductor device shown in Fig. 5(A) will be described. For example, transistors 103 and 104 can be provided not only in the semiconductor device shown in Fig. 1(A), but also in the semiconductor devices shown in Figs. 3(A) to (D) and Figs. 4(A) to (C). The semiconductor devices shown in Figs. 3(A) to (D) and Figs. 4(A) to (C) provided with transistors 103 and 104 have the same functions and the same effects as the semiconductor device shown in Fig. 5(A). Fig. 7(A) shows an example of the case where transistors 103 and 104 are provided in the semiconductor device shown in Fig. 3(A). Fig. 7(B) shows an example of the case where transistors 103 and 104 are provided in the semiconductor device shown in Fig. 3(B). Fig. 7(C) shows an example of the case where transistors 103 and 104 are provided in the semiconductor device shown in Fig. 3(C). In the semiconductor device shown in Fig. 7(C), wiring 113 is omitted.

[0135]

[0136]

[0137]

[0138]

[0139] ​​​​​​​​​​​​Therefore, the number of wirings and signals can be reduced.

[0140] Fig. 8(A) shows an example of the case where transistors 103 and 1 04 are provided in the semiconductor device shown in Fig. 4(A).

[0141] Fig. 8(B) shows an example of the case where transistors 103 and 1 04 are provided in the semiconductor device shown in Fig. 4(B).

[0142] Fig. 8(C) shows an example of the case where transistors 103 and 1 04 are provided in the semiconductor device shown in Fig. 4(C).

[0143] Also, for example, in the semiconductor devices shown in Fig. 5(A), Figs. 7(A) to (C), and Figs. 8(A) to (C), it is possible to omit transistor 104. By omitting transistor 104, the number of transistors can be reduced, so that the layout area can be made smaller.

[0144] Fig. 9(A) shows an example of the case where transistor 104 is omitted in the semiconductor device shown in Fig. 5(A).

[0145] Fig. 9(B) shows an example of the case where transistor 104 is omitted in the semiconductor device shown in Fig. 7(C).

[0146] Next, an example of a circuit (also referred to as a control circuit) having a function of controlling a semiconductor device will be described.

[0147] Fig. 10 shows a circuit 130 for controlling a semiconductor device. In Fig. 10, as the semiconductor device, the semiconductor device shown in Fig. 5(A) is used. However, as the semiconductor device, Fig. 5(A For example, the semiconductor device may be the semiconductor device shown in the embodiment 1. A semiconductor device, a semiconductor device described in this embodiment, or a semiconductor device described in any other embodiment It is possible to use:

[0148] The circuit 130 has a function of applying a potential to each wiring of the semiconductor device. The function of controlling the timing of signal output and voltage supply to each wiring of a semiconductor device is Yes.

[0149] The circuit 130 includes a circuit 131, a circuit 132, a circuit 133, and a circuit 134. The circuit 131 has a function of supplying a voltage V1 to the wiring 111. The circuit 132 has a function of supplying a signal to the wiring 113. The circuit 133 has a function of supplying a signal to the wiring 114. 15. In this manner, the circuit 131, the circuit 132, and the circuit 133 has a function as a signal generating circuit or a timing generator circuit. The circuit 131 and the circuit 134 function as a voltage generating circuit or a regulator circuit. do.

[0150] The circuits 131 to 134 are, respectively, an amplifier circuit, a bipolar transistor, and a MOS transistor. resistors, capacitance elements, resistance elements, coils, DC voltage sources, AC voltage sources, DC current sources and switches The present invention can be configured with at least one of the following:

[0151] Note that a protective circuit 140 can be connected to the wiring 113 and the wiring 114. The protection circuit 140 includes a plurality of transistors 141 and a plurality of transistors 142 . The first terminal of transistor 141 is connected to wiring 115, and the second terminal of transistor 141 is connected to wiring 113 or wiring 114, and the gate of transistor 141 is connected to wiring 115. The first terminal of transistor 142 is connected to wiring 111, and the second terminal of transistor 142 is connected to wiring 113 or wiring 114, and the gate of transistor 142 is connected to wiring 113 or wiring 114. Note that one of transistor 141 and transistor 142 can be omitted.

[0152] This embodiment can be appropriately combined with other embodiments.

[0153] (Embodiment 3) In this embodiment, an example of a semiconductor device and an example of a driving method of the semiconductor device will be described In particular, an example of a NOR circuit and a NAND circuit using the semiconductor device shown in Embodiment 2 and an example of a driving method of the NOR circuit and the NAND circuit will be described.

[0154] First, a configuration for providing the semiconductor device shown in Embodiment 2 with a function as a NOR circuit will be described with reference to FIG.

[0155] In the semiconductor device shown in Embodiment 2, between wiring 115 and wiring 112, N (N is a natural number) transistors 103 (denoted as transistors 103_1 to 103_N) are connected in parallel The gates of the N transistors 103 are each connected to N wirings 114 (wirings 11 4_1 to 114_N). Then, between wiring 115 and node 11, N transistors 104 (denoted as transistors 104_1 to 104_N) are connected in parallel . The gates of the N transistors 104 are each connected to N wirings 114. For example , the first terminal of transistor 103_i (where i is any one of 1 to N) is connected to wiring 115 , the second terminal of transistor 103_i is connected to wiring 112, and the gate of transistor 103_i is connected to wiring 114_i. The first terminal of transistor 104_i (where i is any one of 1 to N) is connected to wiring 115, the second terminal of transistor 104_i is connected to node 11, and the gate of transistor 104_i is connected to wiring 114 _i. With such a configuration, the semiconductor device shown in Embodiment 2 can function as an N-input NOR circuit.

[0156] FIG. 11(A) shows an example of a NOR circuit in which the above configuration is added to the semiconductor device shown in FIG. 7(C).

[0157] FIG. 11(B) shows an example of a NOR circuit in which the above configuration is added to the semiconductor device shown in FIG. 5(A). In the NOR circuit shown in FIG. 11(B), an inverted signal of the signal input to any one of the N wirings 114 may be input to wiring 113.

[0158] Next, an example of the operation of the NOR circuit using the semiconductor device shown in Embodiment 2 will be described by taking the semiconductor device shown in FIG. 11 (A) as an example. Here, the operation in two cases will be described: when a potential V1 is applied to at least one of the N wirings 114, and when a potential V2 is applied to all of the N wirings 114.

[0159] The operation when a potential V1 is applied to at least one of the N wirings 114 will be described. Here, it is assumed that a potential V1 is applied to wiring 114_1 and a potential V2 is applied to the other wirings (wirings 114_2 to 114_N). Also, it is assumed that a potential V1 is applied to wiring 111 and a potential V2 is applied to wiring 1 15. Therefore, transistor 104_1 turns on, and transistors 104_2 to 104_N turn off, so that wiring 115 and node 11 become conductive. At this time, transistor 102 turns on, so that wiring 111 and node 1 1 become conductive. In this way, the potential of wiring 115 and the potential of wiring 111 are supplied to node 11. Thus, the potential of node 11 exceeds the potential of wiring 115 (potential V2) and is less than the potential of wiring 111 (potential V1). Here, it is assumed that the potential of node 11 is less than V2 + Vth101. Therefore, transistor 101 turns off, so that wiring 111 and wiring 112 become non-conductive. At this time, transistor 103_1 turns on, and transistors 103_2 to 103_N turn off, so that wiring 115 and wiring 112 become conductive. In this way, the potential of wiring 115 is supplied to wiring 112, and the potential of wiring 112 becomes a value equal to potential V2 (see Fig. 12(A)). The operation when potential V2 is applied to all of the N wirings 114 will be described. Also it is assumed that potential V1 is applied to wiring 111 and potential V2 is applied to wiring 115. Therefore, transistors 104_1 to 104_N turn off, so that wiring 115 and node 11 become non-conductive. At this time, transistor 102 turns on, so that wiring 111 and node 1

[0160] 1 become conductive. Then, the potential of wiring 111 is supplied to node 11, so that node 11. Since transistor 104_1~104_N are turned off, wiring 115 and node 11 are in a non-conductive state. At this time, since transistor 102 is turned on, wiring 111 and node 1 1 are in a conductive state. Then, the potential of wiring 111 is supplied to node 11, so that node 11. The potential of node 11 starts to rise. Eventually, the potential of node 11 rises to V2 + Vth101. Therefore, transistor 101 turns on, and wiring 111 and wiring 112 become conductive. At this time, transistors 103_1 to 103_N are off, and wiring 115 and wiring 112 are non-conductive. Thus, the potential of wiring 111 is supplied to wiring 112, and the potential of wiring 112 starts to rise. After that, the potential of node 11 rises to V1 - Vth102. Therefore, transistor 102 turns off, and wiring 111 and node 11 become non-conductive. Then, node 11 becomes a floating state. At this time, the potential of wiring 112 continues to rise. Therefore, the potential of node 11 rises to V1 + Vth101 + Va due to the parasitic capacitance between the gate and the second terminal of transistor 101. This is a so-called bootstrap operation. Thus, the potential of wiring 112 rises to a value equal to potential V1 (see Fig. 12(B)). It is desirable that the channel widths of the N transistors 103 are equal to each other. Due to circuit layout limitations and the like, it may be difficult to make the channel widths of the N transistors 103 equal to each other. In such a case, it is good to make at least two of the channel widths of the N transistors 103 equal to each other. By making the channel widths equal to each other, circuit design becomes easier, and malfunctions in operation can be suppressed. The same applies to transistor 104. Moreover, it is preferable that the N transistors 103 have a large driving ability in order to drive wiring 112. Therefore, at least one of the channel widths of the N transistors 103 is

[0161]

[0162] ​​​​​​​​​​​​​​​​ It is preferably larger than at least one channel width of the N transistors 104. In particular, at least one channel width of the N transistors 103 is preferably higher than 1 times and not more than 10 times that of at least one channel width of the N transistors 104. More preferably, it is not less than 1.5 times and not more than 7 times. Even more preferably, it is not less than 2 times and not more than 5 times.

[0163] In addition, when the potential V2 is applied to the N wirings 114, the potential of the node 11 preferably becomes a value such that the transistor 101 is turned off. Therefore, at least one channel width of the N transistors 104 is preferably larger than the channel width of the transistor 102. In particular, at least one channel width of the N transistors 104 is preferably higher than 1 times and not more than 10 times that of the channel width of the transistor 102. More preferably, it is not less than 2 times and not more than 5 times. Even more preferably, it is not less than 2.5 times and not more than 3.5 times.

[0164] Next, a configuration for providing the semiconductor device shown in Embodiment 2 with a function as a NAND circuit will be described.

[0165] The following shows a configuration for providing the semiconductor device shown in Embodiment 2 with a function as a NAND circuit. In the semiconductor device shown in Embodiment 2, between the wiring 115 and the wiring 112, N (N is a natural number) transistors 103 (denoted as transistors 103_1 to 103_N) are connected in series. The gates of the N transistors 103 are each connected to the N wirings 114 (wirings 114_1 to 114_N). And between the wiring 115 and the node 11 ) are connected in series. The gates of the N transistors 103 are each connected to the N wirings 114 (wirings 114_1 to 114_N). And between the wiring 115 and the node 11 To this, N transistors 104 (denoted as transistors 104_1 to 104_N) are connected in series. The gates of the N transistors 104 are each connected to N wirings 114. For example, the first terminal of transistor 103_i (where i is any one of 1 to N) is connected to the second terminal of transistor 103_i + 1, and the second terminal of transistor 103_i is connected to the first terminal of transistor 103_i - 1, and the gate of transistor 103_i is connected to wiring 114_i. The first terminal of transistor 104_i (where i is any one of 1 to N) is connected to the second terminal of transistor 104_i + 1, and the second terminal of transistor 104_i is connected to the first terminal of transistor 104_i - 1, and the gate of transistor 104_i is connected to wiring 114_i. However, the second terminal of transistor 103_1 is connected to wiring 112. The first terminal of transistor 103_N is connected to wiring 115. The second terminal of transistor 104_1 is connected to node 11 and the first terminal of transistor 104_N is connected to wiring 115. With such a configuration, the semiconductor device shown in Embodiment 2 can function as an N-input NAND circuit.

[0166]

[0167] FIG. 13(A) shows an example of a NAND circuit in which the above configuration is added to the semiconductor device shown in FIG. 7(C).

[0167]

[0168] FIG. 13(B) shows an example of a NAND circuit in which the above configuration is added to the semiconductor device shown in FIG. 5(A). Note that an inverted signal of the signal input to any one of the N wirings 114 may be input to wiring 113.

[0168] Next, an example of the operation of a NAND circuit using the semiconductor device shown in Embodiment 2 will be described with reference to FIG. 1 3(A). Here, the case where the potential V2 is applied to at least one of the N wirings 114 and the case where the potential V1 is applied to all of the N wirings 114 will be described.

[0169] The operation when the potential V2 is applied to at least one of the N wirings 114 will be described. Here, it is assumed that the potential V1 is applied to the wiring 114_1 and the potential V2 is applied to the other wirings (wirings 114_2 to 114_N). Also, it is assumed that the potential V1 is applied to the wiring 111 and the potential V2 is applied to the wiring 1 115. Therefore, the transistor 104_1 is turned on, and the transistors 104_2 to 104_N are turned off, so that the wiring 115 and the node 11 are in a non-conductive state. At this time, since the transistor 102 is turned on, the wiring 111 and the node 11 are in a conductive state. Then, the potential of the wiring 111 is supplied to the node 11, so that the potential of the node 11 starts to rise. Eventually, the potential of the node 11 rises to V2 + Vth101 up to. Therefore, since the transistor 101 is turned on, the wiring 111 and the wiring 11 2 are in a conductive state. At this time, the transistor 103_1 is turned on, and the transistors 103_2 to 103_N are turned off, so that the wiring 115 and the wiring 112 are in a non-conductive state become. Thus, the potential of the wiring 111 is supplied to the wiring 112, so the potential of the wiring 112 starts to rise. After that, the potential of the node 11 rises to V1 - Vth102. At this time, since the transistor 102 is turned off, the wiring 111 and the node 11 are in a non-conductive state become. Then, the node 11 becomes a floating state. At this time, the potential of the wiring 112 rises, Therefore, the potential of the node 11 is connected to the gate of the transistor 101 and the second terminal Due to the parasitic capacitance between the This is a trapping action. Thus, the potential of the wiring 112 rises to a value equal to the potential V1. (See Figure 14(A)).

[0170] The operation will be described when the potential V1 is applied to all of the N wirings 114. It is assumed that a potential V1 is applied to the wiring 111 and a potential V2 is applied to the wiring 115. Since the transistors 104_1 to 104_N are turned on, the wiring 115 and the node 11 are electrically connected. At this time, the transistor 102 is turned on, so that the wiring 111 and the node 11 Thus, the node 11 is connected to the potential of the wiring 115 and the potential of the wiring 111. Therefore, the potential of the node 11 exceeds the potential of the wiring 115 (potential V2), The potential of the wiring 111 is lower than the potential V1. Here, the potential of the node 11 is V2+Vt Therefore, the transistor 102 is turned off, and the wiring 111 and the wiring The line 112 is not electrically connected. At this time, the transistors 103_1 to 103_N are turned on. Therefore, the wiring 115 and the wiring 112 are electrically connected to each other. Since the potential of the wiring 112 is supplied to the wiring 112, the potential of the wiring 112 becomes equal to the potential V2 (see FIG. 14(B)).

[0171] It is preferable that the channel widths of the N transistors 103 are equal to each other. Due to limitations in placement, it is difficult to make the channel widths of the N transistors 103 equal to each other. In a difficult case, the channel widths of at least two of the N transistors 103 are set equal to each other. This is preferable. By making the channel widths equal to each other, circuit design becomes easier, and malfunctions in operation can be suppressed. The same applies to the transistor 104.

[0172] In addition, in order to shorten the fall time of the potential of the wiring 112, it is preferable that the channel widths of the N transistors 103 are larger. However, if the channel width is too large, the layout area will become large. Therefore, at least one of the channel widths of the N transistors 103 should be equal to or less than N times the channel width of the transistor 101. It is preferably. More preferably, it is 1 / 3 times or more and 3 times or less. Even more preferably, it is 1 / 2 times or more and 2 times or less.

[0173] In addition, when the potential V1 is applied to all of the N wirings 114, in order to make the potential of the node 11 less than V2 + Vth101, it is preferable that the channel widths of the N transistors 104 are larger. However, if the channel width is too large, the layout area will become large. Therefore, at least one of the channel widths of the N transistors 104 should be equal to or less than N times the channel width of the transistor 102. It is preferably. More preferably, it is 1 / 3 times or more and 3 times or less. Even more preferably, it is 1 / 2 times or more and 2 times or less.

[0174] As described above, using the semiconductor device shown in the second embodiment, the NOR circuit or NAND circuit of this embodiment can be configured. Therefore, the NOR circuit and NAND circuit of this embodiment can obtain the same effects as the semiconductor devices shown in the first and second embodiments.

[0175] ​​​This embodiment can be appropriately combined with other embodiments.

[0176] (Embodiment 4) In this embodiment, an example of a semiconductor device and an example of a driving method for the semiconductor device will be described. In particular, an example of a decoder circuit using the semiconductor device shown in Embodiment 3 and an example of a driving method for the decoder circuit will be described.

[0177] First, an example of the configuration of the semiconductor device according to this embodiment will be described.

[0178] FIG. 16 shows an example of the decoder circuit according to this embodiment. The decoder circuit shown in FIG. 16 includes m ( m is a natural number) NOR circuits 201 (denoted as NOR circuits 201_1 to 201_m). It has.

[0179] Note that as the m NOR circuits 201, the NOR circuits shown in Embodiment 3 may be used respectively. It is good.

[0180] To each of the m NOR circuits 201, a control signal of N (N is a natural number, 2 N > m) bits is input. The N-bit control signal is selected from the control signals D1 to DN and the control signals Db1 to DbN. The control signals Db1 to DbN are inverted signals of the control signals D1 to DN. And different control signals are input to the m NOR circuits 201. For example, to the NOR circuit 201_1, the control signals D1 to DN are input. To the NOR circuit 201_2, the control signal Db1 and the control signals D2 to DN are input. To the NOR circuit 201_3, the control signal D 1, the control signal Db2, and the control signals D3 to DN are input. In this way, by making the control signals input to the m NOR circuits 201 different from each other, the m NOR circuits 20 1, the control signal Db2, and the control signals D3 to DN are input. In this way, by making the control signals input to the m NOR circuits 201 different from each other, the m NOR circuits 20 circuits 201, by making the control signals input to the m NOR circuits different from each other, the m NOR circuits 20 Only the signal output from any one of 1 can have a value different from the signal output from the other NOR circuits 201. Specifically, the signal output from any one of the m NOR circuits 201 can be set to the H level, and the signals output from the other NOR circuits 201 can be set to the L level. Then, by changing the values of the control signals D1 to DN and the control signals Db1 to Db N at every predetermined time (for example, one gate selection period), the NOR circuits 20 1_1 to 201_m can output signals at the H level in sequence. Or, signals at the H level can be output from the m NOR circuits 201 in any order.

[0181] Note that the control signals D1 to DN are input to the decoder circuit via N wirings 212 (denoted as wirings 212_1 to 212_N). The control signals Db1 to DbN are input to the decoder circuit via N wirings 213 (denoted as the wirings 213_1 to 213_N). The output signals of the m NOR circuits 201 are each output to m wirings 211 (wirings 211_1 to 211_m).

[0182] Note that the control signals Db1 to DbN can be generated by inverting the control signals D1 to DN using an inverter circuit or the like. As the inverter circuit for generating the control signals Db1 to DbN, it is possible to use the semiconductor device shown in Embodiment 1.

[0183] Note that the decoder circuit can be configured not only with NOR circuits but also with NAND circuits. As the NAND circuit, it is advisable to use the NAND circuit shown in Embodiment 3. Fig. 1 ​​​​​​​​​7 shows a circuit diagram when a decoder circuit is configured by a NAND circuit. The decoder circuit shown in FIG. 17 uses m NAND circuits 202 (denoted as NAND circuits 202_1 to 202_m) instead of the m NOR circuits 201 used in the decoder circuit shown in FIG. 16, which is different in this point.

[0184] In the decoder circuit shown in FIG. 17, a signal output from any one of the m NAND circuits 202 becomes an L level, and signals output from the other NAND circuits 202 become an H level. Therefore, it is possible to provide m inverter circuits 203 (denoted as inverter circuits 203 _1 to 203_m) as necessary. The output signals of the m NAND circuits 202 are output to m wirings 211 via the m inverter circuits 203.

[0185] As described above, the decoder circuit of this embodiment can be configured using the NOR circuit or NAND circuit shown in Embodiment 3. Therefore, the decoder circuit of this embodiment can obtain the same effects as the semiconductor devices shown in Embodiments 1 and 2.

[0186] This embodiment can be appropriately combined with other embodiments.

[0187] (Embodiment 5) In this embodiment, an example of the configuration of a semiconductor device and an example of the manufacturing process of the semiconductor device will be described. In particular, an example of a thin film transistor in which a channel formation region is formed of an oxide semiconductor and an example of the manufacturing process of the thin film transistor will be described.

[0188] <Configuration Example of Transistor> FIG. 15(D) shows a transistor 450 (for example, a thin film transistor), which is an example of the configuration of a semiconductor device. It is a cross-sectional view showing a transistor. The transistor 450 shown in Fig. 15(D) is an inverted staggered thin film transistor. Fig. 15(D) shows a thin film transistor with a single gate structure, but if necessary, it can be a multi-gate structure thin film transistor having a plurality of channel formation regions. The thin film transistor will be described as an n-type transistor, but it may also be a p-type transistor.

[0189] The transistor 450 includes a gate electrode layer 411 provided on a substrate 400, a gate insulating layer 402 covering the gate electrode layer 411, an oxide semiconductor layer 406a provided on the gate electrode layer 411, and a source electrode layer and drain electrode layers 408a and 408b that are electrically connected to the oxide semiconductor layer 406a. Also, an insulating layer 412 and an insulating layer 418 are provided on the transistor 450. Note that the insulating layer 412 and the insulating layer 418 are not essential components and can be omitted as appropriate.

[0190] For the oxide semiconductor layer 406a, an In-Sn-Ga-Zn-O system which is a quaternary metal oxide, or an In-Ga-Zn-O system which is a ternary metal oxide, an In-Sn-Zn-O system, an In-Al-Zn-O system, a Sn-Ga-Zn-O system, an Al-Ga-Zn-O system, a Sn-Al-Zn-O system, or an In-Zn-O system, a Sn-Zn-O system, an Al-Zn-O system, a Zn-Mg-O system, a Sn-Mg-O system, an In-Mg-O system, an In-O system, a Sn-O system, a Zn-O system, etc. are used. Among them, an In-Ga-Zn-O based oxide semiconductor material has a sufficiently high resistance when there is no electric field and

[0191] is highly ​​It is possible to make the leakage current sufficiently small, and since the field-effect mobility is also high, it is suitable as a semiconductor material for use in semiconductor devices.

[0192] As a representative example of an In-Ga-Zn-O-based oxide semiconductor material, there is one represented by InGaO3(ZnO) m (m > 0 and m is not a natural number). Also, replacing Ga with M, there is an oxide semiconductor material represented as InMO3(ZnO) (m > 0 and m is not a natural number). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), aluminum (Al), iron ( m Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied . Note that the above composition is derived from the crystal structure and is merely an example . Also, the oxide semiconductor material denoted as In-Ga-Zn-O in this specification is InGaO3(ZnO) (m > 0 and m is not a natural number), and the fact that m is not a natural number can be confirmed using ICP-MS analysis or RBS analysis. . It should be noted that the above composition is derived from the crystal structure and is merely an example . Also, the oxide semiconductor material denoted as In-Ga-Zn-O in this specification is InGaO3(ZnO) (m > 0 and m is not a natural number), and the fact that m is not a natural number can be confirmed using ICP-MS analysis or RBS analysis. m (m > 0 and m is not a natural number), and the fact that m is not a natural number can be confirmed using ICP-MS analysis or RBS analysis.

[0193] The hydrogen concentration of the oxide semiconductor layer is preferably 5×10 19 (atoms / cm 3 ) or less.

[0194] <Method for manufacturing a transistor> Next, the method for manufacturing the above-described thin-film transistor will be described with reference to FIGS. 15(A) to 15(D).

[0195] First, a gate electrode layer 411 is formed on a substrate 400, and then a gate electrode layer 411 is formed on the substrate 400. The gate insulating layer 402 is formed as shown in FIG. 406 is formed (see FIG. 15(A)).

[0196] For example, a glass substrate can be used as the substrate 400. The glass substrate is made of a non-alkali material. The non-alkali glass substrate is preferably an aluminosilicate glass substrate. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass The substrate 400 may be a ceramic substrate, a quartz substrate, a safa substrate, or the like, in addition to a glass substrate. The surface of an insulating substrate made of an insulator such as an insulating substrate, or a semiconductor substrate made of a semiconductor material such as silicon The surface of a conductive substrate made of a conductor such as metal or stainless steel is covered with an insulating material. Also, materials having flexibility such as plastic can be used. Although the heat resistance of synthetic resin boards generally tends to be low, Any material can be used as the substrate 400 as long as it can withstand the processing temperatures.

[0197] The gate electrode layer 411 is formed by forming a conductive layer on the substrate 400 and selectively etching the conductive layer. The gate electrode layer 411 can be formed by a method such as a sputtering method. PVD (Physical Vapor Deposition) method and Plasma C Using CVD methods such as VD (Chemical Vapor Deposition) The gate electrode layer 411 can be formed of aluminum, chromium, copper, or tin. Metallic materials selected from tantalum, titanium, molybdenum, and tungsten, or materials containing the above elements, It can be formed using an alloy material or the like as a component. A material containing any one or more of manganese, magnesium, zirconium, and beryllium may be used. Also, a material in which one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are contained in aluminum may be used. Also, the gate electrode layer 411 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3—ZnO), or a material in which silicon or silicon oxide is contained in these metal oxide materials can be used. The gate electrode layer 411 may have a single-layer structure or a laminated structure of two or more layers. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. The gate insulating layer 402 can be formed using a CVD method, a sputtering method, or the like. Also, it is preferable that the gate insulating layer 402 be formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

[0198] The gate electrode layer 411 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3—ZnO), or a material in which silicon or silicon oxide is contained in these metal oxide materials can be used. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3—ZnO), or a material in which silicon or silicon oxide is contained in these metal oxide materials can be used. The gate electrode layer 411 may have a single-layer structure or a laminated structure of two or more layers. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. The gate electrode layer 411 may have a single-layer structure or a laminated structure of two or more layers. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. The gate electrode layer 411 may have a single-layer structure or a laminated structure of two or more layers. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used.

[0199] The gate electrode layer 411 may have a single-layer structure or a laminated structure of two or more layers. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. In addition, in this embodiment, since heat treatment is performed at a relatively high temperature after the formation of the gate electrode layer 411, it is desirable that the gate electrode layer 411 be formed using a material having heat resistance sufficient to withstand this heat treatment. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used. Examples of materials having heat resistance include titanium, tantalum, tungsten, molybdenum, etc. Also, polysilicon with enhanced conductivity by adding impurity elements can also be used.

[0200] The gate insulating layer 402 can be formed using a CVD method, a sputtering method, or the like. The gate insulating layer 402 can be formed using a CVD method, a sputtering method, or the like. Also, it is preferable that the gate insulating layer 402 be formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Yes. The gate insulating layer 402 may have a single-layer structure or a laminated structure of two or more layers. The film thickness of the gate insulating layer can be, for example, 10 nm or more and 500 nm or less.

[0201] Also, as the gate insulating layer 402, hafnium silicate (HfSiO x ), hafnium silicate (HfSi with nitrogen added x O y N z ), hafnium aluminate (HfAl with nitrogen added x O y N z ), high-k materials such as hafnium oxide and yttrium oxide can be used to reduce gate leakage. Furthermore, a layer using a high-k material and one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed into a laminated structure.

[0202] Note that the gate insulating layer 402 is preferably formed so as to contain as few impurities such as hydrogen and water as possible. If hydrogen or water is contained in the gate insulating layer 402, hydrogen may penetrate into the oxide semiconductor layer 406a, or oxygen in the oxide semiconductor layer 406a may be extracted by hydrogen, which may deteriorate the characteristics of the transistor.

[0203] For example, when forming the gate insulating layer 402 using a sputtering method or the like, it is desirable to form it in a state where the residual moisture in the processing chamber has been removed. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. A turbo pump can be combined with You may also use the one with an old trap added. The process of evacuating using a cryopump or the like Since the chamber has sufficiently removed hydrogen, water, etc., the impurities contained in the gate insulating layer 402 can be reduced in concentration.

[0204] In addition, the high-density plasma CVD method using microwaves (for example, a frequency of 2.45 GHz) is suitable in that it can form a high-quality gate insulating layer 402 that is dense and has a high breakdown voltage. Also when the oxide semiconductor layer 406a and the high-quality gate insulating layer 402 are in close contact, the interface level can be reduced and the interface characteristics can be made good. In particular, 1×10 11 / cm 3 or higher plasma density can be achieved. It is preferable to use a high-density plasma device. In this way while improving the interface characteristics with the gate insulating layer 402 and removing impurities in the oxide semiconductor, particularly water elements and water, etc., it is possible to obtain a stable transistor in which the threshold voltage (Vth) does not fluctuate even for a gate bias - thermal stress test (BT test: for example, 8 6 5°C, 2×10 V / cm, 12 hours, etc.).

[0205] Also, when forming the gate electrode layer 411, it is desirable to use a high-purity gas in which impurities such as hydrogen and water are reduced to a concentration of several ppm and a concentration of several ppb.

[0206] Note that the oxide semiconductor layer (highly purified oxide semiconductor layer) that is i - type or substantially i - type in a later process is extremely sensitive to interface levels and interface charges, so the interface with the gate insulating layer is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor layer High quality is required. Therefore, high-density plasma CVD using microwaves (2.45 GHz) D is preferable because it can form a high-quality insulating film that is dense and has high breakdown voltage. By closely contacting the highly purified oxide semiconductor with the high-quality gate insulating layer, the interface states can be reduced and the interface characteristics can be made good. Of course, the film quality as the gate insulating layer is good, and it is important to reduce the interface state density with the oxide semiconductor layer and form a good interface.

[0207] The oxide semiconductor layer 406 can be formed by sputtering in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. The formation atmosphere of the oxide semiconductor layer 406 is, for example, a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to about several ppm by concentration (preferably about several ppb by concentration).

[0208] Before forming the oxide semiconductor layer 406 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove powdery substances (also called particles and dust) adhering to the surface of the gate insulating layer 402. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0209] The oxide semiconductor layer 406 is a quaternary metal oxide such as In-Sn-Ga-Zn-O, or a ternary Oxide semiconductors such as In-Ga-Zn-O, In-Sn-Zn-O, In-Al- Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O systems, and binary metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O , Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O , Zn-O, etc. can be used for formation.

[0210] Among them, the In-Ga-Zn-O oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the offset current. Also, since the field-effect mobility is high, it is suitable as a semiconductor material for semiconductor devices.

[0211] In this embodiment, an amorphous oxide semiconductor layer 406 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target.

[0212] As the target for forming the In-Ga-Zn-O-based oxide semiconductor layer 406 by sputtering, a target represented by a composition ratio of In:Ga:Zn = 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less ) may be used. For example, a target having a composition ratio of In:Ga:Zn = 1:1: 1 [atomic ratio] (x = 1, y = 1), (that is, In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio]) may be used. Also, a target having a composition ratio of In:Ga:Zn = 1:1:0.5 [atomic ratio] as an oxide semiconductor target , or a target having a composition ratio of In:Ga:Zn = 1:1:2 [atomic ratio], In:Ga ​:A target having a composition ratio of Zn=1:0:1 [atomic ratio] (x = 0, y = 1) is used It is also possible. Further, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used to form a film and include SiOx (X>0) in the oxide semiconductor layer 406

[0213] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 95% or more more preferably 99.9% or more. By using an oxide semiconductor target with a high relative density it is possible to form an oxide semiconductor layer 406 with a dense structure

[0214] When forming the oxide semiconductor layer 406, for example, the substrate is held in a processing chamber maintained in a reduced pressure state and the substrate temperature is heated to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced and the oxide semiconductor layer 406 is formed using the above target. By forming the oxide semiconductor layer 406 while heating the substrate the impurities contained in the oxide semiconductor layer 406 can be reduced Also, the damage due to sputtering is reduced. To remove the residual moisture in the processing chamber, it is preferable to use the above-described adsorption type vacuum pump. For example the processing chamber evacuated using a cryopump has had hydrogen, water, etc. removed, so the concentration of impurities contained in the oxide semiconductor layer 406 can be reduced

[0215] As the formation conditions of the oxide semiconductor layer 406, for example, the distance between the substrate and the target is 1 70 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon In addition, a pulsed direct current (DC) power supply is used. This reduces dust (powder or flake-like material formed during film formation) and improves film thickness distribution. The thickness of the oxide semiconductor layer 406 is preferably greater than or equal to 2 nm and less than or equal to 200 nm. However, depending on the oxide semiconductor material and the application, the thickness is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material and application, so the thickness should be selected according to the material and application. That's good.

[0216] Next, the oxide semiconductor layer 406 is selectively etched to form an island-shaped oxide semiconductor layer 406a After that, a conductive film is formed so as to cover the gate insulating layer 402 and the oxide semiconductor layer 406a. The conductive layer is then etched to form the source and drain electrode layers 408. a, 408b are formed (see FIG. 15(B)).

[0217] The oxide semiconductor layer may be etched by dry etching or wet etching. The oxide semiconductor layer is etched into a desired shape. In order to achieve this, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The incubation time, temperature, etc. should be set appropriately.

[0218] As dry etching, parallel plate type RIE (Reactive Ion Etch) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode It is necessary to set appropriately (such as temperature, etc.).

[0219] Etching gases that can be used for dry etching include, for example, gases containing chlorine ( chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoro methane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), gases added with noble gases such as helium (He) or argon (Ar), etc. can also be used.

[0220] Etching solutions that can be used for wet etching include a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5 :2:2), etc. Also, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Inc.) can be used.

[0221] Next, it is preferable to perform a first heat treatment on the oxide semiconductor layer 406a. By performing the first heat treatment, excess water (including hydroxyl groups) and water elements in the oxide semiconductor layer 406a can be removed. The temperature of the first heat treatment is, for example, 400 °C or higher and 750 °C or lower, or 400 °C or higher and less than the distortion point of the substrate. The first heat treatment is, for example, performed by introducing the substrate 400 into an electric furnace using a resistance heating element, etc., at 450 °C for 1 hour in a nitrogen atmosphere. During this period, it is preferable to prevent the oxide semiconductor layer 406a from coming into contact with the atmosphere and prevent the mixing of water and hydrogen.

[0222] The heat treatment apparatus is not limited to an electric furnace, and may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, a lamp heating type RTA ( LRTA; Lamp Rapid Thermal Anneal) apparatus, a gas heating type RTA (GRTA; Gas Rapid Thermal An neal) apparatus using heated gas, or an RTA apparatus equipped with both lamp heating type and gas heating type can be used. When using a gas heating type apparatus, as the gas, an inert gas such as argon or nitrogen that does not react with the object to be treated by heat treatment is used. neal) apparatus, or an RTA apparatus equipped with both lamp heating type and gas heating type can be used. When using a gas heating type apparatus, as the gas, an inert gas such as argon or nitrogen that does not react with the object to be treated by heat treatment is used. neal) apparatus, or an RTA apparatus equipped with both lamp heating type and gas heating type can be used. When using a gas heating type apparatus, as the gas, an inert gas such as argon or nitrogen that does not react with the object to be treated by heat treatment is used. For example, as a first heat treatment, the substrate is put into an inert gas atmosphere heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the substrate is taken out from the inert gas atmosphere for GRTA treatment. For example, as a first heat treatment, the substrate is put into an inert gas atmosphere heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the substrate is taken out from the inert gas atmosphere for GRTA treatment. GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate.

[0223] For example, when using a glass substrate, shrinkage of the substrate becomes a problem at a temperature exceeding the heat-resistant temperature (strain point), but this is not a problem in the case of short-time heat treatment. During the treatment, GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate. GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate. GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate. GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate. GRTA treatment may be performed. Using GRTA treatment enables high-temperature heat treatment in a short time. Also, since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate. the inert gas may be switched to a gas containing oxygen. This is because by performing the first heat treatment in an atmosphere containing oxygen, defects caused by oxygen deficiency can be reduced. the inert gas may be switched to a gas containing oxygen. This is because by performing the first heat treatment in an atmosphere containing oxygen, defects caused by oxygen deficiency can be reduced.

[0224] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) without containing water, hydrogen, etc. is preferably applied. That is, for nitrogen introduced into the heat treatment apparatus and noble gases such as helium, neon, and argon, the purity is set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, in ultra-dry air with H 2O of 20 ppm or less, and more preferably in ultra-dry air with H2O of 1 ppm or less, the first heat treatment may be performed. By such a first heat treatment, water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 406 can be removed.

[0225] By performing the first heat treatment as described above, the hydrogen contained in the oxide semiconductor layer 406 can be reduced, preferably, the hydrogen contained in the oxide semiconductor layer 406 can be removed, and the oxide semiconductor layer can be highly purified so as to contain as few impurities as possible other than the main components.

[0226] Note that the first heat treatment performed on the oxide semiconductor layer can also be performed on the oxide semiconductor layer 406 before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating device, and then etching using a mask or the like is performed.

[0227] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer can be performed at any step after the formation of the oxide semiconductor layer, after laminating the source electrode layer and the drain electrode layer on the oxide semiconductor layer, and after forming the protective insulating film on the source electrode layer and the drain electrode layer.

[0228] The source electrode layer and the drain electrode layers 408a and 408b are formed by forming a conductive layer so as to cover the oxide semiconductor layer 406a, and then selectively etching the conductive layer. The conductive layer is a sp It can be formed using a patterning method or a vacuum evaporation method. As the material of the conductive layer, a metal material selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy material containing the above-described elements as components, or an alloy material combining the above-described elements can be mentioned. Further, a material selected from any one or more of manganese, magnesium, zirconium, beryllium, and yttrium may be used. Also, a material containing one or more elements selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

[0229] Also, the source electrode layer and the drain electrode layers 408a and 408b may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, and a three-layer structure in which an aluminum film is laminated on a titanium film and then a titanium film is laminated on the aluminum film can be mentioned.

[0230] When performing heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer 406a on the conductive layer, it is preferable to use a conductive layer having heat resistance sufficient to withstand this heat treatment.

[0231] At the time of etching the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 406a is not removed.

[0232] In this embodiment, a titanium film is used as the conductive layer, an In-Ga-Zn-O-based oxide is used for the oxide semiconductor layer 406a, and aqueous ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant.

[0233] In addition, when etching the conductive layer, only a part of the oxide semiconductor layer 406a may be etched , resulting in an oxide semiconductor layer 406a having groove portions (recessed portions). Also, in this step , the mask used may be formed by an inkjet method. Forming the mask by the inkjet method does not use a photomask, so the manufacturing cost can be reduced.

[0234] Also, in order to reduce the number of photomasks and the number of steps used in the photolithography process, a resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has multiple intensities, may be used for the etching process. The resist mask formed using the multi-tone mask has a shape with multiple film thicknesses, and the shape can be further deformed by performing ashing. Therefore, it can be used in a plurality of etching processes for processing into different patterns . Thus, a resist mask corresponding to at least two or more different patterns can be formed using a single multi-tone mask. Therefore, the number of exposure masks can be reduced , and the corresponding photolithography process can also be reduced, enabling simplification of the process. . Therefore, a resist mask corresponding to at least two or more different patterns can be formed using a single multi-tone mask. Thus, the number of exposure masks can be reduced , and the corresponding photolithography process can also be reduced, making it possible to simplify the process.

[0235] Next, plasma treatment is performed using a gas such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar). By this plasma treatment, adsorbed water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0236] Next, an insulating layer 412 is formed so as to cover the oxide semiconductor layer 406a and the source electrode layer and drain electrode layers 408a, 408 b (see FIG. 15(C)).

[0237] The insulating layer 412 can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the insulating layer 412, such as sputtering or CVD. If hydrogen is contained in the insulating layer 412, it will penetrate into the oxide semiconductor layer 406a, causing the back channel of the oxide semiconductor layer 406a to have a lower resistance (become N-type) and form a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 412 becomes a film that contains as little hydrogen as possible. The insulating layer 412 is preferably formed to contain silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. In particular, a silicon oxide film formed by using the sputtering method is preferred. Note that the insulating layer 412 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 412 is not particularly limited, but for example, it can be 10 nm or more and 500

[0238] nm or less, preferably 50 nm or more and 200 nm or less. Next, it is preferable to perform the second heat treatment on the oxide semiconductor layer 406a in an inert gas atmosphere or an oxygen atmosphere. By performing the second heat treatment, oxygen is supplied to the oxygen deficiency of the oxide semiconductor layer 406a to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close as possible to the i-type. Also, by performing the second heat treatment, the variation in the electrical characteristics of the transistor can be reduced. The temperature of the second heat treatment is 200

[0239] °C or more and 450 °C or less, desirably 250 °C or more and 350 °C or less. The second heat treatment can be, for example, a heat treatment at 250 °C for 1 hour in a nitrogen atmosphere.

[0240] ​​​​​​​​ Through the above steps, the transistor 450 can be formed.

[0241] An insulating layer 418 may be further formed on the insulating layer 412. The insulating layer 418 does not contain impurities such as moisture, hydrogen ions, and OH - and blocks the intrusion of these from the outside. It is preferable to use an inorganic insulating material, for example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. In this embodiment, for example, an RF sputtering method is used to form the silicon nitride film. The RF sputtering method is preferable as a film formation method for the insulating layer 418 because of its good mass productivity (see Fig. 15(D)).

[0242] Note that depending on the conditions of the first heat treatment and the second heat treatment, or the material of the oxide semiconductor layer 406a, a part of the oxide semiconductor layer 406a may crystallize, and microcrystals or polycrystals may be formed in the oxide semiconductor layer 406a. In this way, by making the oxide semiconductor layer 406a have a structure with a non-single crystal region, a transistor with higher field-effect mobility and on-current can be obtained. Also, when the oxide semiconductor layer 406a has an amorphous structure, variations in characteristics between a plurality of elements can be reduced.

[0243] By performing the first heat treatment as described above, the hydrogen contained in the oxide semiconductor layer 406 can be reduced, preferably, the hydrogen contained in the oxide semiconductor layer 406 can be removed, and the oxide semiconductor layer 40 6 can be highly purified so as to contain as few impurities other than the main components as possible. As a result, defect levels formed by excess hydrogen atoms can be reduced. The hydrogen concentration of the oxide semiconductor layer 406 at this time is 5×1019 (atoms / cm 3 ) is preferable. Also, the carrier density of the oxide semiconductor layer 406 is 1 × 10 14 cm -3 or less, preferably 1 × 10 12 cm -3 or less, more preferably 1.45 × 10 10 cm -3 or less is preferable. That is, the carrier density of the oxide semiconductor layer 406 is as close to zero as possible. Also, the band gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more.

[0244] When such a highly purified oxide semiconductor layer 406 is used in the channel formation region, the off-current of the transistor can be reduced. The off-current flows due to the generation-recombination of holes and electrons by direct recombination or indirect recombination. However, since the oxide semiconductor layer has a wide band gap and requires a large amount of thermal energy for the excitation of electrons, direct recombination and indirect recombination are less likely to occur. In the off state, since the minority carriers, holes, are substantially zero, direct recombination and indirect recombination are less likely to occur, and the off-current can be reduced as much as possible. Therefore, an excellent transistor with reduced off-current and improved on-current and field-effect mobility is obtained. As described above, the highly purified oxide semiconductor layer functions as a path, and carriers are

[0245] supplied by the source and drain electrodes. By appropriately selecting the electron affinity χ and Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work function of the source and drain electrodes, the carrier density of the oxide semiconductor layer can be reduced while ​​Moreover, carriers can be injected from the source electrode and the drain electrode, and n-type transistors and p-type transistors can be appropriately fabricated.

[0246] In addition, the intrinsic carrier density of the highly purified oxide semiconductor is extremely low compared with that of silicon. The intrinsic carrier densities of silicon and the oxide semiconductor can be obtained from approximate formulas of the Fermi-Dirac distribution and the Boltzmann distribution. The intrinsic carrier density n of silicon is 1.45×10 i 10 cm -3 , and the intrinsic carrier density n of the oxide semiconductor (here, an In-Ga-Zn-O layer) is 1.2×10 i -7 cm -3 . The former has an intrinsic carrier density 10 17 times larger than the latter. That is, it can be seen that the intrinsic carrier density of the oxide semiconductor is extremely low compared with that of silicon.

[0247] In this embodiment, the case of fabricating a thin-film transistor with a bottom gate structure has been described, but one aspect of the present invention is not limited thereto, and a thin-film transistor with a top gate structure can also be fabricated.

[0248] 〈Electrical mechanism of a transistor using an oxide semiconductor〉 Next, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 23 to 26. In the following description, an ideal situation is assumed for ease of understanding, and not all of them reflect the actual situation. It should be noted that the following description is only a speculation.

[0249] ​​​​​​​​​FIG. 23 is a cross-sectional view of an inverted staggered transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI) on a gate electrode layer (GE), and a source electrode layer (S) and a drain electrode layer (D) are provided thereon.

[0250] FIGS. 24(A) and 24(B) show energy band diagrams (schematic diagrams) in the A-A' cross section of FIG. 23. FIG. 24(A) shows the case where the potential difference between the source and the drain is zero (equipotential, V = D 0 V), and FIG. 24(B) shows the case where the potential of the drain is higher than that of the source (V > 0). D

[0251] FIGS. 25(A) and 25(B) show energy band diagrams (schematic diagrams) in the B-B' cross section of FIG. 23. FIG. 25(A) shows the state where a positive potential (+V ) is applied to the gate (GE1), indicating the on state in which carriers (electrons) flow between the source and the drain. FIG. 25(B) shows the state where a negative potential (-V G ) is applied to the gate (GE1), indicating the off state (the state where minority carriers do not flow). G

[0252] FIG. 26 shows the relationship between the vacuum level, the work function of the metal (φM), and the electron affinity of the oxide semiconductor (χ).

[0253] Since the electrons in the metal are degenerate, the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E ) is located at the center of the band gap. f The intrinsic Fermi level (E i) is located away from and near the conduction band. Note that in the oxide semiconductor it is known that hydrogen is a donor and one of the factors for n-type doping. Also, oxygen deficiency is known to be one of the factors for n-type doping.

[0254] On the other hand, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor for n-type doping, from the oxide semiconductor, purifies it to be as free as possible from elements (impurity elements) other than the main components of the oxide semiconductor, and removes oxygen deficiency to make it intrinsic (i-type), or bring it close to being intrinsic. That is, instead of adding impurity elements to make it i-type, by removing impurities such as hydrogen and water and oxygen deficiency as much as possible, it is characterized by being a highly purified i-type (intrinsic semiconductor) or approaching it. As a result, the Fermi level (E ) can be made comparable to the intrinsic Fermi level (E ). When the bandgap (E f ) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is i said to be 4.3 eV. The work

[0255] function of titanium (Ti) constituting the source electrode and the drain electrode is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor g ) interface, a Schottky-type barrier is not formed for electrons. That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 24(A) is shown. In Fig. 24(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain, the electrons

[0256] That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when the two come into contact, an energy band diagram (schematic diagram) as shown in Fig. 24(A) is shown.

[0257] In Fig. 24(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain, the electrons Electrons are injected into the oxide semiconductor over the barrier (h) and flow toward the drain. The barrier (h) height changes depending on the gate voltage and the drain voltage. When a positive drain voltage is applied, it becomes lower than the height of the barrier in Fig. 24(A) without voltage application, that is, half of the band gap (E ). g )

[0258] At this time, as shown in Fig. 25(A), electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest energy-stable part of the oxide semiconductor).

[0259] Also, as shown in Fig. 25(B), when a negative potential (reverse bias) is applied to the gate electrode (GE1), since the number of minority carriers, holes, is substantially zero, the current becomes a value extremely close to zero.

[0260] For example, even for an element with a channel width W of 1×10 4 μm and a channel length of 3 μm , an off-current of 10 -13 A or less and a subthreshold swing value (S value) of 0.1 V / dec. (gate insulating layer film thickness 100 nm) can be obtained at room temperature.

[0261] In this way, by highly purifying the oxide semiconductor so as to contain as few impurities as possible other than the main components, the operation of the thin-film transistor can be made good. For example, the off-current at room temperature can be reduced from 1×10 A (10 zA (zeptoampere)) to about 1×10 A (100 zA). -20 -19

[0262] The above-described oxide semiconductor suppresses fluctuations in electrical characteristics. Therefore, hydrogen, moisture, which are factors causing fluctuations​​​​​​ Intentionally exclude impurities such as hydroxyl groups or hydrides (also referred to as hydrogen compounds), and oxygen, which is the main component material constituting the oxide semiconductor and will be reduced simultaneously by the impurity removal process, to obtain an oxide semiconductor that is highly purified and electrically type-I (intrinsic). By supplying .

[0263] Thus, the less hydrogen in the oxide semiconductor, the better. The hydrogen concentration in the oxide semiconductor should be 5×10 19 (atoms / cm 3 ) or less, and the hydrogen in the oxide semiconductor should be removed as much as possible to be close to zero. The hydrogen concentration of the oxide semiconductor can be measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy ). )

[0264] In addition, the number of carriers in the highly purified oxide semiconductor is extremely small (close to zero), and the carrier density is less than 1×10 cm 12 -3 , preferably less than 1.45×10 10 cm -3 . That is, the carrier density of the oxide semiconductor layer is made as close to zero as possible. Since the number of carriers in the oxide semiconductor layer is extremely small, in a thin-film transistor, the off-current can be reduced . The smaller the off-current, the better. For a thin-film transistor, the current value per 1 μm of the channel width (w) is 100 aA (i.e., 100 aA / μm) or less, preferably 1 0 aA (i.e., 10 aA / μm) or less, and more preferably 1 aA (i.e., 1 aA / μ m) or less. Furthermore, since there is no pn junction and no hot carrier degradation, these do not affect the electrical characteristics of the thin-film transistor . 0 aA (i.e., 10 aA / μm) or less, and more preferably 1 aA (i.e., 1 aA / μ m) or less. Furthermore, since there is no pn junction and no hot carrier degradation, these do not affect the electrical characteristics of the thin-film transistor . ​

[0265] Thus, by thoroughly removing hydrogen contained in the oxide semiconductor layer, a highly purified oxide semiconductor layer is obtained. A thin film transistor using the oxide semiconductor layer for the channel formation region of the thin film transistor can make the off-current extremely small. That is, in the non-conductive state of the thin film transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be performed. On the other hand, in the conductive state of the thin film transistor, the oxide semiconductor layer can be expected to have a higher current supply capacity than a

[0266] semiconductor layer formed of amorphous silicon. Also, in a thin film transistor having low-temperature polysilicon, it is estimated that the off-current is about 10,000 times larger than that of a thin film transistor fabricated using an oxide semiconductor, and design and the like are carried out accordingly. Therefore, in a thin film transistor having an oxide semiconductor, when the holding capacitance is the same (about 0.1 pF) as that of a thin film transistor having low-temperature polysilicon, the voltage holding period can be extended about 10,000 times. As an example, when video display is performed at 60 frames per second, the holding period due to one signal writing can be set to about 160 seconds, which is 10,000 times longer. And even with a small number of

[0267] image signal writing times, a still image can be displayed on the display unit. By applying the transistor shown in this embodiment to the semiconductor devices shown in Embodiments 1

[0268] (Embodiment 6) In this embodiment, an example of a display device will be described.

[0269] FIG. 18(A) shows an example of a display device. The display device shown in FIG. 18(A) includes a circuit 5361 , a circuit 5362, a circuit 5363_1, a circuit 5363_2, and a pixel section 5364 . A plurality of wirings 5371 extend from the circuit 5362 and are arranged in the pixel section 5364 , and a plurality of wirings 5372 extend from the circuit 5363_1 and the circuit 5363_2 and are arranged . And pixels 5367 are arranged in a matrix in the intersection regions of the plurality of wirings 5371 and the plurality of wirings 5372 .

[0270] The circuit 5361 is assumed to have a function of controlling the operation timing of the circuit 5362, the circuit 5363_1, and the circuit 5363_2 . For this purpose, the circuit 5361 supplies a signal, a voltage, or a current, etc. to the circuit 5362, the circuit 5363_1, and the circuit 5363_2 according to the video signal 53 60. For example, the circuit 5361 supplies a start signal (SSP) for a source driver circuit, a clock signal (SCK) for a source driver circuit, an inverted clock signal (SCKB) for a source driver circuit, data for a video signal (DATA), and a latch signal (LAT) to the circuit 5362 . Also, the circuit 5361 supplies a start signal (GSP) for a gate driver circuit, a clock signal (GCK) for a gate driver circuit, and an inverted clock signal (GCKB) for a gate driver circuit to the circuit 5363_1 and the circuit 5363_2 . In this way, the circuit 5361 is assumed to have a function as a controller, a control circuit, a timing generator, a power supply circuit, or a regulator, etc . . The circuit 5362 receives signals (for example, SSP, SCK, SCKB ) supplied from the circuit 5361 . .

[0271] . ​, DATA, LAT), has a function of outputting a video signal to a plurality of wirings 5371 shall be. That is, the circuit 5362 has a function as a source driver circuit shall be.

[0272] Circuits 5363_1 and 5363_2 have a function of outputting a gate signal to a plurality of wirings 5372 in response to the signals (GSP, GCK, GCKB) supplied from the circuit 5361 shall be. That is, the circuits 5363_1 and 5363_2 can function as gate driver circuits is possible.

[0273] In the display device shown in FIG. 18(A), since the same signal is supplied to the circuit 5363_1 and the circuit 5363_2, the circuit 5363_1 and the circuit 5363_2 often output a gate signal to the plurality of wirings 5372 at substantially the same timing. Thereby, the loads of the circuits 5363_1 and 5363_2 can be reduced. However, an example of this embodiment is not limited thereto. For example, as shown in FIG. 18(B), different signals can be input to the circuit 5363_1 and the circuit 5363_2. Thus, a part of the plurality of wirings 5372 (for example, odd rows) can be controlled by the circuit 5363_1, and another part of the plurality of wirings 5372 (for example, even rows) can be controlled by the circuit 5363_2. Therefore, the driving frequencies of the circuits 5363_1 and 5363_2 can be reduced be. shall be.

[0274] As shown in FIG. 18(B), the display device can have a circuit 5365 and a lighting device 5366. The circuit 5365 is backlight control supplied from the circuit 5361 Control the amount of power supplied to the lighting device 5366, or the time, etc. according to the signal (BLC). It shall have a function to do so. Thereby, the luminance (or average luminance) of the lighting device 5366 can be controlled according to the image signal 5360. Therefore, backlight area control can be realized. Or, when the image is dark overall, the luminance of the lighting device 5366 can be lowered, and when the image is bright overall, the luminance of the lighting device 5366 can be increased. In this way, the contrast ratio can be improved, or power consumption can be reduced.

[0275] Note that the plurality of wirings 5371 and the plurality of wirings 5372 shall have the function as signal lines. In particular, the plurality of wirings 5371 shall have the function as source signal lines (also called video signal lines). In particular, the plurality of wirings 5372 shall have the function as gate signal lines (also called scanning signal lines or selection signal lines).

[0276] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted. Also, it is possible to newly provide a circuit having the same function as the circuit 5363_1 and the circuit 5363_2.

[0277] Note that in the pixel portion 5364, one or a plurality of wirings (for example, capacitance lines, power supply lines, gate signal lines, and / or source signal lines, etc.) can be arranged according to the configuration of the pixel 5367. In such a case, a circuit for controlling the potential of the newly provided wiring can also be newly provided. In particular, when using a liquid crystal element or an electrophoretic element, etc. as the display element, it is preferable to provide a capacitance line in the pixel portion 5364. In particular, when using an EL element as the display element ​​​​​​​​​​​​​When using it, it is preferable to provide the power supply to the pixel portion 5364.

[0278] Next, as shown in FIG. 19(A), in the display device shown in FIG. 18(A), the circuit 5362, the circuit 5363_1, and the circuit 5363_2 can be formed on the same substrate 5380 as the pixel portion 5364. And the circuit 5361 of the display device shown in FIG. 18(A) can be formed on a substrate different from the pixel portion 53 64.

[0279] Note that, as shown in FIG. 19(B), in the display device shown in FIG. 18(A), the circuit 5361 and the circuit 5362 can be formed on a substrate different from the pixel portion 5364. The circuit 536 3_1 and the drive frequency of the circuit 5363_2 are often lower than those of the circuit 5361 and the circuit 5362. Therefore, the circuit 5361 and the circuit 5 362 are preferably formed on a substrate different from the circuit 5363_1 and the circuit 5 363_2. As a result, since the drive frequencies of the circuit 5361 and the circuit 536 2 can be increased, the display device can be enlarged. Also the circuit 5363_1 and the circuit 5363_2 can be formed on the same substrate as the pixel portion 5364, and the display device can be manufactured at low cost.

[0280] Note that, as shown in FIG. 19(C), in the display device shown in FIG. 18(A), the circuit 5362a (a part of the circuit 5362) is formed on the same substrate as the pixel portion 5364, and the circuit 5361 and the circuit 53 62b (another part of the circuit 5362) can be formed on a substrate different from the pixel portion 5364. As the circuit 5362a, a circuit with a relatively low drive frequency such as a switch, a shift register, and / or a selector can be used. Therefore, the circuit 5361 and Since the driving frequency of circuit 5362b can be increased, the display device can be enlarged. Alternatively, since circuit 5362a, circuit 5363_1, and circuit 5363_2 can be formed on the same substrate as pixel section 53 64, the display device can be manufactured at low cost.

[0281] Note that in the display device shown in FIG. 18(A), as shown in FIG. 19(D), circuit 5361a (a part of circuit 5361) is formed on the same substrate as pixel section 5364, and circuit 5361b (another part of circuit 53 61) can be formed on a substrate different from pixel section 5364. Note that a circuit (also referred to as an external circuit) formed on a substrate different from pixel section 5364 supplies signals, voltages

[0282] , or currents, etc. to a circuit or wiring formed on the same substrate as pixel section 5364 via input terminal 5381. Note that the external circuit often supplies signals, voltages , or currents, etc. to a circuit or wiring formed on the same substrate as pixel section 5364 via input terminal 5381.

[0283] Note that the external circuit can be mounted on an FPC (Flexible Printed Circuit) using the TAB (Tape Automated Bonding) method. Alternatively, the external circuit can be mounted on the same substrate 5380 as pixel section 5364 by the COG (Chip on Glass) method. Note that the external circuit is preferably formed on a single-crystal substrate or an SOI substrate or the like. Thereby, it is possible to improve the driving frequency, improve the driving voltage, or reduce the variation in output signals.

[0284] Note that the display device of the present embodiment can apply the semiconductor devices shown in Embodiments 1 to 4. In particular, as circuits 5362 and 5363, Embodiments 1 to 4 Thereby, it is possible to improve the driving frequency, improve the driving voltage, or reduce the variation in output signals. can be achieved.

[0285] Note that the display device of the present embodiment can apply the semiconductor devices shown in Embodiments 1 to 4. In particular, as circuits 5362 and 5363, Embodiments 1 to 4 can be applied. It is possible to use the semiconductor device shown in Form 4. Thereby, the driving ability of the circuit (for example, circuit 5362 and circuit 5363) for driving the pixel portion 5364 can be improved. Therefore, the resolution of the pixel can be improved. Or, the display device can be made larger.

[0286] In addition, in this specification and the like, a display element, a display device which is a device having the display element, a light emitting element, and a light emitting device which is a device having the light emitting element can use various forms or have various elements. As an example of the display element, the display device, the light emitting element or the light emitting device, there are an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, etc.), a transistor (a transistor that emits light according to an electric current), an electron emission element, a liquid crystal element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a digital micromirror device (DMD), a piezoelectric ceramic display, etc., and those having a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to an electromagnetic action. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron emission element, there is a field emission display (FED) or an SED type flat panel display (SED: Surface e-conduction Electron-emitter Disply), etc. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, etc.). , projection type liquid crystal display, etc. Display devices using electronic ink or electrophoretic elements One example is electronic paper.

[0287] An example of an EL element includes an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. One example of an EL layer is a device that uses light emission (fluorescence) from singlet excitons. Those that utilize emission from triplet excitons (phosphorescence), and those that utilize emission from singlet excitons (fluorescence). These include those that utilize light (photoluminescence) and those that utilize light emission from triplet excitons (phosphorescence), Those formed by organic matter, those formed by inorganic matter, those formed by organic matter those made of polymeric materials and inorganic materials; those made of low molecular weight materials; or those containing polymeric and low molecular weight materials. However, the EL element is not limited to this, and various elements can be used as the EL element.

[0288] An example of a liquid crystal element is a liquid crystal display device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is caused by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field, or oblique electric field). Specifically, the liquid crystal element is controlled by an electric field in the forward direction. , nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, Motropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal ( PDLC), Ferroelectric Liquid Crystal, Antiferroelectric Liquid Crystal, Main Chain Liquid Crystal, Side Chain Polymer Liquid Crystal, Plasma Adapter The following liquid crystals are also available: non-transparent liquid crystal (PALC), banana-shaped liquid crystal, etc. include TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axially Symmetrically aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, Blue Phase mode, etc. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used. sted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (M ulti-domain Vertical Alignment) mode, PVA (P atterned Vertical Alignment) mode, ASV (Adva nced Super View) mode, ASM (Axially Symmetri c aligned Micro-cell) mode, OCB (Optically C ompensated Birefringence) mode, ECB (Electri cally Controlled Birefringence) mode, FLC (F erroelectric Liquid Crystal) mode, AFLC (Ant iFerroelectric Liquid Crystal) mode, PDLC (P olymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, Blue Phase mode, etc. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used. to these, and there are also various other modes such as the guest-host mode and the Blue Phase mode. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used.

[0289] As an example of the display method of electronic paper, those displayed by molecules (such as optical anisotropy, dye molecule orientation, etc.), those displayed by particles (such as electrophoresis, particle movement, particle rotation, phase change, etc.), those displayed by the movement of one end of a film, the color development / phase change of molecules change, etc.), those displayed by the movement of one end of a film, the color development / phase change of molecules Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. Those displayed by, those displayed by molecular light absorption, or those displayed by spontaneous emission due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid (registered trademark), magnetophoresis type, magnetic thermosensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color change by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various ones can be used as the electronic paper and its display method. Here, by using microcapsule electrophoresis as the display method of electronic paper, aggregation and precipitation of electrophoresis particles, which are drawbacks of the electrophoresis method, can be solved. Also, by using electronic powder fluid (registered trademark) as the display method of electronic paper, it has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc.

[0290] In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. In addition, as an example of the light source of a display device that requires a light source, such as a liquid crystal display (transmissive liquid crystal display, transflective liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display), a display device using a grating light valve (GLV), a display device using a digital micromirror device (DMD), etc., examples of the light source include electroluminescence, cold cathode tube, hot cathode tube, LED, laser light source, mercury lamp, etc. can be used. However, it is not limited thereto, and various light sources can be used .

[0291] In addition, in this specification and the like, transistors can be formed using various substrates . The type of substrate is not limited to a specific one. As an example of a substrate for forming a transistor , there are a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate , a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil , a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film, etc. . As an example of a glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass, etc. . As an example of a flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) , or a synthetic resin having flexibility such as acrylic, etc. . As an example of a laminated film, there are polypropylene, polyester, vinyl, polyvinyl fluoride , or vinyl chloride, etc. . As an example of a base film, there are polyester, polyamide, polyimide, an inorganic vapor deposition film, or papers, etc. . In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., variations in characteristics, sizes, or shapes are small, and a transistor having a high current capacity and a small size can be manufactured. When a circuit is configured with such a transistor, low power consumption of the circuit or high integration of the circuit can be achieved . . . .

[0292] Note that a transistor may be formed using a certain substrate and then transferred to another substrate, and the transistor may be disposed on another substrate. An example of the substrate to which the transistor is transferred includes, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), a leather substrate, or a rubber substrate. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor

[0293] with low power consumption, manufacture a device that is difficult to break, impart heat resistance, reduce weight, or make it thinner. Note that it is possible to form all of the circuits necessary to realize a predetermined

[0294] function on the same substrate (for example, a glass substrate, a plastic substrate, a single-crystal substrate, or an SOI substrate, etc.). Note that it is also possible not to form all of the circuits necessary to realize a predetermined function on the same substrate. That is, a part of the circuits necessary to realize a predetermined function may be formed on one substrate, and another part of the circuits necessary to realize a predetermined function may be formed on another substrate. For example, a part of the circuits necessary to realize a predetermined By Chip On Glass, it is possible to connect to a glass substrate and place the IC chip on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board, etc. In addition, transistors that make up the drive circuit (for example, circuit 5362 and circuit 5363), and / or transistors that make up the pixel portion 5354 can use the transistors shown in Embodiment 5. (Embodiment 7) In this embodiment, an example of a pixel and a method for driving the pixel will be described. In particular, an example of a pixel including a display element having memory characteristics and an example of a method for driving the pixel will be described.

[0295] FIG. 20(A) shows an example of a circuit diagram of a pixel. Pixel 5450 has a transistor 5451, a capacitive element 5452, and a display element 5453. The first terminal of transistor 5451 is connected to wiring 5461. The second terminal of transistor 5451 is connected to one electrode of capacitive element 5452 and one electrode of display element 5453 (also referred to as a pixel electrode). The gate of transistor 5451 is connected to wiring 5462. The other electrode of capacitive element 5452 is connected to wiring 5463. The other electrode of display element 5453 is connected to electrode 5454 (also referred to as a common electrode, common electrode, counter electrode, cathode electrode).

[0296] Note that one electrode of display element 5453 is denoted as electrode 5455. In addition, the transistor that makes up the drive circuit (for example, circuit 5362 and circuit 5363), and / or transistors that make up the pixel portion 5354 can use the transistors shown in Embodiment 5.

[0297] FIG. 20(A) shows an example of a circuit diagram of a pixel. Pixel 5450 has a transistor 5451, a capacitive element 5452, and a display element 5453. The first terminal of transistor 5451 is connected to wiring 5461. The second terminal of transistor 5451 is connected to one electrode of capacitive element 5452 and one electrode of display element 5453 (also referred to as a pixel electrode). The gate of transistor 5451 is connected to wiring 5462. The other electrode of capacitive element 5452 is connected to wiring 5463. The other electrode of display element 5453 is connected to electrode 5454 (also referred to as a common electrode, common electrode, counter electrode, cathode electrode). Note that one electrode of display element 5453 is denoted as electrode 5455. The gate of transistor 5451 is connected to wiring 5462. The other electrode of capacitive element 5452 is connected to wiring 5463. The other electrode of display element 5453 is connected to electrode 5454 (also referred to as a common electrode, common electrode, counter electrode, cathode electrode). Note that one electrode of display element 5453 is denoted as electrode 5455. The other electrode of display element 5453 is connected to electrode 5454 (also referred to as a common electrode, common electrode, counter electrode, cathode electrode).

[0298] Note that one electrode of display element 5453 is denoted as electrode 5455.

[0299] It is preferable that the display element 5453 has memory properties. As for the driving method of the display element 5453 or the display element , there are a microcapsule type electrophoresis method, a microcup type electrophoresis method , a horizontal movement type electrophoresis method, a vertical movement type electrophoresis method, a twist ball method, a powder movement method , an electrophoretic ink (registered trademark) method, a cholesteric liquid crystal element, a chiral nematic liquid crystal, an antiferroelectric liquid crystal, a polymer dispersed liquid crystal, a charged toner, an electro-wetting method, an electro trochromism method, an electrodeposition method, etc.

[0300] FIG. 20(B) shows a cross-sectional view of a pixel using a microcapsule type electrophoresis method. A plurality of microcapsules 5480 are arranged between the electrode 5454 and the electrode 5455. The plurality of microcapsules 5480 are fixed by a resin 5481. The resin 5481 has a function as a binder. The resin 5481 preferably has translucency. However, the space formed by the electrode 54 54, the electrode 5455, and the microcapsules 5480 may be filled with a gas such as air or an inert gas. Note that one or both of the surfaces of the electrode 5454 and the electrode 5455 may form a layer containing an adhesive or the like to fix the microcapsules 5480 .

[0301] The microcapsules 5480 have a film 5482, a liquid 5483, particles 5484, and particles 5 485. The liquid 5483, the particles 5484, and the particles 5485 are encapsulated in the film 5482 . The film 5482 has translucency. The liquid 5483 has a function as a dispersion liquid. The liquid 5483 separates the particles 5484 and the particles 5485 within the film 5482 . It can be dispersed. The liquid 5483 preferably has translucency and is uncolored. The particles 5484 and 5485 have different colors from each other. For example, one of the particles 5484 and 5485 is black, and the other of the particles 5484 and 5485 is white. The particles 5484 and 5485 are charged so that their charge densities are different from each other. For example, one of the particles 5484 and 5485 is positively charged, and the other of the particles 5484 and 5485 is negatively charged. Thereby, when a potential difference is generated between the electrode 5454 and the electrode 5455, the particles 5484 and 5485 move according to the direction of the electric field. In this way, the reflectance of the display element 5453 changes, and thus the gradation can be controlled. However, the structure of the microcapsule 5480 is not limited to the above-described one. For example, the liquid 5483 can be colored. As another example, the number of types of particles encapsulated in the film 5482 can be one, or can be three or more. As another example, the particles 5484 and 5485 can be selected from not only white and black but also red, green, blue, cyan, magenta, yellow, emerald green, vermilion, etc.

[0302] Examples of the film 5482 include materials having translucency (e.g., acrylic resins (e.g., methyl methacrylate, ethyl polymethacrylate, etc.), urea resins, or natural gums such as gum arabic). The film 5482 is preferably gelatinous. Thereby, since improvements in flexibility, bending strength, mechanical strength, etc. can be achieved, the flexibility can be improved. Or, the microcapsules 5480 are filled in the film without gaps and uniformly.​ It can be arranged on a substrate such as this.

[0303] As the liquid 5483, an oily liquid having translucency may be used. Specifically, the liquid 5 483 includes alcohol solvents (such as methanol, ethanol, isopropanol , butanol, octanol, or methyl cellosolve, etc.), esters (such as ethyl acetate or butyl acetate, etc.), aliphatic hydrocarbons (such as acetone, methyl ethyl ketone, methyl ketones such as isobutyl ketone, pentane, hexane, or octane, etc.), alicyclic hydrocarbons (such as cyclohexane or methylcyclohexane, etc.), aromatic hydrocarbons having a long-chain alkyl group (such as benzene, toluene, xylene, hexylbenzene , butylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene , dodecylbenzene, tridecylbenzene, or tetradecylbenzene, etc.), halogenated hydrocarbons (such as methylene chloride, chloroform, carbon tetrachloride, or dichloroethane, etc.), carboxylates, water, or other oils, etc. Or, there are mixtures of at least two or more of these materials. Or, there are those in which a surfactant or the like is blended with these materials or mixtures of at least two or more of these materials. There are, for example, carboxylic acid salts, water, or other oils, etc. Or, there are mixtures of at least two or more of these materials. Or, there are those in which a surfactant or the like is blended with these materials or mixtures of at least two or more of these materials. Among these materials, there are mixtures of at least two or more of them. Or, there are those in which a surfactant or the like is blended with these materials or mixtures of at least two or more of these materials. There are those in which a surfactant or the like is blended with these materials or mixtures of at least two or more of these materials.

[0304] Particles 5484 and particles 5485 are each composed of a pigment. The pigments constituting particles 5484 and particles 5485 are preferably of different colors from each other. For example, particles 548 4 may be composed of a black pigment, and particles 5485 may be composed of a white pigment. Examples of the black pigment include aniline black or carbon black. Examples of the white pigment Examples include titanium dioxide, zinc white (zinc oxide), or antimony trioxide. Note that charge control agents (such as electrolytes, surfactants, metal soaps, resins, rubbers, oils , varnishes, or compounds), dispersants (such as titanium-based coupling agents, aluminum -based coupling agents, or silane-based coupling agents), lubricants, or stabilizers can be added to these pigments.

[0305] FIG. 21(A) shows a cross-sectional view of a pixel when the twist ball method is used as the method of the display element 5453. The twist ball method changes the reflectance by rotating the display element and controls the gradation. The difference from FIG. 20(B) is that a twist ball 5486 is disposed between the electrodes 5454 and 5455 instead of the microcapsules 5480. The twist ball 5486 is composed of particles 5487 and a cavity 5488 formed around the particles 5487. The particles 5487 are spherical particles each having a hemispherical surface painted with a certain color and a color different from the certain color. Here, it is assumed that the particles 5487 have their hemispherical surfaces painted white and black, respectively. Note that a charge density difference is provided between the two hemispherical surfaces. Therefore, by generating a potential difference between the electrodes 5454 and 5455, the particles 5487 can be rotated according to the direction of the electric field. The cavity 5488 is filled with a liquid. The liquid can be the same as the liquid 5483. However, the twist ball 5486 is not limited to the structure shown in FIG. 21(A). For example, the structure of the twist ball 5486 can be a cylinder, an ellipse, or the like.

[0306] FIG. 21(B) shows a cross-sectional view of a pixel in the case where the electrophoretic method of the micro-cup type is used as the method of the display element 5453. The micro-cup array is made of a UV curable resin or the like and has a plurality of concave portions. The micro-cup 5491 is filled with charged dye particles 5493 dispersed in a dielectric solvent 5492 and sealed with a sealing layer 5494, and can be manufactured. An adhesive layer 5495 may be formed between the sealing layer 5494 and the electrode 5455. As the dielectric solvent 5492, it is possible to use a non-colored solvent, or it is also possible to use a colored solvent such as red or blue. Here, the case where there is one type of charged dye particle is illustrated, but there may be two or more types of charged dye particles. Since the micro-cup has a wall structure that divides the cell, it has sufficient durability against impact and pressure. Alternatively, since the contents of the micro-cup are sealed, the influence of environmental changes can be reduced. pressure. Also, since the contents of the micro-cup are sealed, the influence of environmental changes can be reduced.

[0307] FIG. 21(C) shows a cross-sectional view of a pixel in the case where the electropowder fluid (registered trademark) method is used as the method of the display element 5453. The electropowder fluid (registered trademark) exhibits fluidity and is a substance having the characteristics of both a fluid and particles. In this method, the cell is divided by a partition wall 5504, and the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark) 5503 are arranged in the cell. As the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark) 5503, it is preferable to use white particles and black particles. However, the types of the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark ) 5503 are not limited to this. For example, as the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark) 5503, it is possible to use colored particles of two colors other than white and black. As another example, the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark and the electropowder fluid (registered trademark) 5503, it is possible to use colored particles of two colors other than white and black. As another example, the electropowder fluid (registered trademark) 5502 and the electropowder fluid (registered trademark ​ It is possible to omit one of them and the reference numeral 5503.

[0308] Assume that a signal is input to the wiring 5461. In particular, assume that a signal (for example, a video signal) for controlling the gradation of the display element 5 453 is input to the wiring 5461. In this way, the wiring 5461 is assumed to have a function as a signal line or a source signal line (also referred to as a video signal line or a source line ). Assume that a signal is input to the wiring 5462. In particular, assume that a signal (for example, a gate signal, a scanning signal, a selection signal, etc.) for controlling the conduction state of the transistor 5451 is input to the wiring 5462. In this way, the wiring 5 462 is assumed to have a function as a signal line or a gate signal line (also referred to as a scanning signal line or a gate line). Assume that a constant voltage is supplied to the wiring 5463. The wiring 546 3 is connected to the capacitor element 5452. Therefore, the wiring 5463 is assumed to have a function as a power supply line or a capacitor line. Assume that a constant voltage is supplied to the electrode 5454. The electrode 5454 is often common among a plurality of pixels or all pixels. Therefore, the electrode 5454 is assumed to have a function as a common electrode (also referred to as a common electrode, a counter electrode, or a cathode electrode).

[0309] Note that the signal or voltage input to the wiring 5461, the wiring 5462, the wiring 5463, and the electrode 5454 is not limited to those described above, and various other signals or various voltages can be input thereto. For example, it is possible to input a signal to the wiring 5463. By this the potential of the electrode 5455 can be controlled, so that the signal input to the wiring 5461 The amplitude voltage can be reduced. Therefore, the wiring 5463 can function as a signal line. As another example, by changing the voltage supplied to the electrode 5454, the voltage applied to the display element 5453 can be adjusted. As a result, the amplitude voltage of the signal input to the wiring 5461 can be reduced.

[0310] The transistor 5451 has a function of controlling the conduction state between the wiring 5461 and the electrode 5455. Alternatively, the transistor 5451 has a function of controlling the timing of supplying the potential of the wiring 5461 to the electrode 5455. Alternatively, the transistor 5451 has a function of controlling the timing of selecting the pixel 5450. In this way, the transistor 5451 shall have a function as a switch or a selection transistor. Note that the transistor 5451 is of the N-channel type. Therefore, the transistor 5451 turns on when an H signal is input to the wiring 5462 and turns off when an L signal is input to the wiring 5462. However, the polarity of the transistor 5451 is not limited to the N-channel type, and the transistor 5451 can be of the P-channel type. In this case, the transistor 5451 turns on when an L signal is input to the wiring 5462 and turns off when an H signal is input to the wiring 5462. The capacitive element 5452 has a function of holding the potential difference between the electrode 5455 and the wiring 5463. Alternatively, the capacitive element 5452 has a function of maintaining the potential of the electrode 5455 at a predetermined value. As a result, even when the transistor 5451 turns off, a voltage can continue to be applied to the display element 5453. In this way, the capacitive element 5452 has a function of maintaining the potential of the electrode 5455 at a predetermined value. As a result, even when the transistor 5451 turns off, a voltage can continue to be applied to the display element 5453. In this way, the capacitive element 5452 Assume that 452 has a function as a holding capacity. However, the functions of the transistor 5451 and the capacitive element 5452 are not limited to those described above, and it is possible to have various other functions.

[0311] Next, an outline of the operation of the pixel of this embodiment will be described. The gradation control of the display element 5453 is performed by applying a voltage to the display element 5453 to generate an electric field in the display element 5453. The control of the voltage applied to the display element 5453 is performed by controlling the potential of the electrode 5454 and the potential of the electrode 5455. Specifically, the control of the potential of the electrode 5454 is performed by controlling the voltage supplied to the electrode 5454. The control of the potential of the electrode 5455 is performed by controlling the signal input to the wiring 5461. Note that the signal input to the wiring 54 61 is supplied to the electrode 5455 when the transistor 5451 is turned on.

[0312] Note that by controlling the intensity of the electric field applied to the display element 5453, the direction of the electric field applied to the display element 5453, the time for applying the electric field to the display element 5453, etc., the gradation of the display element 5453 can be controlled. Note that by not generating a potential difference between the electrode 5454 and the electrode 5455, the gradation of the display element 5453 can be held.

[0313] Next, an example of the operation of the pixel of this embodiment will be described. The timing chart shown in FIG. 22(A) shows a period T having a selection period and a non-selection period. The period T refers to the period from the start time of the selection period to the start time of the next selection period.

[0314] ​​During the selection period, since an H signal is input to wiring 5462, the potential of wiring 5462 (denoted as potential V5 462) becomes the H level. Therefore, transistor 5451 turns on, so , wiring 5461 and electrode 5455 are in a conductive state. As a result, the signal input to wiring 5461 is supplied to electrode 5455 via transistor 5451. And the potential of electrode 5455 (denoted as potential V5455) becomes equal to the value of the signal input to wiring 5461 . At this time, capacitor element 5452 holds the potential difference between electrode 5455 and wiring 5463. During the non-selection period, since an L signal is input to wiring 5462, the potential of wiring 5462 becomes the L level. Therefore, transistor 5451 turns off, so wiring 54 61 and electrode 5455 are in a non-conductive state. Then, electrode 5455 becomes floating. At this time, capacitor element 5452 holds the potential difference between electrode 5455 and wiring 5463 during the selection period . Therefore, the potential of electrode 5455 remains equal to the value of the signal input to wiring 546 1 during the selection period. Thus, even when transistor 5451 turns off during the non-selection period, a voltage can continue to be applied to display element 5453 . As described above, by controlling the signal input to wiring 5461 during the selection period, the voltage applied to display element 5453 can be controlled. That is, the gradation control of display element 5453 can be performed by controlling the signal input to wiring 5461 during the selection period .

[0315] Note that the potential of electrode 5455 during the non-selection period is affected by the off-current of transistor 5451, the feed-through of transistor 5451, and the charge injection of transistor 5451 ​Due to the influence of factors such as noise, it may be different from the signal input to wiring 5461 during the selection period. It is different.

[0316] As shown in FIG. 22(B), during a part of the selection period, it is possible to make the potential of electrode 5455 equal to the value of electrode 5454. Therefore, even if the same signal continues to be input to wiring 5461 continuously, by changing the potential of electrode 5455 during a part of the selection period, the electric field strength of display element 5453 can be changed. Therefore, afterimages can be reduced. Or, the response speed can be increased. Or, the variation in response speed between pixels can be reduced, and unevenness or afterimages can be prevented. In order to realize such a driving method, it is preferable to divide the selection period into period T1 and period T2. Then, during period T1, the signal input to wiring 5461 may be made equal to the value of electrode 5454. Note that during period T2, the signal input to wiring 5461 may be set to various values in order to control the gradation of display element 5453. If the time of period T1 is too long, the time for writing the signal for controlling the gradation of display element 5453 to pixel 5450 becomes short. Therefore, it is preferable that period T1 is shorter than period T2. In particular, it is preferable that period T1 is 1% or more and 20% or less of the selection period. More preferably, it is 3% or more and 15% or less. Even more preferably, it is 5% or more and 10% or less. Next, an example of the operation of the pixel of the present embodiment, in which the gradation of display element 5453 is controlled by the time for applying a voltage to display element 5453, will be described. The timing chart shown in FIG. 22(C) has period Ta and period Tb. And period Ta has N (N is a natural number) pieces. Then, during period T1, the signal input to wiring 5461 may be made equal to the value of electrode 5454. Note that during period T2, the signal input to wiring 5461 may be set to various values in order to control the gradation of display element 5453. If the time of period T1 is too long, the time for writing the signal for controlling the gradation of display element 5453 to pixel 5450 becomes short. Therefore, it is preferable that period T1 is shorter than period T2. In particular, it is preferable that period T1 is 1% or more and 20% or less of the selection period. More preferably, it is 3% or more and 15% or less. Even more preferably, it is 5% or more and 10% or less. Therefore, it is preferable that period T1 is shorter than period T2. In particular, it is preferable that period T1 is 1% or more and 20% or less of the selection period. More preferably, it is 3% or more and 15% or less. Even more preferably, it is 5% or more and 10% or less. % or more and 15% or less. Even more preferably, it is 5% or more and 10% or less.

[0317] Next, an example of the operation of the pixel of the present embodiment, in which the gradation of display element 5453 is controlled by the time for applying a voltage to display element 5453, will be described. The timing chart shown in FIG. 22(C) has period Ta and period Tb. And period Ta has N (N is a natural number) pieces. The timing chart shown in FIG. 22(C) has period Ta and period Tb. And period Ta has N (N is a natural number) has a period T. Each of the N periods T is the same as the period T shown in FIGS. 22(A) to (B). The period Ta is a period for changing the gradation of the display element 5453 (for example, an address period, a writing period, an image rewriting period, etc.). The period Tb is a period (holding period) for holding the gradation of the display element 5453 during the period Ta.

[0318] Assume that a voltage V0 is supplied to the electrode 5454. Therefore, a potential V0 is applied to the electrode 5454. A signal having at least three values is input to the wiring 5463. Let the potentials of the three values of the signal be a potential VH (VH > V0), a potential V0, and a potential VL (VL < V0), respectively. Therefore, the potential VH, the potential V0, and the potential VL are selectively applied to the electrode 5455.

[0319] During the N periods T included in the period Ta, the voltage applied to the display element 5453 can be controlled by controlling the potential applied to the electrode 5455. For example, when the potential VH is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is VH - VL. Thus, a positive voltage can be applied to the display element 5453. When the potential V0 is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is zero. Thus, a voltage of zero can be applied to the display element 5453. When the potential VL is applied to the electrode 5455, the potential difference between the electrode 5454 and the electrode 5455 is VL - VH. Thus, a negative voltage can be applied to the display element 5453. As described above, during the period Ta, a positive voltage (VH - VL) can be applied to the display element 5453. ​​​​​​) and a negative voltage (VL - VH) and zero can be applied in various orders. Thereby , the gradation of the display element 5453 can be finely controlled. Or, afterimages can be reduced . Or, the response speed can be increased.

[0320] Note that in this embodiment, when a positive voltage is applied to the display element 5453, the display element 545 3's gradation is assumed to approach black (also referred to as the first gradation). When a negative voltage is applied to the display element 5453, the gradation of the display element 5453 is assumed to approach white (also referred to as the second gradation). When a voltage of zero is applied to the display element 5453, the gradation of the display element 5453 is assumed to be held.

[0321] During the period Tb, the signal input to the wiring 5461 is not written to the pixel 5450. Therefore, during the period Tb, the potential applied to the electrode 5455 in the Nth period T of the period Ta continues to be applied to the electrode 5455. In particular, during the period Tb, it is preferable to hold the gradation of the display element 5453 by not generating an electric field in the display element 5453. For this purpose, it is preferable that a potential V0 is applied to the electrode 5455 in the Nth period T of the period Ta. Thereby, also during the period Tb, the potential V0 is applied to the electrode 5455, so a voltage of zero is applied to the display element 5453. Therefore, the gradation of the display element 5453 can be held.

[0322] Note that the closer the gradation that the display element 5453 will display next is to the first gradation, the longer the time during which the potential VH is applied to the electrode 5455 in the period Ta may be. Or, the number of times the potential VH is applied to the electrode 5455 among the N periods T may be increased. Or, in the period Ta among them, the number of times the potential VH is applied to the electrode 5455 may be increased. Or, in the period Ta Among them, it is preferable to increase the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455. Or, among the N periods T, it is preferable to increase the number obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455. In addition, the closer the gradation to be next displayed by the display element 5453 is to the second gradation, the longer the time during which the potential VL is applied to the electrode 5455 in the period Ta is preferably. Or, among the N periods T, it is preferable to increase the number of times the potential VL is applied to the electrode 5455. Or, in the period Ta, it is preferable to increase the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455. Or, among the N periods T, it is preferable to increase the number obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455.

[0323] Note that, the closer the gradation to be next displayed by the display element 5453 is to the second gradation, the longer the time during which the potential VL is applied to the electrode 5455 in the period Ta is preferably. Or, among the N periods T, it is preferable to increase the number of times the potential VL is applied to the electrode 5455. Or, in the period Ta, it is preferable to increase the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455. Or, among the N periods T, it is preferable to increase the number obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455. In addition, the closer the gradation to be next displayed by the display element 5453 is to the second gradation, the longer the time during which the potential VL is applied to the electrode 5455 in the period Ta is preferably. Or, among the N periods T, it is preferable to increase the number of times the potential VL is applied to the electrode 5455. Or, in the period Ta, it is preferable to increase the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455. Or, among the N periods T, it is preferable to increase the number obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455.

[0324] Note that, in the period Ta, the combination of the potentials (potential VH, potential V0, potential VL) applied to the electrode 5455 depends not only on the gradation to be next displayed by the display element 5453 but also on the gradation already displayed by the display element 5453. Therefore, even when the gradations to be displayed by the next display element 5453 are the same, if the gradations already displayed by the display element 5453 are different, the combination of the potentials applied to the electrode 5455 may be different.

[0325] For example, in the period Ta for displaying the gradation already displayed by the display element 5453, the longer the time during which the potential VH is applied to the electrode 5455, The longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, the larger the number of times the potential VH is applied to the electrode 5455 within N periods T, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Alternatively, the number of times the potential VL is applied to the electrode 5455 within N periods T may be increased. Alternatively, the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455 within the period Ta may be lengthened. Alternatively, the number of times obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within N periods T may be increased. Thereby, afterimages can be reduced. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be. Among the N periods T, the longer the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455, or the larger the number of times the potential VH is applied to the electrode 5455, or the larger the value obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455 within N periods T, the longer the time during which the potential VL is applied to the electrode 5455 within the period Ta may be.

[0326] As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. Alternatively, the number of times the potential VH is applied to the electrode 5455 within the N periods T may be increased. Alternatively, the time obtained by subtracting the time when the potential VL is applied to the electrode 5455 from the time when the potential VH is applied to the electrode 5455 within the period Ta may be lengthened. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. As another example, during the period Ta for displaying the gradation that the display element 5453 has already displayed, the longer the time during which the potential VL is applied to the electrode 5455, the longer the time obtained by subtracting the time when the potential VH is applied to the electrode 5455 from the time when the potential VL is applied to the electrode 5455, the larger the number of times the potential VL is applied to the electrode 5455 among the N periods T, or the larger the value obtained by subtracting the number of times the potential VH is applied to the electrode 5455 from the number of times the potential VL is applied to the electrode 5455 within the N periods T, the longer the time during which the potential VH is applied to the electrode 5455 within the period Ta may be. Yes. Or, among the N periods T, it is preferable to increase the number obtained by subtracting the number of times the potential VL is applied to the electrode 5455 from the number of times the potential VH is applied to the electrode 5455. Thereby, the residual image can be reduced.

[0327] Note that each of the N periods T is assumed to have an equal length. However, the lengths of the N periods T are not limited to this. For example, at least two of the N periods T can have different lengths from each other. In particular, it is preferable to weight the lengths of the N periods T. For example, when N = 4, if the length of the first period T is time h, the length of the second period T may be time h×2. The length of the third period T may be time h×4. The length of the fourth period T may be time h×8. By weighting the lengths of the N periods T in this way, the number of times of selecting the pixel 5450 can be reduced, and the time of applying a voltage to the display element 5453 can be finely controlled. Therefore, power consumption can be reduced.

[0328] Note that the potential VH and the potential VL can be selectively applied to the electrode 5454. In this case, it is preferable to selectively apply the potential VH and the potential VL to the electrode 5455 as well. For example, when the potential VH is applied to the electrode 5454, if the potential VH is applied to the electrode 5455, a voltage of zero is applied to the display element 5453. If the potential VL is applied to the electrode 5455, a negative voltage is applied to the display element 5453. On the other hand, when the potential VL is applied to the electrode 5454, if the potential VH is applied to the electrode 5455, a positive voltage is applied to the display element 5453. If the potential VL is applied to the electrode 5455, a voltage of zero is applied to the display element 5453. ​​​​​​​​​​​​​​​​ is imprinted. In this way, the signal input to the wiring 5461 can be made binary (digital signal) and can be achieved. Therefore, the circuit for outputting a signal to the wiring 5461 can be simplified.

[0329] Note that during the period Tb or a part of the period Tb, it is possible not to input a signal to the wiring 5461 and the wiring 5462. That is, it is possible to float the wiring 5461 and the wiring 5462. Note that during the period Tb or a part of the period Tb, it is possible not to input a signal to the wiring 5463. That is, it is possible to float the wiring 5463. Note that during the period Tb or a part of the period Tb, it is possible not to supply a voltage to the electrode 5454. That is, it is possible to float the electrode 5454.

[0330] The memory - having display element shown in this embodiment needs to have a larger voltage applied compared to a normal liquid crystal element (e.g., TN liquid crystal). As a circuit for driving the memory - having display element, by applying the semiconductor devices of Embodiments 1 - 4 using the transistor of Embodiment 5, the driving voltage can be increased. This is because the breakdown voltage of the transistor shown in Embodiment 5 is higher compared to an a - Si TFT (amorphous silicon thin - film transistor) or a p - Si TFT (polycrystalline silicon thin - film transistor), etc.

[0331] Furthermore, when applying the transistor shown in Embodiment 5 to the circuit for driving the memory - having display element, it is preferable to use the transistor shown in Embodiment 5 as the transistor 5451 that constitutes a pixel together with the memory - having display element. Thereby, the ​​​​​​​​​​​​​Since the off-current of the transistor 5451 can be reduced, the channel width of the transistor 5451 can be reduced. Or, the area of the capacitive element 5452 can be reduced. Therefore, the area of the pixel can be reduced. Thus, by providing the pixel of the present embodiment in the pixel portion of the display device, the display device can be made high-definition. Also, a circuit for driving a display element having a memory property and a pixel portion including a display element having a memory property can be easily formed on the same substrate.

[0332] (Embodiment 8) In the present embodiment, an example of an electronic device will be described.

[0333] FIGS. 27(A) to 27(H) and FIGS. 28(A) to 28(D) are diagrams showing an electronic device. These electronic devices can have a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, a sensor 5007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 5008, etc.

[0334] FIG. 27(A) is a mobile terminal, and in addition to the above-described components, it can have a switch 5009, an infrared port 5010, etc. FIG. 27(B) is a portable image playback device having a recording medium (for example, a DVD playback device), and in addition to the above-described components, it can have a second display unit 5002, a recording medium reading unit 5011, etc. FIG. 27(E) is a portable television. , in addition to those described above, it can have an antenna 5014, etc. Fig. 27(D) is a portable type gaming machine, which can have a recording medium reading unit 5011, etc. in addition to those described above. Fig. 27(C) is a projector, which can have a light source 5033, projection lenses 5034, etc. in addition to those described above. Fig. 27(F) is a portable gaming machine, which can have a second display unit 5002, a recording medium reading unit 5011, etc. in addition to those described above. Fig. 27(G) is a television receiver, which can have a tuner, an image processing unit, etc. in addition to those described above. Fig. 27(H) is a portable television receiver, which can have a charger 5017 capable of transmitting and receiving signals, etc. in addition to those described above. Fig. 28(A) is a disk spray, which can have a support base 5018, etc. in addition to those described above. Fig. 28(B) is a camera, which can have an external connection port 5019, a shutter button 5015, an imaging unit 5016, etc. in addition to those described above. Fig. 28(C) is a computer, which can have a pointing device 5020, an external connection port 501 9, a reader / writer 5021, etc. in addition to those described above. Fig. 28(D) is a mobile phone, which can have an antenna 5014, a tuner for 1-segment reception service for mobile phones / mobile terminals, etc. in addition to those described above. Fig. 28(D) is a mobile phone, which can have an antenna 5014, a tuner for 1-segment reception service for mobile phones / mobile terminals, etc. in addition to those described above. Fig. 28(D) is a mobile phone, which can have an antenna 5014, a tuner for 1-segment reception service for mobile phones / mobile terminals, etc. in addition to those described above. Fig. 28(D) is a mobile phone, which can have an antenna 5014, a tuner for 1-segment reception service for mobile phones / mobile terminals, etc. in addition to those described above. Fig. 28(D) is a mobile phone, which can have an antenna 5014, a tuner for 1-segment reception service for mobile phones / mobile terminals, etc. in addition to those described above.

[0335] The electronic devices shown in Figs. 27(A) to 27(H) and Figs. 28(A) to 28(D) can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, displaying a calendar, date, or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using wireless communication functions, A function to transmit or receive various data using a program recorded on a recording medium The data can be read out and displayed on the display unit. In electronic devices with displays, one display unit is used primarily to display image information, and another A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or in the camera) It can have functions such as storing the captured image on a built-in memory and displaying the captured image on the display unit. Note that the electronic devices shown in FIGS. The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0336] Next, application examples of the semiconductor device will be described.

[0337] FIG. 28(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The semiconductor device is a wall-mounted type that is integrated with the building and requires a large space to install. It can be installed without requiring a large space.

[0338] FIG. 28(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. Well. The display panel 5026 is attached integrally with the unit bath 5027, and the bather can view the display panel 5026.

[0339] In addition, in this embodiment, a wall and a unit bath are exemplified as buildings, but this embodiment is not limited to this, and semiconductor devices can be installed in various buildings.

[0340] Next, an example in which a semiconductor device is provided integrally with a moving body will be shown.

[0341] FIG. 28(G) is a diagram showing an example in which a semiconductor device is provided in an automobile. The display panel 5028 is attached to the vehicle body 5029 of the automobile, and can display the operation of the vehicle body or information input from inside and outside the vehicle body on demand. Note that it may have a navigation function.

[0342] FIG. 28(H) is a diagram showing an example in which a semiconductor device is provided integrally with a passenger aircraft. FIG. 28(H) is a diagram showing the shape during use when a display panel 5031 is provided on the ceiling 5030 above the seat of a passenger aircraft. The display panel 5031 is integrally attached to the ceiling 50 30 via a hinge portion 5032, and the passenger can view the display panel 5031 by the expansion and contraction of the hinge portion 5032. The display panel 5031 has a function of displaying information by being operated by the passenger.

[0343] In addition, in this embodiment, examples of the moving body include an automobile body and an aircraft body, but it is not limited to this, and it can be installed in various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0344] ​​​​​​​​ It is preferable to mount the semiconductor devices of Embodiments 1 to 4 on the electronic device shown in this embodiment. In particular, it is preferable to mount the semiconductor devices of Embodiments 1 to 4 as a circuit for driving the display unit of the electronic device. By mounting the semiconductor devices of Embodiments 1 to 4 as a circuit for driving the display unit of the electronic device, the area of the drive circuit can be reduced, and the display unit can be enlarged. Or, the resolution of the display unit can be improved. The area of the drive circuit can be reduced, and the display unit can be enlarged. Or, the resolution of the display unit can be improved. The area of the drive circuit can be reduced, and the display unit can be enlarged. Or, the resolution of the display unit can be improved. The area of the drive circuit can be reduced, and the display unit can be enlarged. Or, the resolution of the display unit can be improved.

[0345] (Embodiment 9) In this embodiment, another example of the structure and manufacturing method of the semiconductor device according to Embodiment 5 will be described with reference to FIG. 29. In this embodiment, the differences from Embodiment 5 will be described in detail, and the same points will be incorporated by reference to the description of Embodiment 5. First, after forming the gate electrode layer 411 on the substrate 400, a gate insulating layer 402 is formed so as to cover the gate electrode layer 411. Then, a first oxide semiconductor layer 404 is formed on the gate insulating layer 402. First, after forming the gate electrode layer 411 on the substrate 400, a gate insulating layer 402 is formed so as to cover the gate electrode layer 411. Then, a first oxide semiconductor layer 404 is formed on the gate insulating layer 402.

[0346] First, after forming the gate electrode layer 411 on the substrate 400, a gate insulating layer 402 is formed so as to cover the gate electrode layer 411. Then, a first oxide semiconductor layer 404 is formed on the gate insulating layer 402. First, after forming the gate electrode layer 411 on the substrate 400, a gate insulating layer 402 is formed so as to cover the gate electrode layer 411. Then, a first oxide semiconductor layer 404 is formed on the gate insulating layer 402. The first oxide semiconductor layer 404 is a ternary metal oxide, and an oxide semiconductor material represented by In-M

[0347] -Zn X -Zn Y -O Z ( Y = 0.5 to 5) can be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary and include the case where the content of M is zero (i.e., x = 0). On the other hand, the contents of In and Zn are zero. Y = 0.5 to 5) can be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary and include the case where the content of M is zero (i.e., x = 0). On the other hand, the contents of In and Zn are zero. Y = 0.5 to 5) can be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary and include the case where the content of M is zero (i.e., x = 0). On the other hand, the contents of In and Zn are zero. Y = 0.5 to 5) can be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary and include the case where the content of M is zero (i.e., x = 0). On the other hand, the contents of In and Zn are zero. It is not B. That is, the above notations include In-Ga-Zn-O, In-Zn-O, etc. are included.

[0348] Also, the first oxide semiconductor layer 404 is a quaternary metal oxide such as In-Sn-Ga-Zn-O or a ternary metal oxide such as In- Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Z n-O, Al-Ga-Zn-O, Sn-Al-Zn-O, or a binary metal oxide such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn- Mg-O, In-Mg-O, or In-O, Sn-O, Zn-O, etc. can also be used. In this embodiment, the first oxide semiconductor layer 404 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. That is all.

[0349] In this embodiment, the first oxide semiconductor layer 404 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. That is all.

[0350] As a target for producing the first oxide semiconductor layer 404 of the In-Ga-Zn-O system by sputtering, for example, a metal oxide target mainly composed of zinc oxide can be used. In addition, the composition ratio of the oxide semiconductor target containing In, Ga, and Zn is In:Ga:Zn = 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom ratio] (x = 1, y = 1) (that is, In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio]) can be used. In addition, as the oxide semiconductor target, a target having a composition ratio of In:Ga:Zn = 1: 1:0.5 [atom ratio], or a target having a composition ratio of In:Ga:Zn = 1: 1:1 [atom ratio] can also be used. For example, a target having a composition ratio of In:Ga:Zn = 1: 1:0.5 [atom ratio], or a target having a composition ratio of In:Ga:Zn = 1: 1:2 [atomic ratio], In:Ga:Zn = 1:0:1 [atomic ratio] (x = 0, y = 1 ) can also be used as a target having the composition ratio. In this embodiment, since heat treatment is performed later to intentionally crystallize the first oxide semiconductor layer 404, it is preferable to use an oxide semiconductor target in which crystals are likely to form.

[0351] Next, by performing the first heat treatment on the first oxide semiconductor layer 404, at least the region including the surface of the first oxide semiconductor layer 404 is crystallized (see Fig. 29(A)). Also, by performing the first heat treatment on the first oxide semiconductor layer 404, excess water (including hydroxyl groups) and hydrogen in the first oxide semiconductor layer 404 can be removed. The first heat treatment temperature is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, the time of the first heat treatment is 1 minute or more and 24 hours or less.

[0352] In this embodiment, as the first heat treatment, heat treatment is performed at 700°C for 1 hour in a nitrogen atmosphere. After dehydration or dehydrogenation is performed, the atmosphere is switched to an oxygen atmosphere to supply oxygen into the first oxide semiconductor layer 404.

[0353] Regarding other heat treatment conditions, since reference may be made to the first heat treatment in Embodiment 5, detailed description thereof will be omitted.

[0354] By performing the first heat treatment on the first oxide semiconductor layer 404, a non-single crystal region can be formed in at least the region including the surface of the first oxide semiconductor layer 404. The non-single crystal region formed in the region including the surface of the first oxide semiconductor layer 404 extends from the surface to the inside It is formed by crystal growth toward. The non-single crystal region has an average thickness of 2 nm or more and is a plate-like non-single crystal layer with a thickness of 10 nm or less. Further, the non-single crystal region is a region having a non-single crystal layer in which the c-axis is oriented in a direction substantially perpendicular to the surface of the first oxide semiconductor layer 404. Here, "substantially parallel" means a state within ±10° from the parallel direction. Also, "substantially perpendicular" means a state within ±10° from the perpendicular direction.

[0355] Next, a second oxide semiconductor layer 405 is formed on the first oxide semiconductor layer 404 (see FIG. 2 9(B)).

[0356] The second oxide semiconductor layer 405 is, like the first oxide semiconductor layer 404, a quaternary metal oxide such as In-Sn-Ga-Zn-O, or a ternary metal oxide such as In-Ga-Zn- O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, A l-Ga-Zn-O, Sn-Al-Zn-O, or a binary metal oxide such as In-Zn -O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. can be used to form it.

[0357] The second oxide semiconductor layer 405 preferably uses a material having the same main component as the first oxide semiconductor layer 404, or has the same crystal structure and a close lattice constant (mismatch of 1% or less). When using a material with the same main component for the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404, in the second heat treatment performed later, when crystal growth is carried out using the non-single crystal region of the first oxide semiconductor layer 4 04 as a seed, the second oxide semiconductor layer 405 is crystallized ​ It becomes easier to form. Also, when they have the same main component, interfacial physical properties such as the adhesion between the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404, and electrical properties are also good.

[0358] Alternatively, the second oxide semiconductor layer 405 may be formed using a material having a main component different from that of the first oxide semiconductor layer 404. When using materials with different main components, the electrical properties of each layer can be made different. Thus, for example, by using a material with high electrical conductivity for the second oxide semiconductor layer 405 and a material with low electrical conductivity for the first oxide semiconductor layer 404, it is possible to realize a semiconductor device with reduced influence of the underlying interface. Also, by using a material that is easy to crystallize for the first oxide semiconductor layer 404 to form good seed crystals, and then forming and crystallizing the second oxide semiconductor layer 405, the crystallinity of the second oxide semiconductor layer 405 can be improved regardless of its ease of crystallization.

[0359] In this embodiment, the second oxide semiconductor layer 405 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. The film formation of the second oxide semiconductor layer 405 may be performed in the same manner as the film formation of the first oxide semiconductor layer 404. However, the thickness of the second oxide semiconductor layer 405 is preferably made thicker than the thickness of the first oxide semiconductor layer 404. Also, it is preferable to form the second oxide semiconductor layer 405 such that the sum of the thicknesses of the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 is 3 nm or more and 50 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material and application to be used, etc., and thus the thickness may be selected according to the material and application to be used. ​​​​​​​​​​​​​

[0360] Next, a second heat treatment is performed on the second oxide semiconductor layer 405, and crystal growth is performed using the non-single crystal region of the first oxide semiconductor layer 404 as a seed to form a crystallized second oxide semiconductor layer 405 (see Fig. 29(C)). By performing the second heat treatment on the second oxide semiconductor layer 405, crystal growth of the entire second oxide semiconductor layer 405 can be achieved from the non-single crystal region formed at the interface between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405, and a crystallized second oxide semiconductor layer 405 can be formed. Also, by performing the second heat treatment, the first oxide semiconductor layer 404 can be made into a non-single crystal layer having a higher degree of orientation. (See Fig. 29(C)).

[0361] Note that, in the first oxide semiconductor layer 404, the region overlapping with the unevenness of the gate insulating layer 402 has crystal grain boundaries and becomes a non-single crystal. Also, in the second oxide semiconductor layer 405, the region that becomes the channel formation region has at least a flat surface. Further, the region that becomes the channel formation region in the second oxide semiconductor layer 405 includes a non-single crystal having the same C-axis orientation as the first oxide semiconductor layer 404. The height difference on the surface of the second oxide semiconductor layer 405 is preferably 1 nm or less (preferably 0.2 nm or less) in the region overlapping with the gate electrode layer 411 (channel formation region). Also, in the second oxide semiconductor layer 405, the a-axis and b-axis of the non-single crystal in the channel formation region are also shifted. For example, when an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 405, the second oxide semiconductor layer 405 is InGaO3(ZnO).

[0362]

[0363] m ​​​​​​​​​​​​​(m > 0 and m is not a natural number), crystals represented thereby, In2Ga2ZnO7 (In:Ga:Zn:O = 2 :2:1:7), and the like may be included. Such crystals are oriented by the second heat treatment so that their c-axis is substantially perpendicular to the surface of the second oxide semiconductor layer 405.

[0364] Here, the above-described crystals contain any of In, Ga, and Zn and can be regarded as a laminated structure of layers parallel to the a-axis and the b-axis. Specifically, the above-described crystals have a structure in which a layer containing In and a layer not containing In (a layer containing Ga or a layer containing Zn) are laminated in the c-axis direction.

[0365] In the In-Ga-Zn-O-based oxide semiconductor, the conductivity in the directions parallel to the a-axis and the b-axis of the layer containing In is good. This is because in the In-Ga-Zn-O-based oxide semiconductor, electrical conduction is mainly controlled by In, and since one 5s orbital of In overlaps with the 5s orbitals of adjacent In, a carrier path is formed.

[0366] Also, when the first oxide semiconductor layer 404 has an amorphous region at the interface with the gate insulating layer 402, by performing the second heat treatment, crystal growth occurs from the crystal region formed on the surface of the first oxide semiconductor layer 404 toward the lower surface of the first oxide semiconductor layer 404, and the amorphous region may be crystallized. Note that depending on the material constituting the gate insulating layer 402 and the heat treatment conditions, etc., the amorphous region may remain.

[0367] ​​​​​When the same main component oxide semiconductor material is used for the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405, as shown in FIG. 29(C), when the first oxide semiconductor layer 404 is crystal grown upward toward the surface of the second oxide semiconductor layer 405 as the seed of crystal growth, the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 have the same crystal structure. Therefore, although shown by a dotted line in FIG. 29(C), the boundary between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 cannot be discriminated, and the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer. When using the same main component oxide semiconductor material for the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405, as shown in FIG. 29(C), when the first oxide semiconductor layer 404 is crystal grown upward toward the surface of the second oxide semiconductor layer 405 as the seed of crystal growth, the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 have the same crystal structure. Therefore, although shown by a dotted line in FIG. 29(C), the boundary between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 cannot be discriminated, and the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer. the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 have the same crystal structure. Therefore, although shown by a dotted line in FIG. 29(C), the boundary between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 cannot be discriminated, and the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer. the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 have the same crystal structure. Therefore, although shown by a dotted line in FIG. 29(C), the boundary between the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 cannot be discriminated, and the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer. the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer. the first oxide semiconductor layer 404 and the second oxide semiconductor layer 406 may be regarded as the same layer.

[0368] Thus, by performing the second heat treatment, the entire second oxide semiconductor layer 405 can be crystallized from the non-single crystal region formed at the interface between the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404. Also, by performing the second heat treatment, the first oxide semiconductor layer 404 can be made into a non-single crystal layer having a higher orientation. Thus, by performing the second heat treatment, the entire second oxide semiconductor layer 405 can be crystallized from the non-single crystal region formed at the interface between the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404. Also, by performing the second heat treatment, the first oxide semiconductor layer 404 can be made into a non-single crystal layer having a higher orientation. Thus, by performing the second heat treatment, the entire second oxide semiconductor layer 405 can be crystallized from the non-single crystal region formed at the interface between the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404. Also, by performing the second heat treatment, the first oxide semiconductor layer 404 can be made into a non-single crystal layer having a higher orientation. Thus, by performing the second heat treatment, the entire second oxide semiconductor layer 405 can be crystallized from the non-single crystal region formed at the interface between the second oxide semiconductor layer 405 and the first oxide semiconductor layer 404. Also, by performing the second heat treatment, the first oxide semiconductor layer 404 can be made into a non-single crystal layer having a higher orientation.

[0369] The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The time of the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more and 20 hours or less, and typically 10 hours. The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The time of the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more and 20 hours or less, and typically 10 hours. The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The time of the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more and 20 hours or less, and typically 10 hours.

[0370] Also, in the second heat treatment, it is preferable that nitrogen, oxygen, or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher. Also, in ultra-dry air with H2O of 20 ppm or less, Also, in the second heat treatment, it is preferable that nitrogen, oxygen, or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher. Also, in ultra-dry air with H2O of 20 ppm or less, Also, in the second heat treatment, it is preferable that nitrogen, oxygen, or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher. Also, in ultra-dry air with H2O of 20 ppm or less, Also, in the second heat treatment, it is preferable that nitrogen, oxygen, or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher. Also, in ultra-dry air with H2O of 20 ppm or less, Preferably, the second heat treatment may be performed in ultra-dry air with H2O of 1 ppm or less. . By such a second heat treatment, water (including hydroxyl groups) and hydrogen in the second oxide semiconductor layer 405 can be removed. Therefore, impurities are reduced and the purity is increased, and the first oxide semiconductor layer 404 and the second oxide semiconductor layer 405 which are i-type or substantially i-type can be formed.

[0371] Also, when raising the temperature of the second heat treatment, the inside of the furnace may be set to a nitrogen atmosphere, and when cooling, the atmosphere may be switched to an oxygen atmosphere. After dehydration or dehydrogenation is performed in a nitrogen atmosphere , by switching the atmosphere to an oxygen atmosphere, oxygen can be supplied to the inside of the second oxide semiconductor layer 405.

[0372] For the heat treatment apparatus used for the second heat treatment, the heat treatment apparatus of Embodiment 5 may be referred to, and detailed description will be omitted.

[0373] For the subsequent steps, Embodiment 5 (Figs. 15(B) to (D)) may be referred to.

[0374] As described above, the transistor 450 using the oxide semiconductor layer 406a is completed (refer to Fig. 29( D)).

[0375] As described above, by forming a non-single crystal region in the oxide semiconductor layer 406a, the mobility of the transistor can be improved. Thus, by applying the transistor with improved mobility to a circuit that requires high speed operation, the driving ability of the circuit can be improved.

[0376] The transistor shown in this embodiment is applied to the semiconductor devices shown in Embodiments 1 to 3. By applying it, the driving ability of the semiconductor device can be improved.

[0377] Also, the transistor shown in this embodiment and the transistor shown in Embodiment 5 can be combined and applied to the semiconductor devices shown in Embodiments 1 to 4.

Explanation of Reference Numerals

[0378] 101 Transistor 102 Transistor 103 Transistor 104 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 121 Capacitor Element 130 Circuit 131 Circuit 132 Circuit 133 Circuit 134 Circuit 140 Protection Circuit 141 Transistor 142 Transistor 201 NOR Circuit 202 NAND Circuit 203 Inverter Circuit 211 Wiring 212 Wiring 213 Wiring 400 Substrate 402 Gate Insulating Layer 404 Oxide Semiconductor Layer 405 Oxide Semiconductor Layer 406 Oxide Semiconductor Layer 406a Oxide Semiconductor Layer 408a Source Electrode Layer and Drain Electrode Layer 408b Source Electrode Layer and Drain Electrode Layer 411 Gate Electrode Layer 412 Insulating Layer 418 Insulating Layer 450 transistors 111A wiring 111B wiring 5000 housing 5001 display unit 5002 display unit 5003 speaker 5004 LED lamp 5005 operation key 5006 connection terminal 5007 sensor 5008 microphone 5009 switch 5010 infrared port 5011 recording medium reading section 5014 antenna 5015 shutter button 5016 image receiving section 5017 charger 5018 support stand 5019 external connection port 5020 pointing device 5021 reader / writer 5022 housing 5023 display unit 5024 remote control device 5025 speaker 5026 display panel 5027 unit bus 5028 display panel 5029 vehicle body 5030 ceiling 5031 display panel 5032 hinge part 5033 light source 5034 projection lens 5354 pixel section 5360 video signal 5361 circuit 5362 circuit 5363 circuit 5364 pixel section 5365 circuit 5366 lighting device 5367 pixel 5371 Wiring 5372 Wiring 5380 Substrate 5381 Input Terminal 5450 Pixel 5451 Transistor 5452 Capacitive Element 5453 Display Element 5454 Electrode 5455 Electrode 5461 Wiring 5462 Wiring 5463 Wiring 5480 Microcapsule 5481 Resin 5482 Film 5483 Liquid 5484 Particle 5485 Particle 5486 Twist Ball 5487 Particle 5488 Cavity 5491 Microcup 5492 Dielectric Solvent 5493 Charged Dye Particle 5494 Sealing Layer 5495 Adhesive Layer 5502 Electron Ink Fluid (Registered Trademark) 5503 Electron Ink Fluid (Registered Trademark) 5504 Partition Wall 5361a Circuit 5361b Circuit 5362a Circuit 5362b Circuit

Claims

1. A multi-stage circuit is provided. Each of the multiple stages of circuits includes a first transistor to an eighth transistor, In at least one of the multiple stages of circuits, One of the source and the drain of the first transistor is always electrically connected to a first wiring, the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring, the other of the source and the drain of the second transistor is always electrically connected to a third wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of a source and a drain of the fourth transistor is always electrically connected to the first wiring, the other of the source and the drain of the fourth transistor is always electrically connected to the third wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; a gate of the seventh transistor is always electrically connected to a gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eighth transistor is always electrically connected to a fourth wiring; the gate of the eighth transistor is always electrically connected to the fourth wiring; the first wiring has a function of outputting a first signal; the second wiring has a function as a clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function of inputting a second signal; a gate of the second transistor and a gate of the third transistor are always electrically connected to a gate of the second transistor and a gate of the third transistor included in another circuit among the multiple stages of circuits. Semiconductor device.

2. A multi-stage circuit is provided. Each of the multiple stages of circuits includes a first transistor to an eighth transistor, In at least one of the multiple stages of circuits, One of the source and the drain of the first transistor is always electrically connected to a first wiring, the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring, the other of the source and the drain of the second transistor is always electrically connected to a third wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to the third wiring; a gate of the third transistor is always electrically connected to a gate of the second transistor; one of a source and a drain of the fourth transistor is always electrically connected to the first wiring, the other of the source and the drain of the fourth transistor is always electrically connected to the third wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring, the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; a gate of the seventh transistor is always electrically connected to a gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the eighth transistor is always electrically connected to a fourth wiring; the gate of the eighth transistor is always electrically connected to the fourth wiring; the first wiring has a function of outputting a first signal; the second wiring has a function as a clock signal line, The third wiring has a function as a power supply line, the fourth wiring has a function of inputting a second signal; a third signal is input to a gate of the second transistor and a gate of the third transistor; a fourth signal is input to a gate of the fourth transistor and a gate of the fifth transistor; a fifth signal is input to a gate of the fifth transistor and a gate of the sixth transistor; a gate of the second transistor and a gate of the third transistor are always electrically connected to a gate of the second transistor and a gate of the third transistor included in another circuit among the multiple stages of circuits. Semiconductor device.

3. In claim 1 or 2, At least one of the second transistor, the fourth transistor, and the sixth transistor has a channel width larger than each of the third transistor, the fifth transistor, and the seventh transistor. Semiconductor device.

4. In any one of claims 1 to 3, each of the first to eighth transistors includes a channel formation region in an oxide semiconductor film; Semiconductor device.

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