Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and a calculation circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer containing metal oxide in a channel formation region. The calculation circuit includes a third transistor. The third transistor includes a semiconductor layer containing silicon in the channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided on a layer including the third transistor. The layer including the second transistor is provided on the layer including the first transistor. The first memory circuit has a data holding characteristic different from that of the second memory circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

Background Art

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like have become widespread. In such electronic devices, in order to process a large amount of data at high speed, technical development regarding performance improvement of semiconductor devices is active. As a technique for realizing higher performance, for example, there is a so-called SoC (System on Chip) in which an accelerator such as a GPU (Graphics Processing Unit) and a CPU are tightly coupled. In semiconductor devices with improved performance by SoC, heat generation and increased power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, since the amount of computation and the number of parameters become extremely large, the amount of operation increases. The increase in the amount of operation is a factor that increases heat generation and power consumption. Therefore, architectures for reducing the amount of operation have been actively proposed. Representative architectures include Binary Neural Network (BNN) and Ternary Neural Network (TNN), which are particularly effective for reducing circuit scale and power consumption (see, for example, Patent Document 1). For example, in BNN, data originally represented with 32-bit or 16-bit precision can be compressed into two values of "+1" or "-1", significantly reducing the amount of computation and the number of parameters. Since BNN is effective in reducing circuit scale and power consumption, it is considered to be compatible with applications that require low power consumption in limited hardware resources such as embedded chips.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] When performing arithmetic processing of AI technology using an accelerator, the weight data used in the arithmetic is transmitted to the accelerator at high speed from a chip manufactured by a process different from that of the accelerator such as DRAM or SRAM. In order to reduce the data transfer frequency, a large amount of storage capacity for holding weight data or intermediate data is required on the accelerator side. If the storage capacity of the accelerator is small, high-speed data transfer is required. Furthermore, if the distance from the chip storing the weight data is large, the parasitic capacitance or resistance of the wiring increases, resulting in a possible increase in power consumption.

[0007] One aspect of the present invention aims to reduce power consumption in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention aims to suppress heat generation in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention aims to miniaturize a semiconductor device equipped with an accelerator. Or, one aspect of the present invention aims to reduce the number of data transfers between a semiconductor device that functions as a CPU and a semiconductor device that functions as a memory in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention aims to improve the data transfer speed between a semiconductor device that functions as a storage memory and a semiconductor device that functions as a cache memory in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention aims to provide a semiconductor device with a novel configuration.

[0008] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will become apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0009] One aspect of the present invention has a CPU and an accelerator. The accelerator has a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit has a first transistor, the second memory circuit has a second transistor, and the first transistor and the second transistor each have a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit has a third transistor, and the third transistor has a semiconductor layer having silicon in a channel formation region. The CPU has a CPU core having a flip-flop provided with a backup circuit. The backup circuit has a fourth transistor, and the fourth transistor has a semiconductor layer having a metal oxide in a channel formation region. The first transistor and the second transistor are provided in different layers, and the layer having the first transistor and the layer having the second transistor are provided on the layer having the third transistor. It is a semiconductor device.

[0010] In one aspect of the present invention, it is preferable that the backup circuit has a function of holding the data held in the flip-flop in a state where the supply of the power supply voltage is stopped when the CPU is in power gating.

[0011] In one aspect of the present invention, it is preferable that the first memory circuit and the second memory circuit have a function of holding the data input to the arithmetic circuit.

[0012] In one aspect of the present invention, it is preferable that the second memory circuit has a circuit configuration different from that of the first memory circuit.

[0013] One aspect of the present invention has a CPU and an accelerator. The accelerator has a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit has a first transistor, the second memory circuit has a second transistor, and the first transistor and the second transistor each have a semiconductor layer having a metal oxide in a channel formation region. The arithmetic circuit has a third transistor, and the third transistor has a semiconductor layer having silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer having the first transistor is provided on the layer having the third transistor, and the layer having the second transistor is provided on the layer having the first transistor. The first memory circuit has data retention characteristics different from those of the second memory circuit, and is a semiconductor device.

[0014] In one aspect of the present invention, it is preferable that the semiconductor device has a function of holding data input to the arithmetic circuit or data output from the arithmetic circuit in the first memory circuit.

[0015] In one aspect of the present invention, it is preferable that the amplitude voltage for driving the first transistor is smaller than the amplitude voltage for driving the second transistor.

[0016] In one aspect of the present invention, it is preferable that the film thickness of the gate insulating film of the first transistor is smaller than the film thickness of the gate insulating film of the second transistor.

[0017] In one aspect of the present invention, it is preferable that the second memory circuit has a circuit configuration different from that of the first memory circuit.

[0018] In one aspect of the present invention, it is preferable that the arithmetic circuit is a circuit that performs a multiply-accumulate operation.

[0019] In one aspect of the present invention, it is preferable that the metal oxide contains In, Ga, and Zn.

[0020] For other aspects of the present invention, they are described in the embodiments described below and in the drawings.

Advantages of the Invention

[0021] One aspect of the present invention can reduce power consumption in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention can suppress heat generation in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention can miniaturize a semiconductor device equipped with an accelerator. Or, one aspect of the present invention can reduce the number of data transfers between a semiconductor device that functions as a CPU and a semiconductor device that functions as a memory in a semiconductor device equipped with an accelerator. Or, one aspect of the present invention can improve the data transfer speed between a semiconductor device that functions as a storage memory and a semiconductor device that functions as a cache memory in a semiconductor device equipped with an accelerator. Or, a semiconductor device with a novel configuration can be provided.

[0022] The description of multiple effects does not prevent the existence of other effects. Also, one form of the present invention does not necessarily have to have all of the exemplified effects. Also, for one form of the present invention, other problems, effects, and novel features will become apparent from the description and drawings in this specification.

Brief Description of the Drawings

[0023]

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Embodiments for Carrying Out the Invention

[0024] Embodiments of the present invention will be described below. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0025] In the present specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of the present specification and the like, a component referred to as "first" may be a component referred to as "second" in other embodiments or in the claims. For another example, in one of the embodiments of the present specification and the like, a component referred to as "first" may be omitted in other embodiments or in the claims.

[0026] In the drawings, the same reference numerals may be given to the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously, and repeated explanations thereof may be omitted.

[0027] In the present specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0028] Also, when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, identification symbols such as "_1", "_2", "[n]", "[m,n]" may be appended to the reference numeral for description. For example, the second wiring GL is described as wiring GL[2].

[0029] (Embodiment 1) The configuration, operation, etc. of a semiconductor device which is one aspect of the present invention will be described.

[0030] Note that in the present specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. It can be said that display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. have semiconductor devices.

[0031] FIGS. 1A and 1B are diagrams for explaining a semiconductor device 100 which is an aspect of the present invention. The semiconductor device 100 includes a CPU 10, an accelerator 20, and a bus 30. The accelerator 20 includes an arithmetic processing unit 21 and a memory unit 22. The arithmetic processing unit 21 includes an arithmetic circuit 23. The memory unit 22 includes a memory circuit 24. The memory unit 22 may be a device memory or a shared memory. The memory circuit 24 includes a transistor 25 having a semiconductor layer 29 with a channel formation region. The arithmetic circuit 23 and the memory circuit 24 are electrically connected via a wiring 31.

[0032] The CPU 10 has a function of performing general-purpose processing such as execution of an operating system, control of data, execution of various operations and programs. The CPU 10 includes one or more CPU cores. The CPU 10 includes, for example, a transistor (Si transistor) having silicon in a channel formation region. By making the Si transistor a complementary transistor, a CMOS circuit (SiCMOS) can be formed. The CPU 10 is connected via the accelerator 20 and the bus 30.

[0033] Each of the CPU cores preferably has a configuration including a data holding circuit capable of holding data even when the supply of a power voltage is stopped. With this configuration, the supply of the power voltage can be controlled by electrical disconnection by a power switch or the like from a power domain (power domain). Note that the power voltage may be referred to as a drive voltage. As the data holding circuit, for example, a memory including a transistor (OS transistor) having an oxide semiconductor in a channel formation region is suitable. The configuration of the CPU core including the data holding circuit having the OS transistor will be described in Embodiment 3.

[0034] The accelerator 20 has a function of executing a program (also called a kernel or a kernel program) called from a host program. The accelerator 20 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations of neural networks, parallel processing of floating-point operations in scientific and technical calculations, and the like.

[0035] The memory unit 22 has a function of storing data processed by the accelerator 20. Specifically, it can store data such as weight data used for parallel processing of product-sum operations of neural networks, data input to or output from the arithmetic processing unit 21.

[0036] The memory unit 22 is provided over a plurality of memory circuit layers 22_1 to 22_N (N is a natural number of 2 or more). Each of the plurality of memory circuit layers 22_1 to 22_N has a memory circuit 24. The memory circuit 24 of each layer included in the plurality of memory circuit layers 22_1 to 22_N is electrically connected to the arithmetic circuit 23 included in the arithmetic processing unit 21 via a wiring 31 and has a function of holding a binary or ternary digital value. In the memory circuit 24, the semiconductor layer 29 included in the transistor 25 is an oxide semiconductor. That is, the transistor 25 is an OS transistor. The memory circuit 24 is preferably a memory having an OS transistor (hereinafter also referred to as an OS memory).

[0037] Since the bandgap of the metal oxide is 2.5 eV or more, the OS transistor has an extremely small off-current. As an example, when the voltage between the source and the drain is 3.5 V and at room temperature (25 °C), the off-current per channel width of 1 μm is less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24It can be less than A. That is, the on / off current ratio of the drain current can be 20 digits or more and 150 digits or less. Therefore, the amount of charge leaking from the holding node to the OS memory via the OS transistor is extremely small. Accordingly, the OS memory can function as a non-volatile memory circuit. Also, power gating of the accelerator becomes possible.

[0038] In a highly integrated semiconductor device, heat may be generated due to the driving of the circuit. Due to this heat generation, when the temperature of the transistor rises, the characteristics of the transistor may change, and changes in the field-effect mobility or a decrease in the operating frequency may occur. Since the OS transistor has higher heat resistance than the Si transistor, changes in the field-effect mobility due to temperature changes are less likely to occur, and a decrease in the operating frequency is also less likely to occur. Furthermore, the OS transistor is likely to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage even when the temperature rises. Therefore, by using the OS transistor, stable operation in a high-temperature environment can be achieved.

[0039] Metal oxides applied to the OS transistor include zinc oxide, zinc-tin oxide, gallium-tin oxide, indium-gallium oxide, indium-zinc oxide, indium-M-zinc oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), etc. In particular, when a metal oxide using Ga as M is adopted for the OS transistor, it is preferable because a transistor excellent in electrical characteristics such as field-effect mobility can be obtained by adjusting the ratio of the elements. Also, the oxide containing indium and zinc may contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0040] For improving the reliability and electrical characteristics of the OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal part such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0041] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. Note that the strain refers to a location where the orientation of the lattice array changes between a region where the lattice arrays are aligned and another region where the lattice arrays are aligned in the region where the plurality of nanocrystals are connected.

[0042] CAC-OS has a function of allowing carriers (electrons or holes) to flow and a function of not allowing carriers (electrons) to flow. By separating the function of allowing electrons to flow and the function of not allowing electrons to flow, both functions can be maximally enhanced. That is, by using CAC-OS in the channel formation region of the OS transistor, both a high on-current and an extremely low off-current can be realized.

[0043] Due to the large bandgap of the metal oxide and the difficulty of exciting electrons, and the large effective mass of holes, etc., the OS transistor may be less likely to cause avalanche breakdown, etc., compared to a general Si transistor. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. By being able to suppress hot carrier degradation, the OS transistor can be driven at a high drain voltage.

[0044] The OS transistor is an accumulation-type transistor with electrons as majority carriers. Therefore, compared with an inversion-type transistor having a pn junction (typically, a Si transistor), the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short-channel effects, is small. That is, the OS transistor has higher resistance to the short-channel effect than the Si transistor.

[0045] Since the OS transistor has high resistance to the short-channel effect, the channel length can be reduced without degrading the reliability of the OS transistor. Therefore, the integration degree of the circuit can be increased by using the OS transistor. As the channel length is miniaturized, the drain electric field becomes stronger. However, as described above, the OS transistor is less likely to cause avalanche breakdown than the Si transistor.

[0046] In addition, since the OS transistor has high resistance to the short-channel effect, it is possible to make the gate insulating film thicker than that of the Si transistor. For example, even in a fine transistor with a channel length and a channel width of 50 nm or less, it may be possible to provide a gate insulating film about 10 nm thick. By making the gate insulating film thicker, the parasitic capacitance can be reduced, so that the operating speed of the circuit can be improved. Also, by making the gate insulating film thicker, the leakage current through the gate insulating film is reduced, leading to a reduction in the static power consumption.

[0047] From the above, the accelerator 20 has the memory circuit 24 which is an OS memory, so that data can be retained even when the supply of the power voltage is stopped. Therefore, power gating of the accelerator 20 becomes possible, and a significant reduction in power consumption can be achieved.

[0048] The memory circuit 24 composed of OS transistors can be provided in a stacked manner with the arithmetic circuit 23 that can be composed of Si CMOS. That is, the plurality of memory circuit layers 22_1 to 22_N are provided on the substrate on which the arithmetic processing unit 21 is provided. The plurality of memory circuit layers 22_1 to 22_N can be provided by being stacked respectively. Therefore, it can be arranged without causing an increase in the circuit area, and the storage capacity required for the arithmetic processing in the accelerator 20 can be increased. Since the number of transfers of data required for arithmetic processing can be reduced, power consumption can be reduced. The memory circuit layers 22_1 to 22_N having a plurality of memory circuits 24 are electrically connected to the arithmetic circuit 23 via wirings 31 that extend in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 23 is provided (the z direction perpendicular to the xy plane in FIG. 1B). Note that "substantially perpendicular" means a state of being arranged at an angle of 85 degrees or more and 95 degrees or less.

[0049] Although the OS transistor is cited as an example of the transistor included in the memory circuit 24, any transistor that can be stacked with the Si transistor included in the lower arithmetic circuit 23 may be used. For example, an Si transistor stacked on a substrate having an Si transistor using a bonding technique or the like can also be used as the upper transistor. In this case, it is preferable that the Si transistor provided in the upper layer has a longer channel length than the Si transistor in the lower layer so that the off-current becomes small.

[0050] The memory circuit 24 included in the accelerator 20 may be a single layer in addition to the stacked configuration such as the plurality of memory circuit layers 22_1 to 22_N. The single memory circuit layer 22_1 having an OS transistor can be provided in a stacked manner with the arithmetic circuit 23 that can be composed of Si CMOS. Therefore, by reducing the physical distance between the arithmetic circuit 23 and the memory circuit 24, the wiring distance can be shortened, the parasitic capacitance generated in the signal line can be reduced, and power consumption can be reduced.

[0051] In the accelerator 20, by adopting a configuration in which transistors are stacked, an increase in the circuit area can be suppressed, so that the number of arithmetic circuits 23 can be increased and arranged. Since the number of circuits (core number) performing arithmetic operations in the arithmetic circuit 23 can be increased, the frequency of the signal for driving the arithmetic circuit 23 can be lowered. Also, the power supply voltage for driving the arithmetic circuit 23 can be reduced. As a result, the power consumption required for arithmetic operations can be reduced at a rate such as one tenth.

[0052] The memory circuit 24 can have a circuit configuration of NOSRAM. "NOSRAM (registered trademark)" is an abbreviation of "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which memory cells are 2-transistor type (2T) or 3-transistor type (3T) gain cells and access transistors are OS transistors. The memory circuit 24 can be provided by stacking each layer of the memory circuit layers 22_1 to 22_N using OS transistors. Also, the OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, leakage current. NOSRAM can be used as a non-volatile memory by holding charges corresponding to data in the memory circuit using the characteristic of extremely small leakage current. In particular, since NOSRAM can read the held data without destroying it (non-destructive readout), it is suitable for parallel processing of the sum-of-products operation of neural networks that repeatedly perform a large number of only data readout operations.

[0053] The arithmetic processing unit 21 has a function of performing arithmetic processing using digital values. Digital values are less affected by noise. Therefore, the accelerator 20 is suitable for performing arithmetic processing that requires high-precision arithmetic results. Note that the arithmetic processing unit 21 is preferably composed of Si CMOS, that is, transistors having silicon in the channel formation region (Si transistors). By adopting such a configuration, it can be provided stacked with the OS transistor.

[0054] The arithmetic circuit 23 has a function of performing any one of processes such as integer arithmetic, single-precision floating-point arithmetic, and double-precision floating-point arithmetic using the data of digital values held in each of the memory circuits 24 of the plurality of memory circuit layers 22_1 to 22_N. The arithmetic circuit 23 has a function of repeatedly executing the same process such as a multiply-accumulate operation.

[0055] Note that the arithmetic circuit 23 is configured such that one arithmetic circuit 23 is provided for each read bit line of the memory circuit 24, that is, for each column (Column-Parallel Calculation). With this configuration, data for one row (maximum all bit lines) of the memory circuit 24 can be processed in parallel. Compared with the multiply-accumulate operation using the CPU 10, since it is not limited by the data bus size (such as 32 bits) between the CPU and the memory, in Column-Parallel Calculation, the degree of parallelism of the operation can be significantly increased, so that it is possible to improve the operation efficiency related to huge operation processes such as learning of a deep neural network (deep learning), which is an AI technology, and scientific and technical calculations that perform floating-point arithmetic. In addition, since the operation of the data output from the memory circuit 24 can be completed and read out, the power generated by memory access (data transfer between the CPU and the memory and operation by the CPU) can be reduced, and an increase in heat generation and power consumption can be suppressed. Furthermore, by reducing the physical distance between the arithmetic circuit 23 and the memory circuit 24, for example, the wiring distance can be shortened by stacking, the parasitic capacitance generated in the signal line can be reduced, so that low power consumption is possible.

[0056] The multiply-accumulate operation in the inference process requires a large amount of data and thus a huge bandwidth (data transfer rate). By arranging a plurality of memory circuit layers 22_1 to 22_N on the arithmetic circuit 23 as in the configuration of FIG. 1B, a wide bandwidth can be ensured. In addition, since the distance between circuits can be reduced, the transfer speed of a plurality of data can be increased. Therefore, the power consumption required for the multiply-accumulate operation in the inference process can be reduced at a rate such as one-tenth.

[0057] Note that the inference process based on the deep neural network is optimized for data with a bit width of preferably 32 bits or less, more preferably 16 bits or less, and even more preferably 8 bits or less, rather than operations using data with a large bit width such as 64 bits. By doing so, it is possible to reduce power consumption without degrading the operation accuracy.

[0058] The bus 30 electrically connects the CPU 10 and the accelerator 20. That is, the CPU 10 and the accelerator 20 can perform data transmission via the bus 30.

[0059] FIG. 2A is a diagram schematically showing the reading of data from the memory circuit 24 to the arithmetic circuit 23 in the stacked plurality of memory circuit layers 22_1 to 22_N in the accelerator 20 shown in FIG. 1B. In FIG. 2A, the arrows represent the movement of data. As shown in FIG. 2A, the semiconductor device according to one aspect of the present invention can read data from the memory circuit 24 included in the plurality of stacked memory circuit layers 22_1 to 22_N via the wiring 31. Since the physical distance between the arithmetic circuit 23 and the memory circuit 24 in the stacked positional relationship is very close, the wiring distance is short. Therefore, the parasitic capacitance generated in the wiring 31 can be reduced, and thus power consumption can be reduced.

[0060] Note that as the number of the stacked plurality of memory circuit layers 22_1 to 22_N increases, the parasitic capacitance generated in the wiring 31 increases. Therefore, it is preferable to provide switches SW_1 to SW_N in each of the memory circuit layers 22_1 to 22_N between the wiring to which the memory circuit 24 is connected, for example, the read bit line, and the wiring 31. The switches SW_1 to SW_N are configured to be turned off in the memory circuit layers 22_1 to 22_N that do not read data and turned on in the memory circuit layers 22_1 to 22_N that read data. With this configuration, the parasitic capacitance of the wiring 31 associated with an increase in the number of the memory circuit layers 22_1 to 22_N can be reduced, and thus power consumption can be reduced.

[0061] Also, in each of the plurality of stacked memory circuit layers 22_1 to 22_N, the number of memory circuits 24 may be varied by varying the circuit layout, channel length of transistors, channel width, or transistor density. For example, as shown in FIG. 3A, the memory circuit 24 in the lower layer (e.g., memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N may have a circuit layout with a higher transistor density, and the circuit layout may have a lower transistor density as it goes up to the upper layer (z direction in the figure). With this configuration, the number of memory circuits with a short physical distance from the arithmetic circuit 23 can be increased, and the data retention characteristics of the memory circuit 24 in the upper layer can be improved.

[0062] Alternatively, as shown in FIG. 3B, the memory circuit 24 in the upper layer (e.g., memory circuit layer 22_N) of the memory circuit layers 22_1 to 22_N may have a circuit layout with a higher transistor density, and the circuit layout may have a lower transistor density as it goes down to the lower layer (the side of the memory circuit layer 22_1 in the figure). With this configuration, the data retention characteristics of the memory circuit with a short physical distance from the arithmetic circuit 23 can be improved, and the data density can be increased.

[0063] One aspect of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator such as AI technology with a huge amount of computation and a large number of parameters. Or, one aspect of the present invention can miniaturize a semiconductor device that functions as an accelerator such as AI technology with a huge amount of computation and a large number of parameters. Or, one aspect of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator such as AI technology with a huge amount of computation and a large number of parameters. Or, one aspect of the present invention can reduce the number of data transfers between a semiconductor device that functions as an accelerator such as AI technology with a huge amount of computation and a large number of parameters and a semiconductor device that functions as a CPU and a memory. In other words, a semiconductor device that functions as an accelerator such as AI technology with a huge amount of computation and a large number of parameters has a non-Neumann architecture and can perform parallel processing with extremely low power consumption compared to a Neumann architecture in which power consumption increases as the processing speed increases.

[0064] FIG. 4A is a diagram for explaining an example of a circuit configuration applicable to each of the memory circuit layers 22_1 to 22_N included in the semiconductor device 100 of the present invention. In FIG. 4A, write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and read bit lines RBL_1 to RBL_N arranged in a matrix direction of M rows and N columns (M and N are natural numbers of 2 or more) are illustrated. Also, memory circuits 24 connected to each word line and bit line are illustrated.

[0065] FIG. 4B is a diagram for explaining an example of a circuit configuration applicable to the memory circuit 24. The memory circuit 24 includes a transistor 25, a transistor 26, a transistor 27, and a capacitor element 28 (also referred to as a capacitor).

[0066] One of the source or drain of the transistor 25 is connected to the write bit line WBL. The gate of the transistor 25 is connected to the write word line WWL. The other of the source or drain of the transistor 25 is connected to one electrode of the capacitor element 28 and the gate of the transistor 26. One of the source or drain of the transistor 26 and the other electrode of the capacitor element 28 are connected to a wiring that provides a fixed potential, for example, a ground potential. The other of the source or drain of the transistor 26 is connected to one of the source or drain of the transistor 27. The gate of the transistor 27 is connected to the read word line RWL. The other of the source or drain of the transistor 27 is connected to the read bit line RBL. The read bit line RBL is connected to the arithmetic circuit 23 via a wiring 31 or the like that extends in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 23 is provided, as described above.

[0067] The circuit configuration of the memory circuit 24 shown in FIG. 4B corresponds to a NOSRAM of a 3-transistor type (3T) gain cell. The transistors 25 to 27 are OS transistors. The OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, a leakage current. The NOSRAM can be used as a non-volatile memory by holding charges corresponding to data in the memory circuit using the characteristic of an extremely small leakage current.

[0068] The circuit configuration applicable to the memory circuit 24 in FIG. 4A is not limited to the 3T-type NOSRAM in FIG. 4B. For example, a circuit corresponding to the DOSRAM shown in FIG. 5A may be used. Note that DOSRAM is a RAM having a 1T1C-type memory cell and is an abbreviation for Dynamic Oxide Semiconductor RAM. In FIG. 5A, a memory circuit 24A having a transistor 25A and a capacitor element 28A is illustrated. The transistor 25A is an OS transistor. The memory circuit 24A is illustrated as an example connected to a bit line BL, a word line WL, and a back gate line BGL.

[0069] The circuit configuration applicable to the memory circuit 24 in FIG. 4A may also be a circuit corresponding to the 2T-type NOSRAM illustrated in FIG. 5B. In FIG. 5B, a memory circuit 24B having a transistor 25B, a transistor 26B, and a capacitor element 28B is illustrated. The transistor 25B and the transistor 26B are OS transistors. The transistor 25B and the transistor 26B may be OS transistors in which semiconductor layers are disposed in different layers, or may be OS transistors in which semiconductor layers are disposed in the same layer. The memory circuit 24B is illustrated as an example connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0070] The circuit configuration applicable to the memory circuit 24 in FIG. 4A may also be a circuit combining the 3T-type NOSRAM illustrated in FIG. 5C. In FIG. 5B, a memory circuit 24C having a memory circuit 24_P capable of holding different logical data and a memory circuit 24_N is illustrated. In FIG. 5B, a memory circuit 24_P having a transistor 25_P, a transistor 26_P, a transistor 27_P, and a capacitor element 28_P and a memory circuit 24_N having a transistor 25_N, a transistor 26_N, a transistor 27_N, and a capacitor element 28_N are illustrated. Each transistor included in the memory circuit 24_P and the memory circuit 24_N is an OS transistor. Each transistor included in the memory circuit 24_P and the memory circuit 24_N may be an OS transistor in which semiconductor layers are disposed in different layers, or may be an OS transistor in which semiconductor layers are disposed in the same layer. The memory circuit 24C is illustrated as an example connected to a write bit line WBL_P, a read bit line RBL_P, a write bit line WBL_N, a read bit line RBL_N, a write word line WWL, and a read word line RWL. The memory circuit 24C can read out data at high speed by holding different logical data, reading the different logical data out to the read bit line RBL_P and the write bit line WBL_N, and amplifying the data by a sense amplifier or the like.

[0071] In the configuration of FIG. 5C, an exclusive OR circuit (XOR circuit) may be provided so that data corresponding to the multiplication of the data held in the memory circuit 24_P and the memory circuit 24_N is output to the read bit line RBL. With this configuration, the operation corresponding to multiplication in the arithmetic circuit 23 can be omitted, so that power consumption can be reduced.

[0072] The circuit configuration applicable to the memory circuit 24 in FIG. 4A may be a NAND-type memory circuit having a charge storage layer such as a MONOS type shown in FIG. 5D. FIG. 5D shows a memory circuit 24D having transistors 32[1] to 32[n], transistors SW1, and SW2. The transistors 32[1] to 32[n], the transistors SW1, and SW2 are OS transistors. The transistors 32[1] to 32[n], the transistors SW1, and SW2 may be OS transistors having semiconductor layers provided in the same layer, or may be OS transistors having semiconductor layers provided in different layers. The transistors 32[1] to 32[n] have a configuration including a control gate electrode and a charge storage layer or a floating gate electrode.

[0073] The transistors 32[1] to 32[n] in FIG. 5D may be a string type (also called a macaroni type) NAND-type memory in which openings are provided in a laminate in which a conductive layer and an insulating layer are alternately laminated, and a conductor, an insulator, a semiconductor, etc. are stacked concentrically on the inner wall of the opening. FIG. 5D shows an example in which the transistors 32[1] to 32[n] are connected to word lines WL[1] to WL[n] and back gate lines BGL[1] to BGL[n], and the transistors SW1 and SW2 are connected to control lines SEL1 and SEL2, read bit lines, and a source line SL.

[0074] The circuit configuration applicable to the memory circuit 24 in FIG. 4A may also be a NAND-type memory circuit combined with the NOSRAM illustrated in FIG. 5E. In FIG. 5E, a memory circuit 24E having transistors 25[1] to 25[n], transistors 26[1] to 26[n], transistors SW1, and SW2 is illustrated. The transistors 25[1] to 25[n], the transistors 26[1] to 26[n], the transistors SW1, and SW2 are OS transistors. The transistors 25[1] to 25[n], the transistors 26[1] to 26[n], the transistors SW1, and SW2 may be OS transistors having semiconductor layers provided in the same layer, or may be OS transistors having semiconductor layers provided in different layers. In the circuit composed of the transistors 25[1] to 25[n] and the transistors 26[1] to 26[n], nodes ND[1] to ND[n] for holding charges corresponding to data are provided by turning off the transistors 25[1] to 25[n].

[0075] In FIG. 5E, the transistors 25[1] to 25[n] and the transistors 26[1] to 26[n] may be NAND-type memories of a vertical channel type (also called a macaroni type) in which openings are provided in a laminate in which a conductive layer and an insulating layer are alternately laminated, and a conductor, an insulator, a semiconductor, etc. are provided concentrically on the inner wall of the opening. Note that a NAND-type memory composed of OS transistors that can be manufactured on a layer having Si transistors has, in addition to the function as a storage memory, a function as a main memory and can be called a universal memory. By having the function of a main memory such as a DRAM (Dynamic RAM) provided as a separate chip, it may be possible to construct a computer system that does not require a DRAM. FIG. shows an example in which the transistors 25[1] to 25[n] are connected to the word lines WL[1] to WL[n], respectively, and the transistors 26[1] to 26[n] are connected to the nodes ND[1] to ND[n], which are data holding nodes of the NOSRAM, respectively. FIG. also shows an example in which the transistors SW1 and SW2 are connected to the control lines SEL1 and SEL2, the read bit line RBL, and the source line SL.

[0076] Also, the circuit configurations of the memory circuits applicable to each of the memory circuit layers 22_1 to 22_N included in the semiconductor device 100 of the present invention may be different for each layer. For example, as shown in FIG. 6A, the memory circuit in the lower layer (for example, the memory circuit layer 22_1) of the memory circuit layers 22_1 to 22_N is defined as the memory circuit 24A, and the memory circuit in the upper layer (for example, the memory circuit layer 22_2, the memory circuit layer 22_N) is defined as the memory circuit 24B. The memory circuit 24A, which is physically close to the arithmetic circuit 23, may apply the circuit configuration of the NOSRAM, and the memory circuit 24B may apply other circuit configurations such as a DOSRAM and a NAND-type memory.

[0077] Regarding a configuration different from FIG. 6A, in the configuration illustrated in FIG. 6B, the memory circuit 24N of the universal memory with a vertical channel type memory circuit in the upper layer (for example, memory circuit layers 22_2 to 22_N) is used. The memory circuit 24A close to the arithmetic circuit 23 in terms of physical distance can apply the circuit configuration of NOSRAM. The memory circuit 24N is a universal memory with a vertical channel type having a high storage density, so that an external memory such as DRAM can be omitted. In addition, by causing NOSRAM, which has a higher write speed and read speed than the universal memory, to hold data necessary for arithmetic processing, arithmetic processing can be performed at high speed. With such a configuration, since the data held in the universal memory (memory circuit 24N) can be arithmetically processed via NOSRAM (memory circuit 24A), in the semiconductor device 100, the storage capacity of data used for arithmetic processing can be significantly increased. In addition, the gap in delay time required for data reading and writing can be alleviated.

[0078] Generally, in a semiconductor device such as a computer, various storage devices are used according to the application. FIG. 7A shows various storage devices used in a semiconductor device by layer. A storage device located in the upper layer is required to have a faster operating speed, and a storage device located in the lower layer is required to have a larger storage capacity and a higher recording density. In FIG. 7A, from the top layer in order, a memory mounted as a register in an arithmetic processing unit (PU), a memory that can be used as a cache such as NOSRAM, a storage memory such as an OS Memory, or a memory that can be used as a main memory (main memory, storage) is shown.

[0079] In FIGS. 7A and 7B, a three-dimensional structure NAND type universal memory using an OS transistor or the like is referred to as "OS Memory". Note that "OS Memory" is preferably an OS transistor having a larger storage capacity than NOSRAM.

[0080] Universal memory can be randomly accessed and has the characteristic that the off-current of the OS transistor is very small. Therefore, even when the power supply is stopped, universal memory can retain the information written over a period of one year or more, and even ten years or more. Thus, universal memory can also be regarded as non-volatile memory.

[0081] Also, since the amount of charge written in universal memory hardly changes over a long period of time, universal memory can retain not only binary (1-bit) but also multi-valued (multi-bit) information.

[0082] Also, since universal memory writes charge to the node via an OS transistor, the high voltage required in conventional NAND flash memory is not necessary, and a high-speed write operation can also be realized. Also, the erase operation before data rewriting performed in NAND flash memory is not required in universal memory. Also, since charge injection and extraction to the floating gate or charge trapping layer are not performed, universal memory can perform data writing and reading an almost unlimited number of times. Universal memory has less degradation and higher reliability compared to conventional NAND flash memory.

[0083] The semiconductor device according to one aspect of the present invention can significantly increase the storage capacity of data used for arithmetic processing. In addition, the gap in the delay time required for data reading and writing can be alleviated. Also, as shown in FIG. 7B, memory circuits having different data retention characteristics or storage capacities are stacked and provided in the z direction (a direction perpendicular to the substrate on which the arithmetic processing unit 21 is provided), and data (Data) can be input and output through each layer. Since the input and output of data (Data) can be performed using the wiring between the layers, the parasitic capacitance or resistance of the wiring can be reduced, and an increase in power consumption due to the input and output of data can be suppressed.

[0084] In another aspect of the present invention, a part of the memory circuit layers 22_1 to 22_N may be a circuit having another function. For example, as shown in FIG. 8A, a circuit 24F having a function different from that of the memory circuit may be provided in the memory circuit layer 22_N at the uppermost layer of the accelerator 20.

[0085] The circuit 24F can be a circuit provided with OS transistors. For example, it can be an amplifier circuit or an amplifier circuit capable of amplifying the potential of the input IN as shown in FIG. 8B at the output OUT. The transistor 33B can be composed of OS transistors. In addition to the configuration of FIG. 8B, the circuit 24F may have, for example, an antenna 34 as shown in FIG. 8C. The antenna 34 can be formed by arranging the conductive layer used for the circuit 24F to function as an antenna. In the case of, for example, an antenna of the fifth-generation mobile communication system (5G), communication frequencies in the 3.7 GHz band, 4.5 GHz band, and 28 GHz band are used in Japan.

[0086] In another aspect of the present invention, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N are made different. The data retention characteristics correspond to the time (data retention time) for which the written data can be retained. In the schematic diagram shown in FIG. 9A, the data retention characteristics are made different between the memory circuit 24A and the memory circuit 24B. When the memory circuit 24A is used as a cache memory, the data retention time of the memory circuit 24A may be several ms. When the memory circuit 24B is used as a main memory or a storage memory, the data retention time of the memory circuit 24B is preferably longer than that of the cache memory.

[0087] As a configuration for varying the retention time, as shown in FIG. 9A, the drive voltages V1 and V2 for driving each memory circuit output by the drive circuit 35 are made different. For example, as shown in FIG. 9B, the amplitude voltages for driving the transistors included in the memory circuit with the drive voltages V1 and V2 are made different. In FIG. 9B, the potential for turning off the transistors included in the memory circuits 24A and 24B is defined as the potential Voff. In FIG. 9B, the potential Von1 for turning on the transistors included in the memory circuit 24A is set to be smaller than the potential Von2 for turning on the transistors included in the memory circuit 24B. By setting the drive voltages V1 and V2 in this way, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different. By adopting a configuration in which the drive voltages V1 and V2 for driving each memory circuit are made different, the S value (subthreshold swing value) and the field-effect mobility in the transistors included in each memory circuit can be made different.

[0088] As another example, for example, as shown in FIG. 9C, the potential for turning on the transistors included in the memory circuits 24A and 24B is defined as the potential Von. In FIG. 9C, the potential Voff1 for turning off the transistors included in the memory circuit 24A is set to be larger than the potential Voff2 for turning off the transistors included in the memory circuit 24B. By setting the drive voltages V1 and V2 in this way, the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N can be made different.

[0089] As a configuration for varying the retention time, a configuration may be adopted in which the film thickness of the insulator that functions as the gate insulating film of the transistors included in the memory circuit is varied for each layer. For example, as shown in FIG. 10, the film thickness of the insulator 36A that functions as the gate insulating film of the transistor 25A included in the memory circuit 24A of the memory circuit layer 22_1 is made smaller than the film thickness of the insulator 36B that functions as the gate insulating film of the transistor 25B included in the memory circuits 24B of the memory circuit layers 22_2 to 2_N. By thus varying the film thickness of the insulator that functions as the gate insulating film of the transistors included in the memory circuit for each layer, it is possible to vary the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N.

[0090] Also, as a configuration for varying the retention time, a configuration may be adopted in which the channel length of the transistors included in the memory circuit is varied for each layer. For example, as shown in FIG. 11, the channel length L1 of the transistor 25A included in the memory circuit 24A of the memory circuit layer 22_1 is made smaller than the channel length L2 of the transistor 25B included in the memory circuits 24B of the memory circuit layers 22_2 to 2_N. By thus varying the channel length of the transistors included in the memory circuit for each layer, it is possible to vary the data retention characteristics of the memory circuits provided in the memory circuit layers 22_1 to 22_N. Although FIG. 11 illustrates a configuration in which the channel length is varied for each layer, a configuration may also be adopted in which the channel width of the transistor, or the ratio (W / L) of the channel length to the channel width, or the drive frequency is varied for each layer, or a combination of these configurations may be adopted.

[0091] FIG. 12A is a diagram for explaining an example of a circuit configuration applicable to the arithmetic processing unit 21 included in the semiconductor device 100 of the present invention. The arithmetic processing unit 21 includes N arithmetic circuits 23_1 to 23_N. Each of the N arithmetic circuits 23_1 to 23_N receives a signal from any one of N read bit lines RBL_1 to RBL_N and outputs output signals Q_1 to Q_N. The signals of the read bit lines RBL_1 to RBL_N may be amplified by a sense amplifier or the like and read out. The output signals Q_1 to Q_N correspond to data obtained by performing a sum-of-products operation using the data held in the memory circuit 24.

[0092] FIG. 12B is a diagram for explaining an example of a circuit configuration of the arithmetic circuit 23 applicable to the arithmetic circuits 23_1 to 23_N. FIG. 13 is a circuit for executing arithmetic processing based on the architecture of a Binary Neural Network (BNN). The arithmetic circuit 23 includes a read circuit 41 to which a signal of the read bit line RBL is applied, a bit sum-of-products calculator 42, an accumulator 43, a latch circuit 44, and an encoding circuit 45 that outputs an output signal Q.

[0093] A configuration example showing more details of the configuration of the arithmetic circuit 23 illustrated in FIG. 12B is illustrated in FIG. 13. In FIG. 13, as an example, a configuration is illustrated in which a sum-of-products operation of 8-bit signals (W[0] to W[7], A[0] to A[7]) is performed, and a 1-bit output signal Q and an 11-bit output signal (accout[10:0]) are output. In FIG. 12B, since one row is selected per clock for memory access, the product of M (=1 bit × M rows) and its sum are executed in M clocks. In the arithmetic circuit of FIG. 13, since the same M products and their sum can be executed in 8 parallel × 1 bit × M / 8 rows, M / 8 clocks are required. Therefore, the configuration of FIG. 13 can shorten the arithmetic time by executing the sum-of-products operation in parallel, and thus can improve the arithmetic efficiency.

[0094] The arithmetic circuit 23 shown in FIGS. 12A and 12B can reduce the circuit area by adopting a circuit configuration that performs a sum-of-products operation specialized for inference processing. Therefore, when multiple accelerators 20 are used for data transmission and reception, the power consumption required can be reduced by a ratio such as one-tenth or so.

[0095] In addition to the reduction of power consumption in the above-described operations, the reduction of power consumption by operations specialized for sum-of-products operations during inference processing, and the reduction of power consumption by downsizing the circuit area, by optimizing the computer architecture or software, or optimizing the driving method, it is possible to reduce the power consumption in existing data centers or supercomputers by a ratio such as one-thousandth.

[0096] In FIG. 13, the bit sum-of-products calculator 42 has an integrator into which 8-bit signals (W[0] to W[7], A[0] to A[7]) are input, and an adder into which the value obtained by the integrator is input. As shown in FIG. 13, the products of 1-bit signals calculated in parallel are shown as WA0 to WA7, the sum thereof is further shown as WA10, WA32, WA54, WA76, and the sum thereof is further shown as WA3210, WA7654.

[0097] In FIG. 13, the accumulator 43 that functions as an adder outputs the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 to the latch circuit 44. Note that the signal input to the adder of the accumulator 43 is switched according to the control signal TxD_EN. When the control signal TxD_EN is 0 (TxD_EN = 0), the sum of the signal of the bit sum-of-products calculator 42 and the output signal of the latch circuit 44 is output to the latch circuit 44. When the control signal TxD_EN is 1 (TxD_EN = 1), the sum of the signal of the logic circuit 47 (11-bit selector) and the output signal of the latch circuit 44 is output to the latch circuit 44.

[0098] In FIG. 13, the logic circuit 47 composed of AND circuits adds the signal W[7] while switching with the data for batch normalization, specifically the switching signal (th select[10:0]), after the sum-of-products operation of the signals A[0] to A[7] and the signals W[0] to W[7] is completed. Note that the data for batch normalization may be configured to be simultaneously read from and selected from signals W[0] to W[6] other than the signal W[7], for example. Batch normalization is an operation for adjusting so that the distribution of the output data of each layer in the neural network converges to a constant. For example, image data often used in the operations in the neural network may have a different distribution from the prediction data (input data) because the distribution of the data used for learning is likely to vary. Batch normalization can improve the learning accuracy in the neural network by normalizing the distribution of the input data to the intermediate layer of the neural network to a Gaussian distribution with a mean of 0 and a variance of 1. In a Binary Neural Network (BNN), since the output results of each layer are binarized by activation, by suppressing the bias of the data distribution with respect to the threshold value, appropriate activation, that is, information can be separated.

[0099] The latch circuit 44 holds the output signal (accout[10:0]) of the accumulator 43. The binary data passed to the next layer (NN layer) in the neural network by batch normalization becomes the most significant bit of the sum-of-products operation result held by the latch circuit 44. In the output signal (accout[10:0]), the most significant bit signal (accout10) represents the sign of the latched data calculated by two's complement, and is inverted by the inverter circuit 46 that functions as an encoding circuit and output as the output signal Q in order to pass the positive data as 1 and the negative data as 0 to the next NN layer. Since Q is the output of the intermediate layer, it is temporarily held in the buffer memory (also referred to as the input buffer) in the accelerator 20 and then used for the operation of the next layer.

[0100] FIG. 14A illustrates a hierarchical neural network based on the architecture of a Binary Neural Network (BNN). In FIG. 14A, a fully connected neural network of neurons 50, one input layer (I1), three intermediate layers (M1 to M3), and one output layer (O1) is illustrated. Assuming that the number of neurons in the input layer I1 is 786, the number of neurons in the intermediate layers M1 to M3 is 256, and the number of neurons in the output layer O1 is 10, the number of connections in each layer (layers 51, 52, 53, and 54) is (786×256)+(256×256)+(256×256)+(256×10), which totals 334,336. That is, since the total number of weight parameters required for neural network calculations is about 330K bits, it is possible to have a memory capacity that can be sufficiently implemented even in a small-scale system.

[0101] Next, FIG. 14B shows a detailed block diagram of the semiconductor device 100 that can perform the operations of the neural network illustrated in FIG. 14A.

[0102] In FIG. 14B, in addition to the memory circuit layer 22_1, the memory circuit 24, and the wiring 31 among the arithmetic processing unit 21, the arithmetic circuit 23, and the memory unit 22 described in FIGS. 1A and 1B, a configuration example of the peripheral circuit for driving each configuration illustrated in FIGS. 1A and 1B is shown.

[0103] In FIG. 14B, a controller 61, a row decoder 62, a word line driver 63, a column decoder 64, a write driver 65, a precharge circuit 66, a sense amplifier 67, a selector 68, an input buffer 71, and an arithmetic control circuit 72 are shown.

[0104] FIG. 15A is a diagram in which the blocks for controlling the memory circuit layers 22_1 to 22_N of the memory unit 22 for each configuration illustrated in FIG. 14B are extracted. In FIG. 15A, the controller 61, the row decoder 62, the word line driver 63, the column decoder 64, the write driver 65, the precharge circuit 66, the sense amplifier 67, and the selector 68 are extracted and shown.

[0105] The controller 61 processes an externally input signal to generate control signals for the row decoder 62 and the column decoder 64. The externally input signal is a control signal for controlling the memory circuit layers 22_1 to 22_N of the memory unit 22, such as a write enable signal or a read enable signal. Also, the controller 61 performs input / output of data written to the memory circuit layers 22_1 to 22_N of the memory unit 22 or data read from the memory circuit layers 22_1 to 22_N of the memory unit 22 via a bus to / from the CPU 10.

[0106] The row decoder 62 generates a signal for driving the word line driver 63. The word line driver 63 generates signals to be applied to the write word line WWL and the read word line RWL. The column decoder 64 generates signals for driving the sense amplifier 67 and the write driver 65. The sense amplifier 67 amplifies the potential of the read bit line RBL. The write driver generates signals for controlling the read bit line RBL and the write bit line WBL. The precharge circuit 66 has a function of precharging the read bit line RBL and the like. The signal read from the memory circuit 24 of the memory circuit layers 22_1 to 22_N of the memory unit 22 can be output via the selector 68 in addition to being input to the arithmetic circuit 23. The selector 68 can sequentially read out data corresponding to the bus width and output necessary data to the CPU 10 or the like via the controller 61.

[0107] FIG. 15B is a diagram in which blocks for controlling the arithmetic processing unit 21 are extracted from the configurations illustrated in FIG. 14B.

[0108] The controller 61 processes an externally input signal to generate a control signal for the arithmetic control circuit 72. Further, the controller 61 generates various signals for controlling the arithmetic circuit 23 included in the arithmetic processing unit 21. Further, the controller 61 inputs and outputs data regarding the arithmetic result via the input buffer 71. By using this buffer memory, parallel calculation with a bit number equal to or greater than the data bus width of the CPU becomes possible. Further, since the number of times of transferring an enormous number of weight parameters to and from the CPU 10 can be reduced, power consumption can be reduced.

[0109] One aspect of the present invention can reduce the size of a semiconductor device that functions as an accelerator such as AI technology with a huge amount of calculation and a huge number of parameters. Alternatively, one aspect of the present invention can reduce the power consumption of a semiconductor device that functions as an accelerator such as AI technology with a huge amount of calculation and a huge number of parameters. Alternatively, one aspect of the present invention can suppress heat generation in a semiconductor device that functions as an accelerator such as AI technology with a huge amount of calculation and a huge number of parameters. Alternatively, one aspect of the present invention can reduce the number of data transfers between a semiconductor device that functions as an accelerator such as AI technology with a huge amount of calculation and a huge number of parameters and a semiconductor device that functions as a CPU and a memory. In other words, a semiconductor device that functions as an accelerator such as AI technology with a huge amount of calculation and a huge number of parameters has a non - von Neumann architecture, and can perform parallel processing with extremely low power consumption as compared with the von Neumann architecture in which power consumption increases as the processing speed increases.

[0110] (Embodiment 2) In the present embodiment, an example of the operation when a part of the operations of the program executed by the CPU 10 described in the above embodiment is executed by the accelerator 20 will be described.

[0111] FIG. 16 is a diagram for explaining an example of the operation when a part of the operations of the program executed by the CPU is executed by the accelerator.

[0112] A host program is executed by the CPU (step S1).

[0113] When the CPU confirms an instruction to secure an area for data required when performing an operation using the accelerator in the memory unit (step S2), the CPU secures the area for the data in the memory unit (step S3). For example, in the first embodiment described above, the memory unit 22 secures the data required when the accelerator 20 performs an operation in the arithmetic processing unit 21.

[0114] Next, the CPU transmits the input data from the main memory to the memory unit (step S4). The memory unit receives the input data and stores the input data in the area secured in step S2 (step S5).

[0115] When the CPU confirms an instruction to start the kernel program (step S6), the accelerator starts the execution of the kernel program (step S7).

[0116] Immediately after the accelerator starts the execution of the kernel program, the CPU may be switched from the operation state to the PG (power gating) state (step S8). In that case, immediately before the accelerator finishes the execution of the kernel program, the CPU is switched from the PG state to the operation state (step S9). By setting the CPU to the PG state during the period from step S8 to step S9, it is possible to suppress the power consumption and heat generation of the entire semiconductor device.

[0117] When the accelerator finishes the execution of the kernel program, the output data is stored in the memory unit (step S10).

[0118] After the execution of the kernel program ends, when the CPU requests an instruction to transmit the output data stored in the memory unit to the main memory (step S11), the accelerator transmits the output data to the main memory, and the output data is stored in the main memory (step S12).

[0119] When the CPU issues an instruction to release the data area secured on the memory unit (step S13), the data area secured on the memory unit is released (step S14).

[0120] By repeating the operations from step S1 to step S14 above, while suppressing the power consumption and heat generation of the CPU and the accelerator, a part of the operations of the program executed by the CPU can be executed by the accelerator.

[0121] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0122] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0123] FIG. 17 shows a configuration example of the CPU 10. The CPU 10 includes a CPU core 200, an L1 (level 1) cache memory device 202, an L2 cache memory device 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 includes flip-flops 220.

[0124] The bus interface unit 205 interconnects the CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203.

[0125] In response to an interrupt signal (Interrupts) input from the outside and signals such as the signal SLEEP1 issued by the CPU 10, the PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals. The clock signal GCLK1 and the PG control signals are input to the CPU 10. The PG control signals control the power switches 210 to 212 and the flip-flops 220.

[0126] Power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to the virtual power line V_VDD (hereinafter referred to as the V_VDD line). Power switch 212 controls the supply of voltage VDDH to the virtual power line V_VDH (hereinafter referred to as the V_VDH line). Voltages VSSS are input to the CPU 10 and the PMU 193 without passing through a power switch. Voltage VDDD is input to the PMU 193 without passing through a power switch.

[0127] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is lower than voltage VDDD and is the drive voltage in the sleep state. Voltage VDDH is the drive voltage for the OS transistor and is higher than voltage VDDD.

[0128] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. One or more power switches are provided in the power domain that can be power-gated. These power switches are controlled by a PG control signal.

[0129] Flip-flop 220 is used for a register. A backup circuit is provided in flip-flop 220. Flip-flop 220 will be described below.

[0130] FIG. 18A shows a circuit configuration example of flip-flop 220 (Flip-flop). Flip-flop 220 has a scan flip-flop (Scan Flip-flop) 221 and a backup circuit (Buckup Circuit) 222.

[0131] Scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and clock buffer circuit 221A.

[0132] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. The clock signal GCLK1 is input to the clock buffer circuit 221A. The analog switches of the scan flip-flop 221 are connected to nodes CK1 and CKB1 of the clock buffer circuit 221A. Node RT is an input node for the reset signal.

[0133] Signal SCE is a scan enable signal and is generated by PMU193. PMU193 generates signals BK and RC. The level shifter 214 level-shifts signals BK and RC to generate signals BKH and RCH. Signals BK and RC are backup signals and recovery signals.

[0134] The circuit configuration of the scan flip-flop 221 is not limited to FIG. 18A. Flip-flops prepared in a standard circuit library can be applied.

[0135] The backup circuit 222 includes nodes SD_IN, SN11, transistors M11 to M13, and a capacitive element C11.

[0136] Node SD_IN is an input node for scan test data and is connected to node Q1 of the scan flip-flop 221. Node SN11 is a holding node of the backup circuit 222. The capacitive element C11 is a holding capacitor for holding the voltage of node SN11.

[0137] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 controls the conduction state between node SD_IN and node SD. The on / off states of transistors M11 and M13 are controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH.

[0138] Transistors M11 to M13 are OS transistors, similar to transistors 25 to 27 of the memory circuit 24 described above. Transistors M11 to M13 are illustrated with a back gate. The back gates of transistors M11 to M13 are connected to a power supply line that supplies voltage VBG1.

[0139] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the characteristic of the OS transistor that the off-current is extremely small, the voltage drop at node SN11 can be suppressed, and since almost no power is consumed for data retention, the backup circuit 222 has non-volatile characteristics. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is not restricted in principle by the number of rewrite times, can perform data writing and reading with low energy.

[0140] It is highly preferable that all transistors of the backup circuit 222 are OS transistors. As shown in Fig. 18B, the backup circuit 222 can be stacked on the scan flip-flop 221 composed of a silicon CMOS circuit.

[0141] Since the backup circuit 222 has a very small number of elements compared to the scan flip-flop 221, it is not necessary to change the circuit configuration and layout of the scan flip-flop 221 for stacking the backup circuit 222. That is, the backup circuit 222 is a highly versatile backup circuit. Also, since the backup circuit 222 can be provided so as to overlap within the region where the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be made zero even when the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 in the flip-flop 220, power gating of the CPU core 200 becomes possible. Since the energy required for power gating is small, it is possible to perform power gating of the CPU core 200 with high efficiency.

[0142] By providing the backup circuit 222, the parasitic capacitance due to the transistor M11 will be added to the node Q1. However, since it is smaller compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. That is, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0143] As low power consumption states of the CPU core 200, for example, a clock gating state, a power gating state, and a sleep state can be set. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, the signal SLEEP1, etc. For example, when transitioning from the normal operation state to the clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0144] For example, when transitioning from the normal operation state to the sleep state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 in order to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not erase the data of the scan flip-flop 221. When performing frequency scaling, the PMU 193 decreases the frequency of the clock signal GCLK1.

[0145] When the CPU core 200 transitions from the normal operation state to the power gating state, an operation to back up the data of the scan flip-flop 221 to the backup circuit 222 is performed. When the CPU core 200 resumes from the power gating state to the normal operation state, a recovery operation to write back the data of the backup circuit 222 to the scan flip-flop 221 is performed.

[0146] FIG. 19 shows an example of the power gating sequence of the CPU core 200. In FIG. 19, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 210 to 212 and are generated by the PMU193. When the signal PSE0 is “H” / “L”, the power switch 210 is on / off. The same applies to the signals PSE1 and PSE2.

[0147] Before time t1, it is in the normal operation state. The power switch 210 is on, and the voltage VDDD is input to the CPU core 200. The scan flip-flop 221 performs normal operation. At this time, since the level shifter 214 does not need to be operated, the power switch 212 is off, and the signals SCE, BK, and RC are “L”. Since the node SE is “L”, the scan flip-flop 221 stores the data of the node D1. In the example of FIG. 19, at time t1, the node SN11 of the backup circuit 222 is “L”.

[0148] The operation during backup will be described. At the operation time t1, the PMU193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to “H”. The level shifter 214 becomes active and outputs the “H” signal BKH to the backup circuit 222.

[0149] The transistor M11 of the backup circuit 222 turns on, and the data of the node Q1 of the scan flip-flop 221 is written to the node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is “L”, the node SN11 remains “L”, and if the node Q1 is “H”, the node SN11 becomes “H”.

[0150] The PMU193 sets the signals PSE2 and BK to “L” at time t2 and sets the signal PSE0 to “L” at time t3. At time t3, the state of the CPU core 200 shifts to the power gating state. Note that the signal PSE0 may be set low at the timing when the signal BK is set low.

[0151] Describe the operation during power-gating. When the signal PSE0 becomes "L", the voltage of the V_VDD line decreases, so the data of node Q1 is lost. Node SN11 continues to hold the data of node Q1 at time t3.

[0152] Describe the operation during recovery. At time t4, when PMU193 sets the signal PSE0 to "H", it transitions from the power-gating state to the recovery state. The charging of the V_VDD line starts, and when the voltage of the V_VDD line reaches VDDD (at time t5), PMU193 sets the signals PSE2, RC, and SCE to "H".

[0153] Transistor M12 turns on, and the charge of capacitor C11 is distributed to node SN11 and node SD. If node SN11 is "H", the voltage of node SD rises. Since node SE is "H", the data of node SD is written into the input-side latch circuit of scan flip-flop 221. When the clock signal GCLK1 is input to node CK at time t6, the data of the input-side latch circuit is written into node Q1. That is, the data of node SN11 is written into node Q1.

[0154] At time t7, PMU193 sets the signals PSE2, SCE, and RC to "L", and the recovery operation ends.

[0155] The backup circuit 222 using an OS transistor is very suitable for normal-off computing because both dynamic and static low power consumption are small. Even if flip-flop 220 is mounted, it can be made to hardly cause a performance degradation of the CPU core 200 and an increase in dynamic power.

[0156] Note that the CPU core 200 may have a plurality of power domains that can be power-gated. One or more power switches for controlling the input of voltage are provided for the plurality of power domains. Further, the CPU core 200 may have a power domain in which one or more power-gating operations are not performed. For example, a power-gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212 may be provided in the power domain where power-gating is not performed.

[0157] Note that the application of the flip-flop 220 is not limited to the CPU 10. In the arithmetic unit, the flip-flop 220 can be applied to a register provided in a power domain that can be power-gated.

[0158] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0159] (Embodiment 4) Hereinafter, an example of the semiconductor device according to the above embodiment will be described with reference to FIGS. 20 to 25. First, a configuration example of a memory circuit (memory cell) constituting the semiconductor device will be described.

[0160] (Configuration Example of Memory Circuit) FIGS. 20A and 20B show the structure of a memory circuit 860 constituting a semiconductor device according to an aspect of the present invention. FIG. 20A is a top view of the periphery of the memory circuit 860. FIG. 20B is a cross-sectional view of the memory circuit 860, and FIG. 20B corresponds to the portion indicated by the one-dot chain line A1 - A2 in FIG. 20A. In FIG. 20B, a cross-section in the channel length direction of the transistor 600 and a cross-section in the channel width direction of the transistor 700 are shown. In the top view of FIG. 20A, some elements are omitted for clarity of the figure. Here, the X direction, Y direction, and Z direction shown in FIG. 20A are directions that are orthogonal or intersect with each other. Here, the X direction and the Y direction are preferably parallel or substantially parallel to the substrate surface, and the Z direction is preferably perpendicular or substantially perpendicular to the substrate surface.

[0161] The memory circuit 860 shown in this embodiment has the transistor 600, the transistor 700, and the capacitor element 655. The memory circuit 860 corresponds to the memory circuit 24 shown in the previous embodiment. The transistor 600, the transistor 700, and the capacitor element 655 respectively correspond to the transistor 25, the transistor 26, and the capacitor element 28 shown in the previous embodiment 1, and correspond to a 2T-type NOSRAM in which the transistor 27 is omitted. One of the source and drain of the transistor 600, the gate of the transistor 700, and one of the electrodes of the capacitor element 655 are electrically connected.

[0162] As shown in FIGS. 20A and 20B, in the memory circuit 860, the transistor 600 and the transistor 700 are arranged on the insulator 614, the insulator 680 is arranged on a part of the transistor 600 and the transistor 700, the insulator 682 is arranged on the transistor 600, the transistor 700, and the insulator 680, the insulator 685 is arranged on the insulator 682, the capacitor element 655 is arranged on the insulator 685, and the insulator 688 is arranged on the capacitor element 655. The insulator 614, the insulator 680, the insulator 682, the insulator 685, and the insulator 688 function as interlayer films.

[0163] Here, the transistor 600 includes an insulator 616 on an insulator 614, conductors 605 (conductor 605a and conductor 605b) arranged to be embedded in the insulator 616, an insulator 622 on the insulator 616 and on the conductors 605, an insulator 624 on the insulator 622, an oxide 630a on the insulator 624, an oxide 630b on the oxide 630a, oxides 643a and 643b on the oxide 630b, a conductor 642a on the oxide 643a, a conductor 642b on the oxide 643b, an insulator 672 in contact with a part of the insulator 624, side surfaces of the oxide 630a, side surfaces of the oxide 630b, side surfaces of the oxide 643a, side surfaces of the conductor 642a, the upper surface of the conductor 642a, side surfaces of the oxide 643b, side surfaces of the conductor 642b, and the upper surface of the conductor 642b respectively, an insulator 673 on the insulator 672, an oxide 630c on the oxide 630b, an insulator 650 on the oxide 630c, and conductors 660 (conductor 660a and conductor 660b) located on the insulator 650 and overlapping the oxide 630c. Also, the oxide 630c is in contact with the side surfaces of the oxide 643a, the side surfaces of the oxide 643b, the side surfaces of the conductor 642a, and the side surfaces of the conductor 642b respectively. Here, as shown in FIG. 20B, the upper surface of the conductor 660 is arranged to substantially coincide with the upper surface of the insulator 650, the upper surface of the oxide 630c, and the upper surface of the insulator 680. Also, the insulator 682 is in contact with the upper surfaces of the conductors 660, the insulator 650, the oxide 630c, and the insulator 680 respectively.

[0164] In the following, the oxides 630a, 630b, and 630c may be collectively referred to as the oxide 630. Also, the oxides 643a and 643b may be collectively referred to as the oxide 643. Also, the conductors 642a and 642b may be collectively referred to as the conductor 642.

[0165] In the transistor 600, the conductor 660 functions as a gate, and the conductors 642a and 642b function as a source or a drain, respectively. Further, the conductor 605 functions as a back gate. The transistor 600 is self-alignedly formed such that the conductor 660 functioning as a gate fills an opening formed by an insulator 680 or the like. Thus, in the semiconductor device according to the present embodiment, the conductor 660 can be surely disposed in the region between the conductor 642a and the conductor 642b without alignment.

[0166] Also, the transistor 700 includes an insulator 616 on the insulator 614, conductors 705 (conductor 705a and conductor 705b) disposed so as to be embedded in the insulator 616, an insulator 622 on the insulator 616 and on the conductors 705, an insulator 624 on the insulator 622, an oxide 730a on the insulator 624, an oxide 730b on the oxide 730a, oxides 743a and 743b on the oxide 730b, a conductor 742a on the oxide 743a, a conductor 742b on the oxide 743b, an insulator 672 in contact with a part of the insulator 624, side surfaces of the oxide 730a, side surfaces of the oxide 730b, side surfaces of the oxide 743a, side surfaces of the conductor 742a, the upper surface of the conductor 742a, side surfaces of the oxide 743b, side surfaces of the conductor 742b, and the upper surface of the conductor 742b, an insulator 673 on the insulator 672, an oxide 730c on the oxide 730b, an insulator 750 on the oxide 730c, and conductors 760 (conductor 760a and conductor 760b) located on the insulator 750 and overlapping the oxide 730c. Further, the oxide 730c is in contact with side surfaces of the oxide 743a, side surfaces of the oxide 743b, side surfaces of the conductor 742a, and side surfaces of the conductor 742b. Here, as shown in FIG. 20B, the upper surface of the conductor 760 is disposed substantially flush with the upper surface of the insulator 750, the upper surface of the oxide 730c, and the upper surface of the insulator 680. Also, the insulator 682 is in contact with the upper surfaces of the conductor 760, the insulator 750, the oxide 730c, and the insulator 680, respectively.

[0167] Also, hereinafter, oxide 730a, oxide 730b, and oxide 730c may be collectively referred to as oxide 730. Also, oxide 743a and oxide 743b may be collectively referred to as oxide 743. Also, conductor 742a and conductor 742b may be collectively referred to as conductor 742.

[0168] In transistor 700, conductor 760 functions as a gate, and conductor 742a and conductor 742b each function as a source or a drain. Also, conductor 705 functions as a back gate. Transistor 700 is self-alignedly formed such that conductor 760, which functions as a gate, fills an opening formed by insulator 680 or the like. Thus, in the semiconductor device according to the present embodiment, conductor 760 can be surely disposed in the region between conductor 742a and conductor 742b without alignment.

[0169] Here, transistor 700 is formed in the same layer as transistor 600 and has a similar configuration. Therefore, although the cross-section in the channel length direction of transistor 700 is not shown, it has a structure similar to the cross-section in the channel length direction of transistor 600 shown in FIG. 20B. That is, oxide 743 and conductor 742, which are not shown in the cross-sectional view, also have a structure similar to that of oxide 643 and conductor 642 shown in FIG. 20B. Note that the cross-section in the channel width direction of transistor 600 is not shown, but it has a structure similar to the cross-section in the channel width direction of transistor 700 shown in FIG. 20B.

[0170] Therefore, the oxide 730 has the same configuration as the oxide 630, and the description of the oxide 630 can be referred to. The conductor 705 has the same configuration as the conductor 605, and the description of the conductor 605 can be referred to. The oxide 743 has the same configuration as the oxide 643, and the description of the oxide 643 can be referred to. The conductor 742 has the same configuration as the conductor 642, and the description of the conductor 642 can be referred to. The insulator 750 has the same configuration as the insulator 650, and the description of the insulator 650 can be referred to. The conductor 760 has the same configuration as the conductor 660, and the description of the conductor 660 can be referred to. In the following, unless otherwise specified, the configuration of the transistor 700 can refer to the description of the configuration of the transistor 600 as described above.

[0171] Here, for the transistors 600 and 700, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxides 630 and 730 including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0172] For example, as the metal oxide that functions as an oxide semiconductor, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap, the leakage current (off-current) in the non-conducting state of the transistor 600 can be made extremely small.

[0173] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) can be used. In particular, element M is preferably aluminum, gallium, yttrium, or tin. Also, as the oxide semiconductor, In-M oxide, In-Zn oxide, or M-Zn oxide may be used.

[0174] Since transistors 600 and 700 using an oxide semiconductor in the channel formation region have an extremely small off-current, a semiconductor device with low power consumption can be provided. Further, transistors 600 and 700 hardly increase their off-current even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Therefore, a semiconductor device with stable operation and good reliability can be realized even in a high-temperature environment.

[0175] Since the off-current of transistor 600 is extremely small, the capacitance value of capacitor element 655 can be set small. Thereby, the occupied area of memory circuit 860 can be reduced, and integration of the semiconductor device can be achieved.

[0176] As shown in FIG. 20A, conductor 742a, conductor 660, conductor 605, and conductor 705 preferably extend in the Y direction. Conductor 660 functions as the write word line WWL shown in the previous embodiment.

[0177] Capacitor element 655 includes conductor 646a on insulator 685, insulator 686 covering conductor 646a, and conductor 656 disposed on insulator 686 so as to overlap at least a part of conductor 656. Here, conductor 646a functions as one electrode of capacitor element 655, and conductor 646b functions as the other electrode of capacitor element 655. Also, insulator 686 functions as the dielectric of capacitor element 655.

[0178] Further, openings are formed in insulators 622, 624, 672, 673, 680, 682, and 685, and conductors 640 (conductor 640a, conductor 640b, conductor 640c, and conductor 640d) that function as plugs are provided to be embedded in the openings. Also, conductor 640 is provided to be exposed on the upper surface of insulator 685.

[0179] Conductor 640a has its lower surface in contact with conductor 642a and its upper surface in contact with conductor 646a. Conductor 640c has its lower surface in contact with conductor 760 and its upper surface in contact with conductor 646a. In this way, one of the source and drain of transistor 600, the gate of transistor 700, and one of the electrodes of capacitor element 655 are electrically connected.

[0180] Conductor 640b is provided in contact with the side surface of conductor 642b. Conductor 615 and conductor 607 are provided below conductor 640b, and conductor 646b and conductor 657 are provided above conductor 640b. Conductor 607 is provided in an opening formed in insulator 614. Here, conductor 615 is formed in the same layer as conductor 605 and has a similar configuration. Also, conductor 646b is formed in the same layer as conductor 646a and has a similar configuration. Also, conductor 657 is provided in an opening formed in insulator 686 and insulator 688.

[0181] Conductor 640b is electrically connected to the conductor 640b of the lower-layer memory circuit 860 by conductor 607 and conductor 615. Also, conductor 640b is electrically connected to the conductor 640b of the upper-layer memory circuit 860 by conductor 646b and conductor 657. In this way, conductor 607, conductor 615, conductor 640b, conductor 646b, and conductor 657 extend in the Z direction and function as the write bit line WBL shown in the previous embodiment.

[0182] Also, although not shown in the cross-sectional view, conductor 640d is provided in contact with the side surface of conductor 742b. Also, conductor 715 is provided below conductor 640d. Conductors having the same structure as conductor 607, conductor 646b, and conductor 657 are provided, and conductor 640d is electrically connected to the conductor 640d of the upper layer and the lower layer. In this way, conductor 715, conductor 640d, etc. extend in the Z direction and function as the read bit line RBL shown in the previous embodiment.

[0183] As shown in FIG. 20B, by forming the transistor 600 and the transistor 700 in the same layer, they can be formed in the same process as the transistor 600 and the transistor 700. Therefore, the process of manufacturing the semiconductor device can be shortened, and productivity can be improved.

[0184] In the memory circuit 860, the transistor 600, the transistor 700, and the capacitor element 655 are provided such that the channel length directions of the transistor 600 and the transistor 700 are parallel. However, the semiconductor device shown in this embodiment is not limited to this. The memory circuit 860 shown in FIG. 20 and the like is an example of the configuration of the semiconductor device, and transistors or capacitor elements having an appropriate structure may be appropriately arranged according to the circuit configuration and the driving method.

[0185] [Detailed Configuration of Memory Circuit] Hereinafter, the detailed configuration of the memory circuit 860 according to one aspect of the present invention will be described. Hereinafter, it is assumed that the components of the transistor 700 can refer to the description of the components of the transistor 600.

[0186] As shown in FIG. 20B, the oxide 630 preferably has an oxide 630a on the insulator 624, an oxide 630b on the oxide 630a, and an oxide 630c disposed on the oxide 630b and at least partially in contact with the upper surface of the oxide 630b. Here, the side surface of the oxide 630c is preferably provided in contact with the oxide 643a, the oxide 643b, the conductor 642a, the conductor 642b, the insulator 672, the insulator 673, and the insulator 680.

[0187] That is, the oxide 630 has an oxide 630a, an oxide 630b on the oxide 630a, and an oxide 630c on the oxide 630b. By having the oxide 630a under the oxide 630b, diffusion of impurities from a structure formed below the oxide 630a into the oxide 630b can be suppressed. Also, by having the oxide 630c on the oxide 630b, diffusion of impurities from a structure formed above the oxide 630c into the oxide 630b can be suppressed.

[0188] Note that in the transistor 600, a configuration in which three layers of the oxide 630a, the oxide 630b, and the oxide 630c are stacked in the channel formation region and its vicinity is shown, but the present invention is not limited to this. For example, a configuration may be adopted in which a single layer of the oxide 630b, a two-layer structure of the oxide 630b and the oxide 630a, a two-layer structure of the oxide 630b and the oxide 630c, or a stacked structure of four or more layers is provided. For example, the oxide 630c may have a two-layer structure to provide a four-layer stacked structure.

[0189] Also, the oxide 630 preferably has a stacked structure of a plurality of oxide layers having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 630a, the atomic number ratio of the element M in the constituent elements is preferably larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 630b. Also, in the metal oxide used for the oxide 630a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 630b. Also, in the metal oxide used for the oxide 630b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 630a. Also, the oxide 630c can use a metal oxide that can be used for the oxide 630a or the oxide 630b. Note that in the metal oxide used for the oxide 630c, the atomic number ratio of In to the element M may be larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 630b.

[0190] Specifically, as the oxide 630a, a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used.

[0191] Further, as the oxide 630b, a metal oxide having a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, or a composition of 1:1:1 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 630b, a metal oxide having a composition of In:Ga:Zn = 5:1:3 [atomic ratio] or in the vicinity thereof, or a composition of In:Ga:Zn = 10:1:3 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 630b, an In-Zn oxide (for example, a composition of In:Zn = 2:1 [atomic ratio] or in the vicinity thereof, a composition of In:Zn = 5:1 [atomic ratio] or in the vicinity thereof, or a composition of In:Zn = 10:1 [atomic ratio] or in the vicinity thereof) may be used. Further, an In oxide may be used as the oxide 630b.

[0192] Further, as the oxide 630c, a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio or in the vicinity thereof], Ga:Zn = 2:1 [atomic ratio] or in the vicinity thereof, or Ga:Zn = 2:5 [atomic ratio] or in the vicinity thereof may be used. Further, materials that can be used for the oxide 630b may be applied to the oxide 630c, and they may be provided in a single layer or a laminate. For example, specific examples of the case where the oxide 630c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof and In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, a laminated structure of Ga:Zn = 2:1 [atomic ratio] or in the vicinity thereof and In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, a laminated structure of Ga:Zn = 2:5 [atomic ratio] or in the vicinity thereof and In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, a laminated structure of gallium oxide and In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, etc.

[0193] In addition, as the oxides 630b and 630c, it is preferable because the on-current of the transistor, the field-effect mobility, etc. can be increased by increasing the ratio of indium in the film. The composition in the vicinity described above includes a range of ±30% of the desired atomic ratio.

[0194] Also, the composition of the elements contained in the metal oxide may be changed according to the operating frequency required for the transistor, etc. For example, in the transistors included in the memory circuit, the metal oxide may have a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof, and in other transistors, the metal oxide may have a composition of In:Ga:Zn = 5:1:3 [atomic ratio] or a composition in the vicinity thereof. In other transistors, the composition may be In:Ga:Zn = 10:1:3 [atomic ratio] or a composition in the vicinity thereof, or In:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof.

[0195] In addition, the oxide 630b may have crystallinity. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later. Oxides having crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen deficiencies) and high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 630b by the source electrode or the drain electrode. Also, even when heat treatment is performed, the extraction of oxygen from the oxide 630b can be reduced, so the transistor 600 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0196] Further, the oxide 630c is preferably provided in an opening provided in an interlayer film including the insulator 680. Therefore, the insulator 650 and the conductor 660 have a region that overlaps with the stacked structure of the oxide 630b and the oxide 630a via the oxide 630c. With such a structure, since the oxide 630c and the insulator 650 can be formed by continuous film formation, the interface between the oxide 630 and the insulator 650 can be kept clean. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 600 can obtain a high on-current and high frequency characteristics.

[0197] For the oxide 630 (for example, the oxide 630b), it is preferable to use an oxide semiconductor with a low carrier concentration. When reducing the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor may be lowered and the density of defect levels may be lowered. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0198] In particular, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, so oxygen vacancies (V O : also referred to as oxygen vacancy) may be formed in the oxide semiconductor. Further, a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) may function as a donor and electrons as carriers may be generated. In addition, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.

[0199] V OH can function as a donor in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as "donor concentration".

[0200] From the above, when using the oxide semiconductor for the oxide 630, it is preferable to reduce V O H in the oxide 630 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. In this way, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (which may be described as dehydration and dehydrogenation treatment), and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiency (which may be described as oxygen addition treatment). V O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0201] For example, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) of the oxide 630b can be set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using the oxide 630 in which impurities such as hydrogen are sufficiently reduced for the channel formation region of the transistor 600, normally-off characteristics can be achieved, and it has stable electrical characteristics and can improve reliability.

[0202] Also, when an oxide semiconductor is used for the oxide 630, the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 even more preferably less than 1×10 16 cm -3 even more preferably less than 1×10 13 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than 1×10 -9 cm -3 There is no particular limitation on the lower limit value of the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region. For example, it can be 1×10 -9 cm -3 .

[0203] Therefore, as the insulators 614, 622, 672, 673, and 682, it is preferable to use a material that suppresses the diffusion of impurities (hereinafter also referred to as a barrier material for impurities) to reduce the diffusion of impurities such as hydrogen into the oxide 630. In this specification and the like, the term "barrier property" refers to a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it refers to a function of capturing and fixing the corresponding substance (also referred to as gettering). In this specification and the like, an insulating film having barrier properties may be referred to as a barrier insulating film.

[0204] For example, as materials having a function of suppressing the diffusion of hydrogen and oxygen, there are aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride. In particular, silicon nitride or silicon oxynitride has a high barrier property against hydrogen, so it is preferably used as a sealing material.

[0205] In addition, for example, as materials having the function of capturing and fixing hydrogen, there are metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0206] For example, as the insulator 614, it is preferable to use aluminum oxide or hafnium oxide or the like. Thereby, it is possible to suppress the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 600 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 624 or the like to the substrate side.

[0207] The conductor 605 is arranged so as to overlap with the oxide 630 and the conductor 660. Further, the conductor 605 is preferably provided embedded in the insulator 616.

[0208] When the conductor 605 functions as a gate electrode, the threshold voltage (Vth) of the transistor 600 can be controlled by changing the potential applied to the conductor 605 independently without linking it to the potential applied to the conductor 660. In particular, by applying a negative potential to the conductor 605, it is possible to increase the Vth of the transistor 600 and reduce the off-current. Therefore, applying a negative potential to the conductor 605 can make the drain current smaller when the potential applied to the conductor 660 is 0V than when no negative potential is applied.

[0209] Note that, as shown in FIG. 20A, the conductor 605 may be provided to be larger than the size of the region that does not overlap with the conductors 642a and 642b of the oxide 630. In particular, as shown in FIG. 20B, it is preferable that the conductor 605 extends also in a region outside the end portion intersecting the channel width direction of the oxide 630. That is, it is preferable that the conductor 605 and the conductor 660 overlap via an insulator outside the side surface of the oxide 630 in the channel width direction. Alternatively, by providing the conductor 605 to be large, local charging (referred to as charge-up) may be alleviated in the process using plasma in the manufacturing process after the formation of the conductor 605. However, one aspect of the present invention is not limited to this. The conductor 605 may overlap at least the oxide 630 positioned between the conductor 642a and the conductor 642b.

[0210] Further, with reference to the bottom surface of the insulator 624, it is preferable that the height of the bottom surface of the conductor 660 in the region where the oxides 630a and 630b and the conductor 660 do not overlap is arranged at a position lower than the height of the bottom surface of the oxide 630b.

[0211] As shown in FIG. 20B, by adopting a structure in which the conductor 660 functioning as a gate covers the side surface and the upper surface of the oxide 630b in the channel formation region via the oxide 630c and the insulator 650, the electric field generated from the conductor 660 can be easily applied to the entire channel formation region generated in the oxide 630b. Therefore, the on-current of the transistor 600 can be increased and the frequency characteristics can be improved. In this specification, a structure of a transistor that electrically surrounds a channel formation region by the electric fields of a gate (first gate) and a back gate (second gate) is called a surrounded channel (S-channel) structure.

[0212] In addition, the conductor 605a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Also, for the conductor 605b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 605 is illustrated as a two-layer structure, it may also have a multilayer structure of three or more layers.

[0213] Further, the insulators 616, 680, 685, and 688 preferably have a lower dielectric constant than the insulator 614. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 616, 680, 685, and 688, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide having pores can be appropriately used.

[0214] Also, the insulators 616, 680, 685, and 688 may be formed by CVD or ALD using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content. Note that for the CVD method, either thermal CVD or PECVD (Plasma Enhanced CVD) may be used. Also, for the ALD method, either thermal ALD or PEALD (Plasma Enhanced ALD) may be used. However, a film-forming method using plasma such as PECVD or PEALD is more suitable because it has higher mass productivity.

[0215] In the formation of the above insulating film, a gas having a molecule containing a silicon atom is mainly used as the film-forming gas. To reduce the hydrogen contained in the above insulating film, it is preferable that the hydrogen atoms contained in the molecule containing the silicon atom are few, and it is more preferable that the molecule containing the silicon atom does not contain hydrogen atoms. Of course, for the film-forming gas other than the gas having a molecule containing a silicon atom, it is preferable that the contained hydrogen atoms are few, and it is more preferable that it does not contain hydrogen atoms.

[0216] A molecule containing a silicon atom as described above is represented as Si x -R y For example, as the functional group R, at least one of an isocyanate group (-N=C=O), a cyanate group (-O-C≡N), a cyano group (-C≡N), a diazo group (=N2), an azide group (-N3), a nitroso group (-NO), and a nitro group (-NO2) can be used. For example, 1 ≦ x ≦ 3 and 1 ≦ y ≦ 8 may be set. As such a molecule containing a silicon atom, for example, tetraisocyanatosilane, tetracyanatosi lane, tetracyanosilane, hexaisocyanatosilane, octaisocyanatosilane, etc. can be used. Here, molecules in which the same type of functional group is bonded to the silicon atom are exemplified, but the present embodiment is not limited to this. A configuration in which different types of functional groups are bonded to the silicon atom may also be used.

[0217] Further, for example, a configuration may be adopted in which a halogen (Cl, Br, I, or F) is used as the functional group R. For example, 1 ≦ x ≦ 2 and 1 ≦ y ≦ 6 may be set. As such a molecule containing a silicon atom, for example, tetrachlorosilane (SiCl4), hexachlorodisilane (Si2Cl6), etc. can be used. Although an example in which chlorine is the functional group is shown, halogens other than chlorine, such as bromine, iodine, and fluorine, may be used as the functional group. Also, a configuration in which different types of halogens are bonded to the silicon atom may be used.

[0218] The insulators 622 and 624 have the function as a gate insulator.

[0219] Here, the insulator 624 in contact with the oxide 630 preferably desorbs oxygen by heating. In this specification, oxygen that desorbs by heating may be referred to as excess oxygen. For example, the insulator 624 may be appropriately silicon oxide or silicon oxynitride. By providing an oxygen-containing insulator in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced, and the reliability of the transistor 600 can be improved.

[0220] As the insulator 624, specifically, it is preferable to use an oxide material from which some oxygen is desorbed by heating. An oxide that desorbs oxygen by heating means that, by temperature-programmed desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis), the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more, and it is an oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0221] The insulator 622 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen from the substrate side into the transistor 600. For example, the insulator 622 preferably has lower hydrogen permeability than the insulator 624. By the insulator 622 and the insulator 683 surrounding the insulator 624, the oxide 630, etc., it is possible to suppress the entry of impurities such as water or hydrogen from the outside into the transistor 600.

[0222] Furthermore, the insulator 622 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, the insulator 622 preferably has lower oxygen permeability than the insulator 624. Since the insulator 622 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen possessed by the oxide 630 to the lower side of the insulator 622, which is preferable. Also, it is possible to suppress the reaction of the conductor 605 with the oxygen possessed by the insulator 624 and the oxide 630.

[0223] The insulator 622 may be made of an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials. As the insulator containing one or both of oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 622 is formed using such a material, the insulator 622 functions as a layer that suppresses the release of oxygen from the oxide 630 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 600 into the oxide 630.

[0224] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated and used on the above insulators.

[0225] Also, the insulator 622 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0226] Note that the insulator 622 and the insulator 624 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0227] Further, an oxide 643 (oxide 643a and oxide 643b) may be disposed between the oxide 630b and a conductor 642 (conductor 642a and conductor 642b) that functions as a source electrode or a drain electrode. Since the conductor 642 and the oxide 630 do not come into contact with each other, absorption of oxygen from the oxide 630 by the conductor 642 can be suppressed. That is, by preventing oxidation of the conductor 642, a decrease in the conductivity of the conductor 642 can be suppressed. Therefore, the oxide 643 preferably has a function of suppressing oxidation of the conductor 642.

[0228] Therefore, the oxide 643 preferably has a function of suppressing oxygen permeation. By disposing an oxide 643 having a function of suppressing oxygen permeation between the conductor 642 that functions as a source electrode or a drain electrode and the oxide 630b, the electrical resistance between the conductor 642 and the oxide 630b is reduced, which is preferable. With such a configuration, the electrical characteristics and the reliability of the transistor 600 can be improved.

[0229] As the oxide 643, a metal oxide containing an element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. The oxide 643 preferably has a higher concentration of the element M than the oxide 630b. Further, gallium oxide may be used as the oxide 643. Further, a metal oxide such as an In-M-Zn oxide may be used as the oxide 643. Specifically, in the metal oxide used for the oxide 643, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 630b. The film thickness of the oxide 643 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the oxide 643 preferably has crystallinity. When the oxide 643 has crystallinity, release of oxygen in the oxide 630 can be suitably suppressed. For example, if the oxide 643 has a crystal structure such as a hexagonal crystal, release of oxygen in the oxide 630 may be suppressed.

[0230] Note that the oxide 643 is not necessarily provided. In that case, when the conductor 642 (conductor 642a and conductor 642b) is in contact with the oxide 630, oxygen in the oxide 630 may diffuse into the conductor 642, and the conductor 642 may be oxidized. When the conductor 642 is oxidized, the probability of a decrease in the conductivity of the conductor 642 is high. Note that the diffusion of oxygen in the oxide 630 into the conductor 642 can be rephrased as the conductor 642 absorbing oxygen in the oxide 630.

[0231] In addition, when oxygen in the oxide 630 diffuses into the conductor 642 (conductor 642a and conductor 642b), a different layer may be formed between the conductor 642a and the oxide 630b, and between the conductor 642b and the oxide 630b. Since the different layer contains more oxygen than the conductor 642, it is presumed that the different layer has insulating properties. At this time, the three-layer structure of the conductor 642, the different layer, and the oxide 630b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure, or may be called a diode junction structure mainly composed of a MIS structure.

[0232] Note that the above different layer is not limited to being formed between the conductor 642 and the oxide 630b. For example, the different layer may be formed between the conductor 642 and the oxide 630c, or may be formed between the conductor 642 and the oxide 630b and between the conductor 642 and the oxide 630c.

[0233] On the oxide 643, conductors 642 (conductor 642a and conductor 642b) that function as a source electrode and a drain electrode are provided. The film thickness of the conductor 642 may be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0234] As the conductor 642, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0235] The insulator 672 is provided in contact with the upper surface of the conductor 642 and preferably functions as a barrier insulating film. Further, it is preferable to provide an insulator 673 that functions as a barrier insulating film on the insulator 672. With such a configuration, it is possible to suppress the absorption of excess oxygen in the insulator 680 by the conductor 642. Further, by suppressing the oxidation of the conductor 642, it is possible to suppress an increase in the contact resistance between the transistor 600 and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 600.

[0236] Therefore, it is preferable that the insulator 672 and the insulator 673 have a function of suppressing the diffusion of oxygen. For example, it is preferable that the insulator 672 has a function of suppressing the diffusion of oxygen more than the insulator 680. As the insulator 672, for example, an insulator containing one or both oxides of aluminum and hafnium may be formed into a film. As the insulator 673, for example, silicon nitride or silicon oxynitride may be used.

[0237] In addition, it is possible to suppress the diffusion of impurities such as water or hydrogen from an insulator 680 or the like disposed via insulators 672 and 673 toward the transistor 600 side. Thus, it is preferable that the transistor 600 has a structure surrounded by insulators 672 and 673 having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0238] The insulator 650 functions as a gate insulator. The insulator 650 is preferably disposed in contact with the upper surface of the oxide 630c. As the insulator 650, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0239] Similar to the insulator 624, the insulator 650 is preferably formed using an insulator that releases oxygen by heating. By providing, as the insulator 650, an insulator that releases oxygen by heating in contact with the upper surface of the oxide 630c, oxygen can be effectively supplied to the channel formation region of the oxide 630b. Also, similar to the insulator 624, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 650 is reduced. The film thickness of the insulator 650 is preferably 1 nm or more and 20 nm or less.

[0240] In addition, a metal oxide may be provided between the insulator 650 and the conductor 660. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 650 to the conductor 660. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 650 to the conductor 660 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 630. In addition, oxidation of the conductor 660 by oxygen in the insulator 650 can be suppressed.

[0241] In addition, the metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide, silicon oxynitride, etc. for the insulator 650, it is preferable to use a metal oxide which is a high-k material with a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 650 and the metal oxide, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it becomes possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0242] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0243] Alternatively, the metal oxide may function as part of the gate. In this case, it is advisable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0244] In particular, as the conductor that functions as a gate, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0245] The conductor 660 is disposed with its bottom surface and side surfaces in contact with the insulator 650. Although the conductor 660 is shown as a two-layer structure in FIG. 20B, it may be a single-layer structure or a laminated structure of three or more layers.

[0246] For the conductor 660a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0247] Further, since the conductor 660a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 660b from being oxidized by oxygen contained in the insulator 650 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0248] In addition, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 660b. Further, since the conductor 660 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 660b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0249] For the insulator 680, it is preferable to use, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating. Also, the insulator 680 may have a structure in which the above materials are laminated. For example, a laminated structure of silicon oxide formed by a sputtering method and silicon oxynitride formed by a CVD method laminated thereon may be used. Further, silicon nitride may be laminated thereon.

[0250] Here, it is preferable that the insulator 680 has excess oxygen. For example, the insulator 680 may appropriately use silicon oxide or silicon oxynitride. By providing the insulator 680 containing excess oxygen in contact with the oxide 630, oxygen deficiency in the oxide 630 can be reduced, and the reliability of the transistor 600 can be improved. To include excess oxygen in the insulator 680, for example, the film formation of the insulator 682 may be performed by a sputtering method in an oxygen-containing atmosphere. By performing the film formation of the insulator 682 in an oxygen-containing atmosphere using the sputtering method, oxygen can be added to the insulator 680 while forming the film.

[0251] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 680 is reduced. Also, the upper surface of the insulator 680 may be planarized.

[0252] The insulator 682 preferably functions as a barrier insulating film that suppresses the mixing of impurities such as water or hydrogen into the insulator 680 from above. Further, the insulator 682 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 682, for example, an insulator such as aluminum oxide, silicon nitride, or silicon oxynitride may be used. For example, aluminum oxide, which has high barrier properties against oxygen, may be used as the insulator 682.

[0253] As shown in FIG. 20B, the insulator 682 has a structure that directly contacts the oxide 630c. By adopting such a structure, the diffusion of oxygen contained in the insulator 680 into the conductor 660 can be suppressed. Therefore, the oxygen contained in the insulator 680 can be efficiently supplied to the oxides 630a and 630b via the oxide 630c, so that the oxygen deficiencies in the oxides 630a and 630b can be reduced, and the electrical characteristics and reliability of the transistor 600 can be improved.

[0254] Further, it is preferable to provide an insulator 685 that functions as an interlayer film on the insulator 682. Similar to the insulator 624 and the like, the insulator 685 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0255] For the conductor 640, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor 640 may have a laminated structure. In FIG. 20A, the conductor 640 is circular in a top view, but it is not limited thereto. For example, in a top view, the conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of a polygon such as a quadrilateral are rounded.

[0256] When the conductor 640 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Further, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen may be used in a single layer or in a laminate. By using the conductive material, it is possible to further reduce the mixing of impurities such as water or hydrogen diffused from the insulator 680 into the oxide 630 through the conductor 640. Further, it is possible to prevent oxygen added to the insulator 680 from being absorbed by the conductor 640.

[0257] Further, a conductor 646a is disposed in contact with the upper surface of the conductor 640a and the upper surface of the conductor 640c, and a conductor 646b is disposed in contact with the upper surface of the conductor 640b. The conductor 646a and the conductor 646b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor 646a and the conductor 646b may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0258] An insulator 686 is provided so as to cover the insulator 685, the conductor 646a, and the conductor 646b. The insulator 686 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, etc., and can be provided in a laminate or a single layer.

[0259] For example, the insulator 686 may use a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. With this configuration, the capacitor element 655 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric strength by having an insulator with high dielectric strength, thereby suppressing the electrostatic breakdown of the capacitor element 655.

[0260] Note that examples of insulators made of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0261] Alternatively, the insulator 686 may use, for example, a single layer or a laminate of an insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST). For example, when the insulator 686 is a laminate, a three-layer laminate formed in order of zirconium oxide, aluminum oxide, and zirconium oxide, or a four-layer laminate formed in order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide may be used. Also, as the insulator 686, a compound containing hafnium and zirconium may be used. As the semiconductor device is miniaturized and highly integrated, problems such as leakage current in transistors and capacitor elements may occur due to thinning of the gate insulator and the dielectric used in the capacitor element. By using a high-k material for the gate insulator and the insulator that functions as the dielectric used in the capacitor element, it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitor element while maintaining the physical film thickness.

[0262] On one hand, examples of materials with high dielectric breakdown strength (materials with low relative permittivity) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resins.

[0263] The conductor 656 is arranged so as to overlap at least a part of the conductor 646a via the insulator 686. The conductor 656 may be a conductor that can be used for the conductor 646.

[0264] Also, it is preferable to provide an insulator 688 that functions as an interlayer film on the insulator 686 and the conductor 646b. Similar to the insulator 624, etc., it is preferable that the insulator 688 has a reduced concentration of impurities such as water or hydrogen in the film.

[0265] <<Modified Example of Memory Circuit>> Hereinafter, a modified example of the memory circuit will be described with reference to FIGS. 21A and 21B. FIG. 21A is a top view of the periphery of the memory circuit 860. FIG. 21B is a cross-sectional view of the memory circuit 860, and FIG. 21B corresponds to the part indicated by the dashed line A1 - A2 in FIG. 21A. In FIG. 21B, a cross-section in the channel length direction of the transistor 600 and a cross-section in the channel width direction of the transistor 700 are shown. In the top view of FIG. 21A, some elements are omitted for clarity of the figure. The X direction, Y direction, and Z direction shown in FIG. 21A are directions that are orthogonal or intersect with each other. Here, the X direction and Y direction are preferably parallel or substantially parallel to the substrate surface, and the Z direction is preferably perpendicular or substantially perpendicular to the substrate surface.

[0266] The memory circuit 860 shown in FIGS. 21A and 21B is different from the memory circuit 860 shown in FIGS. 20A and 20B in that transistors 690 and 790 are used instead of transistors 600 and 700. Here, transistor 790 is formed in the same layer as transistor 690 and has a similar configuration. In the following, it is assumed that the components of transistor 790 can refer to the description of the components of transistor 690.

[0267] Transistor 690 is different from transistor 600 in that oxide 630c is formed in a U - Shape along the openings formed in insulator 680, insulator 672, insulator 673, conductor 642 (conductor 642a, conductor 642b), and oxide 630b.

[0268] For example, when the channel length of the transistor is miniaturized (typically 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), since transistor 600 has the above structure, the effective L length can be increased. As an example, when the distance between conductor 642a and conductor 642b is 20 nm, the effective L length can be made 40 nm or more and 60 nm or less, which is about 2 times or more and 3 times or less longer than the distance between conductor 642a and conductor 642b, that is, the minimum processing dimension. Therefore, the memory circuit 860 shown in FIGS. 21A and 21B has a structure having transistors 690, 790, and capacitor element 655 that are excellent in miniaturization.

[0269] <<Metal Oxide>> As oxide 630, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxides applicable to oxide 630 according to the present invention will be described.

[0270] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

[0271] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Applicable elements for other element Ms include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0272] In this specification, etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0273] [Composition of Metal Oxide] Here, as a configuration example of the metal oxide, CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) or CAC-metal oxide will be described.

[0274] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is the function of allowing electrons (or holes) serving as carriers to flow, and the insulating function is the function of not allowing electrons serving as carriers to flow. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be enhanced to the maximum extent.

[0275] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0276] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0277] In addition, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide bandgap due to an insulating region and a component having a narrow bandgap due to a conductive region. In such a configuration, when carriers flow, the carriers mainly flow in the component having the narrow bandgap. Further, the component having the narrow bandgap acts complementarily to the component having the wide bandgap, and carriers also flow in the component having the wide bandgap in conjunction with the component having the narrow bandgap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0278] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0279] [Structure of Metal Oxide] Oxide semiconductors (metal oxides) can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0280] In addition, when focusing on the crystal structure, the classification of oxide semiconductors may be different from the above. Here, the classification of the crystal structure in oxide semiconductors will be described with reference to FIG. 26A. FIG. 26A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0281] As shown in FIG. 26A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. Further, completely amorphous is included in Amorphous. Further, CAAC, nc, and CAC are included in Crystalline. Further, single crystal and poly crystal are included in Crystal.

[0282] Note that the structure within the thick frame shown in FIG. 26A belongs to the New crystalline phase. This structure is in the boundary region between Amorphous and Crystal. That is, it can be rephrased as a structure completely different from the energetically unstable Amorphous and Crystalline.

[0283] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) image. Here, the XRD spectra of quartz glass and IGZO having a crystal structure classified as Crystalline (also referred to as crystalline IGZO) are shown in FIGS. 26B and 26C. Further, FIG. 26B is the XRD spectrum of quartz glass, and FIG. 26C is the XRD spectrum of crystalline IGZO. Note that the crystalline IGZO shown in FIG. 26C has a composition of In:Ga:Zn = 4:2:3 [atomic ratio]. Further, the crystalline IGZO shown in FIG. 26C has a thickness of 500 nm.

[0284] As shown by the arrow in FIG. 26B, the XRD spectrum peak of quartz glass is almost symmetric. On the other hand, as shown by the arrow in FIG. 26C, the XRD spectrum peak of crystalline IGZO is asymmetric. The asymmetry of the XRD spectrum peak indicates the presence of crystals. In other words, if the peak of the XRD spectrum is not symmetric, it cannot be said to be Amorphous.

[0285] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. Note that the strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

[0286] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. Note that in CAAC-OS, it is difficult to confirm a clear grain boundary (also called a grain boundary) even in the vicinity of the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0287] Note that a crystal structure in which a clear grain boundary (grain boundary) is confirmed is called a so-called polycrystal. Grain boundaries become recombination centers, and carriers are likely to be captured, causing a decrease in the on-current of the transistor or a decrease in the field-effect mobility. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0288] In addition, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. Further, when indium in the In layer is substituted with element M, it can also be expressed as an (In,M) layer.

[0289] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm distinct grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. In addition, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0290] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0291] Note that In-Ga-Zn oxide (hereinafter referred to as IGZO), which is a type of metal oxide containing indium, gallium, and zinc, may have a stable structure by using the above-described nanocrystals. In particular, since IGZO tends to be difficult to grow crystals in the air, a crystal smaller than a large crystal (here, a crystal of several mm or a crystal of several cm), for example, the above-described nanocrystal, may be structurally more stable.

[0292] The a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0293] Oxide semiconductors (metal oxides) have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0294] [Impurities] Here, the influence of each impurity in the metal oxide will be described.

[0295] When impurities are mixed into the oxide semiconductor, defect levels or oxygen deficiencies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are likely to fluctuate, and the reliability may deteriorate. Further, when the channel formation region contains oxygen deficiencies, the transistor is likely to have normally-on characteristics.

[0296] Further, the defect levels may include trap levels. The charge trapped in the trap levels of the metal oxide may take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a metal oxide with a high trap level density in the channel formation region may have unstable electrical characteristics.

[0297] Further, when impurities are present in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region may be lowered, and the crystallinity of the oxide provided in contact with the channel formation region may also be lowered. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to deteriorate. Further, when the crystallinity of the oxide provided in contact with the channel formation region is low, interface levels are formed, and the stability or reliability of the transistor may deteriorate.

[0298] Therefore, in order to improve the stability or reliability of the transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and in the vicinity thereof. Examples of the impurity include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0299] Specifically, in the channel formation region of the oxide semiconductor and in the vicinity thereof, the concentration of the above-described impurity obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Alternatively, in the channel formation region of the oxide semiconductor and in the vicinity thereof, the concentration of the above-described impurity obtained by elemental analysis using EDX is set to 1.0 atomic% or less. When an oxide containing element M is used as the oxide semiconductor, in the channel formation region of the oxide semiconductor and in the vicinity thereof, the concentration ratio of the above-described impurity to element M is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used when calculating the above-described concentration ratio may be the concentration in the same region as the region where the concentration of the above-described impurity is calculated, or the concentration in the oxide semiconductor.

[0300] In addition, since the metal oxide with a reduced impurity concentration has a low defect level density, the trap level density may also be low.

[0301] In addition, when hydrogen enters the oxygen deficiency in the metal oxide, oxygen deficiency and hydrogen may combine to form V O H. V O H may function as a donor and electrons as carriers may be generated. In addition, part of the hydrogen may combine with oxygen that binds to the metal atom to generate electrons as carriers.

[0302] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. In addition, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.

[0303] That is, V in the metal oxide O It is preferable to reduce H as much as possible to achieve high-purity intrinsic or substantially high-purity intrinsic. In this way, in order to obtain an oxide semiconductor with sufficiently reduced V O H, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (which may be described as dehydration or dehydrogenation treatment), and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (which may be described as oxygen addition treatment). V O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0304] In addition, it is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. When reducing the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0305] In particular, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, a defect in which hydrogen enters an oxygen vacancy may function as a donor, and electrons as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0306] A defect (V O H) in which hydrogen enters an oxygen vacancy may function as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate such a defect. Therefore, in an oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, carrier concentration assuming a state where no electric field is applied may be used as a parameter of the oxide semiconductor. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0307] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0308] In addition, the carrier concentration of the oxide semiconductor in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 even more preferably less than 1×10 16 cm -3 even more preferably less than 1×10 13 cm -3 even more preferably less than 1×10 12 cm -3 even more preferably less than. Note that the lower limit value of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but for example, it can be 1×10 -9 cm -3 .

[0309] According to one aspect of the present invention, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Further, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Further, one aspect of the present invention aims to provide a low-power consumption semiconductor device.

[0310] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 630 is not limited to the above-described metal oxide. As the oxide 630, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0311] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0312] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogen is a general term for elements belonging to Group 16 and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0313] As the oxide 630, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as the oxide 630 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0314] <Configuration Example of Memory Circuit Arrangement> Next, an example of the arrangement of the above-described memory circuit 860 will be described with reference to FIGS. 22 and 23. FIGS. 22 and 23 show a memory circuit block in which 2×2×2 memory circuits 860 are arranged. FIG. 22 is a top view of the memory circuit block. FIG. 23 is a cross-sectional view of the memory circuit block, and FIG. 23 corresponds to the portion indicated by the one-dot chain line B1 - B2 in FIG. 22. In FIG. 23, a cross-section in the channel length direction of the transistor 600 and a cross-section in the channel width direction of the transistor 700 are shown. Note that in the top view of FIG. 22, some elements are omitted for clarity of the drawing. The X direction, Y direction, and Z direction shown in FIG. 22 are directions that are orthogonal or intersect with each other. Here, it is preferable that the X direction and Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0315] In the memory circuit block shown in FIGS. 22 and 23, a memory circuit 860_2 is arranged adjacent to the memory circuit 860_1 in the X direction. Further, memory circuits 860_3 and 860_4 are arranged adjacent to the memory circuit 860_1 and the memory circuit 860_2 in the Y direction. Further, memory circuits 860_5 and 860_6 are arranged adjacent to the memory circuit 860_1 and the memory circuit 860_2 in the Z direction.

[0316] As shown in FIGS. 22 and 23, the memory circuit 860_1 and the memory circuit 860_2 can arrange their respective components in line symmetry. At this time, it is preferable that the side surface of the conductor 640b is in contact with the conductor 642b of the memory circuit 860_1 and the conductor 642b of the memory circuit 860_2. That is, it is preferable that the conductors 607, 615, 640b, 646b, and 657 that function as bit lines WBL are electrically connected to one of the source and drain of the transistor 600 in the memory circuit 860_1 and one of the source and drain of the transistor 600 in the memory circuit 860_2. In this way, by sharing the wiring connecting the memory circuit 860_1 and the memory circuit 860_2, the occupied area of the memory circuit can be further reduced.

[0317] Also, as shown in FIG. 23, conductors 607, 615, 640b, 646b, and 657 that function as write bit lines WBL are also electrically connected to transistors 600 of memory circuits 860_5 and 860_6 disposed in the upper layer. As shown in FIG. 23, conductor 657 of memory circuits 860_1 and 860_2 corresponds to conductor 607 of memory circuits 860_5 and 860_6. In this way, the bit line WBL can be extended in the Z direction. Although not shown in a cross-sectional view, conductors 640d and the like that function as read bit lines RBL can also be extended in the Z direction in the same manner.

[0318] Also, as shown in FIG. 22, conductor 660 of memory circuit 860_1 extends to memory circuit 860_3. In this way, the word line WWL can be extended in the Y direction. Also, as shown in FIG. 22, conductor 742a of memory circuit 860_1 extends to memory circuit 860_3. In this way, the selection line SL can be extended in the Y direction. Note that the selection line SL may be shared with memory circuits 860 adjacent in the X direction. Also, as shown in FIG. 22, conductor 605 of memory circuit 860_1 extends to memory circuit 860_3. In this way, the wiring BGL1 can be extended in the Y direction. Also, as shown in FIG. 22, conductor 705 of memory circuit 860_1 extends to memory circuit 860_3. In this way, the wiring BGL1 can be extended in the Y direction.

[0319] Note that in FIG. 22, the oxide 630c is configured to extend over the conductor 660, but the semiconductor device shown in this embodiment is not limited to this. For example, the oxide 630c may be patterned for each memory circuit 860, and the oxide 630c may be provided separately for each transistor 600. Further, for example, when the oxide 630c has a two-layer stacked structure, either the upper layer or the lower layer of the oxide 630c may be provided separately for each transistor 600.

[0320] <Configuration Example of Semiconductor Device> Next, an example of a semiconductor device in which the above-described memory circuits 860 are stacked will be described with reference to FIG. 24. FIG. 24 is a cross-sectional view of a semiconductor device in which a plurality of memory circuit layers 870 including memory circuits 860 are stacked on a silicon layer 871. The semiconductor device shown in FIG. 24 corresponds to the accelerator 20 shown in FIG. 1 and the like. The silicon layer 871 corresponds to the arithmetic processing unit 21, and the memory circuit layer 870 corresponds to the memory unit 22.

[0321] First, the silicon layer 871 will be described. A plurality of transistors 800 are provided in the silicon layer 871 and constitute the arithmetic circuit 23 and the like shown in FIG. 1 and the like.

[0322] The transistor 800 is provided on a substrate 811 and has a conductor 816 that functions as a gate, an insulator 815 that functions as a gate insulator, a semiconductor region 813 that is part of the substrate 811, and low-resistance regions 814a and 814b that function as a source region or a drain region. The transistor 800 may be either p-channel type or n-channel type.

[0323] Here, in the transistor 800 shown in FIG. 24, the semiconductor region 813 (a part of the substrate 811) where the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 813 are covered with a conductor 816 via an insulator 815. Note that the conductor 816 may be made of a material for adjusting the work function. Since such a transistor 800 utilizes the convex portion of the semiconductor substrate, it is also called a FIN type transistor. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Here, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown, an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0324] Note that the transistor 800 shown in FIG. 24 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0325] Further, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the respective structures. Also, a plurality of wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0326] For example, on the transistor 800, as an interlayer film, an insulator 820, an insulator 822, an insulator 824, and an insulator 826 are laminated and provided in this order. Also, conductors 828, 830, etc. that function as plugs or wiring are embedded in the insulator 820, the insulator 822, the insulator 824, and the insulator 826.

[0327] Further, the insulator that functions as an interlayer film may function as a planarization film that covers the uneven shape below it. For example, the upper surface of the insulator 822 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0328] A wiring layer may be provided on the insulator 826 and the conductor 830. For example, in FIG. 24, the insulators 850, 852, and 854 are sequentially stacked and provided. Further, a conductor 856 is formed on the insulators 850, 852, and 854. The conductor 856 functions as a plug or wiring.

[0329] Examples of insulators that can be used as interlayer dielectrics include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

[0330] For example, by using a material with a low relative permittivity for the insulator that functions as an interlayer dielectric, the parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0331] For example, it is preferable that the insulators 820, 822, 826, 852, 854, etc. have an insulator with a low relative permittivity. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride are thermally stable, a thermally stable and low relative permittivity laminated structure can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0332] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 824, the insulator 850, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0333] As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminated form. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride, etc. can be used.

[0334] As the conductor that can be used for wiring and plugs, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0335] For example, as the conductor 828, conductor 830, conductor 856, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used alone or in a stacked manner. It is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0336] On the silicon layer 871, the insulator 611 and the insulator 612 are disposed, and on the insulator 611 and the insulator 612, the memory circuit layers 870_1 to 870_n are stacked. Note that the value of n is not particularly limited, but is 2 or more and 200 or less, preferably 2 or more and 100 or less, and more preferably 2 or more and 10 or less. For example, 1 ≦ n ≦ 10, preferably 1 ≦ n ≦ 50, and more preferably 1 ≦ n ≦ 100 may be used.

[0337] In each memory circuit layer 870, as in FIG. 22, the memory circuit 860 and various wirings are arranged in a matrix. Also, as shown in FIG. 23, the adjacent memory circuit layers 870 in the stacking direction are electrically connected by wirings such as write bit lines WBL.

[0338] Also, as shown in FIG. 24, in the lowermost memory circuit layer 870_1, the conductor 607 is disposed so as to be embedded in the insulator 611 and the insulator 612. The conductor 607 is in contact with the conductor 857 provided in the same layer as the conductor 856.

[0339] Further, it is preferable that the memory circuit layers 870_1 to 870_n have a structure sealed by the insulators 611, 612, 687, 683, and 684. Here, the insulator 611 is disposed on the silicon layer 871, and the insulator 612 is disposed on the insulator 611. The memory circuit layers 870_1 to 870_n are disposed on the insulator 612, and the insulator 612 is also formed in the same pattern as the memory circuit layers 870_1 to 870_n in a top view. The insulator 687 is disposed in contact with the upper surface of the insulator 611, the side surfaces of the insulator 612, and the side surfaces of the memory circuit layers 870_1 to 870_n. That is, the insulator 687 is formed in a sidewall shape with respect to the memory circuit layers 870_1 to 870_n. The insulator 683 is disposed so as to cover the insulator 611, the insulator 687, and the memory circuit layers 870_1 to 870_n. Further, the insulator 684 is disposed so as to cover the insulator 683.

[0340] It is preferable to use a barrier material for the insulators 611, 612, 687, 683, and 684, similar to the insulator 682 and the like.

[0341] Here, each memory circuit layer 870 is sealed by the insulators 687 and 683. It is preferable to use the same material for the insulators 687 and 683. Also, it is preferable to form the insulators 687 and 683 under the same conditions. By having the insulators 687 and 683 with equal film quality in contact with each other, a highly sealed structure can be obtained.

[0342] Further, it is preferable to use a material having a function of capturing and fixing hydrogen for the insulators 687 and 683. Specifically, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide can be used.

[0343] In addition, the insulator 687 and the insulator 683, which are structures for sealing the memory circuit layer 870, are further covered by the insulator 684.

[0344] It is preferable to use materials having a function of suppressing diffusion with respect to hydrogen and oxygen for the insulator 611, the insulator 612, and the insulator 683. In particular, since silicon nitride or silicon oxynitride has a high barrier property against hydrogen, it is preferably used as a sealing material.

[0345] In addition, it is preferable to provide an insulator 684 having high covering property above the insulator 683 covering above the transistor 600. Note that it is preferable to use the same material for the insulator 684 as that for the insulator 612 and the insulator 683.

[0346] For example, by forming the insulator 612 and the insulator 683 by a sputtering method, a sealing structure can be provided with a film having a relatively low hydrogen concentration in the film.

[0347] On the other hand, a film formed by a sputtering method has relatively low covering property. Therefore, by forming the insulator 611 and the insulator 684 by using a CVD method or the like having high covering property, the sealing property can be further enhanced.

[0348] Therefore, it is preferable that the insulator 612 and the insulator 683 have a lower hydrogen concentration than the insulator 611 and the insulator 684.

[0349] As described above, by sealing the memory circuit layers 870_1 to 870_n with a barrier insulating film, hydrogen diffusing into the oxide semiconductor included in each memory circuit 860 can be reduced, so that a highly reliable memory device can be provided.

[0350] Preferably, the insulators 611, 612, 682, 687, 683, and 684 may be made of a material having oxygen barrier properties. Since the encapsulation structure has oxygen barrier properties, outward diffusion of excess oxygen in the insulator 680 can be suppressed, and it can be efficiently supplied to the transistor 600.

[0351] Further, it is preferable that the insulator 674 is provided so as to embed the memory circuit layers 870_1 to 870_n and the insulator 684. The insulator 674 may be made of an insulator that can be used for the insulator 680. As shown in FIG. 24, the upper surfaces of the insulator 674 and the insulator 684 preferably substantially coincide.

[0352] Also, as shown in FIG. 24, openings may be provided in the insulator 674, the insulator 684, the insulator 683, and the insulator 611, and the conductor 876 may be disposed in the openings. The lower surface of the conductor 876 is in contact with the conductor 856. A conductor 878 that functions as a wiring may be provided in contact with the upper surface of the conductor 876. Further, it is preferable to provide an insulator 689 that functions as an interlayer film to cover the memory circuit layer 870_n, the insulator 674, and the conductor 878. With such a structure, the circuit of the upper-layer wiring (conductor 878) and the silicon layer 871 can be electrically connected without passing through the memory circuit layer 870.

[0353] In FIG. 24, a configuration is shown in which the memory circuit layers 870_1 to 870_n are collectively encapsulated by the insulators 611, 612, 687, 683, and 684, but the semiconductor device according to the present embodiment is not limited to this. For example, as shown in FIG. 25, each memory circuit layer 870 may be encapsulated by the insulators 611, 612, 687, 683, and 684.

[0354] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0355] (Embodiment 5) In this embodiment, the configuration of the integrated circuit including the configuration of the semiconductor device 100 described in the above embodiment will be described with reference to FIGS. 27 and 28.

[0356] FIG. 27 is an example of a block diagram for explaining a configuration example of an integrated circuit including the configuration of the semiconductor device 100.

[0357] The integrated circuit 390 illustrated in FIG. 27 includes a CPU 10, an accelerator 20, an on-chip memory 131, a DMAC (Direct Memory Access Controller) 141, a power supply circuit 160, a power management unit (PMU) 142, a security circuit 147, a memory controller 143, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) controller 144, a USB (Universal Serial Bus) interface circuit 145, a display interface circuit 146, a bridge circuit 150, an interrupt control circuit 151, an interface circuit 152, a battery control circuit 153, and an ADC (Analog-to-digital converter) / DAC (Digital-to-analog converter) interface circuit 154.

[0358] The CPU 10 includes, as an example, a CPU core 111, an instruction cache 112, a data cache 113, and a bus interface circuit 114. The accelerator 20 includes a memory circuit 121, an arithmetic circuit 122, and a control circuit 123.

[0359] The CPU core 111 has a plurality of CPU cores. The instruction cache 112 may be a circuit configuration that temporarily stores instructions to be executed by the CPU core 111. The data cache 113 may be a circuit configuration that temporarily stores data to be processed by the CPU core 111 or data obtained by the processing. The bus interface circuit 114 may be any circuit configuration that can transmit and receive signals such as data and addresses to and from a bus for connecting the CPU 10 and other circuits within the semiconductor device.

[0360] The memory circuit 121 corresponds to the configuration including the memory circuit 24 described in the first embodiment. The memory circuit 121 may be a circuit configuration that stores data to be processed by the accelerator 20. The arithmetic circuit 122 corresponds to the configuration including the arithmetic circuit 23 described in the first embodiment. The arithmetic circuit 122 may be a circuit configuration that performs arithmetic processing on the data held in the memory circuit 121. The control circuit 123 may be a circuit configuration for controlling each circuit within the accelerator 20 as illustrated in FIG. 14B.

[0361] The high-speed bus 140A is a bus for transmitting and receiving various signals at high speed among the CPU 10, the accelerator 20, the on-chip memory 131, the DMAC 141, the power management unit 142, the security circuit 147, the memory controller 143, the DDR SDRAM controller 144, the USB interface circuit 145, and the display interface circuit 146. As an example, AMBA (Advanced Microcontoroller Bus Artcitecture)-AHB (Advanced High-perfermance Bus) can be used as the bus.

[0362] The on-chip memory 131 has a circuit configuration of a circuit included in the integrated circuit 390, for example, for storing data or programs input to and output from the CPU 10 or the accelerator 20.

[0363] DMAC141 is a direct memory access controller. By having DMAC141, peripheral devices other than CPU10 can access the on-chip memory 131 without going through CPU10.

[0364] The power management unit 142 has a circuit configuration for controlling the power gating of circuits such as the CPU core included in the integrated circuit 390.

[0365] The security circuit 147 has a circuit configuration for enhancing the confidentiality of signals, such as encrypting and transmitting / receiving signals between the integrated circuit 390 and external circuits.

[0366] The memory controller 143 has a circuit configuration for writing or reading a program to be executed by the CPU10 or the accelerator 20 from a program memory external to the integrated circuit 390.

[0367] The DDR SDRAM controller 144 has a circuit configuration for writing or reading data to / from a main memory such as a DRAM external to the integrated circuit 390.

[0368] The USB interface circuit 145 has a circuit configuration for transmitting and receiving data with an external circuit of the integrated circuit 390 via a USB terminal.

[0369] The display interface circuit 146 has a circuit configuration for transmitting and receiving data with a display device external to the integrated circuit 390.

[0370] The power supply circuit 160 is a circuit for generating the voltage used within the integrated circuit 390. For example, it is a circuit for generating a negative voltage for stabilizing the electrical characteristics applied to the back gate of an OS transistor.

[0371] The low-speed bus 140B is a bus for transmitting and receiving various signals at a low speed among the interrupt control circuit 151, the interface circuit 152, the battery control circuit 153, and the ADC / DAC interface circuit 154. As an example, AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Transmission and reception of various signals between the high-speed bus 140A and the low-speed bus 140B are performed via the bridge circuit 150.

[0372] The interrupt control circuit 151 has a circuit configuration for performing interrupt processing in response to requests received from peripheral devices.

[0373] The interface circuit 152 has a circuit configuration for enabling interfaces such as UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface).

[0374] The battery control circuit 153 has a circuit configuration for transmitting and receiving data related to charging and discharging of a battery outside the integrated circuit 390.

[0375] The ADC / DAC interface circuit 154 has a circuit configuration for transmitting and receiving data with a device that outputs an analog signal such as a MEMS (Micro Electro Mechanical Systems) device outside the integrated circuit 390.

[0376] FIG. 28A and FIG. 28B are diagrams showing an example of the arrangement of circuit blocks when integrated into an SoC. Each configuration illustrated in the block diagram of FIG. 27, such as the integrated circuit 390 illustrated in FIG. 28A, can be arranged by dividing regions on the chip.

[0377] The on-chip memory 131 described with reference to FIG. 27 can be configured by a memory circuit composed of OS transistors, such as NOSRAM or the like. That is, the on-chip memory 131 and the memory circuit 121 have the same circuit configuration. Therefore, when integrated into a SoC, it is possible to integrate the on-chip memory 131 and the memory circuit 121 and arrange them in the same region as in the integrated circuit 390E shown in FIG. 28B.

[0378] According to one aspect of the present invention described above, a novel semiconductor device and an electronic device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device and an electronic device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device and an electronic device capable of suppressing heat generation can be provided.

[0379] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0380] (Embodiment 6) In this embodiment, an electronic device, a mobile body, and an arithmetic system to which the integrated circuit 390 described in the above embodiment can be applied will be described with reference to FIGS. 29A to 32.

[0381] FIG. 29A shows an external view of an automobile as an example of a mobile body. FIG. 29B is a simplified diagram of data exchange inside the automobile. The automobile 590 has a plurality of cameras 591 and the like. In addition, the automobile 590 is equipped with various sensors (not shown) such as an infrared radar, a millimeter-wave radar, and a laser radar.

[0382] In the vehicle 590, the integrated circuit 390 can be used in a camera 591 or the like. The vehicle 590 processes a plurality of images obtained by the camera 591 in a plurality of imaging directions 592 with the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images together by a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, and enabling autonomous driving. Further, it can be used in a system for performing road guidance, danger prediction, and the like.

[0383] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processes such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (widening the dynamic range), image restoration of a lensless image sensor, positioning, character recognition, and reducing reflection glare can be performed.

[0384] Note that in the above description, a vehicle has been described as an example of a moving body, but the moving body is not limited to a vehicle. For example, examples of the moving body include trains, monorails, ships, flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. The computer according to one aspect of the present invention can be applied to these moving bodies to provide a system utilizing artificial intelligence.

[0385] FIG. 30A is an external view showing an example of a portable electronic device. FIG. 30B is a diagram simplifying the data exchange in the portable electronic device. The portable electronic device 595 includes a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0386] In the portable electronic device 595, the integrated circuit 390 can be provided on the printed wiring board 596. The portable electronic device 595 can improve the convenience for the user by processing and analyzing a plurality of data obtained from a speaker 597, a camera 598, a microphone 599, etc. using the integrated circuit 390 described in the above embodiment. Further, it can be used in a system for performing voice guidance, image search, etc.

[0387] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of an image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (increasing the dynamic range), image restoration of a lensless image sensor, positioning, character recognition, and reducing specular reflection can be performed.

[0388] The portable game machine 1100 shown in FIG. 31A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, etc. The housing 1101, the housing 1102, and the housing 1103 can be removed. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housing 1102 and the housing 1103 to the housing 1109, the housing 1102 and the housing 1103 are integrated and function as an operation unit. The integrated circuit 390 shown in the previous embodiment can be incorporated into chips etc. provided on the substrates of the housing 1102 and the housing 1103.

[0389] FIG. 31B shows a USB connection type stick-shaped electronic device 1120. The electronic device 1120 includes a housing 1121, a cap 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the substrate 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 etc. of the substrate 1124.

[0390] FIG. 31C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0391] Instead of being incorporated into an electronic device, the integrated circuit 390 described in the above embodiment can also be used in a server that communicates with the electronic device. In this case, an operation system is configured by the electronic device and the server. FIG. 32 shows a configuration example of the system 3000.

[0392] The system 3000 is composed of an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via the Internet line 3003.

[0393] The server 3002 has a plurality of racks 3004. A plurality of substrates 3005 are provided on the plurality of racks, and the integrated circuit 390 described in the above embodiment can be mounted on the substrate 3005. Thereby, a neural network is configured in the server 3002. Then, the server 3002 can perform neural network operations using the data input from the electronic device 3001 via the Internet line 3003. The result of the operation by the server 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as needed. Thereby, the operation load on the electronic device 3001 can be reduced.

[0394] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0395] (Supplementary Note Regarding the Descriptions in this Specification, etc.) Regarding the above embodiments and the descriptions of each configuration in the embodiments, the following supplementary notes are provided.

[0396] The configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments or examples to form an aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to combine the configuration examples as appropriate.

[0397] Note that the content described in one embodiment (even part of the content) can be applied, combined, or replaced with respect to other content (even part of the content) described in that embodiment and / or content (even part of the content) described in one or more other embodiments.

[0398] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0399] Note that the figure (even part of it) described in one embodiment can be combined with another part of that figure, another figure (even part of it) described in that embodiment, and / or a figure (even part of it) described in one or more other embodiments to form even more figures.

[0400] Also, in this specification and the like, in the block diagram, the components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components by function, and there may be cases where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0401] In the drawings, the size, layer thickness, or area are shown in arbitrary sizes for convenience of explanation. Therefore, it is not necessarily limited to that scale. The drawings are schematically shown for clarity and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0402] Also, in the drawings and the like, the positional relationship of the components shown is relative. Therefore, when explaining the components with reference to the drawings, terms such as "above" and "below" indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description in this specification and can be appropriately rephrased according to the situation.

[0403] In this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source and drain" (or the second electrode, or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the naming of the source and drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode.

[0404] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" or "wirings" are integrally formed.

[0405] Also, in this specification and the like, voltage and potential can be appropriately rephrased. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground voltage (earthing voltage), the voltage can be rephrased as potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to wiring or the like may change.

[0406] Also, in this specification and the like, a node can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. according to the circuit configuration, device structure, etc. Also, it is possible to rephrase a terminal, wiring, etc. as a node.

[0407] In this specification and the like, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection where an object (such as an element like a switch, transistor element, or diode, or a circuit including the element and wiring) exists between A and B and electrical signal transmission between A and B is possible. Note that when A and B are electrically connected, it includes the case where A and B are directly connected. Here, "A and B are directly connected" means a connection where electrical signal transmission between A and B is possible via wiring (or an electrode) etc. without passing through the above object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0408] In this specification and the like, a switch is something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch is something that has a function of selecting and switching the path through which current flows.

[0409] In this specification and the like, the channel length refers to, for example, in the top view of a transistor, the distance between the source and the drain in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate overlap, or in the region where the channel is formed.

[0410] In this specification and the like, the channel width refers to, for example, the length of the portion where the source and the drain face each other in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed.

[0411] Note that in this specification and the like, terms such as "film" and "layer" can be interchanged with each other in some cases or depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film" in some cases. Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases.

Explanation of Reference Numerals

[0412] BGL1: Wiring, C11: Capacitor Element, CK1: Node, D1: Node, GCLK1: Clock Signal, I1: Input Layer, M1: Intermediate Layer, M3: Intermediate Layer, M11: Transistor, M12: Transistor, M13: Transistor, O1: Output Layer, PSE0: Signal, PSE1: Signal, PSE2: Signal, Q_N: Output Signal, Q_1: Output Signal, Q1: Node, RBL_N: Read Bit Line, RBL_1: Read Bit Line, RWL_M: Read Word Line, RWL_1: Read Word Line, SLEEP1: Signal, SN11: Node, SW_N: Switch, SW_1: Switch, SW1: Transistor, t1: Time, t2: Time, t3: Time, t4: Time, t5: Time, t6: Time, t7: Time, WBL_1: Write Bit Line, WWL_M: Write Word Line, WWL_1: Write Word Line, 10: CPU, 20: Accelerator, 21: Arithmetic Processing Unit, 22: Memory Unit, 22_N: Memory Circuit Layer, 22_1: Memory Circuit Layer, 22_2: Memory Circuit Layer, 23: Arithmetic Circuit, 23_N: Arithmetic Circuit, 23_1: Arithmetic Circuit, 24: Memory Circuit, 24_N: Memory Circuit, 24_P: Memory Circuit, 24A: Memory Circuit, 24B: Memory Circuit, 24C: Memory Circuit, 24D: Memory Circuit, 24E: Memory Circuit, 25: Transistor, 25_N: Transistor, 25_P: Transistor, 25A: Transistor, 25B: Transistor, 26: Transistor, 26_N: Transistor, 26_P: Transistor, 26B: Transistor, 27: Transistor, 27_N: Transistor, 27_P: Transistor, 28: Capacitor Element, 28_N: Capacitor Element, 28_P: Capacitor Element, 28A: Capacitor Element, 28B: Capacitor Element, 29: Semiconductor Layer, 30: Bus, 31: Wiring, 32: Transistor, 33A: Transistor, 33B: Transistor, 34: Antenna, 35: Drive Circuit, 36A: Insulator, 36B: Insulator, 41: Read Circuit, 42: Bit Multiplication and Summation Unit, 43: Accumulator, 44: Latch Circuit, 45: Encoding Circuit, 46: Inverter Circuit, 47: Logic Circuit, 50: Neuron, 51: Layer, 52: Layer, 53: Layer, 54: Layer, 61: Controller, 62: Row Decoder, 63: Word Line Driver, 64: Column Decoder, 65: Driver, 66: Precharge Circuit, 67: Sense Amplifier, 68: Selector, 71: Input Buffer, 72: Arithmetic Control Circuit, 76: WA,100: Semiconductor device, 110: Drive circuit layer, 111: CPU core, 112: Instruction cache, 113: Data cache, 114: Bus interface circuit, 121: Memory circuit, 122: Arithmetic circuit, 123: Control circuit, 131: On-chip memory, 140A: High-speed bus, 140B: Low-speed bus, 141: DMAC, 142: Power management unit, 143: Memory controller, 144: Controller, 145: Interface circuit, 146: Display interface circuit, 147: Security circuit, 150: Bridge circuit, 151: Control circuit, 152: Interface circuit, 153: Battery control circuit, 154: Interface circuit, 160: Power supply circuit, 193: PMU, 200: CPU core, 202: Cache memory device, 203: Cache memory device, 205: Bus interface section, 210: Power switch, 211: Power switch, 212: Power switch, 214: Level shifter, 220: Flip-flop, 221: Scan flip-flop, 221A: Clock buffer circuit, 222: Backup circuit, 390: Integrated circuit, 390E: Integrated circuit, 590: Automobile, 591: Camera, 592: Imaging direction, 593: Bus, 594: Host controller, 595: Portable electronic device, 596: Printed wiring board, 597: Speaker, 598: Camera, 599: Microphone, 600: Transistor, 605: Conductor, 605a: Conductor, 605b: Conductor, 607: Conductor, 611: Insulator, 612: Insulator, 614: Insulator, 615: Conductor, 616: Insulator, 622: Insulator, 624: Insulator, 630: Oxide, 630a: Oxide, 630b: Oxide, 630c: Oxide, 640: Conductor, 640a: Conductor, 640b: Conductor, 640c: Conductor, 640d: Conductor, 642: Conductor, 642a: Conductor, 642b: Conductor, 643: Oxide, 643a: Oxide, 643b: Oxide, 646: Conductor, 646a: Conductor, 646b: Conductor, 650: Insulator, 655: Capacitor element, 656: Conductor, 657: Conductor, 660: Conductor, 660a: Conductor, 660b: Conductor, 672: Insulator, 673: Insulator, 674: Insulator, 680: Insulator, 682: Insulator, 683: Insulator, 684: Insulator, 685: Insulator, 686: Insulator, 687: Insulator,688: Insulator, 689: Insulator, 690: Transistor, 700: Transistor, 705: Conductor, 705a: Conductor, 705b: Conductor, 715: Conductor, 730: Oxide, 730a: Oxide, 730b: Oxide, 730c: Oxide, 742: Conductor, 742a: Conductor, 742b: Conductor, 743: Oxide, 743a: Oxide, 743b: Oxide, 750: Insulator, 760: Conductor, 760a: Conductor, 760b: Conductor, 790: Transistor, 800: Transistor, 811: Substrate, 813: Semiconductor region, 814a: Low-resistance region, 814b: Low-resistance region, 815: Insulator, 816: Conductor, 820: Insulator, 822: Insulator, 824: Insulator, 826: Insulator, 828: Conductor, 830: Conductor, 850: Insulator, 852: Insulator, 854: Insulator, 856: Conductor, 857: Conductor, 860: Memory circuit, 860_1: Memory circuit, 860_2: Memory circuit, 860_3: Memory circuit, 860_4: Memory circuit, 860_5: Memory circuit, 860_6: Memory circuit, 870: Memory circuit layer, 870_n: Memory circuit layer, 870_1: Memory circuit layer, 871: Silicon layer, 876: Conductor, 878: Conductor, 1100: Portable game machine, 1101: Housing, 1102: Housing, 1103: Housing, 1104: Display unit, 1105: Connection part, 1107: Operation key, 1108: Housing, 1109: Housing, 1120: Electronic device, 1121: Housing, 1122: Cap, 1123: USB connector, 1124: Substrate, 1125: Memory chip, 1126: Controller chip, 1130: Robot, 2101: Sensor, 2106: Sensor, 2110: Control circuit, 3000: System, 3001: Electronic device, 3002: Server, 3003: Internet line, 3004: Rack, 3005: Substrate, 3210: WA, 7654: WA,

Claims

1. It has an accelerator, the accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit; the first memory circuit includes a first transistor; the second memory circuit includes a second transistor; each of the first transistor and the second transistor has a semiconductor layer having a metal oxide in a channel formation region; the arithmetic circuit includes a third transistor; the third transistor has a semiconductor layer having silicon in a channel formation region; a channel length direction of the transistor of the first memory circuit is parallel to an upper surface of a substrate; a channel length direction of the transistor of the second memory circuit is perpendicular to an upper surface of the substrate; a layer having the second transistor is provided on a layer having the first transistor; A semiconductor device, wherein a layer having the first transistor and a layer having the second transistor are provided on a layer having the third transistor.

2. In claim 1, The first memory circuit and the second memory circuit have a function of holding data input to the arithmetic circuit.

3. In claim 1 or 2, The second memory circuit has a circuit configuration different from that of the first memory circuit.

Images