Semiconductor storage device and control method thereof

Abstract

To provide a semiconductor storage device capable of reducing leakage current generated in a sense amplifier in a data retained state, and a control method thereof.SOLUTION: A semiconductor storage device includes: a sense amplifier 10 connected to a pair of bit lines BLT and BLB, which is a sense amplifier 10 including at least one of transistors 10a, 10b, 10c, and 10d connected to the bit line BLB on a low-voltage power side among the pair of bit lines BLT and BLB; and a control unit 20 that sets a voltage of the bit line BLB on the low-voltage power side to a predetermined voltage VBLL higher than a voltage VSS of the low voltage power in a state where a predetermined operation is not being performed and the sense amplifier 10 retains data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a control method thereof.

Background Art

[0002] For example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is configured to generate a weak potential difference between a pair of bit lines based on data held in a memory cell, and amplify this potential difference by a sense amplifier to read the data. As a general sense amplifier, one including a pair of N-channel field effect transistors (nMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)) and a pair of P-channel field effect transistors (pMOSFETs) is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Incidentally, the operating voltage of the semiconductor memory device has been lowered in response to the reduction of power consumption of the semiconductor memory device. Along with this reduction in the operating voltage, the threshold voltage of the transistors in the sense amplifier also decreases. Further, when the voltage of the bit line on the low-voltage power supply side among a pair of bit lines is set to 0V in a state where the sense amplifier holds data (the state after sensing the data), there exists a transistor in at least one transistor connected to the bit line on the low-voltage power supply side where the gate-source voltage becomes 0V. However, when the threshold voltage of the transistor decreases, there is a risk that the leakage current generated in the transistor where the gate-source voltage becomes 0V in the data holding state of the sense amplifier increases.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor memory device and a control method thereof capable of reducing the leakage current generated in a sense amplifier in a data holding state.

Means for Solving the Problems

[0006] In order to solve the above problems, the present invention provides a semiconductor memory device including: a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to the bit line on the low-voltage power supply side among the pair of bit lines; and a control unit configured to set the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply in a state where no predetermined operation is being performed and the sense amplifier is holding data.

[0007] According to such an invention, in a state where a predetermined operation is not being performed and the sense amplifier is holding data, by setting the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply, for example, when the voltage of the low-voltage power supply is 0V, the back gate-source voltage of a transistor whose gate-source voltage becomes 0V becomes a negative voltage, and since the threshold voltage of the transistor increases due to the back-bias effect, it becomes possible to reduce the leakage current generated in the transistor. Thereby, the leakage current generated in the sense amplifier in the data holding state can be reduced.

[0008] Further, the present invention is a control method for a semiconductor memory device, wherein the semiconductor memory device includes a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to the bit line on the low-voltage power supply side among the pair of bit lines, and a control unit of the semiconductor memory device, in a state where a predetermined operation is not being performed and the sense amplifier is holding data, executes a step of setting the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply, thereby providing a control method for a semiconductor memory device.

Effects of the Invention

[0009] According to the semiconductor memory device and its control method of the present invention, the leakage current generated in the sense amplifier in the data holding state can be reduced.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0011] FIG. 1 and FIG. 2 are diagrams showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. As shown in FIGS. 1 and 2, the semiconductor memory device includes at least one sense amplifier 10 connected to a pair of complementary bit lines BLT and BLB, and a control unit 20. In the present embodiment, for simplicity of explanation, detailed descriptions of other well-known configurations (for example, a power supply circuit, a command decoder, an address decoder, a clock generator, etc.) in the semiconductor memory device are omitted.

[0012] In the present embodiment, the case where the semiconductor memory device is a DRAM is described as an example, but the semiconductor memory device may be other semiconductor memory devices (for example, SRAM (Static Random Access Memory), flash memory, etc.).

[0013] The sense amplifier 10 is a cross-coupled latch type sense amplifier, and as shown in FIG. 1, includes a pair of P-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) 10a and 10b, and a pair of N-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) 10c and 10d. Here, the pMOSFETs 10a and 10b are an example of the "pair of first transistors" of the present invention, and the nMOSFETs 10c and 10d are an example of the "pair of second transistors" of the present invention.

[0014] Of the pair of pMOSFETs 10a and 10b, the source terminal of one pMOSFET 10a is connected to the node CSP on the high-voltage power supply side, the drain terminal is connected to the bit line BLT on the high-voltage power supply side, and the gate terminal is connected to the bit line BLB on the low-voltage power supply side. Also, of the pair of pMOSFETs 10a and 10b, the source terminal of the other pMOSFET 10b is connected to the node CSP on the high-voltage power supply side, the drain terminal is connected to the bit line BLB on the low-voltage power supply side, and the gate terminal is connected to the bit line BLT on the high-voltage power supply side. In this embodiment, as an example, the case where the voltage of the high-voltage power supply is 1V and the voltage VSS of the low-voltage power supply is 0V will be described.

[0015] Furthermore, of the pair of nMOSFETs 10c and 10d, the drain terminal of one nMOSFET 10c is connected to the bit line BLT on the high-voltage power supply side, the source terminal is connected to the node CSN on the low-voltage power supply side, and the gate terminal is connected to the bit line BLB on the low-voltage power supply side. Furthermore, of the pair of nMOSFETs 10c and 10d, the drain terminal of the other nMOSFET 10d is connected to the bit line BLB on the low-voltage power supply side, the source terminal is connected to the node CSN on the low-voltage power supply side, and the gate terminal is connected to the bit line BLT on the high-voltage power supply side.

[0016] Also, the bit line BLT on the high-voltage power supply side is connected to one of the pair of complementary local data lines LDQT and LDQB, i.e., the local data line LDQT, via an nMOSFET 10e to which a column selection signal CSL corresponding to a column address input from the outside is input to the gate terminal. Furthermore, the bit line BLB on the low-voltage power supply side is connected to the other local data line LDQB of the pair of complementary local data lines LDQT and LDQB via an nMOSFET 10f to which the column selection signal CSL is input to the gate terminal. Furthermore, a memory cell 11 is connected to the bit line BLB on the low-voltage power supply side. The memory cell 11 may have a well-known configuration including, for example, an nMOSFET 11a to which a row selection signal WL is input to the gate terminal and a capacitor 11b.

[0017] Note that the configuration of the sense amplifier 10 shown in FIG. 1 is an example, and the sense amplifier 10 may have other circuits (for example, an equalizer circuit or the like) not shown in FIG. 1.

[0018] Here, when the voltage of the bit line BLB on the low-voltage power supply side among the pair of bit lines BLT and BLB is set to 0V in a state where the sense amplifier 10 holds data (a state after sensing data), the gate-source voltage of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f becomes 0V. In this case, when the operating voltage of the semiconductor memory device decreases in response to power consumption reduction of the semiconductor memory device, the threshold voltages of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f also decrease, and there is a possibility that the leakage current generated in each of the pMOSFET 10b, nMOSFET 10c, and nMOSFET 10f increases in the data holding state of the sense amplifier. Therefore, in the present embodiment, in the data holding state of the sense amplifier, the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL higher than the voltage VSS (for example, 0V) of the low-voltage power supply.

[0019] With reference to FIG. 2, a configuration example of the control unit 20 will be described. The control unit 20 is configured to set the voltage of the bit line BLB on the low-voltage power supply side to a predetermined voltage VBLL higher than the voltage VSS of the low-voltage power supply in a state where no predetermined operation is being performed and the sense amplifier 10 holds data.

[0020] Further, when a predetermined operation is performed in a state where the voltage of the bit line BLB on the low-voltage power supply side is set to the predetermined voltage VBLL, the control unit 20 may set the voltage of the bit line BLB on the low-voltage power supply side to the voltage VSS of the low-voltage power supply. Thereby, since the voltage of the bit line BLB on the low-voltage power supply side is set to the voltage VSS when a predetermined operation is performed, it becomes possible to perform the predetermined operation normally.

[0021] Here, the predetermined operation may include reading, writing, and at least one of precharging of a pair of bit lines BLT and BLB, of the data stored in the memory cell 11 connected to the sense amplifier 10. Thereby, when at least one of reading, writing, and at least one of precharging of a pair of bit lines BLT and BLB of the data stored in the memory cell 11 is not performed, it becomes possible to set the voltage of the bit line BLB on the low-voltage power supply side to a predetermined voltage VBLL.

[0022] Also, the predetermined voltage VBLL may be lower than the voltage of the bit line BLT on the high-voltage power supply side (1V in this embodiment) of the pair of bit lines BLT and BLB. Thereby, it becomes possible to generate a potential difference between the pair of bit lines BLT and BLB in a state where the sense amplifier 10 holds data.

[0023] As shown in FIG. 2, the control unit 20 includes a first supply unit 21 that supplies the voltage VSS of the low-voltage power supply to the bit line BLB on the low-voltage power supply side, and a second supply unit 22 that supplies a predetermined voltage VBLL to the bit line BLB on the low-voltage power supply side in a state where the predetermined operation is not performed.

[0024] The first supply unit 21 includes a first switch unit 21a that supplies the predetermined voltage VBLL supplied from the second supply unit 22 to the bit line BLB on the low-voltage power supply side when a first control signal PD indicating that the predetermined operation is not performed is input, and a second switch unit 21b that supplies the voltage VSS of the low-voltage power supply to the bit line BLB on the low-voltage power supply side when a second control signal NSE indicating that the predetermined operation is performed is input.

[0025] In this embodiment, the first switch unit 21a is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to the second supply unit 22. Also, a first control signal PD is input to the gate terminal. When a high-level first control signal PD indicating that a predetermined operation is not performed is input to the gate terminal, the first switch unit 21a supplies a predetermined voltage VBLL supplied from the second supply unit 22 to the node CSN on the low-voltage power supply side of each sense amplifier 10. Then, the predetermined voltage VBLL is supplied to the bit line BLB on the low-voltage power supply side.

[0026] In this embodiment, the second switch unit 21b is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to the voltage VSS of the low-voltage power supply. Also, a second control signal NSE is input to the gate terminal. When a high-level second control signal NSE indicating that a predetermined operation is performed is input to the gate terminal, the second switch unit 21b supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. Then, the voltage VSS of the low-voltage power supply is supplied to the bit line BLB on the low-voltage power supply side.

[0027] Note that the first control signal PD and the second control signal NSE may be complementary signals to each other. Also, the first control signal PD and the second control signal NSE may be generated in the control unit 20, or may be generated by another circuit provided in the semiconductor memory device.

[0028] The second supply unit 22 includes a comparator 22a and a switch unit 22b. The comparator 22a has a first terminal (+ terminal) to which the voltage of the bit line BLB on the low-voltage power supply side is input (connected to the node CSN on the low-voltage power supply side of each sense amplifier 10), and a second terminal (- terminal) to which a reference voltage VREF (= a predetermined voltage VBLL) is input. Also, the output terminal of the comparator 22a is connected to the switch unit 22b. In the present embodiment, the switch unit 22b is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the node CSN on the low-voltage power supply side of each sense amplifier 10 via the first switch unit 21a of the first supply unit 21, and the source terminal is connected to the voltage VSS of the low-voltage power supply. Also, a signal output from the comparator 22a is input to the gate terminal. With such a configuration, the second supply unit 22 outputs a predetermined voltage VBLL.

[0029] Referring to FIG. 3, an example of the operation of the control unit 20 will be described. Here, first, it is assumed that a predetermined operation (reading, writing, or precharging of a pair of bit lines BLT and BLB of the data stored in the memory cell 11) is being performed in the semiconductor memory device. In this case, the first control signal PD is at a low level, and the second control signal NSE is at a high level. At this time, the control unit 20 supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. As a result, the voltage VSS of the low-voltage power supply is supplied to the bit line BLB on the low-voltage power supply side.

[0030] Next, when the predetermined operation ends (when the predetermined operation is not performed) and the sense amplifier 10 holds data, at time t0, the first control signal PD becomes high level and the second control signal NSE becomes low level. At this time, the control unit 20 supplies a predetermined voltage VBLL to the node CSN on the low-voltage power supply side of each sense amplifier 10. As a result, the predetermined voltage VBLL is supplied to the bit line BLB on the low-voltage power supply side.

[0031] Here, in a state where a predetermined operation is not being performed and the sense amplifier 10 is holding data, by setting the voltage of the bit line BLB on the low-voltage power supply side to a predetermined voltage VBLL that is higher than the voltage VSS of the low-voltage power supply, for example, when the voltage VSS of the low-voltage power supply is 0V, the back gate-source voltage of a transistor (in the example shown in FIG. 1, nMOSFET10c, nMOSFET10f) whose gate-source voltage becomes 0V becomes a negative voltage, and the threshold voltage of the transistors 10c, 10f increases due to the back-bias effect. Therefore, the leakage current generated in the transistors 10c, 10f is reduced.

[0032] Next, when a predetermined operation (either reading, writing the data stored in the memory cell 11, or precharging the pair of bit lines BLT, BLB) is performed at time t1, the first control signal PD becomes a low level and the second control signal NSE becomes a high level. At this time, the control unit 20 supplies the voltage VSS of the low-voltage power supply to the node CSN on the low-voltage power supply side of each sense amplifier 10. In this way, when a predetermined operation is performed, since the voltage of the bit line BLB on the low-voltage power supply side is set to the voltage VSS, it becomes possible to perform the predetermined operation normally.

[0033] As described above, according to the semiconductor memory device and its control method of the present embodiment, in a state where a predetermined operation is not being performed and the sense amplifier 10 is holding data, the voltage of the bit line BLB on the low-voltage power supply side is set to a predetermined voltage VBLL that is higher than the voltage VSS of the low-voltage power supply. For example, when the voltage of the low-voltage power supply is 0V, the back gate-source voltage of a transistor (in the example shown in FIG. 1, nMOSFET10c, nMOSFET10f) whose gate-source voltage becomes 0V becomes a negative voltage, and the threshold voltage of the transistors 10c, 10f increases due to the back-bias effect. Therefore, it becomes possible to reduce the leakage current generated in the transistors 10c, 10f. Further, in nMOSFET10f, since the gate-source voltage becomes a negative voltage, it becomes possible to reduce the leakage current generated in nMOSFET10f. Thereby, the leakage current generated in the sense amplifier 10 in the data holding state can be reduced.

[0034] The embodiments described above are described to facilitate the understanding of the present invention and are not described to limit the present invention. Therefore, each element disclosed in the above embodiments is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[0035] For example, in the above-described embodiment, the case where the control unit 20 has the configuration shown in FIG. 2 is described as an example, but the present invention is not limited to this case. For example, the control unit 20 may have another configuration as shown in FIG. 4. Referring to FIG. 4, the first supply unit 21 of the control unit 20 includes a first switch unit 21a, a second switch unit 21b, a third switch unit 21c, and a fourth switch unit 21d. Here, the configurations of each of the first switch unit 21a and the second switch unit 21b are the same as those in the above-described embodiment.

[0036] The third switch section 21c is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the node CSN on the low-voltage power supply side of each sense amplifier 10, and the source terminal is connected to the drain terminal of the nMOSFET that constitutes the fourth switch section 21d. Also, a signal output from the comparator 22a of the second supply section 22 is input to the gate terminal.

[0037] The fourth switch section 21d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the source terminal of the third switch section 21c, and the source terminal is connected to the voltage VSS of the low-voltage power supply. Also, the first control signal PD is input to the gate terminal.

[0038] Also, the second supply section 22 of the control section 20 shown in FIG. 4 includes a comparator 22a, a NOT circuit 22c, and a switch section 22d. Here, the configuration of the comparator 22a is the same as that of the above-described embodiment. The first control signal PD is input to the NOT circuit 22c. The switch section 22d is composed of an nMOSFET. The drain terminal of this nMOSFET is connected to the node CSN on the low-voltage power supply side of each sense amplifier 10 via the first switch section 21a of the first supply section 21, and the source terminal is connected to the voltage VSS of the low-voltage power supply. Also, a signal output from the NOT circuit 22c is input to the gate terminal.

[0039] The control section 20 configured as shown in FIG. 4 can also operate in the same manner as the embodiment when the control signals PD and NSE are input as shown in FIG. 3.

[0040] Also, in the examples shown in FIGS. 2 and 4, the case where each of the switch sections 21a, 21b, 21c, 21d, 22b, and 22d is composed of a MOSFET has been described as an example, but the present invention is not limited to this case. For example, each of the switch sections 21a, 21b, 21c, 21d, 22b, and 22d may be composed of a transistor other than a MOSFET, or may be composed of an element or circuit other than a transistor.

[0041] Furthermore, in the examples shown in FIGS. 2 and 4, the case where the control unit 20 includes one first supply unit 21 and one second supply unit 22 has been described as an example, but the present invention is not limited to this case. For example, the control unit 20 may include a plurality of first supply units 21 and one second supply unit 22. In this case, each of the plurality of first supply units 21 is connected to the node CSN on the low-voltage power supply side of each of the plurality of sense amplifiers 10, in the same manner as in the examples shown in FIGS. 2 and 4, and one second supply unit 22 may be connected to each of the plurality of first supply units 21. Thereby, it becomes possible for one second supply unit 22 to supply a predetermined voltage VBLL to the bit line BLB on the low-voltage power supply side via each of the plurality of first supply units 21.

[0042] Furthermore, the configurations of the sense amplifier 10 and the control unit 20 in the above-described embodiments are examples, and may be appropriately changed, or various other configurations may be adopted.

Explanation of Reference Numerals

[0043] 10…Sense amplifier (SA) 10a, 10b…Pair of P-channel field-effect transistors (pMOSFETs) 10c, 10d…Pair of N-channel field-effect transistors (nMOSFETs) 11…Memory cell 20…Control unit 21…First supply unit 21a…First switch unit 21b…Second switch unit 22…Second supply unit 22a…Comparator BLT, BLB…Pair of bit lines NSE…Second control signal PD…First control signal VBLL…Predetermined voltage VSS…Voltage of low-voltage power supply

Claims

1. A sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to the bit line on the low-voltage power supply side of the pair of bit lines; A control unit configured to set a voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than a voltage of the low-voltage power supply in a state where a predetermined operation is not being performed and the sense amplifier is holding data. A semiconductor memory device.

2. When the predetermined operation is performed in a state where the voltage of the bit line on the low-voltage power supply side is set to the predetermined voltage, the control unit sets the voltage of the bit line on the low-voltage power supply side to the voltage of the low-voltage power supply. The semiconductor memory device according to Claim 1.

3. The predetermined operation includes at least one of reading data stored in a memory cell connected to the sense amplifier, writing data, and precharging the pair of bit lines. The semiconductor memory device according to Claim 1.

4. The control unit includes: One or more first supply units configured to supply the voltage of the low-voltage power supply to the bit line on the low-voltage power supply side; A second supply unit configured to supply the predetermined voltage to the bit line on the low-voltage power supply side in a state where the predetermined operation is not being performed. The semiconductor memory device according to Claim 1.

5. The first supply unit includes: A first switch unit configured to supply the predetermined voltage supplied from the second supply unit to the bit line on the low-voltage power supply side when a first control signal indicating that the predetermined operation is not being performed is input; A second switch unit configured to supply the voltage of the low-voltage power supply to the bit line on the low-voltage power supply side when a second control signal indicating that the predetermined operation is being performed is input. The semiconductor memory device according to Claim 4.

6. The second supply unit includes: A comparator having a first terminal to which the voltage of the bit line on the low-voltage power supply side is input and a second terminal to which the predetermined voltage is input. The semiconductor memory device according to Claim 4 or 5.

7. The predetermined voltage is lower than the voltage of the bit line on the high-voltage power supply side of the pair of bit lines. The semiconductor memory device according to Claim 1.

8. The sense amplifier includes: A pair of first transistors, where one of the first transistors is connected to the bit line on the high-voltage power supply side and the other first transistor is connected to the bit line on the low-voltage power supply side. A pair of second transistors, wherein one of the second transistors is connected to a bit line on the high-voltage power supply side and the other second transistor is connected to a bit line on the low-voltage power supply side, and the pair of second transistors. The semiconductor memory device according to claim 1.

9. One of the pair of first transistors and the pair of second transistors is an N-channel field-effect transistor, and the other of the pair of first transistors and the pair of second transistors is a P-channel field-effect transistor. The semiconductor memory device according to claim 8.

10. The voltage of the low-voltage power supply is 0V. The semiconductor memory device according to claim 1.

11. A control method for a semiconductor memory device, wherein the semiconductor memory device includes a sense amplifier connected to a pair of bit lines, the sense amplifier including at least one transistor connected to a bit line on the low-voltage power supply side among the pair of bit lines. a control unit of the semiconductor memory device executes a step of setting the voltage of the bit line on the low-voltage power supply side to a predetermined voltage higher than the voltage of the low-voltage power supply in a state where a predetermined operation is not being performed and the sense amplifier is holding data. A control method for a semiconductor memory device.

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