Inverter adjustment apparatus and inverter adjustment method

Abstract

To suppress reduction of the service life of an inverter that has a plurality of switching elements connected in parallel.SOLUTION: An inverter adjustment apparatus according to an embodiment is a device for adjusting an inverter that is formed by connecting a plurality of switching elements in parallel. The inverter adjustment apparatus includes a heat generation amount measurement device and an ON time ratio determination unit. The heat generation amount measurement device measures a heat generation amount of each of the switching elements. The ON time ratio determination unit determines the ratio between an ON time and an OFF time of each of the switching elements so as to adjust the variation of the respective heat generation amounts of the switching elements measured by the heat generation amount measurement device within a prescribed range.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments of the present invention relate to an inverter adjustment device and an inverter adjustment method.

Background Art

[0002] In high-power inverters, in many cases, a plurality of switching elements are connected in parallel in order to reduce the load applied to each switching element. However, since there are variations in characteristics such as on-resistance and gate capacitance among the switching elements, the loads applied to each of the switching elements connected in parallel do not become the same.

[0003] The switching element with a concentrated load generates more heat, and the degree of deterioration progresses faster, so there is a high possibility of breakage at an early stage. The switching element often breaks in the short-circuit mode. Therefore, when any one of the plurality of switching elements connected in parallel is damaged, the inverter is damaged. Accordingly, when the load concentrates on any one of the plurality of switching elements connected in parallel, the life of the inverter is reduced.

[0004] There are reports on load distribution when a plurality of inverters are connected in parallel, but no reports have been found on a technique for suppressing the difference in loads applied to a plurality of switching elements connected in parallel within one inverter.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to suppress a reduction in the life of an inverter having a plurality of switching elements connected in parallel.

Means for Solving the Problems

[0007] An inverter adjustment device according to an embodiment for solving the above problems is a device for adjusting an inverter configured by connecting a plurality of switching elements in parallel. The inverter adjustment device includes a calorific value measurement device and an on-time ratio determination unit. The calorific value measurement device measures the calorific value of each switching element. The on-time ratio determination unit determines the ratio of the on-time and off-time of each switching element so that the difference in the calorific value of each switching element measured by the calorific value measurement device is within a predetermined range.

Brief Description of the Drawings

[0008]

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Mode for Carrying Out the Invention

[0009] Hereinafter, this embodiment will be described with reference to the drawings. For the description, an XYZ coordinate system composed of an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other will be used as appropriate. The diagrams and flowcharts used in the description of this embodiment are illustrative examples.

[0010] FIG. 1 is a perspective view of an elevator device 10 according to this embodiment. The elevator device 10 is disposed inside a hoistway 100 provided in a building such as a commercial facility or a residential facility. As shown in FIG. 1, the elevator device 10 includes a car 31, a counterweight 50, a hoisting motor 40, guide rails 21 to 24, and a control panel 70 (elevator control device).

[0011] Each of the guide rails 21 to 24 is a member whose longitudinal direction is the Z-axis direction. The guide rails 21 and 22 are a pair of members for guiding the car 31 to move up and down freely. Further, the guide rails 23 and 24 are a pair of members for guiding the counterweight 50 to move up and down freely. The guide rails 21 and 22 are arranged apart from each other in the Y-axis direction. Also, the guide rails 23 and 24 are similarly arranged apart from each other in the Y-axis direction. In FIG. 1, the guide rails 23 and 24 of the counterweight 50 are arranged apart from the guide rails 21 and 22 of the car 31 in the X-axis direction. Note that the arrangement of the guide rails 21 to 24 is not limited to the arrangement shown in FIG. 1.

[0012] The car 31 is a unit that accommodates users and moves up and down the hoistway 100. The car 31 is arranged between the guide rails 21 and 22 and is attached to the guide rails 21 and 22 so as to be movable in the vertical direction.

[0013] An opening 31a for entering and exiting the interior is formed on the +X side surface of the car 31. The opening 31a is closed or opened by a pair of doors 32 that move along the side surface of the car 31. The doors 32 are opened and closed by an opening / closing motor (not shown in FIG. 1).

[0014] The counterweight 50 is attached to the guide rails 23 and 24 so as to be movable in the vertical direction. The weight of the counterweight 50 is adjusted to a predetermined ratio with respect to the weight of the car 31.

[0015] The hoisting motor 40 is a motor for hoisting the car 31. The hoisting motor 40 is arranged at the upper part of the hoistway 100 such that the rotation axis is parallel to the Y-axis. A pulley 42 is fixed to the rotation axis of the hoisting motor 40. A wire 43 is wound around the pulley 42 of the hoisting motor 40. One end of the wire 43 is fixed to the car 31 and the other end is fixed to the counterweight 50.

[0016] The control panel 70 is disposed in the hoistway 100. The control panel 70 houses a control device for controlling the hoisting motor 40 and the devices provided in the car 31 and the like.

[0017] FIG. 2 is a block diagram showing the control system of the elevator apparatus 10. The control system includes a control unit 80 and a drive unit 91 housed in the control panel 70, and an operation panel 36 provided in the car 31.

[0018] The operation panel 36 is provided on the inner wall surface of the car 31. The operation panel 36 is an interface for receiving the destination floor and the like from the users of the car 31. The user can register the destination floor of the car 31 and open and close the door 32 by operating the operation panel 36. The operation panel 36 is connected to the control unit 80 housed in the control panel 70 via the cable 44 shown in FIG. 1.

[0019] The drive unit 91 shown in FIG. 2 drives the hoisting motor 40 by supplying power to the hoisting motor 40. The drive unit 91 drives the hoisting motor 40 based on an instruction from the control unit 80. The control unit 80 controls the drive unit 91 based on an input from the operation panel 36 or the call panels on each floor. For example, when the control unit 80 rotates the hoisting motor 40 forward via the drive unit 91, the car 31 ascends and the counterweight 50 descends. When the control unit 80 rotates the hoisting motor 40 in reverse via the drive unit 91, the car 31 descends and the counterweight 50 ascends.

[0020] Figure 3 is a block diagram of the drive unit 91. The drive unit 91 includes a converter 11 and an inverter 13. The converter 11 is a power supply device that converts the AC voltage supplied from the commercial power supply 1 into a DC voltage. The converter 11 is composed of a switching regulator. In the present embodiment, the converter 11 supplies a positive voltage and a negative voltage with respect to the ground potential to the inverter 13. The inverter 13 is a power supply device that converts the DC voltage supplied from the converter 11 into an AC voltage with a predetermined voltage at a predetermined frequency and supplies power to the lifting motor 40. The inverter 13 is composed of a switching regulator.

[0021] Figure 4 is a circuit example of the inverter 13. The inverter 13 includes an oscillation circuit 155, an on-time setting unit 150, a gate resistor group 140, and a switching element group 130. The oscillation circuit 155 supplies a clock with a predetermined frequency to the switching element group 130 via the gate resistor group 140 and the on-time setting unit 150. The gate resistor group 140 and the on-time setting unit 150 constitute a part of the inverter adjustment device 75 described later.

[0022] Figure 5 is a diagram for explaining the drive circuit of the FET constituting the switching element group 130 of the inverter 13. Figure 5 shows the drive circuit of one FET 134. Specifically, the clock output from the oscillation circuit 155 is supplied to the gate of the FET 134 via the on-time setting unit 150 and the gate resistor group 140. The on-time setting unit 150 and the gate resistor group 140 are provided for each switching element.

[0023] The on-time setting unit 150 is a circuit that determines the ratio of the on-time (the time when the clock supplied to the gate is at a high level) and the off-time (the time when the clock supplied to the gate is at a low level) of each switching element. The on-time setting unit 150 includes a plurality of delay elements with different selectable delay times and an AND circuit. Here, it is assumed that the delay time of the delay element ta151 shown in FIG. 5 is smaller than the delay time of the delay element tb152, and the delay time of the delay element tb152 is smaller than the delay time of the delay element tc153. The delay time of the delay element ta151 with the smallest delay time may be 0 seconds. The delay times of the delay element ta151, the delay element tb152, and the delay element tc153 are determined by variations in the on-resistance of the FETs, etc. When any one of the delay element ta151, the delay element tb152, and the delay element tc153 is specified, the on-time setting unit 150 sets the ratio of the high-level time and the low-level time of the clock supplied to the switching element by taking the AND of the clock output from the oscillation circuit 155 and the clock delayed by the specified delay element. The larger the delay time by the delay element, the shorter the high-level time of the clock, and the smaller the on-time ratio of the switching element. The delay times of the delay element ta151, the delay element tb152, and the delay element tc153 are set such that, for example, the high-level times of the clocks supplied to the gates of the FETs differ by 2% each. The method of setting the delay times of the delay element ta151, the delay element tb152, and the delay element tc153 will be described later.

[0024] The gate resistor group 140 is provided with a plurality of resistors having different resistance values so that they can be selected. Here, it is assumed that the resistance value of the gate resistor Ra141 shown in FIG. 5 is smaller than the resistance value of the gate resistor Rb142, and the resistance value of the gate resistor Rb142 is smaller than the resistance value of the gate resistor Rc143. The resistance values of the gate resistor Ra141, the gate resistor Rb142, and the gate resistor Rc143 are determined by the gate capacitance of the FET and the impedance of the lifting motor 40, etc. The resistance values of the gate resistor Ra141, the gate resistor Rb142, and the gate resistor Rc143 are set, for example, so that the resistance values differ by 10% from each other. The gate resistor group 140 selects one resistor from the plurality of resistors constituting the gate resistor group 140 and supplies the clock supplied from the oscillation circuit 155 to the gate of the FET134.

[0025] For each of the plurality of FETs (FET132 and FET134) constituting the switching element group 130, a voltage measuring device 161 for measuring the voltage Vds (switching voltage) between the drain and source of the FET, a current measuring device 162 for measuring the current Ids flowing through the FET, and a temperature measuring device 163 for measuring the temperature of the FET are provided.

[0026] FIG. 6 is a circuit example of the switching element group 130. The switching elements that make up the switching element group 130 are composed of transistors or FETs (Field Effect Transistors), insulated gate bipolar transistors (IGBTs), and the like. Here, the case where an FET is used as the switching element will be described as an example. The switching element group 130 is configured by connecting three FETs 132 connected in parallel and three FETs 134 connected in parallel in series. A DC voltage output by the converter 11 is applied between the terminal P1 and the terminal P2. The terminal P3 is connected to the lifting motor 40. Clocks output by the oscillation circuit 155 are supplied to the gates of the FETs 132 and 134 via the on-time setting unit 150 and the gate resistor group 140. The FETs 132 and 134 are in the on state during the period when the clock supplied to the gate is at a high level, and in the off state during the period when it is at a low level.

[0027] FIG. 7 is a physical block diagram of the control unit 80. The control unit 80 is a computer having a CPU (Central Processing Unit) 81, a main memory unit 82, an auxiliary storage unit 83, and an interface unit 84 interconnected via a bus 85. The CPU 81 executes the processes described later according to the programs stored in the auxiliary storage unit 83. The main memory unit 82 has a RAM (Random Access Memory) or the like. The main memory unit 82 is used as a work area for the CPU 81. The auxiliary storage unit 83 has non-volatile memories such as a ROM (Read Only Memory) and a semiconductor memory. The auxiliary storage unit 83 stores the programs executed by the CPU 81 and various parameters.

[0028] The interface unit 84 has a serial interface, a parallel interface, a wireless LAN interface, etc. The operation panel 36 and the drive unit 91 are connected to the CPU 81 via the interface unit 84. Also, an input / output device 93 composed of a keyboard, a display, etc. is connected to the interface unit 84.

[0029] Figure 8 is a functional block diagram of the control unit 80. The control unit 80 realizes the functions of the inverter adjustment device 75 by executing the programs stored in the auxiliary storage unit 83. The inverter adjustment device 75 has a measurement data acquisition unit 77, a gate resistance determination unit 78, and an on-time ratio determination unit 79. The inverter adjustment device 75 includes the above-described on-time setting unit 150 and the gate resistance group 140.

[0030] The measurement data acquisition unit 77 acquires the data measured by the voltage measurement device 161, the current measurement device 162, and the temperature measurement device 163.

[0031] The gate resistance determination unit 78 performs control to select one resistance from the plurality of resistances constituting the gate resistance group 140. The gate resistance determination unit 78 selects the resistance of the gate resistance group 140 so that the surge voltage of each of the FETs 132 and 134 measured by the voltage measurement device 161 does not exceed the absolute rating of the FET (switching element).

[0032] The on-time ratio determination unit 79 determines the ratio of the on-time and off-time of each switching element (FET) so that the difference in the heat generation amount of each switching element (FET) measured by the temperature measurement device 163, which is a heat generation amount measurement device, is within a predetermined range. The on-time ratio determination unit 79 determines the ratio of the on-time and off-time of each switching element by selecting the delay element constituting the on-time setting unit 150.

[0033] Next, with reference to the flowchart shown in FIG. 9, the gate resistance determination process (gate resistance determination step) will be described. The following control is performed based on a program stored in the auxiliary storage unit 83, and the control entity is the control unit 80 (CPU 81). In the initial state, it is assumed that the resistance of the gate resistance group 140 is such that the gate resistance Ra141 with the smallest resistance value is selected.

[0034] The voltage measurement device 161 measures the waveform data of the voltage Vds between the drain and source of each of the plurality of FETs constituting the switching element group 130, and notifies the measurement value to the inverter adjustment device 75. The measurement data acquisition unit 77 acquires the waveform data measured by the voltage measurement device 161 (step S11). FIG. 10 is an image diagram of the waveform data of the voltage Vds between the drain and source of the FET acquired by the measurement data acquisition unit 77. The voltage Vds between the drain and source often has a surge voltage (overshoot voltage) surrounded by a broken-line circle in FIG. 10.

[0035] Next, the gate resistance determination unit 78 determines the resistance of the gate resistance group 140 based on the waveform data of the voltage between the drain and source of the FET acquired by the measurement data acquisition unit 77 (step S12). Specifically, the resistance of the gate resistance group 140 is determined so that the maximum value Vpeak of the surge voltage (overshoot voltage) of the voltage Vds shown in FIG. 10 does not exceed a reference value with a margin from the absolute rating of the FET.

[0036] Here, referring to FIGS. 11 to 14, the resistance value of the gate resistor group 140 and the waveform data of the voltage Vds between the drain and source of the FET will be described. The signal output from the oscillation circuit 155 is supplied to the gate of the FET through the resistance of the gate resistor group 140. When a high-level signal is applied to the gate of the FET, as the charge accumulates in the floating capacitance of the gate, the gate voltage gradually rises. The time constant for the rise of the gate voltage is determined by the value of the gate resistance and the floating capacitance of the gate. As the gate voltage rises, the voltage Vds between the drain and source gradually decreases, and the current Ids flowing from the collector to the emitter gradually increases. The greater the rate of change of this current Ids, due to the characteristics of the coil constituting the inverter 13, the maximum value (Vpeak) of the surge voltage of the voltage Vds between the drain and source tends to increase. That is, there is a correlative relationship between the time constant (the value of the gate resistance) for the rise of the gate voltage and the maximum value Vpeak of the surge voltage.

[0037] FIG. 11 schematically shows the gate voltage of the FET when the resistance value of the gate resistor is small and the rise of the gate voltage is steep. In this case, as shown in FIG. 12, the maximum value Vpeak of the surge voltage of Vds of the FET tends to increase. FIG. 13 schematically shows the gate voltage of the FET when the resistance value of the gate resistor is large and the rise of the gate voltage is not steep. In this case, as shown in FIG. 14, the maximum value Vpeak of Vds of the FET is smaller than the maximum value of the surge voltage shown in FIG. 12.

[0038] Returning to FIG. 9, the gate resistor determination unit 78 first selects the gate resistor Ra141 with the smallest resistance value among the gate resistor group 140. The gate resistor determination unit 78 determines whether the maximum value Vpeak of the surge voltage of the voltage Vds of the FET is equal to or greater than a reference value (step S13). The reference value is set to a value with a margin from the absolute rating of the FET to be used. When the maximum value Vpeak of the surge voltage of the voltage Vds of the FET is equal to or greater than the reference value (step S13: Yes), the process returns to step S11.

[0039] In the process of the second step S12, the gate resistance determination unit 78 selects a gate resistance Rb142 with a larger resistance value next to the initial gate resistance Ra141. In the process of the third step S12, the gate resistance determination unit 78 selects a gate resistance Rc143 with a larger resistance value next to the second gate resistance Rb142. In this way, the gate resistance determination unit 78 selects a gate resistance for which the maximum value Vpeak of the surge voltage of the Vds of the FET is less than the reference value. When the gate resistance for which the maximum value Vpeak of the surge voltage is less than the reference value is determined (step S13: No), the process proceeds to step S14.

[0040] Next, the gate resistance determination unit 78 determines whether the gate resistances of all the FETs have been determined (step S14). If the determination process of the gate resistance has not been completed for all the FETs (step S14: No), the process returns to step S11, and the processes from step S11 to step S13 are performed for the FETs for which the determination process of the gate resistance has not been performed. If the determination process of the gate resistance has been completed for all the FETs (step S14: Yes), the gate resistance determination process ends.

[0041] Next, the on-time ratio determination process will be described with reference to the flowchart shown in FIG. 15. The following control is performed based on the program stored in the auxiliary storage unit 83, and the main body of the control is the control unit 80 (CPU 81). In the initial state, it is assumed that the delay element ta151 with the smallest delay time is selected for all the on-time setting units 150 connected to the FETs via the gate resistance group 140.

[0042] Here, the heat generation amount of the FET will be described. FIG. 16 shows the clock supplied to the gate of the FET. The current Ids shown in FIG. 17 is the current flowing from the drain to the source of the FET. The Vds shown in FIG. 17 is the voltage between the drain and source of the FET. When the clock is at a high level, the FET is in an on state, and a current Ids flows between the drain and source. During the period of ton in FIG. 17, the FET is in an on state. The voltage Vds during the period of ton in FIG. 17 is the on-voltage of the FET, and the current Ids during the period of ton is the on-current of the FET. During the period of toff in FIG. 17, the FET is in an off state, and the current Ids flowing from the drain to the source becomes zero. The heat generation amount of the FET is proportional to the product (Vds × Ids) of the voltage Vds and the current Ids. Therefore, the FET does not generate heat during the period of toff in FIG. 17.

[0043] The clock supplied to the gate of the FET shown in FIG. 18 shortens the on-time of the clock shown in FIG. 16 by a time td. As a result, the on-time ton of the FET shown in FIG. 19 is shorter than the on-time ton of the FET shown in FIG. 17 by a time td. That is, the waveform shown in FIG. 19 has a smaller on-time ratio of the FET compared to the waveform shown in FIG. 17. Since the heat generation amount of the FET becomes smaller as the on-time ratio of the FET becomes smaller, the heat generation amount in the case shown in FIG. 19 is smaller than the heat generation amount in the case shown in FIG. 17.

[0044] The larger the delay time of the delay element selected in the on-time setting unit 150, the larger the time td shown in FIGS. 18 and 19. Therefore, the larger the delay time of the delay element selected in the on-time setting unit 150, the smaller the on-time ratio of the FET, and the smaller the heat generation amount of the FET.

[0045] Returning to FIG. 15, the measurement data acquisition unit 77 acquires the temperature data measured by the thermometer 163 (step S31). Step S31 is a heat generation amount measurement step for measuring the heat generation amount of each FET (switching element). Next, the on-time ratio determination unit 79 determines whether the temperature difference between the switching elements (FETs) connected in parallel is equal to or less than a threshold value (step S32). In the example shown in FIG. 6, it is determined whether the temperature differences between the three FETs 132 connected in parallel and the three FETs 134 connected in parallel are equal to or less than the threshold value. In the present embodiment, adjustment is not performed to make the temperature difference between the FET 132 and the FET 134 equal to or less than the threshold value.

[0046] On the other hand, when the temperature difference between the FETs connected in parallel is not equal to or less than the threshold value (step S32: No), the on-time ratio determination unit 79 decreases the on-time ratio of the clock supplied to the switching element (FET) having the highest temperature (step S33). Step S33 is an on-time ratio determination step for determining the ratio of the on-time and off-time of each switching element so that the difference in the heat generation amount of each switching element measured in the heat generation amount measurement step of step S31 is within a predetermined range. Specifically, the on-time ratio determination unit 79 performs control to switch the delay element of the on-time setting unit 150 from the delay element ta151 having the smallest delay time to the delay element tb152 having the next larger delay time. When the delay element of the on-time setting unit 150 is changed to the delay element tb152, the process returns to step S31.

[0047] In the second processing of step S33, control is performed to switch from the delay element tb152 to the delay element tc153 having the next larger delay time. Here, the case where there are three types of delay elements is described as an example, but the type (number) of delay elements is not limited. The processing of steps S31 to S33 is repeated while sequentially switching from the delay element having a small delay time to the delay element having a large delay time. The actually required type of delay element is determined by the degree of variation in the on-resistance of the FET and the allowable difference in the heat generation amount of the FET.

[0048] For example, assume that the threshold value of the temperature difference in step S32 is set such that the difference in the heat generation amount of the FETs is 1% or less. In this case, if the switching frequency of the inverter 13 is fs, the difference in the delay times of the delay element ta151 and the delay element tb152 is set to, for example, (1 / (10×fs)). By setting the delay elements in this way, the heat generation amount of the FETs can be changed by approximately 0.1% each time the delay elements are switched.

[0049] When the temperature difference between the FETs connected in parallel is equal to or less than the threshold value (step S32: Yes), the process ends.

[0050] The gate resistance determination process shown in FIG. 9 and the on-time ratio determination process shown in FIG. 15 are performed each time the car body 31 moves up and down.

[0051] As described above, the inverter adjustment device according to Embodiment 1 has an on-time ratio determination unit 79 that determines the ratio of the on-time and off-time of each switching element so that the difference in the heat generation amount of each switching element measured by the thermometer 163 (heat generation amount measurement device) is within a predetermined range. Thereby, variations in the load applied to the switching elements connected in parallel can be reduced, and the temperature difference between the switching elements connected in parallel can be reduced. Therefore, it is possible to suppress a reduction in the lifespan of the inverter having a plurality of switching elements connected in parallel.

[0052] Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above description, the case where the gate resistance determination process shown in FIG. 9 and the on-time ratio determination process shown in FIG. 15 are performed each time the car body 31 moves up and down has been described, but for example, they may be performed at each regular inspection.

[0053] In the above description, the case where the on-time ratio of the FET is adjusted by controlling the delay time in the on-time setting unit 150 has been described. However, the method for adjusting the on-time of the FET does not necessarily have to be limited to this. For example, a plurality of types of clock generation circuits with different on-times may be provided, and any one of the clocks may be selected.

[0054] In the above description, the case where the rising speed of the gate voltage is adjusted by changing the value of the gate resistance has been described. As another method, capacitors with different capacitances may be arranged at the gate of the FET, and any one of the capacitors may be selected, or the combination of capacitors connected in parallel may be changed to adjust the rising speed of the gate voltage.

[0055] Also, when the maximum value Vpeak of the surge voltage of Vds of the FET hardly changes due to the on-time ratio determination process, either the gate resistance determination process or the on-time ratio determination process described above may be performed first.

[0056] (Modification example) In the description of Embodiment 1, the case where the on-time ratio of the FET is adjusted based on the measurement data of the temperature measurement device 163 has been described. As another embodiment, the on-time ratio of the FET can also be adjusted based on the measurement data of the voltage measurement device 161 and the current measurement device 162. In the modification example, the voltage measurement device 161 and the current measurement device 162 constitute a calorific value measurement device. The value obtained by multiplying the voltage Vds between the drain and source of the FET measured by the voltage measurement device 161 and the current Ids measured by the current measurement device 162 is the heat generated in the FET. Therefore, the value obtained by integrating (Vds×Ids) over a predetermined time corresponds to the temperature measured by the temperature measurement device 163. The predetermined time is set to about 1 second, for example. By controlling the on-time setting unit 150 so that the difference between the integrated values of (Vds×Ids) of each switching element is within a predetermined range, it is possible to suppress a reduction in the life of an inverter having a plurality of switching elements connected in parallel.

[0057] It takes a predetermined time for the temperature of the FET to change. On the other hand, the voltage measurement device 161 and the current measurement device 162 can measure the data of the instantaneous changes in the voltage Vds and the current Ids. Therefore, compared with the first embodiment, in some cases, the adjustment of the inverter 13 can be performed in a shorter time in the modified example. On the other hand, considering the heat generation during the on / off transient period of the FET, it should be noted that the value obtained by integrating (Vds×Ids) does not exactly correlate with the actual temperature of the FET.

[0058] (Second Embodiment) In the first embodiment, a method for extending the life of an inverter having a configuration in which a plurality of switching elements are connected in parallel by adjusting the delay time of the on-time setting unit 150 to equalize the load applied to the FETs has been described. In the second embodiment, a method for extending the life of an inverter having a configuration in which a plurality of switching elements are connected in parallel by adjusting the gate resistors that drive the switching elements to equalize the load applied to the FETs will be described.

[0059] In the inverter adjustment device 75 according to the second embodiment, in FIGS. 4 and 5, the on-time setting unit 150 is deleted. Also, in FIG. 8, the on-time ratio determination unit 79 and the on-time setting unit 150 are deleted.

[0060] Here, the heat generation amount of the FET will be described. When a high-level signal is applied to the gate of the FET, as the charge accumulates in the base stray capacitance, the base voltage gradually rises. As the base voltage rises, the voltage Vds between the collector and the emitter gradually decreases, and the current Ids flowing from the collector to the emitter gradually increases. When the signal applied to the gate becomes low level, as the charge accumulated in the gate stray capacitance is discharged, the gate voltage gradually decreases. As the gate voltage decreases, the voltage Vds between the drain and the source gradually increases, and the current Ids flowing from the drain to the source gradually decreases.

[0061] The heat generation amount of the FET is proportional to the product of the voltage Vds and the current Ids. During the period when the current Ids is completely "0", there is no heat generation in the FET. Also, when the FET is in the on state, the value of the voltage Vds is small (for example, 0.1 V), so the heat generation amount in the FET is small. The FET has a large value of (Vds × Ids) and a large heat generation amount in the transition state from the on state to the off state and the transition state from the off state to the on state.

[0062] The smaller the resistance value selected by the gate resistor group 140, the steeper the rise and fall changes of the gate voltage of the FET, the shorter the periods of the transition state from the on state to the off state and the transition state from the off state to the on state of the FET, and the smaller the heat generation amount of the FET. On the other hand, the larger the resistance value selected by the gate resistor group 140, the slower the rise and fall changes of the gate voltage of the FET, the longer the periods of the transition state from the on state to the off state and the transition state from the off state to the on state of the FET, and the larger the heat generation amount of the FET.

[0063] Next, the second gate resistor determination process will be described with reference to the flowchart shown in FIG. 20. Here, the determination process of the minimum value of the gate resistor described using FIG. 8 and the like will be referred to as the first gate resistor determination process. The description of the first gate resistor determination process is the same as the description of Embodiment 1. It is assumed that the minimum value of the gate resistor has been determined in the first gate resistor determination process. The descriptions of step S51 and step S52 shown in FIG. 20 are the same as the descriptions of step S31 and step S32 of Embodiment 1.

[0064] The gate resistor determination unit 78 increases the value of the gate resistor connected to the FET with the lowest temperature (step S53). For example, when the gate resistor Ra141 with the smallest resistance value is selected in the first gate resistor determination process, the next gate resistor Rb142 with a larger resistance value is then selected. Then, the process returns to step S51.

[0065] In the process of the second step S53, control is performed to switch from the gate resistor Rb142 to the gate resistor Rc143 with the next larger resistance value. Here, the case where there are three types of gate resistor values is described as an example, but the types of gate resistors are not limited. While sequentially switching to gate resistors with larger resistance values, the processes of steps S51 to S53 are repeatedly performed. By repeating the processes from step S51 to step S53, the temperature difference of the FETs connected in parallel becomes equal to or less than the threshold value.

[0066] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0067] 1…Commercial power supply 10…Elevator device 11…Converter 13…Inverter 130…Switching element group 132, 134…FET (Switching element) 140…Gate resistor group 141…Gate resistor Ra 142…Gate resistor Rb 143…Gate resistor Rc 150…On-time setting unit 151…Delay element ta 152…Delay element tb 153…Delay element tc 155…Oscillation circuit 161…Voltage measurement device 162…Current measurement device 163…Temperature measurement device 21 - 24…Guide rail 31…Car 31a…Opening 32…Door 36…Operation panel 40…Lifting motor (hoist) 42…Pulley 43…Wire 44…Cable 50…Counterweight 70…Control panel 75…Inverter adjustment device 77…Measurement data acquisition unit 78…Gate resistance determination unit 79…On-time ratio determination unit 80…Control unit 81…CPU 82…Main memory unit 83…Auxiliary memory unit 84…Interface unit 85…Bus 91…Drive unit 93…Input / output device 100…Lifting path

Claims

1. In an inverter configured by connecting a plurality of switching elements in parallel, a calorific value measuring device that measures the calorific value of each of the switching elements; an on-time ratio determination unit that determines the ratio of the on-time and off-time of each of the switching elements so that the difference in the calorific value of each of the switching elements measured by the calorific value measuring device is within a predetermined range; An inverter adjustment device having the above.

2. a voltage measuring device that measures the switching voltage of each of the switching elements; a gate resistor group provided in each of the switching elements and having a plurality of resistors with different resistance values selectable; a gate resistor determination unit that selects the resistance of the gate resistor group so that the maximum value of the surge voltage of each of the switching elements measured by the voltage measuring device does not exceed a preset reference value; The inverter adjustment device according to claim 1, having the above.

3. In an inverter configured by connecting a plurality of switching elements in parallel, a gate resistor group provided in each of the switching elements and having a plurality of resistors with different resistance values selectable; a calorific value measuring device that measures the calorific value of each of the switching elements; a gate resistor determination unit that selects the resistance of the gate resistor group so that the difference in the calorific value of each of the switching elements measured by the calorific value measuring device is within a predetermined range; An inverter adjustment device having the above.

4. having a voltage measuring device that measures the switching voltage of each of the switching elements, The gate resistor determination unit determines the resistance of the gate resistor group so that the maximum value of the surge voltage of each of the switching elements measured by the voltage measuring device does not exceed a preset reference value. The inverter adjustment device according to claim 3.

5. The calorific value measuring device is composed of a voltage measuring device, a current measuring device, or a temperature measuring device. The inverter adjustment device according to any one of claims 1 to 4.

6. In an inverter configured by connecting a plurality of switching elements in parallel, a calorific value measuring step of measuring the calorific value of each of the switching elements; an on-time ratio determination step of determining the ratio of the on-time and off-time of each of the switching elements so that the difference in the calorific value of each of the switching elements measured in the calorific value measuring step is within a predetermined range; An inverter adjustment method including the above.

7. In an inverter configured by connecting a plurality of switching elements in parallel, a heat generation amount measurement step of measuring the heat generation amount of each of the switching elements; a gate resistor determination step of selecting one resistor from a group of gate resistors composed of a plurality of resistors having different resistance values provided for each of the switching elements so that the difference in the heat generation amount of each of the switching elements measured in the heat generation amount measurement step is within a predetermined range; An inverter adjustment method including the above steps.

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