Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device capable of improving the recognition of a recognition mark.SOLUTION: A semiconductor device 10 includes: a wiring board 20; a semiconductor element 30 that is mounted on the wiring board 20; and a heat sink 40 that is provided above the semiconductor element 30. The semiconductor device 10 fills a space between the wiring board 20 and the heat sink 40, and includes a sealing resin 50 that seals the semiconductor element 30. The heat sink 40 includes: a main body part 41 that is provided at a position overlapped in a plan view with the semiconductor element 30; and a lead part 43 that is projected to an external side from the main body part 41. The lead part 43 is formed to be thinner than the main body part 41. An upper surface 50T of the sealing resin 50 is provided below an upper surface 41T of the main body part 41. The sealing resin 50 is formed so as to cover a part of a side surface of the main body part 41 and an upper surface 43T of the lead part 43. The sealing resin 50 is formed so as to expose the whole surface of the upper surface 41T of the main body part 41, and expose the side surface in the upper part of the main body part 41.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device having a wiring board, a semiconductor element mounted on the wiring board, a lead frame mounted on the wiring board via a connection member, and a sealing resin for sealing the semiconductor element and the connection member is known (for example, see Patent Document 1). In this type of semiconductor device, the lower surface of the lead frame and the lower surface of the sealing resin are formed flush. In this type of semiconductor device, the lower surface of the lead frame exposed from the sealing resin may be used as a recognition mark such as an alignment mark.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above-described semiconductor device, improvement in the recognition property of the recognition mark is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, there are provided a wiring board, a semiconductor element mounted on the wiring board, a heat sink provided above the semiconductor element, and a sealing resin that fills a space between the wiring board and the heat sink and seals the semiconductor element. The heat sink has a main body portion provided at a position overlapping the semiconductor element in plan view and a lead portion protruding outward from the main body portion. The lead portion is formed thinner than the main body portion. The lead portion has a second outer surface exposed from a first outer surface of the sealing resin. The sealing resin is formed to cover a part of a side surface of the main body portion and an upper surface of the lead portion. An upper surface of the sealing resin is provided below an upper surface of the main body portion. The sealing resin is formed to expose an entire upper surface of the main body portion and a side surface at an upper portion of the main body portion.

Advantages of the Invention

[0006] According to one aspect of the present invention, there is an effect that the recognition performance of the recognition mark can be improved.

Brief Description of the Drawings

[0007]

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DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment will be described with reference to the accompanying drawings. Note that the attached drawings may, for the sake of convenience, show the characteristic parts enlarged to make the characteristics easier to understand, and the dimensional ratios of the respective components may be different in each drawing. Also, in sectional views, in order to make the sectional structure of each member easier to understand, the hatching of some members is shown by replacing it with a satin pattern, and the hatching of some members is omitted. In this specification, "plan view" means looking at the object from the vertical direction (the up-and-down direction in the figure) such as in Fig. 1(a), and "planar shape" means the shape of the object when viewed from the vertical direction such as in Fig. 1(a). The "up-and-down direction" and "left-and-right direction" in this specification are the directions when the signs indicating the respective members in each drawing can be read correctly in the correct position. The "opposite" in this specification means that surfaces or members are in a position facing each other, including not only the case where they are completely in a facing position but also the case where they are partially in a facing position. The "opposite" in this specification includes both the case where a member different from the two parts is interposed between the two parts and the case where nothing is interposed between the two parts.

[0009] (Overall Configuration of Semiconductor Device 10) First, the structure of the semiconductor device 10 will be described with reference to Fig. 1(a). The semiconductor device 10 includes a wiring substrate 20, one or more (in this embodiment, one) semiconductor elements 30, a heat sink 40, a sealing resin 50, and external connection terminals 60.

[0010] (Configuration of Wiring Substrate 20) The wiring substrate 20 has a substrate body 21. On the lower surface of the substrate body 21, a wiring layer 22 and a solder resist layer 23 are laminated in this order. On the upper surface of the substrate body 21, a wiring layer 24 and a solder resist layer 25 are laminated in this order.

[0011] As the substrate body 21, a wiring structure in which an insulating resin layer and a wiring layer are alternately laminated can be used. The wiring structure may have, for example, a core substrate or may not have a core substrate. As the material of the insulating resin layer, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, insulating resins such as epoxy resin, polyimide resin, and cyanate resin can be used. Further, as the material of the insulating resin layer, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The insulating resin layer may contain, for example, fillers such as silica and alumina.

[0012] As the material of the wiring layer in the substrate body 21 and the wiring layers 22 and 24, for example, copper (Cu) or a copper alloy can be used. As the material of the solder resist layers 23 and 25, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The solder resist layers 23 and 25 may contain, for example, fillers such as silica and alumina.

[0013] The wiring layer 22 is formed on the lower surface of the substrate body 21. The wiring layer 22 is the lowermost wiring layer of the wiring substrate 20. The solder resist layer 23 is laminated on the lower surface of the substrate body 21 so as to cover the wiring layer 22. The solder resist layer 23 is the outermost layer (here, the lowermost layer) insulating layer of the wiring substrate 20.

[0014] A plurality of openings 23X are formed in the solder resist layer 23 to expose a part of the lower surface of the wiring layer 22 as an external connection pad P1. An external connection terminal 60 used when mounting the wiring substrate 20 on a mounting substrate such as a motherboard is connected to the external connection pad P1.

[0015] On the lower surface of the wiring layer 22 exposed at the bottom of the opening 23X, a surface treatment layer is formed as required. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating the Ni layer and the Au layer in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating the Ni layer, the Pd layer, and the Au layer in this order), and the like. Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating the Ni layer and the Pd layer in this order), a Pd layer / Au layer (a metal layer formed by laminating the Pd layer and the Au layer in this order), and the like. Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. As these Au layer, Ni layer, and Pd layer, for example, a metal layer (electroless plating layer) formed by an electroless plating method or a metal layer (electrolytic plating layer) formed by an electrolytic plating method can be used. Further, as the surface treatment layer, an OSP (Organic Solderability Preservative) film formed by performing an antioxidant treatment such as OSP treatment on the lower surface of the wiring layer 22 exposed at the opening 23X can be used. As the OSP film, an organic film such as an azole compound or an imidazole compound can be used. When a surface treatment layer is formed on the lower surface of the wiring layer 22, the surface treatment layer functions as an external connection pad P1.

[0016] In this example, the external connection terminal 60 is provided on the external connection pad P1. However, the wiring layer 22 itself exposed at the bottom of the opening 23X (or, when a surface treatment layer is formed on the wiring layer 22, the surface treatment layer itself) may be used as the external connection terminal.

[0017] The wiring layer 24 is formed on the upper surface of the substrate body 21. The wiring layer 24 is the topmost wiring layer of the wiring substrate 20. The wiring layer 24 is electrically connected to the wiring layer 22, for example, via the wiring layers and through electrodes in the substrate body 21. The wiring layer 24 is arranged in a matrix in a plan view in the mounting region where the semiconductor element 30 is mounted, for example, according to the arrangement form of the bumps 31 of the semiconductor element 30. The wiring layer 24 functions as a pad for mounting electronic components for electrically connecting to electronic components such as the semiconductor element 30, for example.

[0018] The solder resist layer 25 is laminated on the upper surface of the substrate body 21 so as to expose the wiring layer 24. The solder resist layer 25 is the outermost layer (here, the topmost layer) insulating layer of the wiring substrate 20. The solder resist layer 25 is formed so as to surround the mounting region where the semiconductor element 30 is mounted, for example, in a plan view. In other words, the solder resist layer 25 has an opening 25X that exposes the upper surface of the substrate body 21 and the wiring layer 24 in the mounting region.

[0019] (Configuration of the semiconductor element 30) The semiconductor element 30 has a plurality of bumps 31 formed on the circuit formation surface (here, the lower surface) of the semiconductor element 30. The semiconductor element 30 is mounted on the upper surface of the wiring substrate 20. The semiconductor element 30 is flip-chip mounted on the upper surface of the wiring substrate 20. The semiconductor element 30 is electrically connected to the wiring layer 24 of the wiring substrate 20 via the bumps 31. Thus, the semiconductor element 30 is electrically connected to the wiring layer 24 of the wiring substrate 20 via the bumps 31.

[0020] As the semiconductor element 30, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Further, as the semiconductor element 30, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip or a flash memory chip can be used. When a plurality of semiconductor elements 30 are mounted on the wiring board 20, a logic chip and a memory chip may be combined and mounted on the wiring board 20.

[0021] As shown in FIG. 2, the planar shape of the semiconductor element 30 is formed in a rectangular shape, for example. The planar shape of the semiconductor element 30 is not limited to a rectangle and can be any shape. The planar size of the semiconductor element 30 can be, for example, about 3 mm × 3 mm to 12 mm × 12 mm. The thickness of the semiconductor element 30 can be, for example, about 50 μm to 100 μm.

[0022] As the bump 31 shown in FIG. 1(a), for example, a gold bump or a solder bump can be used. As the material of the solder bump, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and silver (Ag), an alloy of Sn, Ag and Cu, etc. can be used.

[0023] (Configuration of the heat sink 40) As shown in FIG. 1(a), the heat sink 40 is provided above the semiconductor element 30. The heat sink 40 is provided, for example, apart from the semiconductor element 30 in the thickness direction of the sealing resin 50 (the vertical direction in the figure). The heat sink 40 is provided, for example, on the back surface (here, the upper surface) opposite to the circuit formation surface of the semiconductor element 30 via the sealing resin 50. The heat sink 40 is also called a heat spreader. The heat sink 40 has a function of dispersing the density of heat generated by the semiconductor element 30.

[0024] As shown in FIGS. 1(a) and 2, the heat sink 40 has, for example, a main body portion 41, a protruding portion 42, and a plurality (here, four) of lead portions 43. The heat sink 40 is formed such that the main body portion 41, the protruding portion 42, and the plurality of lead portions 43 are continuously integrated.

[0025] The main body portion 41 is formed, for example, in a flat plate shape. The main body portion 41 is provided so as to overlap with the semiconductor element 30 in a plan view. The main body portion 41 is provided, for example, so as to overlap with the entire semiconductor element 30 in a plan view. The main body portion 41 is provided, for example, in the mounting region of the semiconductor element 30. As shown in FIG. 2, the planar shape of the main body portion 41 is formed in a shape similar to the planar shape of the semiconductor element 30, here a rectangle. That is, the outer shape of the main body portion 41 is formed in a rectangle in a plan view. The planar shape of the main body portion 41 is formed, for example, slightly larger than the planar shape of the semiconductor element 30. The planar shape of the main body portion 41 is formed smaller than the planar shape of the substrate main body 21. The thickness of the main body portion 41 can be, for example, about 100 μm to 500 μm.

[0026] As shown in FIG. 1(a), the main body portion 41 has a lower surface 41U facing the semiconductor element 30 and an upper surface 41T on the side opposite to the lower surface 41U. The lower surface 41U of the main body portion 41 is thermally coupled to the back surface of the semiconductor element 30 via the encapsulating resin 50. The upper surface 41T of the main body portion 41 is exposed from the encapsulating resin 50. The upper surface 41T of the main body portion 41 is provided, for example, at a position protruding upward from the upper surface 50T of the encapsulating resin 50. The upper surface 41T of the main body portion 41 functions as a recognition mark M1 such as an alignment mark. The recognition mark M1 is used, for example, when mounting the semiconductor device 10 on other components.

[0027] As shown in FIG. 2, the protruding portion 42 is formed so as to surround the outer peripheral edge of the main body portion 41 in a plan view. The protruding portion 42 continuously surrounds, for example, the outer periphery of the main body portion 41 over the entire circumferential direction.

[0028] As shown in FIG. 3, the protruding portion 42 is formed so as to protrude outward from the side surface of the main body portion 41. The protruding portion 42 is formed, for example, so as to protrude from the side surface of the main body portion 41 toward the outer peripheral edge side of the semiconductor device 10. The thickness of the protruding portion 42 is formed, for example, to be thinner than the thickness of the main body portion 41. The thickness of the protruding portion 42 can be set, for example, to about 0.3 to 0.7 times the thickness of the main body portion 41. The thickness of the protruding portion 42 can be, for example, about 50 μm to 200 μm. The protruding portion 42 is formed so as to be recessed from the upper surface 41T side of the main body portion 41 toward the wiring board 20. The upper surface 42T of the protruding portion 42 is provided below the upper surface 41T of the main body portion 41. The upper surface 42T of the protruding portion 42 is covered with the sealing resin 50. The lower surface 42U of the protruding portion 42 is formed flush with the lower surface 41U of the main body portion 41, for example. The lower surface 42U of the protruding portion 42 is covered with the sealing resin 50. The side surface of the protruding portion 42 is covered with the sealing resin 50.

[0029] As shown in FIG. 2, each lead portion 43 is formed so as to protrude outward from the side surface of the protruding portion 42, for example. Each lead portion 43 is formed so as to protrude from the side surface of the protruding portion 42 located on the outer peripheral edge side of the semiconductor device 10 toward the outer peripheral edge side of the semiconductor device 10, for example. Each lead portion 43 extends to the outer side surface of the semiconductor device 10, for example.

[0030] The plurality of lead portions 43 are provided at intervals along the circumferential direction of the main body portion 41, for example. The plurality of lead portions 43 are provided in the outer peripheral region of the semiconductor device 10, for example. The plurality of lead portions 43 are provided at a predetermined interval along the outer peripheral edge of the semiconductor device 10. The plurality of lead portions 43 are provided on at least two of the four sides constituting the outer shape of the rectangular main body portion 41, for example. In the present embodiment, one lead portion 43 is provided on each of the four sides constituting the outer shape of the main body portion 41.

[0031] As shown in Fig. 1(a), the thickness of each lead portion 43 is formed, for example, to be the same as the thickness of the protruding portion 42. The thickness of each lead portion 43 is formed, for example, to be thinner than the thickness of the main body portion 41. The thickness of each lead portion 43 can be set, for example, to about 0.3 to 0.7 times the thickness of the main body portion 41. The thickness of each lead portion 43 can be, for example, about 50 μm to 200 μm. Each lead portion 43 is formed so as to be recessed from the upper surface 41T side of the main body portion 41 toward the wiring board 20. The upper surface 43T of each lead portion 43 is provided below the upper surface 41T of the main body portion 41. The upper surface 43T of each lead portion 43 is formed flush with, for example, the upper surface 42T of the protruding portion 42. The upper surface 43T of each lead portion 43 is covered, for example, with the encapsulating resin 50. The lower surface 43U of each lead portion 43 is formed flush with, for example, the lower surface 41U of the main body portion 41 and the lower surface 42U of the protruding portion 42. The lower surface 43U of each lead portion 43 is covered, for example, with the encapsulating resin 50.

[0032] As shown in Figs. 1(a) and 4, each lead portion 43 has an outer surface 43S that is exposed from the outer surface 50S of the encapsulating resin 50. In other words, the outer surface 43S of each lead portion 43 that is located on the outer peripheral edge of the semiconductor device 10 is exposed from the outer surface 50S of the encapsulating resin 50. The outer surface 43S of each lead portion 43 is formed flush with, for example, the outer surface 50S of the encapsulating resin 50. As shown in Fig. 2, the side surfaces of each lead portion 43 excluding the outer surface 43S are covered with the encapsulating resin 50.

[0033] (Configuration of the encapsulating resin 50) As shown in FIG. 1(a), the encapsulating resin 50 is formed to fill the space between the wiring substrate 20 and the heat sink 40 and to encapsulate the semiconductor element 30. The encapsulating resin 50 is formed on the upper surface of the substrate body 21. The encapsulating resin 50 is formed, for example, to entirely cover the semiconductor element 30 including the bumps 31. The encapsulating resin 50 is formed, for example, to cover the entire surface of the semiconductor element 30. The encapsulating resin 50 is formed, for example, to fill the space between the wiring substrate 20 and the semiconductor element 30. The encapsulating resin 50 is formed, for example, to entirely cover the upper surface of the substrate body 21 and the wiring layer 24 exposed in the opening 25X of the solder resist layer 25.

[0034] The encapsulating resin 50 is formed to fill the space between the semiconductor element 30 and the heat sink 40. Here, the distance between the back surface (here, the upper surface) of the semiconductor element 30 and the lower surface of the heat sink 40, specifically, the shortest distance between the back surface of the semiconductor element 30 and the lower surface of the heat sink 40 can be, for example, about 40 μm to 100 μm. Only the encapsulating resin 50, for example, is provided in the space between the back surface of the semiconductor element 30 and the lower surface of the heat sink 40. In other words, the heat sink 40 is provided above the semiconductor element 30 only via the encapsulating resin 50. The heat sink 40 is thermally coupled to the semiconductor element 30 only via the encapsulating resin 50. The encapsulating resin 50 that fills the space between the semiconductor element 30 and the heat sink 40 is formed to cover the entire lower surface 41U of the main body portion 41.

[0035] The sealing resin 50 is formed, for example, so as to fill the space between the solder resist layer 25 and the heat sink 40. In the space between the upper surface of the solder resist layer 25 and the lower surface of the heat sink 40, for example, no spacer member is provided to maintain the distance between the wiring board 20 and the heat sink 40 at a predetermined distance, and only the sealing resin 50 is provided. That is, in the region other than the mounting region of the semiconductor element 30, only the sealing resin 50 is provided in the space between the wiring board 20 and the heat sink 40. In other words, the heat sink 40 is provided above the wiring board 20 only via the sealing resin 50. The heat sink 40 is supported above the wiring board 20 only by the sealing resin 50. The sealing resin 50 is formed, for example, so as to cover the entire upper surface of the solder resist layer 25.

[0036] The sealing resin 50 formed in the outer peripheral region outside the mounting region is formed so as to embed the protruding portion 42 and the lead portion 43 of the heat sink 40. The sealing resin 50 is formed so as to embed at least the upper surfaces 42T, 43T and the lower surfaces 42U, 43U of the protruding portion 42 and the lead portion 43. Specifically, the sealing resin 50 is formed so as to cover the entire upper surface 42T of the protruding portion 42, the entire lower surface 42U of the protruding portion 42, and the entire side surface of the protruding portion 42. The sealing resin 50 is formed so as to cover the entire upper surface 43T of the lead portion 43, the entire lower surface 43U of the lead portion 43, and the entire side surface of the lead portion 43 except for the outer side surface 43S.

[0037] The outer side surface 50S of the sealing resin 50 is formed so as to expose the outer side surface 43S of the lead portion 43. The outer side surface 50S of the sealing resin 50 is formed flush with, for example, the outer side surface 43S of the lead portion 43, the outer side surface of the substrate body 21, and the outer side surfaces of the solder resist layers 23, 25.

[0038] The sealing resin 50 is formed so as to cover a part of the side surface of the main body portion 41 in the thickness direction (the vertical direction in the figure) of the main body portion 41. The sealing resin 50 is formed so as to cover the side surface at the lower part of the main body portion 41. The sealing resin 50 is formed so as to cover the side surface of the main body portion 41 over the entire circumference in the circumferential direction of the main body portion 41. The sealing resin 50 is formed so as to expose the side surface at the upper part of the main body portion 41. The sealing resin 50 is formed so as to expose the entire upper surface 41T of the main body portion 41.

[0039] As shown in FIG. 1(b), the upper surface 50T of the sealing resin 50 is provided below the upper surface 41T of the main body portion 41. Thereby, a step is provided between the upper surface 50T of the sealing resin 50 and the upper surface 41T of the main body portion 41. The distance between the upper surface 50T and the upper surface 41T in the thickness direction (the vertical direction in the figure) of the sealing resin 50 can be, for example, about 1 μm to 30 μm.

[0040] The upper surface 50T has, for example, a flat portion 51 and an inclined portion 52. The upper surface 50T has, for example, the flat portion 51 and the inclined portion 52 continuously formed integrally. The flat portion 51 extends horizontally, for example, along the plane direction (the left - right direction in the figure) orthogonal to the thickness direction of the sealing resin 50. The flat portion 51 extends parallel to the upper surface 41T of the main body portion 41, for example.

[0041] The inclined portion 52 is provided around the main body portion 41. The inclined portion 52 is provided between the flat portion 51 and the side surface of the main body portion 41. The inclined portion 52 is formed so as to contact the side surface of the main body portion 41. For example, in a plan view, the inclined portion 52 is formed so as to surround the main body portion 41. The inclined portion 52 is formed so as to incline downward from the side surface of the main body portion 41 toward the flat portion 51. The inclined portion 52 is formed so as to incline downward as it separates from the side surface of the main body portion 41. For example, the inclined portion 52 is formed so as to incline in a curved shape. For example, the inclined portion 52 is formed on a curved surface that is curved in an arc shape or an elliptical arc shape. Note that the inclined portion 52 may be formed so as to incline linearly in a cross-sectional view. That is, the inclined portion 52 may be formed so as to incline at a constant inclination angle.

[0042] As shown in FIG. 1(a), the heat sink 40 is fixed to the wiring board 20 by the encapsulating resin 50, and the semiconductor element 30 is encapsulated. That is, the encapsulating resin 50 functions as a support member that supports the heat sink 40 on the wiring board 20 and also functions as a protection member that protects the semiconductor element 30. Further, by providing the encapsulating resin 50, the mechanical strength of the entire semiconductor device 10 can be increased. For this reason, the wiring board 20 and the heat sink 40 can be thinned, and the entire semiconductor device 10 can be thinned.

[0043] As the material of the encapsulating resin 50, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. As the material of the encapsulating resin 50, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which fillers such as silica or alumina are mixed into these resins can be used. As the encapsulating resin 50, for example, a mold resin can be used.

[0044] (Configuration of the external connection terminal 60) The external connection terminal 60 is formed on the external connection pad P1 of the wiring board 20. The external connection terminal 60 is a connection terminal that is electrically connected to a pad provided on a mounting board such as a motherboard (not shown), for example. As the external connection terminal 60, for example, solder balls or lead pins can be used. The external connection terminal 60 of the present embodiment is a solder ball.

[0045] (Method for manufacturing semiconductor device 10) Next, a method for manufacturing the semiconductor device 10 will be described. For convenience of explanation, parts that will finally become the components of the semiconductor device 10 will be described with the reference numerals of the final components.

[0046] First, in the process shown in FIG. 5, a large-sized first substrate 80 is prepared. The first substrate 80 has a plurality of first product regions 81 and a first non-product region 82. In the first substrate 80, for example, a plurality of first product regions 81 are arranged in a matrix (here, 3×3). In each first product region 81, a structure corresponding to the wiring board 20 shown in FIG. 1(a) is formed. The first non-product region 82 is formed so as to surround the nine first product regions 81 in a plan view. The first non-product region 82 is formed so as to surround each of the nine first product regions 81 in a plan view, for example. The first non-product region 82 has, for example, a first outer peripheral region 83 that collectively surrounds the nine first product regions 81 and a first connection region 84 provided between two adjacent first product regions 81 in the vertical direction in the figure. The first connection region 84 extends along the left-right direction in the figure.

[0047] Here, after a structure corresponding to the semiconductor device 10 shown in Fig. 1(a) is formed in each first product region 81, it is finally cut along the cutting line indicated by the dashed line and fragmented into individual pieces, each becoming an individual semiconductor device 10. That is, the portion outside each first product region 81, namely the first non-product region 82, is the portion that will ultimately be discarded. In other words, the first non-product region 82 is the portion that does not remain in the finally fragmented semiconductor device 10. In the example shown in Fig. 5, the first substrate 80 has nine first product regions 81, but the number of first product regions 81 is not particularly limited. Hereinafter, for simplicity of explanation, the description will be given by focusing on one first product region 81 and the first non-product region 82 provided around the one first product region 81.

[0048] As shown in Fig. 6, each first product region 81 of the first substrate 80 has a substrate body 21, a wiring layer 22 and a solder resist layer 23 laminated on the lower surface of the substrate body 21, and a wiring layer 24 and a solder resist layer 25 laminated on the upper surface of the substrate body 21. At this time, a wiring layer 26 laminated on the upper surface of the substrate body 21 is formed in the first non-product region 82 of the first substrate 80. An opening 25Y is formed in the solder resist layer 25 provided in the first non-product region 82 to expose a part of the upper surface of the wiring layer 26 as the first connection portion A1. As shown in Fig. 5, in the first outer peripheral region 83 of the first non-product region 82, a plurality of rows of first connection portions A1 are arranged, for example, peripherally in a plan view. That is, the plurality of rows of first connection portions A1 provided in the first outer peripheral region 83 are provided along the outer peripheral edge of the first substrate 80. A plurality of first connection portions A1 are provided in the first connection region 84 of the first non-product region 82. The first connection portions A1 provided in the first connection region 84 are provided between two adjacent first product regions 81 in the vertical direction in the figure.

[0049] Next, in the process shown in Fig. 7, a solder layer 85 is formed on the upper surface of the wiring layer 26 exposed through the opening 25Y of the solder resist layer 25, that is, on the first connection portion A1. The solder layer 85 can be formed, for example, by applying a solder paste on the first connection portion A1 by screen printing or the like.

[0050] Also, in the process shown in FIG. 7, the semiconductor element 30 is prepared. The semiconductor element 30 has a plurality of bumps 31 formed on the circuit formation surface (here, the lower surface). Subsequently, the semiconductor element 30 is mounted on the upper surface of the wiring layer 24 in each first product region 81. For example, the bumps 31 of the semiconductor element 30 are flip-chip bonded onto the wiring layer 24 in each first product region 81. Specifically, when the bumps 31 are solder bumps, a flux (not shown) is appropriately applied onto the wiring layer 24, the wiring layer 24 and the bumps 31 are aligned, and then a reflow process is performed at a temperature of about 230°C to 260°C. Thereby, the solder bumps 31 are melted, and the bumps 31 are electrically connected to the wiring layer 24.

[0051] Next, in the process shown in FIG. 8, a large-sized second substrate 90 is prepared. The second substrate 90 is, for example, a metal plate. The second substrate 90 in the present embodiment is a copper plate. The second substrate 90 has a plurality of second product regions 91 and a second non-product region 92. The second substrate 90 has, for example, a plurality of second product regions 91 arranged in a matrix (here, 3×3). In each second product region 91, a structure corresponding to the heat sink 40 shown in FIG. 1(a) is formed. The second non-product region 92 is formed so as to surround the nine second product regions 91 in a plan view. The second non-product region 92 is formed so as to surround each of the nine second product regions 91 in a plan view, for example. The second non-product region 92 has, for example, a second outer peripheral region 93 that collectively surrounds the nine second product regions 91, and a second connection region 94 provided between two adjacent second product regions 91 in the vertical direction in the drawing. The second connection region 94 extends along the horizontal direction in the drawing.

[0052] Here, after a structure corresponding to the semiconductor device 10 shown in Fig. 1(a) is formed in each second product region 91, it is finally cut along the cutting line indicated by the dashed line to be fragmented, and each becomes an individual semiconductor device 10. That is, the portion outside each second product region 91, namely the second non-product region 92, is the portion that is finally discarded. In other words, the second non-product region 92 is the portion that does not remain in the finally fragmented semiconductor device 10. In the example shown in Fig. 8, the second substrate 90 has nine second product regions 91, but the number of second product regions 91 is not particularly limited. Hereinafter, for the sake of simplicity of explanation, the description will be given focusing on one second product region 91 and the second non-product region 92 provided around the one second product region 91.

[0053] As shown in Figs. 8 and 9, in each second product region 91 of the second substrate 90, a main body portion 41, a protruding portion 42, and a lead portion 43 are formed. In other words, as shown in Fig. 8, in each second product region 91, an opening 91X that defines the main body portion 41, the protruding portion 42, and the lead portion 43 is formed. As shown in Fig. 9, in each second product region 91, recesses 91Y are formed in the upper surface 42T of the protruding portion 42 and the upper surface 43T of the lead portion 43. That is, the protruding portion 42 and the lead portion 43 in this example are thinned from the upper surface side of the second substrate 90. The above-described opening 91X and recess 91Y can be formed, for example, by etching or pressing.

[0054] As shown in Fig. 8, in the second connection region 94 of the second non-product region 92, a connection portion 95 that connects the lead portions 43 formed in two second product regions 91 adjacent in the vertical direction in the figure is formed. In other words, the lead portion 43 formed in each second product region 91 is connected to the lead portion 43 formed in the second product region 91 adjacent in the vertical direction in the figure via the connection portion 95. Also, the lead portion 43 formed in each second product region 91 is directly connected to, for example, the lead portion 43 formed in the second product region 91 adjacent in the horizontal direction in the figure.

[0055] In the process shown in FIG. 9, a metal layer 96 is formed on the lower surface of the second substrate 90 in the second non-product region 92. In this example, the metal layer 96 is partially formed on a part of the lower surface of the second substrate 90 in the second non-product region 92. The metal layer 96 can be formed, for example, by an electrolytic plating method that uses the second substrate 90 as a power supply layer. For example, a resist layer covering the entire surface of the second substrate 90 except for the formation region of the metal layer 96 is formed, and the metal layer 96 is formed on the second substrate 90 exposed from the resist layer by an electrolytic plating method using the resist layer as a plating mask. Also, the metal layer 96 may be formed by a sparger method. Examples of the metal layer 96 include an Ag layer, an Au layer, a Ni layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, and a Ni layer / Ag layer. The outermost layer of the metal layer 96 in the present embodiment is composed of, for example, a noble metal plating layer such as an Au layer, an Ag layer, or a Pd layer. The outermost layer of the metal layer 96, that is, the lower surface of the metal layer 96, functions as a second connection portion A2 that is connected to the first connection portion A1 of the first substrate 80 shown in FIG. 7. The plurality of second connection portions A2 are provided at positions corresponding to the plurality of first connection portions A1, respectively.

[0056] Specifically, as shown in FIG. 8, in the second outer peripheral region 93 of the second non-product region 92, a plurality of rows of second connection portions A2 are arranged, for example, peripherally in a plan view. That is, the plurality of rows of second connection portions A2 provided in the second outer peripheral region 93 are provided along the outer peripheral edge of the second substrate 90. A plurality of second connection portions A2 are provided in the connection portion 95 provided in the second connection region 94. The second connection portions A2 provided in the connection portion 95 are provided between two adjacent second product regions 91 in the vertical direction in the figure.

[0057] Subsequently, in the process shown in FIG. 10, a solder layer 97 is formed on the lower surface of the metal layer 96, that is, on the second connection portion A2. The solder layer 97 can be formed, for example, by applying a solder paste on the second connection portion A2 by screen printing or the like. Next, a columnar metal post 98 is mounted (joined) on the second connection portion A2. For example, the metal post 98 is mounted on the solder layer 97, and a reflow process is performed at a predetermined temperature to melt the solder layer 97 and fix the metal post 98 on the second connection portion A2. At this time, since the outermost layer of the metal layer 96 is composed of a noble metal plating layer, the solder can be suitably spread over the metal layer 96. Note that, as the material of the metal post 98, for example, copper or a copper alloy can be used.

[0058] Next, in the process shown in FIG. 11, the second substrate 90 is disposed above the first substrate 80. At this time, the first substrate 80 and the second substrate 90 are disposed such that the first product region 81 and the second product region 91 overlap each other in plan view. That is, the first substrate 80 and the second substrate 90 are disposed such that the first product region 81 and the second product region 91 are vertically aligned. Further, the first substrate 80 and the second substrate 90 are disposed such that the first connection portion A1 of the first substrate 80, the second connection portion A2 of the second substrate 90, and the metal post 98 face each other.

[0059] Next, in the process shown in FIG. 12, the first connection portion A1 and the second connection portion A2 are connected via the metal post 98, and the second substrate 90 is mounted on the first substrate 80. For example, after appropriately applying a flux on the solder layer 85 of the first substrate 80, the second substrate 90 is disposed on the first substrate 80 with the metal post 98 interposed therebetween. The first substrate 80 and the second substrate 90 thus overlapped are heated and pressed at a temperature of about 230° C. to 260° C. Thereby, the solder layers 85 and 97 are melted, and the metal post 98 is joined to the first connection portion A1 and the second connection portion A2. By this process, the second substrate 90 is fixed to the first substrate 80 via the metal post 98, and the first connection portion A1 and the second connection portion A2 are electrically connected via the metal post 98. In this process, although the reflow process is performed while pressing the second substrate 90 toward the first substrate 80, the metal post 98 functions as a spacer. Therefore, the distance between the first substrate 80 and the second substrate 90 can be suitably maintained at a predetermined distance.

[0060] Next, in the process shown in FIG. 13, an adhesive film 100 is mounted on the upper surface of the second substrate 90. The adhesive film 100 is provided on the upper surface of the second substrate 90 so as to close, for example, the opening of the recess 91Y. The adhesive film 100 is provided on the upper surface of the second substrate 90 so as to close, for example, the upper opening of the opening 91X shown in FIG. 8. As the material of the adhesive film 100, for example, a material excellent in chemical resistance and heat resistance can be used. As the material of the adhesive film 100, for example, a material excellent in flexibility can be used. As the adhesive film 100, for example, a polytetrafluoroethylene (PTFE) film or a polyethylene terephthalate (PET) film can be used.

[0061] Subsequently, in the process shown in FIG. 14, the adhesive film 100 is pressed toward the second substrate 90 so that the upper part of the second substrate 90 is recessed into the adhesive film 100. By this process, the adhesive film 100 is provided so as to house the upper part of the second substrate 90, specifically, the upper part of the main body 41. The adhesive film 100 is provided so as to cover the side surface at the upper part of the main body 41. In other words, the adhesive film 100 is provided so as to cover a part of the inner side surface of the recess 91Y. That is, by this process, the adhesive film 100 is pushed into the recess 91Y. Thus, in the processes shown in FIGS. 13 and 14, the adhesive film 100 is adhered to the upper surface of the second substrate 90 so as to house the upper part of the second substrate 90.

[0062] Next, in the process shown in FIG. 15, a sealing resin 50 is formed to fill the space between the first substrate 80 and the second substrate 90. The sealing resin 50 is formed so as to fill the space between the first substrate 80 and the semiconductor element 30 and the space between the semiconductor element 30 and the second substrate 90. The sealing resin 50 is formed so as to fill the recess 91Y exposed from the adhesive film 100. The sealing resin 50 is formed so as to fill the opening 91X (see FIG. 8) exposed from the adhesive film 100. The sealing resin 50 can be formed, for example, by a resin molding method. For example, when a mold resin having thermosetting properties is used as the material of the sealing resin 50, the structure shown in FIG. 14 is housed in a mold, and the mold resin fluidized by applying pressure (for example, 5 MPa to 10 MPa) is introduced into the mold. Then, the sealing resin 50 is formed by heating the mold resin at a temperature of about 180° C. to cure it. After the required sealing process is completed, the structure with the sealing resin 50 formed is taken out of the mold. Note that, as a method of filling the mold resin, for example, methods such as a transfer molding method, a compression molding method, and an injection molding method can be used.

[0063] During the encapsulation process of this project, the adhesive film 100 serves to suppress the leakage of the molding resin onto the upper surface of the second substrate 90 (also referred to as "mold flash"). Even when such an adhesive film 100 is provided, the molding resin may enter between the adhesive film 100 and the second substrate 90. Here, when the upper surface 50T of the encapsulation resin 50 and the upper surface 41T of the main body portion 41 are formed flush, the adhesive film 100 is provided on the upper surface 41T of the main body portion 41. In this case, if the molding resin enters between the lower surface of the adhesive film 100 and the upper surface 41T of the main body portion 41, a resin film will be formed on a part of the upper surface 41T of the main body portion 41. When such a resin film is formed, the contrast between the upper surface 41T of the main body portion 41 and the upper surface 50T of the encapsulation resin 50 becomes weak. Therefore, when the upper surface 41T of the main body portion 41 is used as the recognition mark M1, the recognition performance of the recognition mark M1 deteriorates.

[0064] In contrast, in this embodiment, the adhesive film 100 is provided so as to cover the upper part of the second substrate 90, specifically, the upper part of the main body portion 41. Therefore, a step can be provided between the lower surface of the adhesive film 100 and the upper surface 41T of the main body portion 41. Thereby, the distance from the gap between the adhesive film 100 and the second substrate 90 to the upper surface 41T of the main body portion 41 can be made longer than the case where the upper surface 50T of the encapsulation resin 50 and the upper surface 41T of the main body portion 41 are formed flush. Therefore, even when the molding resin enters between the adhesive film 100 and the second substrate 90, it is possible to preferably suppress the leakage of the molding resin to the upper surface 41T of the main body portion 41. That is, by providing a step between the upper surface 41T of the main body portion 41 and the upper surface 50T of the encapsulation resin 50, it is possible to preferably suppress the overflow of the molding resin onto the upper surface 41T of the main body portion 41.

[0065] Subsequently, in the process shown in FIG. 16, the adhesive film 100 shown in FIG. 15 is peeled off. As a result, the upper part of the second substrate 90 embedded in the adhesive film 100 and the upper surface 50T of the encapsulation resin 50 are exposed.

[0066] Through the above manufacturing process, structures corresponding to the semiconductor device 10 can be formed in each first product region 81 and each second product region 91. Next, using a dicing saw or the like, the first substrate 80, the second substrate 90, and the encapsulation resin 50 are cut along the cutting positions indicated by the one-dot chain lines in the figure, that is, along the outer edges of the first product region 81 and the second product region 91, and separated into individual semiconductor devices 10. Through this process, as shown in FIG. 17, the outer surface 43S of the lead portion 43, the outer surface 50S of the encapsulation resin 50, and the outer surface of the substrate body 21, which are the cutting surfaces, are formed flush. Further, through this process, the first non-product region 82 and the second non-product region 92 including the metal posts 98 shown in FIG. 16 are removed.

[0067] Through the above manufacturing process, a plurality of semiconductor devices 10 can be manufactured collectively. Note that the semiconductor device 10 after separation can be used in an upside-down state or arranged at an arbitrary angle.

[0068] Next, the effects of this embodiment will be described. (1) The semiconductor device 10 includes a wiring substrate 20, a semiconductor element 30 mounted on the wiring substrate 20, and a heat sink 40 provided above the semiconductor element 30. The semiconductor device 10 has an encapsulation resin 50 that fills the space between the wiring substrate 20 and the heat sink 40 and encapsulates the semiconductor element 30. The heat sink 40 has a main body portion 41 provided at a position overlapping the semiconductor element 30 in plan view. The encapsulation resin 50 is formed so as to cover a part of the side surface of the main body portion 41. The upper surface 50T of the encapsulation resin 50 is provided below the upper surface 41T of the main body portion 41. The encapsulation resin 50 is formed so as to expose the entire upper surface 41T of the main body portion 41 and the side surface at the upper part of the main body portion 41.

[0069] According to this configuration, since the upper surface 50T of the sealing resin 50 is provided below the upper surface 41T of the main body portion 41, a step is provided between the upper surface 50T of the sealing resin 50 and the upper surface 41T of the main body portion 41. As a result, a step between the main body portion 41 and the sealing resin 50 is formed at the contour portion (outer edge) of the upper surface 41T of the main body portion 41. Therefore, when detecting the contour of the upper surface 41T of the main body portion 41 as the recognition mark M1 by a recognition camera or the like, the contrast between the upper surface 41T of the main body portion 41 and the upper surface 50T of the sealing resin 50 can be easily obtained. Thus, since the contour of the upper surface 41T of the main body portion 41 can be easily recognized, the recognition performance of the recognition mark M1 can be improved.

[0070] (2) Further, since a step is provided between the upper surface 50T of the sealing resin 50 and the upper surface 41T of the main body portion 41, when forming the sealing resin 50, it is possible to preferably suppress the molding resin from rising onto the upper surface 41T of the main body portion 41. Thereby, it is possible to preferably suppress the formation of a resin film covering a part of the upper surface 41T of the main body portion 41. Therefore, compared with the case where a resin film is formed on the upper surface 41T of the main body portion 41, the contrast between the upper surface 41T of the main body portion 41 and the upper surface 50T of the sealing resin 50 is enhanced. As a result, the visibility of the recognition mark M1 can be improved.

[0071] (3) The upper surface 50T of the sealing resin 50 has an inclined portion 52 that contacts the side surface of the main body portion 41. The inclined portion 52 is formed to incline downward as it moves away from the side surface of the main body portion 41. According to this configuration, when irradiating light from above the semiconductor device 10 onto the upper surfaces 41T and 50T to recognize the recognition mark M1, the light is diffusely reflected (scattered reflection) at the inclined portion 52. Thereby, the contrast between the upper surface 41T of the main body portion 41 and the upper surface 50T of the sealing resin 50 is enhanced. As a result, the visibility of the recognition mark M1 can be further improved.

[0072] (4) Further, since the inclined portion 52 contacts the side surface of the main body portion 41, the contact area between the sealing resin 50 and the side surface of the main body portion 41 can be increased as compared with the case where the upper surface 50T of the sealing resin 50 is composed of only the flat portion 51. Thereby, the adhesion between the sealing resin 50 and the heat sink 40 can be improved.

[0073] (5) Since the contact area between the sealing resin 50 and the side surface of the main body portion 41 can be increased, even when thermal stress is applied to the interface between the sealing resin 50 and the main body portion 41 in a reliability test or the like due to a thermal cycle, the thermal stress can be preferably dispersed. Thereby, it is possible to preferably suppress the occurrence of cracks at the interface between the sealing resin 50 and the main body portion 41 due to the thermal stress.

[0074] (6) The inclined portion 52 is a curved surface curved in an arc shape. According to this configuration, a curved surface is formed at the interface between the heat sink 40 and the sealing resin 50. Therefore, even when thermal stress is applied to the interface between the heat sink 40 and the sealing resin 50, the thermal stress can be preferably dispersed by the above-described curved surface. Therefore, even when thermal stress is applied to the interface between the heat sink 40 and the sealing resin 50, it is possible to suppress the occurrence of cracks at the interface between the heat sink 40 and the sealing resin 50 due to the thermal stress.

[0075] (7) The upper surface 41T of the main body portion 41 is exposed from the sealing resin 50. According to this configuration, the heat generated in the semiconductor element 30 is conducted to the heat sink 40 through the sealing resin 50, and the heat is radiated from the upper surface 41T of the main body portion 41 of the heat sink 40 into the atmosphere. Thereby, the heat generated by the semiconductor element 30 can be efficiently radiated as compared with the case where the upper surface 41T of the main body portion 41 is covered with the sealing resin 50.

[0076] (8) The upper surface 43T and the lower surface 43U of the lead portion 43 are covered with the encapsulating resin 50. Thereby, the lead portion 43 can be embedded in the encapsulating resin 50. For this reason, due to the anchor effect, the adhesion between the lead portion 43 and the encapsulating resin 50 can be improved. Therefore, it is possible to preferably suppress the heat dissipation plate 40 having the lead portion 43 from peeling off from the encapsulating resin 50. As a result, it is possible to preferably suppress a decrease in the heat dissipation performance of the semiconductor device 10.

[0077] (9) Further, since the lead portion 43 is embedded in the encapsulating resin 50, it is possible to preferably suppress warping from occurring in the heat dissipation plate 40 having the lead portion 43. For this reason, it is possible to preferably suppress the heat dissipation plate 40 from peeling off from the encapsulating resin 50 due to warping.

[0078] (10) The outer surface 43S of the lead portion 43 is exposed from the encapsulating resin 50. According to this configuration, heat generated in the semiconductor element 30 is conducted to the heat dissipation plate 40 through the encapsulating resin 50, and the heat is dissipated from the outer surface 43S of the lead portion 43 of the heat dissipation plate 40 into the atmosphere. Thereby, compared with the case where the outer surface 43S of the lead portion 43 is covered with the encapsulating resin 50, the heat generated by the semiconductor element 30 can be efficiently dissipated.

[0079] (11) The heat dissipation plate 40 has a protruding portion 42 that protrudes outward from the side surface of the main body portion 41. The protruding portion 42 is formed so as to surround the main body portion 41 in a plan view. The protruding portion 42 is formed thinner than the main body portion 41. The encapsulating resin 50 covers the upper surface 42T and the side surface of the protruding portion 42.

[0080] According to this configuration, the upper and lower surfaces and the side surface of the protruding portion 42 are covered with the encapsulating resin 50. Thereby, the protruding portion 42 formed so as to surround the main body portion 41 can be embedded in the encapsulating resin 50. For this reason, due to the anchor effect, the adhesion between the protruding portion 42 and the encapsulating resin 50 can be improved. Therefore, it is possible to preferably suppress the heat dissipation plate 40 having the protruding portion 42 from peeling off from the encapsulating resin 50. As a result, it is possible to preferably suppress a decrease in the heat dissipation performance of the semiconductor device 10.

[0081] (12) The heat dissipation plate 40 is supported above the wiring board 20 only by the sealing resin 50. In other words, the semiconductor device 10 is not provided with a connecting member (spacer) such as a metal post 98 that connects the heat dissipation plate 40 and the wiring board 20. Therefore, the semiconductor device 10 can be miniaturized compared to the case where a connecting member is provided.

[0082] (13) A metal post 98, which is a connecting member that connects the first substrate 80 and the second substrate 90, is provided in the first non-product area 82 provided outside the first product area 81 and the second non-product area 92 provided outside the second product area 91. Then, with the first substrate 80 and the second substrate 90 connected by the metal post 98, the space between the first substrate 80 and the second substrate 90 and the space between the semiconductor element 30 and the second substrate 90 are filled, and a sealing resin 50 that seals the semiconductor element 30 is formed.

[0083] According to this configuration, the sealing resin 50 can be formed while maintaining the distance between the first substrate 80 and the second substrate 90 at a desired distance by the metal post 98. Thereby, the distance between the wiring board 20 and the heat dissipation plate 40 in the semiconductor device 10 after singulation can be suitably set to a desired distance. Furthermore, the distance between the semiconductor element 30 and the heat dissipation plate 40 in the semiconductor device 10 after singulation can be suitably set to a desired distance. Furthermore, since no metal post 98 remains in the semiconductor device 10 after singulation, the semiconductor device 10 can be miniaturized.

[0084] (Modification example) The above embodiment can be implemented with the following modifications. The above embodiment and the following modification examples can be implemented in combination with each other as long as they do not technically conflict.

[0085] · The upper surface 50T of the sealing resin 50 in the above embodiment can be appropriately changed. For example, the inclined portion 52 may be omitted. In this case, the upper surface 50T is composed of only the flat portion 51.

[0086] ·The structure of the heat sink 40 in the above embodiment can be changed as appropriate. ·For example, as shown in FIG. 18, lead portions 43 may be provided only on two of the four sides that form the outer shape of the rectangular main body portion 41. In this modification example, one lead portion 43 is provided on each of the two sides facing each other in the left-right direction in the figure.

[0087] ·For example, as shown in FIG. 19, the protruding portion 42 (see FIG. 2) may be omitted from the heat sink 40. In this case, each lead portion 43 is formed so as to protrude outward from the side surface of the main body portion 41. In this case, only the lead portions 43 of the heat sink 40 are embedded inside the encapsulating resin 50.

[0088] ·The lead portions 43 may be omitted from the heat sink 40 in the above embodiment. ·The planar shape of the main body portion 41 in the above embodiment can be changed as appropriate. For example, the planar shape of the main body portion 41 may be changed to a polygon other than a quadrilateral, a circle, or an ellipse.

[0089] ·In the above embodiment, the heat sink 40 is supported on the wiring board 20 only by the encapsulating resin 50, but it is not limited thereto. For example, the heat sink 40 may be mounted on the upper surface of the semiconductor element 30 with an adhesive or the like.

[0090] ·In the above embodiment, a surface treatment layer may be formed on the surface of the heat sink 40. As the surface treatment layer, for example, an oxide film can be used. As the surface treatment layer, for example, a film of copper oxide containing a hydroxide can be used.

[0091] ·In the above embodiment, an outer layer plating layer may be formed on the surface of the main body portion 41 exposed from the encapsulating resin 50. Examples of the outer layer plating layer include an Sn layer and a solder layer. As the material of the solder layer, for example, an alloy containing Pb, an alloy of Sn and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, etc. can be used.

[0092] · The structure of the wiring board 20 in the above embodiment can be changed as appropriate. For example, the solder resist layer 25 may be omitted. For example, the number and arrangement of the wiring layers 24 can be changed as appropriate. For example, the number and arrangement of the wiring layers 22 can be changed as appropriate.

[0093] · The number of semiconductor elements 30 mounted on the wiring board 20 in the above embodiment is not particularly limited. For example, a plurality of semiconductor elements 30 may be mounted on the wiring board 20. · The mounting form of the semiconductor element 30 in the above embodiment can be changed as appropriate. Examples of the mounting form of the semiconductor element 30 include flip chip mounting, wire bonding mounting, solder mounting, or a combination of these.

[0094] · In the above embodiment, an underfill resin may be provided between the semiconductor element 30 and the substrate body 21. · In the above embodiment, the connecting member that connects the first substrate 80 and the second substrate 90 may be changed to a connecting member other than the metal post 98. For example, the connecting member may be changed to a solder ball such as a solder ball with a core. The solder ball with a core has, for example, a spherical conductive core ball and a solder layer covering the periphery of the conductive core ball.

[0095] · The structure of the first substrate 80 in the above embodiment can be changed as appropriate. For example, the number and arrangement of the first connection portions A1 can be changed as appropriate. For example, a first connection portion A1 may be provided between two adjacent first product regions 81 in the left - right direction in FIG. 5.

[0096] · The structure of the second substrate 90 in the above embodiment can be changed as appropriate. For example, the number and arrangement of the second connection portions A2 can be changed as appropriate. For example, a second connection portion A2 may be provided between two adjacent second product regions 91 in the left - right direction in FIG. 8.

Description of Reference Numerals

[0097] M1 Recognition Mark 10 Semiconductor device 20 Wiring board 30 Semiconductor element 40 Heat sink 41 Body part 41T Upper surface 41U Lower surface 42 Protrusion 42T Upper surface 42U Lower surface 43 Lead part 43S Outer surface (second outer surface) 43T Upper surface 43U Lower surface 50 Encapsulating resin 50S Outer surface (first outer surface) 50T Upper surface 51 Flat part 52 Inclined part 80 First substrate 90 Second substrate 100 Adhesive film

Claims

1. A wiring board, a semiconductor element mounted on the wiring board, a heat sink provided above the semiconductor element, and a sealing resin that fills a space between the wiring board and the heat sink and seals the semiconductor element. The heat sink has a main body portion provided at a position overlapping the semiconductor element in a plan view, and a lead portion protruding outward from the main body portion. The lead portion is formed thinner than the main body portion. The lead portion has a second outer surface exposed from a first outer surface of the sealing resin. The sealing resin is formed to cover a part of a side surface of the main body portion and an upper surface of the lead portion. An upper surface of the sealing resin is provided below an upper surface of the main body portion. The semiconductor device, wherein the sealing resin is formed to expose an entire upper surface of the main body portion and a side surface at an upper portion of the main body portion.

2. The upper surface of the sealing resin has an inclined portion that contacts a side surface of the main body portion. The semiconductor device according to claim 1, wherein the inclined portion is formed to incline downward as it moves away from the side surface of the main body portion.

3. The semiconductor device according to claim 2, wherein the inclined portion is a curved surface curved in an arc shape.

4. The semiconductor device according to claim 2, wherein the upper surface of the sealing resin has a flat portion formed continuously with the inclined portion.

5. The semiconductor device according to claim 1, wherein the sealing resin is formed to cover a lower surface of the lead portion and side surfaces of the lead portion except the second outer surface.

6. The semiconductor device according to claim 1, wherein the sealing resin is formed to fill a space between the wiring board and the semiconductor element.

7. The heat sink has a protruding portion protruding outward from a side surface of the main body portion. The protruding portion is formed to surround the main body portion in a plan view. The protruding portion is formed thinner than the main body portion. The lead portion protrudes outward from a side surface of the protruding portion. The semiconductor device according to claim 1, wherein the sealing resin covers an upper surface of the protruding portion and a side surface of the protruding portion.

8. A planar shape of the main body portion is formed in a rectangle. The semiconductor device according to claim 1, wherein the lead portion is provided on at least two sides of four sides constituting the rectangle.

9. The sealing resin is formed so as to fill the space between the semiconductor element and the heat sink. The semiconductor device according to claim 1, wherein the heat sink is supported above the wiring board only by the sealing resin.

10. A step of mounting a semiconductor element on a wiring board; A step of disposing a heat sink having a main body portion provided at a position overlapping the semiconductor element in a plan view above the semiconductor element; A step of attaching an adhesive film to the upper surface of the main body portion so as to house the upper portion of the main body portion; A step of forming a sealing resin that fills the space between the wiring board and the heat sink and seals the semiconductor element; A step of removing the adhesive film, and A method of manufacturing a semiconductor device, wherein the upper surface of the sealing resin is provided below the upper surface of the main body portion.

Images