Semiconductor device

Abstract

To provide a semiconductor device with a large ratio of the area of the active area to the area of the semiconductor substrate.SOLUTION: A semiconductor device includes a semiconductor substrate having a top surface, an active part that is provided on the semiconductor substrate and has a transistor, and a gate runner provided above the top surface of the semiconductor substrate. The transistor includes a MOS gate provided with a gate electrode. The gate runner is electrically connected to the gate electrode. The gate runner is provided between the active part and one side of the semiconductor substrate above the top surface of the semiconductor substrate, and is not provided between the active part and any other sides of the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device having gate fingers provided at the center of a semiconductor body is known (see, for example, Patent Document 1). Also, a semiconductor device using a contact plug for a gate trench is known (see, for example, Patent Document 2 or Patent Document 3). In addition, a trench-type MOSFET using polysilicon with different doping concentrations for the gate electrode of a trench is known (see, for example, Patent Document 4). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent No. 6732715 [Patent Document 2] Japanese Patent No. 5975543 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2009-99872 [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2008-218527

Summary of the Invention

Problems to be Solved by the Invention

[0003] In a semiconductor device, it is preferable to increase the ratio of the area of the active portion to the area of the semiconductor substrate.

Means for Solving the Problems

[0004] In one embodiment of the present invention, a semiconductor device including a semiconductor substrate having an upper surface is provided. The semiconductor device may include an active portion provided on the semiconductor substrate and having transistors. Any of the semiconductor devices may include a gate runner provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices, the transistor may include a MOS gate having a gate electrode. In any of the semiconductor devices, the gate runner may be electrically connected to the gate electrode. In any of the semiconductor devices, the gate runner is provided between the active portion and one side of the semiconductor substrate above the upper surface of the semiconductor substrate, and may not be provided between the active portion and any other side of the semiconductor substrate.

[0005] In any of the semiconductor devices, the gate electrode of the transistor may have a metal portion.

[0006] In any of the semiconductor devices, the MOS gate may have a trench provided on the upper surface of the semiconductor substrate. In any of the semiconductor devices, the metal portion may be provided inside the trench.

[0007] In any of the semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type and a channel region of a second conductivity type provided between the upper surface of the semiconductor substrate and the drift region and in contact with the trench. In any of the semiconductor devices, the metal portion may be provided deeper than the channel region.

[0008] Inside the trench of any of the semiconductor devices, the metal portion and polysilicon may be laminated.

[0009] In any of the semiconductor devices, the trench may have a side wall and a bottom. In any of the semiconductor devices, the polysilicon may be provided between the side wall of the trench and the metal portion.

[0010] In any of the above semiconductor devices, the thickness of the polysilicon laminated with the metal portion in the direction perpendicular to the side wall may be 0.2 μm or less.

[0011] In any of the above semiconductor devices, the thickness of the polysilicon formed at the bottom in the depth direction of the trench may be greater than the thickness of the polysilicon provided between the side wall and the metal portion.

[0012] Any of the above semiconductor devices may further include an emitter electrode provided above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may further include an interlayer insulating film that insulates the gate electrode and the emitter electrode. In any of the above semiconductor devices, the interlayer insulating film may be provided inside the trench.

[0013] In any of the above semiconductor devices, the metal portion may contain tungsten.

[0014] Inside the trench of any of the above semiconductor devices, a barrier metal of a metal different from the metal portion may be provided between the metal portion and the polysilicon.

[0015] In any of the above semiconductor devices, the barrier metal may contain titanium.

[0016] Any of the above semiconductor devices may further include an emitter electrode provided above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may further include an interlayer insulating film that insulates the gate electrode and the emitter electrode. In any of the above semiconductor devices, a contact hole connecting the gate runner and the gate electrode may be provided in the interlayer insulating film. In any of the above semiconductor devices, the contact hole may be filled with tungsten. In any of the above semiconductor devices, a barrier metal may be provided between the tungsten filled in the contact hole and the tungsten in the metal portion.

[0017] Any of the above semiconductor devices may further include a well region that surrounds the active portion in a top view and is formed deeper than the trench from the upper surface of the semiconductor substrate toward the inside. In any of the above semiconductor devices, the well region may have a first well region formed on one side of the semiconductor substrate where the gate runner is provided. In any of the above semiconductor devices, it may have a second well region formed on at least one other side where the gate runner is not provided. In any of the above semiconductor devices, the width of the second well region may be smaller than the width of the first well region.

[0018] In any of the above semiconductor devices, the difference between the width of the second well region and the width of the first well region may be at least half of the width of the gate runner.

[0019] In any of the above semiconductor devices, the trench may extend in a stretching direction perpendicular to one side of the semiconductor substrate where the gate runner is provided in a top view. In any of the above semiconductor devices, the first well region and the second well region may overlap with the end of the trench in the stretching direction. In any of the above semiconductor devices, the length of the overlap between the first well region and the trench may be larger than the length of the overlap between the second well region and the trench.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0021] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention. In this specification, the same parts in each figure are denoted by the same reference numerals, and the description may be omitted. Also, for convenience of explanation, some configurations may not be illustrated.

[0022] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0023] In this specification, when explaining technical matters, a rectangular coordinate system of the X-axis, Y-axis, and Z-axis may be used. The rectangular coordinate system only specifies the relative positions of components and does not limit a specific direction. For example, the Z-axis direction does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without indicating positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0024] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and Y-axis. Also, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the directions parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0025] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0026] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0027] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 1, the positions where each member is projected onto the upper surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0028] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate or a silicon carbide substrate. In this specification, the end portion of the outer periphery of the semiconductor substrate 10 in a top view is defined as the outer peripheral end 140. The top view refers to the case of viewing parallel to the Z-axis from the upper surface side of the semiconductor substrate 10. Also, among the outer peripheral ends 140 of the semiconductor substrate 10 in a top view, any one of the side edges is defined as the first side edge 142. In a top view, the direction parallel to the first side edge 142 is defined as the X-axis direction, and the direction perpendicular to the first side edge 142 is defined as the Y-axis direction. Also, the side edges other than the first side edge 142 are defined as other side edges 143. The semiconductor substrate 10 in this example has three other side edges 143-1, 143-2, and 143-3.

[0029] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An upper surface electrode such as a source electrode or an emitter electrode is provided above the active portion 120, but is omitted in FIG. 1.

[0030] The active portion 120 may have a transistor 70. In this example, the entire active portion 120 is a transistor 70. A transistor 70 may be provided in a part of the active portion 120. As an example, the transistor 70 is a MOSFET or an IGBT. In this specification, the case where an IGBT is provided as the transistor 70 in the active portion 120 is described as an example, but the configuration of the active portion 120 is not limited thereto. The active portion 120 may have a diode.

[0031] The active part 120 may be a part that overlaps with the emitter electrode in a top view. Here, the emitter electrode may be a pad connected to a wire, may be an electrode connected to a wire through which a main current flows, or may be an electrode connected to the emitter region of the transistor 70. The emitter electrode may be connected by solder via a nickel film. When there are a plurality of emitter electrodes, the one with the largest area may be regarded as the emitter electrode. For example, the pad for current sensing may not be included in the emitter electrode.

[0032] The transistor 70 includes a MOS gate having a gate electrode 45. The MOS gate in this example has a trench provided on the upper surface of the semiconductor substrate 10, and the gate electrode 45 is provided inside the trench. The gate electrode 45 in this example includes a polysilicon 44 and a metal part 48. In other examples, the gate electrode 45 may be entirely polysilicon 44 or entirely metal part 48. The configuration of the MOS gate will be described later.

[0033] FIG. 1 shows the arrangement of the metal part 48 and the polysilicon 44 in the active part 120. In a top view, the metal part 48 and the polysilicon 44 may extend in a predetermined direction. That is, in a top view, the trench may also be provided extending in a predetermined direction. The polysilicon 44 and the metal part 48 in this example extend in the Y-axis direction.

[0034] The edge termination structure part 90 is provided between the active part 120 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. The edge termination structure part 90 may be arranged in an annular shape so as to surround the active part 120 on the upper surface of the semiconductor substrate 10. The edge termination structure part 90 in this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure part 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure part 90 has, for example, a guard ring, a field plate, a RESURF, and a structure combining these.

[0035] Above the upper surface of the semiconductor substrate 10, a gate pad 112 is provided. The gate pad 112 is provided between the active portion 120 and the first side 142. The gate pad 112 may not be included in the active portion.

[0036] A gate voltage is applied to the gate pad 112, and the gate voltage is applied to the gate electrode 45 of the MOS gate of the transistor 70 via a gate runner described later. Above the upper surface of the semiconductor substrate 10, other pads for current sensing, for example, may be provided. The pad may be formed of a metal material such as aluminum. An aerial wiring such as a wire may be connected to the upper surface of the gate pad 112. The gate pad 112 may have a rectangular shape in a top view.

[0037] The semiconductor device 100 includes a gate runner 130 provided above the upper surface of the semiconductor substrate 10. The gate runner 130 is electrically connected to the gate electrode 45. The gate runner 130 is also electrically connected to the gate pad 112 and transmits the gate voltage to the gate electrode 45. The gate runner 130 in this example is made of metal. However, the gate runner 130 may be made of polysilicon.

[0038] The gate runner 130 is provided between the active portion 120 and one side of the semiconductor substrate 10 above the upper surface of the semiconductor substrate 10, and may not be provided between the active portion 120 and any other side of the semiconductor substrate 10. The gate runner 130 in this example is provided only between the active portion 120 and the first side 142. The gate runner 130 and the gate electrode 45 in this example are connected only between the active portion 120 and the first side 142.

[0039] The first side 142 in this example is a side parallel to the X axis. The width of the gate runner 130 in the Y-axis direction may be smaller than that of the gate pad 112. The width of the gate runner 130 in the Y-axis direction may be equal to or less than half of the width of the gate pad 112 in the Y-axis direction.

[0040] The gate runner 130 has a length in the X-axis direction that is greater than that of the gate pad 112. The gate runner 130 may be connected to all the gate electrodes 45 arranged side by side in the X-axis direction in the active portion 120. The gate runner 130 in this example extends from the position facing the gate electrode 45 arranged at one end in the X-axis direction to the position facing the gate electrode 45 arranged at the other end among the plurality of gate electrodes 45.

[0041] In the example of FIG. 1, the gate runner 130 is provided between the gate pad 112 and the first side 142. In other examples, the gate runner 130 may have a portion provided between the gate pad 112 and the active portion 120. The gate runner 130 may be provided so as to surround the gate pad 112 in a top view. That is, the gate runner 130 may have a bent portion.

[0042] The trench in this example extends in a stretching direction (Y-axis direction) perpendicular to the first side 142 where the gate runner 130 is provided in a top view. However, the perpendicular may have a width of about ±10°.

[0043] The semiconductor device 100 may further include a well region. The well region is formed inward from the upper surface of the semiconductor substrate 10 and may surround the active portion 120 in a top view. The well region may be provided so that at least a part thereof overlaps with the gate runner 130 in a top view. However, the well region is not shown in FIG. 1.

[0044] When the gate voltage is transmitted from the gate pad 112 to each gate electrode 45, variations occur in the time until the gate voltage is transmitted due to the resistance of the transmission path. In this specification, the delay in the transmission of the gate voltage is referred to as gate delay. When the gate delay is large, for example, at the turn-off of the semiconductor device 100, the region with a large gate delay takes longer to turn off than the region with a small gate delay, and current concentrates in the region with a large gate delay.

[0045] To reduce the gate delay, various arrangements of the gate runner 130 are conceivable. For example, the gate runner 130 may be provided so as to surround the active portion 120 along the outer periphery of the active portion 120. Generally, the gate electrode 45 of the MOS gate is formed of polysilicon, and the gate runner 130 is formed of a metal having a lower resistivity than polysilicon. Therefore, the gate delay can be reduced by connecting the gate runner 130 provided between the active portion 120 and the other side 143 of the semiconductor substrate 10 to the gate electrode 45. However, since the area of the gate runner 130 increases, the area of the active portion 120 decreases or the area of the semiconductor substrate 10 increases.

[0046] As another example, the gate runner 130 may be provided so as to cross the center of the active portion 120. Since the gate runner 130 and the gate electrode 45 are connected at the center of the active portion 120, the gate delay can be reduced. However, in this case, the emitter electrode is divided into two by the gate runner 130. In that case, since wires are bonded to the respective emitter electrodes, the resistance values of the respective bonding portions are different, and current imbalance may occur in each emitter electrode, or oscillation may occur in one emitter electrode.

[0047] In the gate runner 130 of this example, since it is provided only between the active portion 120 and the first side 142, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased as compared with the case where the gate runner 130 is also provided on the other sides. Or, the area of the semiconductor substrate 10 having the active portion 120 of the same area can be reduced. Furthermore, in the case of the arrangement of the gate runner 130 of the embodiment, since there is one emitter electrode, current imbalance and oscillation bias do not occur.

[0048] However, in the arrangement of the gate runner 130 of the embodiment, the gate delay may increase. Therefore, the gate electrode 45 of the transistor 70 may have a metal portion 48. The configuration of the MOS gate will be described later.

[0049] FIG. 2 shows a cross-sectional view taken along line A-A' in FIG. 1. The cross-section A-A' is a YZ cross-section passing through the edge termination structure 90, the gate runner 130, and the MOS gate 40 of the transistor 70. In the cross-section A-A', the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a gate runner 130, a field plate 93, and a protective film 60. The semiconductor substrate 10 has an upper surface 21 and a lower surface. However, in the figures after FIG. 2, the configuration on the lower surface side is omitted. There is a first end side 142 on the positive Y-axis side of the cross-section A-A'.

[0050] The semiconductor substrate 10 has an N-type drift region 18 and a P-type channel region 14. The channel region 14 is provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. The drift region 18 in this example is N-type, and the channel region 14 is P-type. Inside the semiconductor substrate 10 in this example, a MOS gate 40 is provided. The MOS gate 40 controls the switching of the transistor 70 according to the applied gate voltage. The channel region 14 is in contact with the MOS gate 40. The channel region 14 is a region where a channel formed by an electron inversion layer is formed on the surface layer of the interface in contact with the MOS gate 40 when a predetermined gate voltage is applied to the gate electrode 45. Let the length of the channel region 14 in the depth direction from the upper surface 21 be t3.

[0051] In the cross-section A-A', the semiconductor substrate 10 has a first well region 11 formed on one side of the semiconductor substrate 10 where the gate runner 130 is provided. The first well region in this example is provided along the first end side 142. At least a part of the first well region 11 is provided between the first end side 142 and the active part 120 in a top view. The first well region 11 is provided from the upper surface 21 of the semiconductor substrate 10 deeper than the channel region 14. The first well region 11 is a region of the second conductivity type with a doping concentration higher than that of the channel region 14. The first well region 11 in this example is of P+ type. As described above, a P+ type well region surrounding the active part 120 may be provided in the semiconductor substrate 10 in a top view. The first well region 11 may refer to a part of the well region that extends along the first end side 142.

[0052] The transistor 70 has a MOS gate 40 provided inward from the upper surface 21 of the semiconductor substrate 10. As shown in FIG. 1, a plurality of MOS gates 40 may be provided. The MOS gate 40 in this example is arranged along the X-axis direction and extends in the Y-axis direction. In this example, the MOS gate 40 will be described as a trench gate structure.

[0053] The MOS gate 40 has a trench 41, a gate insulating film 42, and a gate electrode 45. The trench 41 is provided on the upper surface 21 of the semiconductor substrate 10 and refers to a groove formed in the depth direction from the upper surface 21. The trench 41 in this example reaches the drift region 18. The channel region 14 is in contact with the trench 41. The channel region 14 shown in FIG. 2 is in contact with the end of the trench 41 in the Y-axis direction. Let the length of the trench 41 in the depth direction from the upper surface 21 be t2. In other words, the length of the MOS gate 40 in the depth direction in FIG. 2 is t2.

[0054] The gate insulating film 42 is provided to cover the inner wall of the trench 41. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench 41, or may be formed by a deposition method. The gate electrode 45 is provided inside the trench 41, inside the gate insulating film 42. That is, the gate insulating film 42 insulates the gate electrode 45 and the semiconductor substrate 10.

[0055] The gate electrode 45 in this example has a polysilicon 44 and a metal part 48. Impurities for enhancing conductivity may be implanted in the polysilicon 44. The metal part 48 is made of a metal material. As an example, the metal part 48 contains tungsten. The specific resistance of the metal part 48 is smaller than the specific resistance of the polysilicon 44. By having the metal part 48 with a small specific resistance in the gate electrode 45, the above-described gate delay can be reduced.

[0056] Inside the trench 41, a barrier metal 46 may be provided between the metal part 48 and the polysilicon 44. In that case, the barrier metal 46 may also be included in the gate electrode 45. The barrier metal 46 may be made of a metal different from the metal part 48. As an example, the barrier metal 46 may contain titanium. The barrier metal 46 may have a laminated structure of a titanium nitride layer and a titanium layer from the metal part 48 toward the polysilicon 44. By providing the barrier metal 46, it is possible to prevent the metal element of the emitter electrode 52 from diffusing into the semiconductor substrate 10.

[0057] The metal portion 48 may be provided inside the trench 41. In other words, the metal portion 48 may be provided inside the semiconductor substrate 10 below the upper surface 21 of the semiconductor substrate 10. In this specification, the direction from the upper surface 21 of the semiconductor substrate 10 toward the lower surface may be referred to as downward, and the opposite direction may be referred to as upward. Let the length of the metal portion 48 in the depth direction from the upper surface 21 be t1. The metal portion 48 in this example is provided deeper than the channel region 14. That is, the length t1 is greater than the length t3 in the depth direction of the channel region 14. By the length t1 being greater than the length t3, at least the gate delay in the channel region 14 can be reduced. The length t1 may be 1.1 times or more, 1.2 times or more, 1.5 times or more, or 2 times or more of the length t3.

[0058] The MOS gate 40 is not limited to the trench gate structure. The gate electrode 45 of the transistor 70 may have the metal portion 48. As an example, the gate electrode 45 of the MOS gate 40 having a planar structure may have the metal portion 48. Also in this case, the gate delay can be reduced.

[0059] As an example of the manufacturing method of the MOS gate 40 in this example, first, the trench 41 is filled with polysilicon 44 by the CVD method. Then, the polysilicon 44 in the trench 41 is etched to form a trench contact, and the trench contact is filled with tungsten and a barrier metal by sputtering. Since the tip (-Z-axis direction) of the trench 41 may be thin, the metal portion 48 is difficult to enter up to the tip of the trench 41. By disposing the polysilicon 44 at the tip portion of the trench 41, void formation at the tip portion of the trench 41 can be suppressed.

[0060] In the MOS gate 40 of this example, inside the trench 41, the metal portion 48 and the polysilicon 44 are laminated. The metal portion 48 and the polysilicon 44 may be laminated via the barrier metal 46. Inside the trench 41, the metal portion 48 and the polysilicon 44 may be laminated in the depth direction. In this example, the metal portion 48 is exposed on the upper surface 21 of the semiconductor substrate 10. In the Z-axis direction, the polysilicon 44 is disposed below the metal portion 48. Inside the trench 41, the metal portion 48 and the polysilicon 44 may be laminated in the horizontal direction (particularly in the arrangement direction of the MOS gate 40) as described later.

[0061] The first well region 11 may cover the end of the trench 41 in the extending direction (Y-axis direction) of the trench 41. The first well region 11 of this example covers the entire side wall of the end of the trench 41 in the Y-axis direction and a part of the lower surface of the trench 41 extending from the side wall. A channel region 14 may be in contact with the side wall of the trench 41. The first well region 11 may also cover the channel region 14 in contact with the side wall of the trench 41. Let the length of the overlap between the first well region 11 and the trench 41 be t8. By covering the end of the trench 41 with the first well region 11, the electric field concentration at the end of the trench 41 can be alleviated.

[0062] Let the width of the first well region 11 in the extending direction (Y-axis direction) of the trench 41 be t9. The width t9 is the width of the first well region 11 in the YZ cross-section where the gate pad 112 is not provided. Let the width of the gate runner 130 in the extending direction (Y-axis direction) of the trench 41 be tg. The width t9 may be larger than the width tg. In a top view, at least a part of the gate runner 130 may overlap with the first well region 11, and the whole may overlap with the first well region 11. By overlapping the gate runner 130 and the first well region 11, in a top view, the electric field distribution can be smoothed from the end of the trench 41 to the outer edge termination structure portion 90 of the gate runner 130. Thereby, local electric field concentration can be prevented.

[0063] In the transistor 70, an emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is provided in contact with the upper surface 21 of the semiconductor substrate 10, and insulates the gate electrode 45 and the emitter electrode 52. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. Above the interlayer insulating film 38, a gate runner 130 is provided.

[0064] The interlayer insulating film 38 is provided with a contact hole 54 that connects the gate runner 130 and the gate electrode 45. The contact hole 54 is filled with tungsten 56. Therefore, in the semiconductor device 100 of this example, the metal of the gate runner 130 and the metal of the gate electrode 45 are in direct contact. Note that the tungsten 56 and the barrier metal 58 described later may also be included in the gate runner 130.

[0065] The contact hole 54 is provided with a barrier metal 58. The barrier metal 58 of this example is provided between the tungsten 56 filled in the contact hole 54 and the tungsten of the metal portion 48. By providing the barrier metal 58, it is possible to prevent the metal element of the emitter electrode 52 from diffusing into the semiconductor substrate 10. The barrier metal 58 may also be provided on the sidewall of the contact hole 54.

[0066] In the edge termination structure portion 90, a guard ring 92 is provided in the semiconductor substrate 10. The guard ring 92 is a region of the second conductivity type formed by ion implantation from the upper surface 21 of the semiconductor substrate 10 inward. The doping concentration of the guard ring 92 may be equal to the doping concentration of the first well region 11. The depth of the guard ring 92 may be equal to the depth of the first well region 11.

[0067] Also in the edge termination structure portion 90, an interlayer insulating film 38 is provided in contact with the upper surface 21 of the semiconductor substrate 10. Above the interlayer insulating film 38, a field plate 93 is provided. The field plate 93 is formed of a metal such as aluminum or a conductive material such as polysilicon.

[0068] The interlayer insulating film 38 is provided with a contact hole 55 that connects the field plate 93 and the guard ring 92. Similar to the transistor 70, a barrier metal 58 is provided in the contact hole 55 and tungsten 56 is filled therein.

[0069] Above the interlayer insulating film 38, the emitter electrode 52, the gate runner 130, and the field plate 93, a protective film 60 is provided. The protective film 60 is formed of polyimide as an example.

[0070] FIG. 3 is a view showing the B-B' cross section in FIG. 1. The B-B' cross section is a YZ cross section passing through the MOS gate 40 of the edge termination structure portion 90, the gate runner 130, the gate pad 112, and the transistor 70. The B-B' cross section is different from the A-A' cross section at the point where it crosses the gate pad 112. Since other points are the same as the A-A' cross section, the description is omitted.

[0071] The gate pad 112 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with a contact hole 54 that connects the gate pad 112 and the gate electrode 45 below the gate pad 112. Similar to FIG. 2, a barrier metal 58 is also provided in the contact hole 54 of this example and tungsten 56 is filled therein. However, in FIG. 3, a part of the region including the gate pad 112 is omitted from the illustration. Also, the protective film 60 of this example is separated above the gate pad 112 in the Y-axis direction.

[0072] The first well region 11 is formed up to the active portion 120 side from the gate pad 112. In a top view, the entire gate pad 112 may overlap with the first well region 11. Also in the B-B' cross section, the first well region 11 covers the end portion in the extending direction of the trench 41.

[0073] FIG. 4 is a diagram showing the C-C' cross section in FIG. 1. The C-C' cross section is a YZ cross section passing through the mesa portion of the edge termination structure portion 90, the gate runner 130, the gate pad 112, and the transistor 70. The mesa portion refers to the region sandwiched by the MOS gate 40 in the transistor 70. The C-C' cross section is different from the B-B' cross section at the point of crossing the mesa portion. Since other points are the same as the B-B' cross section, the description is omitted.

[0074] The semiconductor substrate 10 has a channel region 14, an emitter region 12, a contact region 15, and an accumulation region 16 in the mesa portion. The first well region 11 may be included in the mesa portion at the end portion in the extending direction (Y-axis direction) of the trench 41. The first well region 11 and the channel region 14 may be the same as the first well region 11 and the channel region 14 described in FIG. 2. The accumulation region 16 will be described later.

[0075] The emitter region 12 is provided between the upper surface 21 of the semiconductor substrate 10 and the channel region 14, and is a region of the first conductivity type having a higher doping concentration than the drift region 18. The emitter region 12 in this example is N+. The contact region 15 is provided between the upper surface 21 of the semiconductor substrate 10 and the channel region 14, and is a region of the second conductivity type having a higher concentration than the channel region 14. The contact region 15 in this example is P+. The emitter region 12 and the contact region 15 are exposed on the upper surface 21. The emitter region 12 and the contact region 15 in this example are provided alternately in the extending direction (Y-axis direction) of the trench 41.

[0076] On the mesa portion, an interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. In the interlayer insulating film 38, a contact hole 54 that connects the emitter electrode 52, the emitter region 12, and the contact region 15 is provided. Similar to FIG. 2, a barrier metal 58 is also provided in the contact hole 54 of this example, and tungsten 56 is filled therein. The contact hole 54 of the active portion 120 extends in the extending direction (Y-axis direction) of the trench 41.

[0077] FIG. 5 is a view showing the D-D' cross section in FIG. 1. The D-D' cross section is an XZ cross section passing through the emitter region 12 of the edge termination structure portion 90 and the transistor 70. Since the D-D' cross section crosses the other side 143-3 of the semiconductor substrate 10 in FIG. 1, the gate runner 130 is not provided. There is another side 143-3 on the negative X-axis side of the D-D' cross section. Since the edge termination structure portion 90 of the D-D' cross section is the same as the edge termination structure portion 90 shown in FIGS. 2 to 4, the description thereof is omitted.

[0078] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. A contact hole 54 is also provided in the interlayer insulating film 38 of this example. A barrier metal 58 is provided inside the contact hole 54, and tungsten 56 is filled therein.

[0079] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. A protective film 60 is provided above the emitter electrode 52 so as to partially overlap the emitter electrode 52.

[0080] The transistor 70 has a plurality of MOS gates 40 provided inward from the upper surface 21 of the semiconductor substrate 10. The MOS gates 40 in this example are arranged along the X-axis direction and have a longitudinal direction along the Y-axis direction. As described above, the MOS gate 40 has a trench 41, a gate insulating film 42, and a gate electrode 45, and the gate electrode 45 has a polysilicon 44, a barrier metal 46, and a metal portion 48. The MOS gate 40 may function as a gate trench or may function as a dummy trench. Both functions may coexist in the plurality of MOS gates 40. A metal portion may be provided on the gate electrode 45 of the MOS gate 40 that functions as a dummy trench. By providing the metal portion, when the potential of the emitter electrode 52 fluctuates, the potential distribution between the MOS gates 40 is less likely to occur. However, in the MOS gate 40 that functions as a dummy trench, polysilicon 44 may be provided instead of the metal portion 48.

[0081] A mesa portion 62 is provided between the MOS gates 40 of the transistor 70 in the arrangement direction. The mesa portion 62 refers to the region between the MOS gates 40 inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 62 is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 62 is the same as the depth position Zt of the lower end of the trench 41. The mesa portion 62 in this example is provided to extend in the Y-axis direction along the MOS gate 40 on the upper surface 21 of the semiconductor substrate 10. A channel region 14 is provided in the mesa portion 62.

[0082] The transistor 70 has an emitter region 12 provided on the upper surface 21. The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the MOS gate 40. The emitter region 12 may be in contact with the MOS gates 40 on both sides of the mesa portion 62. When the D-D' cross section crosses the contact region 15, the emitter region 12 in FIG. 5 becomes the contact region 15.

[0083] The channel region 14 is provided below the emitter region 12. The channel region 14 in this example is provided in contact with the emitter region 12. The channel region 14 may be in contact with the MOS gates 40 on both sides of the mesa portion 62.

[0084] The accumulation region 16 is provided below the channel region 14. The accumulation region 16 is a region of a first conductivity type having a higher doping concentration than the drift region 18. The accumulation region 16 in this example is of N+ type. By providing the high-concentration accumulation region 16 between the drift region 18 and the channel region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the channel region 14 in each mesa portion 62.

[0085] As described above, the metal portion 48 is provided deeper in the depth direction than the channel region 14. The metal portion 48 in this example is provided to a position overlapping the accumulation region 16 in the depth direction. The metal portion 48 may be provided deeper than the accumulation region 16.

[0086] A second well region 22-1 is provided on the outer periphery of the active portion 120. The second well region 22-1 is a region of a second conductivity type provided from the upper surface 21 of the semiconductor substrate 10 inward. The doping concentration of the second well region 22-1 may be equal to that of the first well region (see FIGS. 2 to 4). The depth at which the second well region 22-1 is provided may be equal to the depth at which the first well region is provided. The first well region 11 and the second well region 22 provided on each side may be connected at the corners of the semiconductor device 100.

[0087] Let the width of the second well region 22-1 in the direction (X-axis direction) perpendicular to the other side 143-3 be t10. The width t10 may be smaller than the width t9 of the first well region 11. As described above, no gate runner 130 is provided between the active portion 120 and the other side 143-3. Therefore, the width t10 can be made smaller than the width t9. Thereby, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased. Or, the area of the semiconductor substrate 10 having the active portion 120 of the same area can be reduced.

[0088] The difference between the width t10 and the width t9 may be at least half of the width tg (see FIG. 2) of the gate runner 130. When the entire gate runner 130 overlaps with the first well region 11, the difference between the width t10 and the width t9 may be at least the width tg of the gate runner 130.

[0089] The second well region 22 may also be provided in the cross section from the edge termination structure portion 90 to the active portion 120 on the other side 143-1. The relationship between the width of the second well region 22 and the width t9 of the first well region 11 may be the same as the relationship between the width t10 and the width t9.

[0090] The second well region 22-1 may be in contact with the MOS gate 40 provided on the outermost side of the active portion 120 and may cover the MOS gate 40. The second well region 22-1 of this example is in contact with approximately half of the MOS gate 40.

[0091] The interlayer insulating film 38 may have a contact hole 54 between the MOS gate 40 provided on the outermost side in the active portion 120 and the edge termination structure portion 90. In this example, the emitter electrode 52 and the second well region 22-1 are electrically connected through the contact hole 54.

[0092] FIG. 6 is an enlarged view of region A in FIG. 5. Region A is a region including the MOS gate 40, the emitter region 12, the channel region 14, and the accumulation region 16.

[0093] The trench 41 may have a sidewall 66 and a bottom 68. The sidewall 66 may be the wall of the trench 41 from the upper surface 21 to the depth of the channel region 14, and may be the wall of the trench 41 perpendicular to the upper surface 21. However, since the wall of the trench 41 usually may not be exactly perpendicular to the upper surface 21, the perpendicularity may have a width of about ±10°. The bottom 68 may be the portion inside the trench 41 other than the sidewall 66. The bottom 68 of this example is the curved surface portion at the tip of the trench 41. The bottom 68 may be the portion where the tangent in the XZ cross-section has an inclination greater than 10° with respect to the normal of the upper surface 21. In FIG. 6, the sidewall 66 is shown by a thick line.

[0094] The polysilicon 44 of this example is provided between the sidewall 66 of the trench 41 and the metal portion 48. Generally, when the material of the gate electrode 45 changes, the threshold voltage changes. Therefore, by providing the polysilicon 44 between the sidewall 66 and the metal portion 48, the variation of the threshold voltage due to the provision of the metal portion 48 can be suppressed. In addition, since voids are likely to be formed in the tungsten of the metal portion 48, if the metal portion 48 is in contact with the sidewall 66, there may be a portion where a channel is not formed due to the voids. On the other hand, voids are not formed in the polysilicon 44. Therefore, a channel can be formed over the entire surface of the channel region 14. The polysilicon 44 may be provided over the entire area between the sidewall 66 of the trench 41 and the metal portion 48. In other words, the metal portion 48 does not have to be in contact with the sidewall 66. In the direction (X-axis direction) perpendicular to the sidewall 66 of the trench 41 passing through the emitter region 12, the polysilicon 44 and the metal portion 48 may be laminated.

[0095] Let the thickness of the polysilicon 44 laminated with the metal portion 48 in the direction (X-axis direction) perpendicular to the sidewall 66 be t4. In other words, the thickness t4 is the thickness of the polysilicon 44 provided between the sidewall 66 and the metal portion 48. The thickness t4 may be 0.2 μm or less. Even if the thickness t4 is small, the effect of suppressing the variation of the threshold voltage described above occurs. The thickness t4 may be 0.1 μm or less. The thickness t4 may be 0.05 μm or more.

[0096] Let the thickness in the depth direction of the trench 41 of the polysilicon 44 formed at the bottom 68 be t5. The thickness t5 may be greater than the thickness t4. As described above, the polysilicon easily enters up to the tip of the trench 41. Also, the deeper the trench 41, the higher the IE effect, and the on-voltage can be lowered, so the trench 41 is formed deeper than the channel region 14. On the other hand, the metal portion 48 does not have to be provided up to the bottom 68. As a result, the polysilicon 44 at the bottom 68 becomes thick.

[0097] Let the width of the metal portion 48 and the barrier metal 46 in the direction perpendicular to the side wall 66 (X-axis direction) be t6. Let the width of the trench 41 in the direction perpendicular to the side wall 66 (X-axis direction) be t7. The width t7 is larger than the width t6. Thereby, the polysilicon 44 can be provided between the side wall 66 and the metal portion 48. The width t6 is, for example, 0.5 μm or more and 1 μm or less.

[0098] FIG. 7 is a view showing the E-E' cross section in FIG. 1. The E-E' cross section is a YZ cross section passing through the edge termination structure portion 90 and the MOS gate 40 of the transistor 70. Hereinafter, the differences from the A-A' cross section (FIG. 2) will be described.

[0099] Since the E-E' cross section crosses the other side 143-2 of the semiconductor substrate 10 in FIG. 1, the gate runner 130 is not provided. There is the other side 143-2 on the negative Y-axis direction side of the E-E' cross section. Also, the second well region 22-2 is provided along the other side 143-2. The doping concentration and depth of the second well region 22-2 may be the same as those of the second well region 22-1 (see FIG. 5).

[0100] Let the width of the second well region 22-2 be t12. The width t12 may be smaller than the width t9 of the first well region 11. As described above, no gate runner 130 is provided between the active portion 120 and the other side 143-2. Therefore, the width t12 can be made smaller than the width t9. As a result, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased. Or, the area of the semiconductor substrate 10 having the active portion 120 of the same area can be decreased.

[0101] The difference between the width t12 and the width t9 may be equal to or greater than half of the width tg (see FIG. 2) of the gate runner 130. When the entire gate runner 130 overlaps with the first well region 11, the difference between the width t12 and the width t9 may be equal to or greater than the width tg of the gate runner 130.

[0102] The second well region 22-2 overlaps with the end of the trench 41 in the extending direction of the trench 41. Let the length of the overlap between the second well region 22-2 and the trench 41 be t11. The length t8 (see FIG. 2) of the overlap between the first well region and the trench 41 may be greater than the length t11. Since no gate runner 130 is provided in the E-E' cross section, the gate electrode 45 of the MOS gate 40 is not electrically connected to other electrodes or the like in this cross section. On the other hand, the gate runner 130 and the gate electrode 45 are connected at the portion where the first well region 11 and the trench 41 overlap (see FIG. 2). Therefore, an electric field is likely to concentrate at the portion where the first well region 11 and the trench 41 overlap.

[0103] However, a gate runner may also be provided in the E-E' cross section. That is, a gate runner may be provided between the active portion 120 and the other side 143-2 along the other side 143-2 of the semiconductor substrate 10. The gate runner may be connected to the gate electrode 45 of each MOS gate 40. The gate runner is not connected to the gate runner 130 provided along the first end side 142 shown in FIG. 1 or the like.

[0104] FIG. 8 is a diagram showing another example of the D-D' cross section in FIG. 1. The D-D' cross section in this example is different from the D-D' cross section shown in FIG. 5 in the arrangement of the interlayer insulating film 38. Since other parts are the same as those in FIG. 5, the description thereof is omitted.

[0105] In the semiconductor device 100 of this example, an interlayer insulating film 38-1 and an interlayer insulating film 38-2 are provided. The interlayer insulating film 38-1 is provided above the upper surface 21 of the semiconductor substrate 10 from the edge termination structure portion 90 to the active portion 120. The interlayer insulating film 38-2 is provided in the active portion 120. The interlayer insulating film 38-2 insulates the gate electrode 45 of the MOS gate 40 and the emitter electrode. The interlayer insulating film 38-2 in this example is provided inside the trench 41. At least a part of the interlayer insulating film 38-2 may be provided inside the trench 41, or the entire interlayer insulating film 38-2 may be provided inside the trench 41. Accordingly, the contact hole 54 in this example is provided across a plurality of mesa portions 62. By providing the interlayer insulating film 38-2 inside the trench 41, the positioning accuracy when forming the contact hole 54 can be reduced, and the miniaturization of the mesa portion 62 becomes easy.

[0106] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the forms with such changes or improvements can also be included in the technical scope of the present invention.

Description of Reference Numerals

[0107] 10 ··· Semiconductor substrate, 11 ··· First well region, 12 ··· Emitter region, 14 ··· Channel region, 15 ··· Contact region, 16 ··· Accumulation region, 18 ··· Drift region, 21 ··· Upper surface, 22 ··· Second well region, 38 ··· Interlayer insulating film, 40 ··· MOS gate, 41 ··· Trench, 42 ··· Gate insulating film, 44 ··· Polysilicon, 45 ··· Gate electrode, 46 ··· Barrier metal, 48 ··· Metal portion, 52 ··· Emitter electrode, 54 ··· Contact hole, 55 ··· Contact hole, 56 ··· Tungsten, 58 ··· Barrier metal, 60 ··· Protective film, 62 ··· Mesa portion, 66 ··· Side wall, 68 ··· Bottom, 70 ··· Transistor, 90 ··· Edge termination structure portion, 92 ··· Guard ring, 93 ··· Field plate, 100 ··· Semiconductor device, 112 ··· Gate pad, 120 ··· Active portion, 130 ··· Gate runner, 140 ··· Outer peripheral end, 142 ··· First side edge, 143 ··· Other side

Claims

1. A semiconductor substrate having a top surface, an active portion provided on the semiconductor substrate and having transistors, and a gate runner provided above the top surface of the semiconductor substrate are provided, the transistor includes a MOS gate having a gate electrode, the gate runner is electrically connected to the gate electrode, the gate runner is provided between the active portion and one side of the semiconductor substrate above the top surface of the semiconductor substrate, and is not provided between the active portion and any other side of the semiconductor substrate semiconductor device.

2. The gate electrode of the transistor has a metal portion The semiconductor device according to claim 1.

3. The MOS gate has a trench provided on the top surface of the semiconductor substrate, the metal portion is provided inside the trench The semiconductor device according to claim 2.

4. The semiconductor substrate, a drift region of a first conductivity type, a channel region of a second conductivity type provided between the top surface of the semiconductor substrate and the drift region and in contact with the trench has, the metal portion is provided deeper than the channel region The semiconductor device according to claim 3.

5. Inside the trench, the metal portion and polysilicon are laminated The semiconductor device according to claim 4.

6. The trench has sidewalls and a bottom, the polysilicon is provided between the sidewalls of the trench and the metal portion The semiconductor device according to claim 5.

7. The thickness of the polysilicon laminated with the metal portion in a direction perpendicular to the sidewalls is 0.2 μm or less The semiconductor device according to claim 6.

8. The thickness of the polysilicon formed on the bottom in the depth direction of the trench is greater than the thickness of the polysilicon provided between the sidewalls and the metal portion The semiconductor device according to claim 6.

9. An emitter electrode provided above the top surface of the semiconductor substrate, the gate electrode, and an interlayer insulating film insulating the emitter electrode are further provided, the interlayer insulating film is provided inside the trench The semiconductor device according to claim 3.

10. The metal portion contains tungsten The semiconductor device according to claim 3.

11. Inside the trench, a barrier metal of a metal different from the metal portion is provided between the metal portion and the polysilicon. The semiconductor device according to claim 5.

12. The barrier metal contains titanium. The semiconductor device according to claim 11.

13. An emitter electrode provided above the upper surface of the semiconductor substrate, The gate electrode, an interlayer insulating film insulating the emitter electrode, Further comprising, In the interlayer insulating film, a contact hole connecting the gate runner and the gate electrode is provided, The contact hole is filled with tungsten, A barrier metal is provided between the tungsten filled in the contact hole and the tungsten of the metal portion. The semiconductor device according to claim 10.

14. In a top view, further comprising a well region that surrounds the active portion and is formed deeper than the trench from the upper surface of the semiconductor substrate toward the inside, The well region is, A first well region formed on one side of the semiconductor substrate where the gate runner is provided, A second well region formed on at least one other side where the gate runner is not provided And has, The width of the second well region is smaller than the width of the first well region. The semiconductor device according to any one of claims 3 to 13.

15. The difference between the width of the second well region and the width of the first well region is at least half of the width of the gate runner. The semiconductor device according to claim 14.

16. The trench extends in a stretching direction perpendicular to one side of the semiconductor substrate where the gate runner is provided in a top view, The first well region and the second well region overlap with the end portion of the trench in the stretching direction, The length of the overlap between the first well region and the trench is larger than the length of the overlap between the second well region and the trench. The semiconductor device according to claim 14.

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