System and method for shaping gate current of gate driver
By employing a driver circuit and current shaping circuit to control the waveform of the gate current, the solution addresses the issues of switching losses and ringing in gate drivers, enhancing the efficiency and reliability of switching converters.
Patent Information
- Application Number
- JP2024204836
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-11-25
- Publication Date
- 2025-06-24
Smart Images
Figure 2025093876000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure generally relates to semiconductor devices. More particularly, the present disclosure relates to gate current shaping of a gate driver to reduce switching losses and ringing.
Background Art
[0002] Gate drivers are used in applications of switching converters such as DC / DC converters, inverters, motor drivers, etc. These systems can include a controller, one or more power switches, and a gate driver for each switch. The gate driver can turn on and off the power switch according to the signal of the controller, and the system provides the required output voltage or power to the load.
Summary of the Invention
[0003] In one embodiment, generally, a semiconductor device is provided. The semiconductor device can include a driver circuit configured to drive a switch. Further, the semiconductor device can include a circuit configured to generate a gate current having a defined waveform shape when the switch transitions. Due to the defined waveform shape of the gate current, the current of the switch can have a constant slew rate during the transition of the switch.
[0004] In one embodiment, generally, a system within a switching converter is provided. The system can include at least one power switch and a gate driver. The gate driver can be configured to drive at least one power switch. Further, the gate driver can be configured to generate a gate current having a defined waveform shape when at least one power switch transitions. Due to the defined waveform shape of the gate current, the current of at least one power switch can have a constant slew rate during the transition of the switch.
[0005] In one embodiment, generally, a method for operating a switching converter is provided. The method can include generating a gate current for driving a switch in the switching converter. Further, the method can include defining a waveform shape of the gate current. With the defined waveform shape of the gate current, the current of the power switch can have a constant slew rate during the transition of the power switch.
[0006] The above summary is illustrative and is not intended to limit in any way. In addition to the aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent from reference to the accompanying drawings and from the following detailed description. In the figures, like reference numerals indicate identical or functionally similar elements.
Brief Description of the Drawings
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Embodiments for Carrying Out the Invention
[0008] In the following description, for the purpose of facilitating the understanding of various embodiments of the present application, a number of specific details including specific structures, components, materials, dimensions, processing steps, and technologies are described. However, those skilled in the art will understand that various embodiments of the present application can be realized without these specific details. In some cases, the description of details of known structures or processing steps is omitted to avoid obscuring the present application.
[0009] FIG. 1A is a diagram showing a system 100 that can implement gate current shaping of a gate driver in one embodiment. The applications of the system 100 can include, but are not limited to, solenoid drivers, buck converters, or boost converters. The system 100 can include at least a controller 102, one or more power switches 108, and a gate driver 104 (e.g., a gate driver circuit) corresponding to each of the one or more power switches 108. Each of the gate drivers 104 can be configured to turn on or off the corresponding power switch among the power switches 108 using a gate current Igate. The gate driver 104 can generate the gate current Igate in response to a signal 101 (e.g., a PWM (pulse width modulation) signal or a PFM (pulse frequency modulation) signal) provided by the controller 102. The system 100 can convert an input voltage Vin into an output voltage Vout or power to a load 107. Here, the output voltage Vout can provide the amount of power required or demanded by the load 107. The system 100 shown in FIG. 1A can be a buck converter where the output voltage Vout is lower than the input voltage Vin. In one embodiment, the power switch 108 can be a FET (field effect transistor) such as a MOSFET (metal oxide semiconductor field effect transistor). In other embodiments, the power switch 108 can be an IGBT (insulated gate bipolar transistor). As will be described in more detail below, the gate driver 104 can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108. By controlling the shape of the gate current Igate, ringing generated by the power switch 108 can be addressed.
[0010] Figure 1B is a diagram showing another system 110 capable of realizing gate current shaping of a gate driver in one embodiment. In system 110, the gate driver 104 can include one gate driver for driving one power switch 108, and system 110 can include a diode 109. The gate driver 104 shown in Figure 1B can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108 in Figure 1B. By controlling the shape of the gate current Igate, it is possible to cope with the ringing generated by the power switch 108.
[0011] Figure 1C is a diagram showing another system 120 capable of realizing gate current shaping of a gate driver in one embodiment. System 120 can be a boost converter in which the output voltage Vout exceeds the input voltage Vin. The gate driver 104 shown in Figure 1C can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108 in Figure 1C. By controlling the shape of the gate current Igate, it is possible to cope with the ringing generated by the power switch 108.
[0012] Figure 1D is a diagram showing another system 130 capable of realizing gate current shaping of a gate driver in one embodiment. System 130 can be a converter for PFC (power factor correction circuit). The gate driver 104 shown in Figure 1D can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108 in Figure 1D. By controlling the shape of the gate current Igate, it is possible to cope with the ringing generated by the power switch 108.
[0013] Figure 1E is a diagram showing another system 140 that can implement gate current shaping of a gate driver in one embodiment. System 140 can be part of, for example, an inverter, a motor driver, or a multi-layer DC / DC converter. The gate driver 104 shown in Figure 1E can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108 in Figure 1E. By controlling the shape of the gate current Igate, it is possible to address the ringing caused by the power switch 108.
[0014] Figures 2A - 2C are diagrams showing the operation of a power switch that may cause ringing. In Figure 2A, the switching node SW between two power switches 108 (shown as HS and LS) can operate alternately in two states. Figure 2B shows the first state of SW where HS is turned on and LS is turned off. Figure 2C shows the second state of SW where HS is turned off and LS is turned on. In embodiments where one power switch 108 is implemented to have a diode 109 (see Figures 1B and 1D), the on state of the diode 109 means that the diode 109 conducts in the forward direction. As shown in Figures 2B and 2C, LC resonance may occur due to parasitic inductance and capacitance. LC resonance is observed as ringing in the current or voltage, as shown in Figure 2D. The amplitude of the ringing depends on multiple factors, such as the transition time shown in Figure 2D.
[0015] FIG. 2D is a diagram showing ringing that may occur in the operation of the power switch. In one aspect, large ringing may damage the power switch 108 due to overvoltage. Also, the ringing may cause the system including the power switch 108 (see, e.g., FIGS. 1A - 1E) to emit unwanted radio frequency noise such as EMI (electromagnetic interference). Therefore, it is desirable to reduce the ringing. However, there is a trade - off relationship between ringing and energy loss. When the driver 104 drives HS and LS at a relatively high speed, the efficiency of the system 100 improves and the loss decreases, but the ringing may increase. When the gate driver 104 drives HS and LS at a relatively low speed, the efficiency of the system decreases and the loss increases, but the ringing may decrease. As will be described in more detail below, the gate driver 104 can include components and circuit configurations configured to control the shape of the gate current Igate used to drive the power switch 108 such as HS or LS in order to reduce the ringing generated by the operation of the power switch 108.
[0016] FIGS. 3A and 3B are diagrams showing the operation of the power switch during transition between the on - state and the off - state. The gate driver 104 can provide a pull - up (FIG. 3A) or pull - down (FIG. 3B) gate current (Igate) 103. Igate 103 can drive the power device 108, and its state changes between on and off during the transition. The current Ids in FIGS. 3A and 3B can be the current flowing through the power switch 108. The transition time depends on the gate current 103 provided by the gate driver 104. Igate 103 can be controlled, for example, by placing a current - limiting resistor between the gate driver 104 and the power switch 108 to maintain a good balance of the above - mentioned trade - off.
[0017] Figure 4A is a diagram showing different scenarios when gate current shaping is ineffective and effective in one embodiment. As described above, the amplitude of ringing depends on the transition time. In other words, it depends on the slew rate of the power switch current such as Igate. Making the slew rate of the switch current during the transition constant is one of the objectives of the present disclosure. A constant slew rate can achieve a fast transition without an increase in ringing. That is, it is possible to achieve power loss reduction and ringing reduction beyond the trade-off relationship in the prior art. The gate current shaping described herein can be applied from a small load current to a large load current. Also, the system does not need to adjust the gate current according to the load current level.
[0018] For example, in an embodiment where a MOSFET is used as the power switch 108, the gate current is
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[0023] FIG. 4B, FIG. 4C, and FIG. 4D are diagrams showing implementation examples of gate current shaping of the gate driver in various embodiments. In one or more embodiments, the gate driver 104 described herein can include a current shaping circuit 106. The current shaping circuit 106 can provide a curvilinear current. In one embodiment, the controller 102 can communicate with the gate driver 104 to configure the waveform of the signal generated by the current shaping circuit 106. In one embodiment, the gate driver 104 can be configured to control the waveform of the signal output by the current shaping circuit 106. The current shaping circuit 106 can be used for pull-up and pull-down as shown in FIG. 4B, or only one side can be combined with a pull-up / pull-down circuit as shown in FIGS. 4C and 4D. In some embodiments, the system can include a plurality of gate drivers 104, and each of the plurality of gate drivers 104 can include a different configuration of the current shaping circuit 106 or an implementation example of the current shaping circuit 106.
[0024] FIG. 5A is a diagram showing an implementation example of a current shaping circuit in one embodiment. In one embodiment, the current shaping circuit 106 can generate the curve shape of Igate by performing interpolation of two signal levels using the setting of an operational amplifier. In the exemplary embodiment of FIG. 5A, the current shaping circuit 106 can include a voltage reference V1 and V2, an operational amplifier 502, at least a resistor R, and a driver transistor M1. The driver transistor M1 can be turned off (e.g., can transition from on to off) while DIN (data-in signal) is low. When DIN first goes high (e.g., transitions from off to on), the current shaping circuit 106 can
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[0028] FIG. 5B is a diagram showing another implementation example of the current shaping circuit in one embodiment. In one embodiment, the current shaping circuit 106 can generate the curve shape of Igate by performing interpolation of two signal levels using the setting of the RC circuit. As shown in the figure, the current shaping circuit 106 can include a voltage reference V1 and V2, a voltage-current converter 215, a switch circuit for changing the input voltage Vs of the voltage-current converter 215, and an RC element. Its operation can be the same as that of the embodiment shown in FIG. 5A. At t = 0, Vs starts to change from V1 to V2, and C and R arranged between V2 and C define the settling time. This is
[0029] [Number] used to produce the curve shape as. Here,
[0030] [Number] is. In one embodiment, the output current Igate can be proportional to Vs. In other embodiments, Igate can be further modulated according to the transfer function of the voltage-current converter 215.
[0031] FIG. 5C is a diagram showing another implementation example of the current shaping circuit in one embodiment. In one embodiment, the current shaping circuit 106 can generate the curve shape of Igate by performing interpolation of multiple signal levels using the setting of the RC circuit. As shown in the figure, the current shaping circuit 106 can include voltage references V1, V2, etc., a voltage-current converter 215, a switch circuit for changing the input voltage Vs of the voltage-current converter 215, and an RC element. Its operation can be the same as that of the embodiment shown in FIG. 5B. By connecting multiple curves, a relatively complex curve shape as shown in the figure can be generated.
[0032] FIG. 5D is a diagram showing another implementation example of the current shaping circuit in one embodiment. The embodiment of FIG. 5D can provide a relatively complex and precise shape for the curve shape by combining a plurality of current shaping circuits. A plurality of segments 302 and 304 of the current shaping circuit, such as any of the embodiments in FIGS. 5A to 5C, can be implemented in the embodiment shown in FIG. 5D.
[0033] FIG. 5E is a diagram showing another implementation example of the current shaping circuit in one embodiment. The current shaping circuit 106 can include a digital pattern generator 402 and a current digital-to-analog converter 404. The output current Igate can be configured in any curve shape.
[0034] FIG. 5F is a diagram showing another implementation example of the current shaping circuit in one embodiment. The current shaping circuit 106 can include a digital pattern generator 402, a voltage-current converter 215, and a voltage digital-to-analog converter 404. The output current Igate can be configured in any curve shape.
[0035] FIG. 6A is a diagram showing an implementation example of a voltage-current converter that can be used in the current shaping circuit of a gate driver in one embodiment. The current shaping circuit 106 can include various implementation examples of the voltage-current converter 215. In the example shown in FIG. 6A, the voltage-current converter 215 can include a high-speed operational amplifier 204, a MOSFET M1, and a resistor Rs (refer to M1 and R in FIG. 5A). Note that it should be noted that the operational amplifier 204 can be configured to operate faster than the operational amplifier 502. The output current is
[0036]
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[0037] FIG. 6B is a diagram showing another implementation example of a voltage-current converter that can be used in the current shaping circuit of a gate driver in one embodiment. In another example shown in FIG. 6B, the voltage-current converter 215 can include an MOSFET M1 and a resistor Rs. Further, the voltage-current converter 215 can further include a switch S1 for quickly turning off M1. The output current is
[0038]
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[0039] FIG. 6C is a diagram showing another implementation example of a voltage-current converter that can be used in the current shaping circuit of a gate driver in one embodiment. In another example shown in FIG. 6C, the voltage-current converter 215 can include an MOSFET M1. Further, the voltage-current converter 215 can further include a switch S1 for quickly turning off M1. The output current is
[0040]
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[0041] FIG. 7 is a diagram showing different waveforms having different shapes obtained as a result of implementing the current shaping circuit of a gate driver in one or more embodiments. In FIG. 7, the waveform Igate_simple is a waveform obtained from the result of implementing the embodiments in FIGS. 5A and 5B. The waveform Iout1 + Iout2 is a waveform obtained from the result of implementing the embodiment in FIG. 5C. This is closer to the ideal curve, and better results, that is, lower losses and lower ringing can be expected.
[0042] Figures 8A and 8B are diagrams showing a system including adaptive control of gate current shaping in one or more embodiments. The gate current shaped by the current shaping circuit 106 can be any implementation example of a current shaping circuit as described above, but is not limited thereto. Also, the system can have feedback control from the detection circuit 110. In Figure 8A, the system can include a current sensor 112 and perform feedback by observing the slew rate of the current in the power switch 108. The detection circuit 110 can configure the current shaping circuit 106 to make the slew rate of the switch current constant during the transition. The detection circuit 110 can know the slew rate of the current by a calculation of dI / dt. Also, the detection circuit 110 can optimize the gate current shaping to obtain better results. Also, the detection current 110 can detect that the switch current has started to flow for the timing generation of the current shaping circuit 106. In Figure 8B, the current sensor 112 can be implemented by an inductor 111. The inductor 111 is in series with the power switch 108. In one embodiment, the inductor 111 can have a parasitic inductance L of the current path from the power switch 108 to the detection circuit 110. In another embodiment, the power switch 108 can include the inductor 111. The voltage at SNS is
[0043]
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[0044] Figures 9A, 9B, and 9C are diagrams showing various implementation examples of feedback control in one or more embodiments. In Figure 9A, the waveform shape of the gate current Igate is ideal. In Figure 9B, the waveform shape of the gate current Igate has a relatively steep gradient. In Figure 9C, the waveform shape of the gate current Igate is relatively flat. SNS represents the voltage shown in Figure 8B. As indicated by the dotted circle, the time or amplitude within the dotted circle, or the subsequent ringing amplitude, can indicate whether the curve of the waveform shape of Igate has a steep gradient or is flat. Therefore, the system can optimize the curve by changing the parameters of the current shaping circuit 106 such as "tau" in Figures 5A and 5B.
[0045] Figure 10 is a diagram showing an implementation example in which temperature estimation is utilized in one embodiment. Generally, the characteristics of the power switch 108 change depending on its junction temperature TJ. That is, the shape of the optimal gate current varies slightly according to TJ. When the system optimizes the gate current shaping, the resulting shape of the gate current reflects TJ. Therefore, TJ can be estimated by the shape of the gate current, that is, by the parameters of the current shaping circuit 106. The estimation of TJ can be used for safety in the system.
[0046] Figure 11 is a flowchart showing a process for implementing gate current shaping of a gate driver in one embodiment. The process can include one or more operations, actions, or functions indicated by one or more blocks 1102 and / or 1104. Although shown as individual blocks in the figure, depending on the desired application, various blocks can be divided into additional blocks, combined into fewer blocks, omitted, executed in a different order, or executed in parallel.
[0047] Process 1100 can be executed, for example, by the driver (e.g., driver 104) and the waveform shaping circuit (e.g., circuit 106) described herein. Process 1100 can start from block 1102. In block 1102, the gate driver can generate a gate current for driving the power switch. Process 1100 can proceed from block 1102 to block 1104. In block 1104, the gate driver can define the waveform shape of the gate current. Here, due to the defined waveform shape of the gate current, the current of the power switch has a constant slew rate during the transition of the power switch.
[0048] In one embodiment, the gate driver can sense the current in the power switch and execute a feedback loop to optimize the waveform shape of the gate current based on the sensed current. In one embodiment, the gate driver can use the waveform shape of the gate current to estimate the junction temperature of the power switch.
[0049] In one embodiment, the gate driver can generate a digital signal including a digital pattern representing the waveform shape of the gate current and convert the digital signal into an analog signal that defines the waveform shape of the gate current.
[0050] In one embodiment, the gate driver can output a gate current at a first amplitude. The gate driver can further switch an operational amplifier to output a gate current at a second amplitude. The operational amplifier can define the waveform shape of the gate current. The waveform shape of the gate current depends on the setting speed of the operational amplifier.
[0051] In one embodiment, the gate driver can use at least one voltage source to generate a voltage and use an RC (resistor - capacitor) network to change the voltage generated by the voltage source. Here, the waveform shape of the gate current can be defined by the RC network.
[0052] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be implemented substantially simultaneously, or depending on the related functions, may sometimes be implemented in the reverse order. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of those blocks, can be implemented by a special-purpose hardware-based system that performs the specified functions or operations, or a combination of special-purpose hardware and computer instructions.
[0053] The terms used in this specification are used only for the purpose of describing particular embodiments and are not intended to limit the present invention. The singular terms used in this specification are also intended to include the plural, unless specifically stated otherwise. It should also be noted that the term "comprising" used in this specification defines the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0054] All means or steps and corresponding structures, materials, acts, and equivalents of the functional elements recited in the appended claims are intended to include any structure, material, or act for achieving a function in combination with other elements specifically recited. The description of the disclosed embodiments of the invention has been provided for purposes of illustration and description, but is not intended to be exhaustive or to be limited to the disclosed forms. It will be apparent to those skilled in the art that many modifications and variations can be made without departing from the scope and spirit of the invention. The above-described embodiments were chosen and described in order to best explain the principles of the invention and its practical application and to enable others skilled in the art to understand the invention in various embodiments with various modifications as are suited to the particular use being considered.
Claims
1. a driver circuit configured to drive the switch; a circuit configured to generate a gate current having a defined waveform shape upon a transition of the switch; Including, the defined waveform shape of the gate current causes the current in the switch to have a constant slew rate during a switch transition; Semiconductor device.
2. The circuit comprises: a pattern generator configured to generate a digital signal including a digital pattern representative of the waveform shape of the gate current; a digital-to-analog converter (DAC) configured to convert the digital signal into an analog signal defining the waveform shape of the gate current; The semiconductor device according to claim 1 ,
3. The circuit includes an operational amplifier configured to output the gate current at a first amplitude; the circuit is configured to switch the operational amplifier to output the gate current at a second amplitude; the operational amplifier defines the waveform shape of the gate current; The waveform shape of the gate current depends on the settling speed of the operational amplifier. The semiconductor device according to claim 1 .
4. The circuit comprises: at least one voltage source configured to generate a voltage; a resistor-capacitor (RC) network including at least one resistor and at least one capacitor configured to vary the voltage generated by the voltage source; Including, the waveform shape of the gate current is defined by the RC network; The semiconductor device according to claim 1 .
5. The semiconductor device according to claim 1 , wherein said circuit is included in a plurality of current waveform shaping circuits.
6. further comprising a detection circuit; The detection circuit includes: Sensing a current in the switch; and configuring said gate current waveform shape control circuit to control said gate current waveform shape based on said sensed current. The semiconductor device according to claim 1 .
7. The semiconductor device of claim 6 , further comprising a junction temperature circuit configured to estimate a junction temperature of the switch using the waveform shape of the gate current.
8. 1. A system including at least one power switch and a gate driver, The gate driver includes: Driving the at least one power switch; configured to generate a gate current having a defined waveform shape upon a transition of the at least one power switch; the defined waveform shape of the gate current causes the current in the at least one power switch to have a constant slew rate during a transition of the at least one power switch. system.
9. further comprising a detection circuit; The detection circuit includes: Sensing a current in the at least one power switch; and configuring said gate current waveform shape control circuit to control said gate current waveform shape based on said sensed current. The system of claim 8.
10. 10. The system of claim 9, further comprising a junction temperature circuit configured to estimate a junction temperature of the at least one power switch using the waveform shape of the gate current.
11. The gate driver includes: a pattern generator configured to generate a digital signal including a digital pattern representative of the waveform shape of the gate current; a digital-to-analog converter (DAC) configured to convert the digital signal into an analog signal defining the waveform shape of the gate current; The system of claim 8 , comprising:
12. the gate driver includes an operational amplifier configured to output the gate current at a first amplitude; the gate driver is configured to switch the operational amplifier to output the gate current at a second amplitude; the operational amplifier defines the waveform shape of the gate current; The waveform shape of the gate current depends on the settling speed of the operational amplifier. The system of claim 8.
13. The gate driver includes: at least one voltage source configured to generate a voltage; a resistor-capacitor (RC) network including at least one resistor and at least one capacitor configured to vary the voltage generated by the voltage source; Including, the waveform shape of the gate current is defined by the RC network; The system of claim 8.
14. 9. The system of claim 8, wherein the at least one power switch is included in a plurality of power switches, and the gate driver includes a plurality of current wave shaping circuits.
15. 1. A method for a gate driver comprising: generating a gate current for driving a power switch; defining a waveform shape of the gate current during a transition of the power switch; Including, the defined waveform shape of the gate current causes the current in the power switch to have a constant slew rate during a transition of the power switch. method.
16. sensing a current in the power switch; implementing a feedback loop to optimize the waveform shape of the gate current based on the sensed current; The method of claim 15 further comprising:
17. 17. The method of claim 16, further comprising estimating a junction temperature of the power switch using the waveform shape of the gate current.
18. generating a digital signal including a digital pattern representative of the waveform shape of the gate current; converting the digital signal into an analog signal defining the waveform shape of the gate current; The method of claim 15 further comprising:
19. outputting the gate current at a first amplitude; switching an operational amplifier to output the gate current at a second amplitude; Further comprising: the operational amplifier defines the waveform shape of the gate current; The waveform shape of the gate current depends on the settling speed of the operational amplifier. The method of claim 15.
20. generating a voltage using at least one voltage source; varying the voltage generated by the voltage source using an RC (resistor-capacitor) network; Further comprising: the waveform shape of the gate current is defined by the RC network; The method of claim 15.