Display device

Abstract

To improve the reliability of a semiconductor device containing low resistance materials such as copper, aluminum, gold or silver as wiring.SOLUTION: The semiconductor device comprises as a pair of electrodes electrically connected to a semiconductor layer, a stacking structure of a first protective layer in contact with the semiconductor layer and a conductive layer containing low resistance materials abutting on the first protective layer. A top face of the conductive layer is covered by a second protective layer which functions as a mask for processing the conductive layer, and a side face thereof is covered by a third protective layer. This structure inhibits constituent elements of the conductive layer containing low resistance materials from migrating or dispersing to the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the invention disclosed in this specification relates to a semiconductor device and a method of manufacturing the same.

Background Art

[0002] Most of the transistors used in flat panel displays typified by liquid crystal display devices and light emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon formed on a glass substrate or polycrystalline silicon. Further, transistors using such silicon semiconductors are also used in integrated circuits (ICs) and the like.

[0003] In addition, with the increase in the area and definition of flat panel displays, the driving frequency increases along with an increase in the resistance and parasitic capacitance of the wiring, resulting in wiring delay. Further, in order to suppress the wiring delay techniques for forming wiring using low resistance materials such as copper, aluminum, gold, silver, etc. have been studied (Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, elements constituting the wiring, such as copper, aluminum, gold, or silver, etc., have a problem that they diffuse into the semiconductor layer during processing.

[0006] Elements constituting the wiring, such as copper, aluminum, gold, or silver, etc., affect the electrical characteristics of the transistor. It is one of the impurities that cause defects. Therefore, when this impurity mixes into the semiconductor layer , the semiconductor layer has a reduced resistance, and there is a problem that the electrical characteristics of the transistor, typically the variation amount of the threshold voltage, increases due to changes over time and stress tests.

[0007] Therefore, in one aspect of the present invention, it is an object to improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as wiring.

[0008] Note that the description of these problems does not prevent the existence of other problems. One aspect of the present invention does not need to solve all of these problems. Also, problems other than the above will be apparent from the description in the specification and the like, and it is possible to extract problems other than the above from the description in the specification and the like.

Means for Solving the Problems

[0009] In a semiconductor device according to one aspect of the present invention, each of a pair of electrodes electrically connected to a semiconductor layer has a first protective layer in contact with the semiconductor layer and a conductive layer containing a low-resistance material in contact with the first protective layer , and the conductive layer has a laminated structure, and the upper surface thereof is covered with a second protective layer that also functions as a mask for processing the conductive layer , and the side surface is covered with a third protective layer. Thereby, the constituent elements of the pair of conductive layers containing the low-resistance material are suppressed from mixing into or diffusing into the semiconductor layer.

[0010] Also, in the above-described electrode formation process, the first protective layer and the conductive layer containing the low-resistance material are processed by separate etching processes. Here, when processing the conductive layer, the semiconductor The layer is covered with a film that serves as the first protective layer. Also, when processing the first protective layer the upper surface of the previously processed conductive layer is covered by the second protective layer, and the side surface is covered by the third protective layer This can suppress the mixing of the constituent elements of the conductive layer into the semiconductor layer during the electrode formation process.

[0011] Furthermore, the first protective layer and the third protective layer can be self - consistently formed by anisotropic etching using the second protective layer as an etching mask. Therefore, without increasing the number of photomasks in the formation process of a pair of electrodes, it is possible to provide a protective layer (the first protective layer, the second protective layer, and the third protective layer) that covers the periphery of the conductive layer, and it becomes possible to provide a highly reliable semiconductor device with good productivity.

[0012] More specifically, for example, the following configuration can be adopted.

[0013] One aspect of the present invention has a semiconductor layer, a conductive layer, a first protective layer, a second protective layer, and a third protective layer. The lower surface of the conductive layer is in contact with the first protective layer, the upper surface of the conductive layer is in contact with the second protective layer, the side surface of the conductive layer is in contact with the third protective layer, the semiconductor layer is in contact with the first protective layer, the conductive layer contains copper, aluminum, gold, or silver, and the lower end portion of the side surface of the third protective layer coincides with the upper end portion of the side surface of the first protective layer.

[0014] Also, one aspect of the present invention has a semiconductor layer, a conductive layer, a first protective layer, a second protective layer, and a third protective layer. The lower surface of the conductive layer is in contact with the first protective layer, the upper surface of the conductive layer is in contact with the second protective layer, the side surface of the conductive layer is in contact with the third protective layer, the semiconductor layer is in contact with the first protective layer ​​​​​​​​​​​, the conductive layer contains copper, aluminum, gold, or silver, and the lower end of the side surface of the third protective layer coincides with the upper end of the side surface of the first protective layer. The upper surface of the first protective layer is in contact with the conductive layer and the third protective layer, and the lower surface of the second protective layer is in contact with the conductive layer and the third protective layer. This is a semiconductor device.

[0015] In the above, the first protective layer is a conductive layer. Also, the conductive layer is preferably formed of titanium, tantalum, tungsten, molybdenum alone or an alloy thereof, or titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

[0016] In any one of the above semiconductor devices, in the semiconductor layer, the thickness of the region in contact with the first protective layer may be larger than the thickness of other regions.

[0017] Also, in any one of the above semiconductor devices, the semiconductor layer is preferably an oxide semiconductor layer containing indium, gallium, or zinc.

[0018] Another aspect of the present invention is to form a first protective film serving as a first protective layer, a conductive film containing copper, aluminum, gold, or silver, and a second protective film serving as a second protective layer on a semiconductor layer, form a first mask on the second protective film, process the second protective film using the first mask to form a second protective layer, process the conductive film using the second protective layer as a mask to form a conductive layer, form a third protective film in contact with the side surface and the upper surface of the second protective layer, the side surface of the conductive layer, and the region exposed from the conductive layer in the first protective film, and process the third protective film and the first protective film by anisotropic etching to form a first protective layer located between the conductive layer and the semiconductor layer ​​A method of manufacturing a semiconductor device that forms a third protective layer in contact with a side surface of a conductive layer.

Advantages of the Invention

[0019] According to one aspect of the present invention, the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as wiring can be improved.

Brief Description of the Drawings

[0020]

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Embodiments for Carrying Out the Invention

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples shown below. Also in the embodiments and examples described below, the same parts or parts having the same function are commonly used with the same reference numerals or the same hatching pattern among different drawings, and the repeated description thereof is omitted.

[0022] In each of the drawings described in this specification, the size, film thickness, or region of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0023] Also, ordinal numbers such as first and second used in this specification are attached to avoid confusion of components and are not numerically limiting. Therefore, for example, "first" can be appropriately replaced with "second" or "third" and so on for explanation.

[0024] Also, the functions of "source" and "drain" may be interchanged when the direction of current changes in circuit operation and the like. For this reason, in this specification and the like, the terms "source" and "drain" shall be interchangeable.

[0025] Also, voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in the electrostatic field at a certain point. Additionally, generally, the potential difference between the potential at a certain point and the reference potential (e.g., ground potential) is simply referred to as potential or voltage, and potential and voltage are often used as synonyms . Therefore, in this specification, unless otherwise specified, potential may be read as voltage or voltage may be read as potential.

[0026] (Embodiment 1) In this embodiment, a semiconductor device which is one aspect of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1 to 4.

[0027] FIGS. 1(A) to 1(D) show a configuration example of a transistor 200 included in the semiconductor device . FIG. 1(A) is a plan view of the transistor 200, and FIG. 1(B) is a cross-sectional view taken along the dashed line X1 - Y1 in FIG. 1(A). FIG. 1(C) is a cross-sectional view taken along the dashed line V1 - W1 in FIG. 1(A), and FIG. 1(D) is a cross-sectional view taken along the dashed line V2 - W2 in FIG. 1(A). ​​​ Yes. In FIG. 1(A), for clarity, some of the components of the transistor 200 (e.g., the insulating film 124, etc.) are omitted from the illustration.

[0028] The transistor 200 shown in FIG. 1 includes a gate electrode 104 on a substrate 102, the insulating films 106 and 108 on the gate electrode 104, and a semiconductor layer 110 overlapping the gate electrode 104 via the insulating films 106 and 108, a pair of electrodes 116a and 116b in contact with the semiconductor layer 110, a pair of second protective layers 118a and 118b in contact with the upper surfaces of the pair of electrodes 116a and 116b, and a pair of third protective layers 120a and 120b in contact with the side surfaces

[0029] In the transistor 200, the insulating films 106 and 108 provided between the gate electrode 104 and the semiconductor layer 110 function as a gate insulating film. Also, in the transistor 200, the gate electrode 104 has a stacked structure of a gate electrode 104a and a gate electrode 104b.

[0030] The pair of electrodes 116a and 116b function as a source electrode and a drain electrode. In the pair of electrodes 116a and 116b, the electrode 116a has at least a stacked structure of a first protective layer 112a and a conductive layer 114a in contact with the semiconductor layer 110. Also, the electrode 116b has at least a stacked structure of a first protective layer 112b and a conductive layer 114b in contact with the semiconductor layer 110.

[0031] Also, a pair of second protective layers 118a and 118b are provided in contact with the upper surfaces of the pair of conductive layers 114a and 114b included in the pair of electrodes 116a On each side of the conductive layers 114a and 114b, a pair of third protective layers 120a and 120b are provided so as to cover at least a part of each side of the pair of second protective layers 118a and 118b.

[0032] The pair of first protective layers 112a and 112b are conductive layers having a function of suppressing the diffusion of metal elements constituting the pair of conductive layers 114a and 114b into the semiconductor layer 110. The pair of first protective layers 112a and 112b can be formed by appropriately using titanium, tantalum, molybdenum, tungsten alone or in alloy, or titanium nitride, tantalum nitride, molybdenum nitride, tungsten nitride, etc.

[0033] The pair of conductive layers 114a and 114b can be a single layer structure or a laminated structure including a single substance or alloy made of a low-resistance material such as copper, aluminum, gold, or silver, or a compound containing these as a main component. For example, the pair of conductive layers 114a and 114b can be a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a copper film, a silver film, or a gold film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a titanium film or a titanium nitride film is formed on an aluminum film, a copper film, a silver film, or a gold film, or a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film, a copper film, a silver film, or a gold film are laminated on the molybdenum film or the molybdenum nitride film, and then a molybdenum film or a molybdenum nitride film is formed thereon, etc.

[0034] Since the pair of electrodes 116a and 116b also function as wiring, the pair of electrodes 116a and 11 The pair of conductive layers 114a and 114b included in 6b are made of a low resistance material such as copper, aluminum, gold, or silver. By forming them in this way, even when a large-area substrate is used as the substrate 102 and the wiring becomes long, it is possible to fabricate a semiconductor device with suppressed wiring delay. .

[0035] A pair of second protective layers 118a , 118b provided in contact with the upper surfaces of the pair of conductive layers 114a and 114b, and a pair of third protective layers 120a, 120b provided in contact with the side surfaces of the pair of conductive layers 114a, 114b have the function of preventing the diffusion of the metal elements constituting the pair of conductive layers 114a, 114b. Therefore, the pair of second protective layers 118a, 118b and the pair of third protective layers 120a, 120b are formed using a material having barrier properties against the metal elements constituting the pair of conductive layers 114a, 114b.

[0036] The pair of second protective layers 118a, 118b are formed using a material having etching resistance during the etching of the pair of conductive layers 114a, 114b. Therefore, the pair of second protective layers 118a, 118b function as an etching protection film when etching the pair of conductive layers 114a, 114b.

[0037] The pair of third protective layers 120a, 120b are provided so as to cover the side surfaces of the pair of second protective layers 118a, 118b, the side surfaces of the pair of conductive layers 114a, 114b, and the upper surfaces of the first protective layers 112a, 112b exposed from the pair of conductive layers 114a, 114b. As shown in FIGS. 1(B) and 1(D), in the cross-sectional shape, the lower end portions of the side surfaces of the pair of third protective layers 120a, 120b coincide with the upper end portions of the side surfaces of the pair of first protective layers 112a, 112b.

[0038] As a pair of second protective layers 118a and 118b and a pair of third protective layers 120a and 120b, specifically, each can be formed by appropriately using nitride insulating films such as a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, and an aluminum oxynitride layer. Note that in this specification and the like, a silicon oxynitride layer and an aluminum oxynitride layer refer to layers with an oxygen content (atomic ratio) higher than that of nitrogen, and a silicon nitride oxide layer and an aluminum nitride oxide layer refer to layers with an oxygen content (atomic ratio) higher than that of nitrogen. In this specification and the like, a silicon oxynitride layer and an aluminum oxynitride layer refer to layers with an oxygen content (atomic ratio) higher than that of nitrogen, and a silicon nitride oxide layer and an aluminum nitride oxide layer refer to layers with an oxygen content (atomic ratio) higher than that of nitrogen. refer to layers with an oxygen content (atomic ratio) higher than that of nitrogen.

[0039] Or, the pair of second protective layers 118a and 118b and the pair of third protective layers 120a and 12 0b may each be formed using a conductive film having translucency, which is formed using a conductive material such as indium tin oxide (hereinafter also referred to as ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. However, when using the above-mentioned conductive film having translucency as the pair of second protective layers 118a and 118b or the pair of third protective layers 120a and 12 0b, the conductive film having translucency also functions as part of the pair of electrodes 116a and 116b.

[0040] Or, the pair of second protective layers 118a and 118b and the pair of third protective layers 120a and 12 0b may be formed by appropriately using an oxide semiconductor containing In, Ga, or Zn. In addition, the oxide semiconductor containing In, Ga, or Zn can also be used for the semiconductor layer 110.

[0041] Or, the pair of second protective layers 118a and 118b and the pair of third protective layers 120a and 12 0b may be formed by appropriately using an oxide semiconductor containing In, Ga, or Zn. In addition, the oxide semiconductor containing In, Ga, or Zn can also be used for the semiconductor layer 110. It is possible.

[0042] Note that, in the transistor 200, a case where a pair of second protective layers 118a and 118b and a pair of third protective layers 120a and 120b are formed using the same material is shown as an example. In this case, the boundaries between the pair of second protective layers 118a and 118b and the pair of third protective layers 120a and 1 20b may become unclear. In FIG. 1, these boundaries are schematically shown by broken lines This is the same in the subsequent drawings.

[0043] In the transistor 200, an insulating film 122 is provided so as to cover the pair of second protective layers 118a and 118b and the semiconductor layer 11 0, and an insulating film 124 is provided on the insulating film 122 The insulating film 122 and / or the insulating film 124 may be included in the components of the transistor 200 Note that, in FIG. 1, the insulating film 122 and the insulating film 124 laminated in order are illustrated However, instead of the insulating film 122 and the insulating film 124, a single-layer insulating film may be provided and three or more laminated insulating films may be provided.

[0044] As shown in the cross-sectional views of the transistor 200 in FIGS. 1(B) and 1(D), in terms of the cross-sectional shape the conductive layer 114a is located between the two side surfaces of the first protective layer 112a and between the two side surfaces of the second protective layer 118a Also, the conductive layer 114b is located between the two side surfaces of the first protective layer 112b and between the two side surfaces of the second protective layer 118b. Therefore, the upper surface of the first protective layer 112a is in contact with the conductive layer 114a and the third protective layer 120a, and the lower surface of the second protective layer 118a is in contact with the conductive layer 114a and the third protective layer 120a. Also, the first protective layer 11 The upper surface of 2b is in contact with the conductive layer 114b and the third protective layer 120b, and the second protective layer 118 The lower surface of b is in contact with the conductive layer 114b and the third protective layer 120b. In the transistor 200 the channel region is formed between the first protective layer 112a and the first protective layer 112b, so that by providing the conductive layers 114a, 114b at the above positions, the conductive layers 11 4a, 114b can be separated from the channel region. Therefore, the diffusion of metal elements constituting the conductive layers 114a, 114b, which can become impurities in the semiconductor layer 110, into the semiconductor layer 110 can be further prevented. Furthermore, by forming the pair of electrodes 116a, 116b near the channel region into a single-layer structure of the pair of first protective layers 11 2a, 112b, the resistance of the region (the region where only the pair of first protective layers 112a, 11

[0045] 2b are provided) can be increased compared to other regions (the regions having a stacked structure of the pair of first protective layers 112a, 112 b and the pair of conductive layers 114a, 114b). Therefore, the electric field between the source and the drain can be relaxed. 2b only) can be increased compared to other regions (regions having a stacked structure of the pair of first protective layers 112a, 112 b and the pair of conductive layers 114a, 114b), so that the electric field between the source and the drain can be relaxed. As described above, the transistor 200 uses the pair of conductive layers 114a, 1

[0046] 14b containing a low-resistance material as wiring, and while suppressing wiring delay, the lower surface, upper surface, and side surfaces of the pair of conductive layers 114 a, 114b are covered with a pair of first to third protective layers that can function as barrier layers, so that the mixing and diffusion of impurities into the semiconductor layer 110 can be suppressed. The transistor 2 00 having a semiconductor layer 110 with reduced impurities is a highly reliable transistor with suppressed fluctuations in electrical characteristics. 00 is a highly reliable transistor with suppressed fluctuations in electrical characteristics.

[0047] Note that a pair of first protective layers 112a and 112b that function as barrier layers for the pair of conductive layers 114a and 114b, a pair of second protective layers 118a and 118b, and a pair of third protective layers 120a and 120b may contain metal elements constituting the pair of conductive layers 114a and 114b as impurities. However, the concentration of metal elements that can be mixed in as impurities is highest in the region in contact with the pair of conductive layers 114a and 114b, and preferably decreases as the distance from the pair of conductive layers 114a and 114b increases. 12a, 118b and a pair of third protective layers 12 0a, 120b may be contaminated with metal elements that make up the pair of conductive layers 114a and 114b as impurities. However, the concentration of metal elements that can be mixed in as impurities is highest in the region in contact with the pair of conductive layers 114a, 114b, and preferably decreases as the distance from the pair of conductive layers 114a, 114b increases.

[0048] Details of other configurations of the transistor 200 will be described below.

[0049] There are no major restrictions on the material of the substrate 102, etc., but it is necessary to have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Also, a single-crystalline semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be used, and those with semiconductor elements provided on these substrates may be used as the substrate 102. When using a glass substrate as the substrate 102, by using a large-area substrate such as the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation (2950 mm × 3400 mm), etc., a large-sized display device can be manufactured. In addition, when using a flexible substrate as the substrate 102, the transistor 200 can be directly formed on the flexible substrate. Sixth generation (1500mm × 1850mm), seventh generation (1870mm × 2200mm), Eighth generation (2200mm × 2400mm), ninth generation (2400mm × 2800mm), Tenth generation (2950mm × 3400mm), etc., a large-sized display device can be fabricated.

[0050] Also, by using a flexible substrate as the substrate 102 and directly forming the transistor 200 on the flexible substrate It may be formed. Alternatively, a release layer may be provided between the substrate 102 and the transistor 200. The release layer can be separated from the substrate 102 after partially or fully completing a semiconductor device thereon and transferred to another substrate. At this time, the transistor 200 can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0051] The gate electrode 104 has a structure in which the gate electrode 104a and the gate electrode 104b are stacked. The gate electrode 104a can be appropriately formed using the same material as the first protective layers 112a and 112b. In addition, the gate electrode 104b can be appropriately formed using the same material as the conductive layers 114a and 114b. By providing the gate electrode 104a, the adhesion between the substrate 102 and the gate electrode 104b can be enhanced.

[0052] Also, the gate electrode 104b can be formed using a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. In addition, a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be formed.

[0053] For the insulating films 106 and 108 that function as a gate insulating film, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or Ga-Zn based metal oxide can be used. Note that in this embodiment, ​​​​​​​​​​In the present embodiment, a gate insulating film having a laminated structure of an insulating film 106 and an insulating film 108 is provided. However, the present invention is not limited to this, and the gate insulating film may have a single layer structure or a structure of three or more layers. The gate insulating film may have a laminated structure.

[0054] In the gate insulating film, the insulating film 106 in contact with the gate electrode 104 is made of silicon nitride. Forming a nitride insulating film such as silicon oxynitride, aluminum nitride, or aluminum oxynitride By this, the diffusion of the metal element constituting the gate electrode 104b included in the gate electrode 104 is suppressed. This is preferable because it can be prevented.

[0055] In addition, it is preferable to use a silicon nitride film or a silicon nitride oxide film as the insulating film 106. The silicon nitride film or silicon nitride oxide film has a dielectric constant lower than that of a silicon oxide film. The gate insulating film is physically thin, so the capacitance is high and the thickness required to obtain the same capacitance is large. For example, the thickness of the insulating film 106 can be increased to 300 nm or more and 400 nm or less. Therefore, the decrease in the dielectric strength of the transistor 200 can be suppressed or the dielectric strength Therefore, electrostatic damage to the semiconductor device can be suppressed.

[0056] In addition, a nitride insulating film that can be suitably used as the insulating film 106 can form a dense film. While the diffusion of metal elements in the gate electrode 104b can be prevented by using the above-mentioned function, the defect level density and internal Since the internal stress is large, forming an interface with the semiconductor layer 110 causes a shift in the threshold voltage. Therefore, when a nitride insulating film is formed as the insulating film 106, Between the semiconductor layer 110 and the insulating film 108, silicon oxide, silicon oxynitride, It is preferable to provide an oxide insulating film such as aluminum oxide or aluminum oxynitride. Half By forming an insulating film 108 made of an oxide insulating film between the semiconductor layer 110 and the insulating film 106 made of a nitride insulating film, it becomes possible to stabilize the interface between the gate insulating film and the semiconductor layer 110. It can be done.

[0057] The film thickness of the insulating film 108 can be, for example, 25 nm or more and 150 nm or less. In addition, When an oxide semiconductor described later is used as the semiconductor layer 110, by using an oxide insulating film as the insulating film 108 in contact with the semiconductor layer 110, it is also possible to supply oxygen to the semiconductor layer 110. Since oxygen vacancies contained in the oxide semiconductor n-type the oxide semiconductor and cause fluctuations in electrical characteristics, supplying oxygen from the insulating film 108 to fill the oxygen vacancies is effective in improving reliability. Or, as the insulating film 106 or the insulating film 108, hafnium silicate (HfSiO By using a high-k material such as hafnium silicate with nitrogen added (HfSi

[0058] O x ) , hafnium aluminate with nitrogen added (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc., the gate leakage of the transistor can be reduced. x O y N z ), hafnium oxide, yttrium oxide, etc., the gate leakage of the transistor can be reduced. The semiconductor layer 110 can appropriately use semiconductor elements such as silicon, germanium, gallium arsenide, and gallium nitride. In addition, the semiconductor layer 110 can be appropriately made into a single crystal structure or a non-single crystal structure. The non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.

[0059] The semiconductor layer 110 can appropriately use semiconductor elements such as silicon, germanium, gallium arsenide, and gallium nitride. Also, the semiconductor layer 110 can be made into a single crystal structure or a non-single crystal structure as appropriate. The non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. It includes a mass structure.

[0060] When using semiconductor elements such as silicon, germanium, gallium arsenide, and gallium nitride as the semiconductor layer 110, the thickness of the semiconductor layer 110 is 20 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less.

[0061] In addition, the semiconductor layer 110 can use an oxide semiconductor containing In, Ga, or Zn. The oxide semiconductor containing In, Ga, or Zn is typically an In-Ga oxide, an In-Zn oxide, or an In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf).

[0062] When the oxide semiconductor is an In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In ≥ M and Zn ≥ M. As such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1:1 and In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor layer to be formed includes fluctuations of plus or minus 30% of the atomic ratio of the metal elements contained in the above sputtering target as errors, respectively.

[0063] When the oxide semiconductor is an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably 25 atomic% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M.

[0064] ​​​​​​​​ The oxide semiconductor has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using such an oxide semiconductor with a wide energy gap for the semiconductor layer 110, the off-current of the transistor 200 can be reduced.

[0065] The oxide semiconductor can be appropriately a single crystal structure or a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalli ne Oxide Semiconductor), a polycrystalline structure, the microcrystalline structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels and CAAC-OS has the lowest density of defect levels.

[0066] When an oxide semiconductor is used for the semiconductor layer 110, the thickness of the semiconductor layer 110 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 5 0 nm or less.

[0067] Note that, as the oxide semiconductor, it is preferable to use an oxide semiconductor with a low impurity concentration and a low density of defect levels to fabricate a transistor having more excellent electrical characteristics. Here, an oxide semiconductor having a low impurity concentration and a low density of defect levels (less oxygen deficiency) is called high-purity genuine or substantially high-purity genuine.

[0068] An oxide semiconductor that is high-purity genuine or substantially high-purity genuine may be able to reduce the carrier density because there are few carrier generation sources. In this case, for a transistor in which a channel region is formed in the semiconductor layer 110 using the oxide semiconductor, the threshold voltage is negative and ​It is less likely to have the resulting electrical characteristics (also referred to as normally on).

[0069] The carrier density of the oxide semiconductor is 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, more preferably 1×10 13 per cm 3 or less, still more preferably 1×1 0 11 per cm 3 or less, which is preferable.

[0070] In addition, an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels and thus the trap level density may also be low.

[0071] In addition, a transistor having an oxide semiconductor that is highly pure intrinsic or substantially highly pure intrinsic has an extremely small off-current. Even for a device with a channel width of 1×10 6 μm and a channel length L of 10 μm when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1× 10 -13 A or less.

[0072] Therefore, a transistor in which a channel region is formed in an oxide semiconductor may have small fluctuations in electrical characteristics and be a highly reliable transistor. Note that the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics. As impurities, hydrogen, nitrogen The charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics. As impurities, hydrogen, nitrogen is formed, the electrical characteristics may become unstable. As impurities, hydrogen, nitrogen There are elements, alkali metals, alkaline earth metals, etc.

[0073] Note that hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Also, in some cases, electrons, which are carriers, are generated when a part of the hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that the hydrogen contained in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is 20 2×10 3 atoms / cm 19 or less, preferably 5×10 m 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 5×1 0 18 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, still more preferably 1×10 16 a toms / cm 3 or less.

[0074] Also, in the oxide semiconductor, when silicon or carbon, which is one of the group 14 elements, is contained, The oxygen vacancies increase and the semiconductor becomes n-type. The concentration of is 2 x 10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0075] In addition, in the oxide semiconductor, an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 Alkali metals and alkaline earth metals are oxide semiconductors. When the semiconductor reacts with the semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor is It is preferable to reduce it.

[0076] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carrier density As a result, transistors using oxide semiconductors containing nitrogen are easily converted to n-type. Therefore, in the oxide semiconductor, nitrogen is It is preferable that the amount of the ions is as small as possible. For example, the amount of the ions obtained by secondary ion mass spectrometry is The nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0077] In addition, the concentration of copper, aluminum, gold, or silver in the semiconductor layer 110 is 1×10 18 atoms / cm 3 The semiconductor layer 110 is made of copper, aluminum, gold, or silver. By setting the concentration to the above concentration, the electrical characteristics of the transistor can be improved. Also, the reliability of the transistor can be enhanced.

[0078] Note that, as the pair of first protective layers 112a and 112b, if a conductive material that easily binds to oxygen, such as titanium, tantalum, tungsten, or molybdenum, in the form of a single element or an alloy, is used, the oxygen contained in the oxide semiconductor binds to the conductive material contained in the pair of first protective layers 112a and 112b, and in the semiconductor layer 110 formed of the oxide semiconductor, an oxygen-deficient region is formed. Also, in some cases, a part of the constituent elements of the conductive material forming the pair of first protective layers 112a and 112b on the semiconductor layer 110 formed of the oxide semiconductor may be mixed in. As a result of these, in the semiconductor layer 110 formed of the oxide semiconductor, a low-resistance region is formed in the vicinity of the region in contact with the pair of first protective layers 112a and 112b. The low-resistance region is in contact with the pair of first protective layers 112a and 112b and is formed between the insulating film 108 and the pair of first protective layers 112a and 112b. Since the low-resistance region has high conductivity, it is possible to reduce the contact resistance between the semiconductor layer 110 formed of the oxide semiconductor and the first protective layers 112a and 112b, and it is possible to increase the on-current of the transistor. The insulating films 122 and 124 can be appropriately an oxide insulating film or a nitride insulating film. Here, an oxide semiconductor is used as the semiconductor layer 110, an oxide insulating film capable of reducing the oxygen deficiency of the oxide semiconductor is used as the insulating film 122, and an external from the outside is used as the insulating film 124. Since the low-resistance region has high conductivity, it is possible to reduce the contact resistance between the semiconductor layer 110 formed of the oxide semiconductor and the first protective layers 112a and 112b, and it is possible to increase the on-current of the transistor.

[0079] The insulating films 122 and 124 can be appropriately an oxide insulating film or a nitride insulating film.

[0080] Here, an oxide semiconductor is used as the semiconductor layer 110, an oxide insulating film capable of reducing the oxygen deficiency of the oxide semiconductor is used as the insulating film 122, and an external from the outside is used as the insulating film 124. A nitride insulating film is used to prevent impurities from moving into the semiconductor layer 110. Hereinafter, the details of the oxide insulating film that can be used as the insulating film 122 and the nitride insulating film that can be used as the insulating film 124 will be described. Hereinafter, the details of the oxide insulating film that can be used as the insulating film 122 and the nitride insulating film that can be used as the insulating film 124 will be described.

[0081] The oxide insulating film is formed using an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition has a part of the oxygen desorbed by heating. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition has a part of the oxygen desorbed by heating. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition is subjected to TDS (Thermal Desorption Spectroscopy) analysis performed by heat treatment at a surface temperature of 100 °C or higher and 700 °C or lower, preferably 100 °C or higher and 500 °C or lower. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition is subjected to TDS (Thermal Desorption Spectroscopy) analysis performed by heat treatment at a surface temperature of 100 °C or higher and 700 °C or lower, preferably 100 °C or higher and 500 °C or lower. In the analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 at oms / cm 3 or more, preferably 3.0×10 20 atoms / cm 3 or more, and is an oxide insulating film. The oxide insulating film is an oxide insulating film.

[0082] Examples of the oxide insulating film that can be used as the insulating film 122 include silicon oxide, silicon oxynitride, etc., with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less. Examples of the oxide insulating film that can be used as the insulating film 122 include silicon oxide, silicon oxynitride, etc., with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less. Examples of the oxide insulating film that can be used as the insulating film 122 include silicon oxide, silicon oxynitride, etc., with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less.

[0083] The nitride insulating film that can be used as the insulating film 124 has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the nitride insulating film as the insulating film 124, the diffusion of oxygen from the semiconductor layer 110 to the outside and the intrusion of hydrogen, water, etc. from the outside into the semiconductor layer 110 can be prevented. Examples of the nitride insulating film include a silicon nitride film, a nitride The nitride insulating film that can be used as the insulating film 124 has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the nitride insulating film as the insulating film 124, the diffusion of oxygen from the semiconductor layer 110 to the outside and the intrusion of hydrogen, water, etc. from the outside into the semiconductor layer 110 can be prevented. Examples of the nitride insulating film include a silicon nitride film, a nitride The nitride insulating film that can be used as the insulating film 124 has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the nitride insulating film as the insulating film 124, the diffusion of oxygen from the semiconductor layer 110 to the outside and the intrusion of hydrogen, water, etc. from the outside into the semiconductor layer 110 can be prevented. Examples of the nitride insulating film include a silicon nitride film, a nitride The nitride insulating film that can be used as the insulating film 124 has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the nitride insulating film as the insulating film 124, the diffusion of oxygen from the semiconductor layer 110 to the outside and the intrusion of hydrogen, water, etc. from the outside into the semiconductor layer 110 can be prevented. Examples of the nitride insulating film include a silicon nitride film, a nitride There are a silicon oxide film, an aluminum nitride film, an aluminum oxynitride film, etc. Note that an oxide insulating film having a blocking effect against oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, etc., a nitride insulating film may be provided instead with an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. Examples of the oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, etc.

[0084] An example of the method for manufacturing the transistor 200 according to the present embodiment will be described below with reference to FIGS. 2 and 3.

[0085] First, a gate electrode 104 including a stacked structure of a gate electrode 104a and a gate electrode 104b is formed on a substrate 102, and an insulating film 106 and an insulating film 108 are stacked on the gate electrode 104 (see FIG. 2(A)).

[0086] The method for forming the gate electrode 104 is shown below. First, a conductive film to be the gate electrode 104a and a conductive film to be the gate electrode 104b are formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, a vapor deposition method, etc., and a mask is formed on the conductive film by a photolithography process. Next, using the mask, a part of each of the conductive film to be the gate electrode 104a and the conductive film to be the gate electrode 104b is etched to form the gate electrode 104 composed of the gate electrode 104a and the gate electrode 104b. After this, the mask is removed.

[0087] ​​​​​​Note that the gate electrode 104 may be formed by an electrolytic plating method, a printing method, an inkjet method, etc. instead of the above-described forming method.

[0088] Here, a titanium film with a thickness of 35 nm and a copper film with a thickness of 200 nm are formed in sequence by a sputtering method. Next, a mask is formed by a photolithography process, and using this mask, a part of the copper film and a part of the titanium film are dry-etched to form a gate electrode 104a formed of the titanium film and a gate electrode 104b formed of the copper film.

[0089] Note that in this embodiment, a gate electrode 104 having a stacked structure is shown, but a gate electrode 104 having a single-layer structure may also be used. For example, the gate electrode 104 may be formed only by the gate electrode 104b.

[0090] The insulating films 106 and 108 that function as a gate insulating film are formed by a sputtering method, a CVD method, a vapor deposition method, etc.

[0091] When forming a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film as the insulating films 106 and 108, as the source gas, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0092] Also, when forming a gallium oxide film as the insulating film 106 or the insulating film 108, it can be formed using the MOCVD (Metal Organic Chemical Vapor Deposition ) method.

[0093] Next, an island-shaped semiconductor layer 110 is formed on the insulating film 108 (see FIG. 2(B)).

[0094] The method for forming the semiconductor layer 110 will be described below. A semiconductor film that will become the semiconductor layer 11 0 is formed on the insulating film 108. Next, a mask is formed on the semiconductor film by a photolithography process, and then using the mask, a part of the semiconductor film is etched to form the element-isolated semiconductor layer 110 as shown in FIG. 2(B). After that, the mask is removed.

[0095] The semiconductor film that will become the semiconductor layer 110 can be formed using a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a CVD method, or the like.

[0096] When forming an oxide semiconductor layer as the semiconductor layer 110, a power supply device for generating plasma in the sputtering method can be appropriately used, such as an RF power supply device, an AC power supply device, or a DC power supply device.

[0097] As the sputtering gas, a noble gas (typically argon), oxygen, or a mixed gas of a noble gas and oxygen can be appropriately used. In the case of a mixed gas of a noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0098] Also, the target can be appropriately selected according to the composition of the oxide semiconductor layer to be formed.

[0099] In order to obtain an oxide semiconductor layer that is highly pure intrinsic or substantially highly pure intrinsic, not only the inside of the chamber needs to be evacuated to a high vacuum but also the sputtering gas needs to be highly purified. The oxygen gas or argon gas used as the sputtering gas has a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. The noble gas has a dew point of -60°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. The purity of the sputtering gas is preferably 99.999% or higher, and more preferably 99.9999% or higher. preferably -100°C or lower. The noble gas has a dew point of -60°C or lower, preferably -80°C or lower, and more preferably -100°C or lower. The purity of the sputtering gas is preferably 99.999% or higher, and more preferably 99.9999% or higher.​​​​ Preferably, a gas purified to -100°C or lower, more preferably -120°C or lower, is used to prevent, as much as possible, moisture and the like from being incorporated into the oxide semiconductor film.

[0100] Here, an In-Ga-Zn oxide target (In:Ga:Zn = 1:1:1) is used, and an In-Ga-Zn oxide film with a thickness of 35 nm is formed as the oxide semiconductor layer by sputtering. Next, a mask is formed on the oxide semiconductor layer, and a part of the oxide semiconductor layer is selectively etched to form the semiconductor layer 110.

[0101] After that, a first heat treatment may be performed. When the semiconductor layer 110 is formed of an oxide semiconductor layer, hydrogen, water, etc. contained in the semiconductor layer 110 can be desorbed by the first heat treatment, and the hydrogen concentration and water concentration contained in the oxide semiconductor layer can be reduced. The temperature of the heat treatment is typically 300°C or higher and 400°C or lower, preferably 320°C or higher and 370°C or lower.

[0102] For the first heat treatment, an electric furnace, an RTA (Rapid Thermal Anneal) apparatus, etc. can be used. By using an RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the distortion point of the substrate for a limited time, so the heat treatment time can be shortened.

[0103] The first heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). Note that hydrogen is added to the above nitrogen, oxygen, ultra-dry air, or noble gas. ​​​​​​​​​​​​​, it is preferably free of water and the like. Further, after heat treatment in a nitrogen or noble gas atmosphere, it may be heated in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, etc. contained in the semiconductor layer 110 can be desorbed, and oxygen can be supplied into the semiconductor layer 110. This results in reducing the amount of oxygen vacancies contained in the semiconductor layer 110.

[0104] Note that the first heat treatment may be performed before processing the semiconductor layer 110 into an island shape.

[0105] Next, a first protective film 112 serving as a first protective layer, a conductive film 114, and a second protective film 113 serving as a second protective layer are formed in this order (see Fig. 2(C)).

[0106] The first protective film 112, the conductive film 114, and the second protective film 113 are formed using a sputtering method, a C VD method, an evaporation method, or the like.

[0107] Here, a titanium film with a thickness of 35 nm is formed as the first protective film 112 by a sputtering method. Also, a copper film with a thickness of 200 nm is formed as the conductive film 114 by a sputtering method. Also, a silicon nitride film with a thickness of 230 nm is formed as the second protective film 113 by a plasma CVD method.

[0108] Next, masks 115a and 115b are formed on the second protective film 113, and a part of the second protective film 113 is etched using the masks 115a and 115b to form a pair of second protective layers 11 3a and 113b (see Fig. 2(D)). As the masks 115a and 115b, a mask formed of an organic resin (typically, a resist mask) can be applied.

[0109] The etching of the second protective film 113 can be appropriately performed using dry etching, wet etching, or the like. Note that the pair of second protective layers 113a and 113b function as a hard mask in a later process, and the distance between the second protective layers 113a and 113b formed as a hard mask becomes the channel length L of the transistor. Therefore, it is preferable to process the second protective film 113 using dry etching that enables anisotropic etching.

[0110] Next, a part of the conductive film 114 is etched using the second protective layers 113a and 113b to form a pair of conductive layers 114a and 114b (see FIG. 3(A)). Here, conditions are used such that the first protective film 112 is not etched and the conductive film 114 is selectively etched. As a result, since the semiconductor layer 110 is not exposed in this etching process, it is possible to suppress the metal elements constituting the conductive film 114 from mixing into the semiconductor layer 110 during the etching of the conductive film 114.

[0111] Also, by etching the conductive film 114 using the wet etching method, the conductive film 114 is etched isotropically. Therefore, the conductive layer 114a is formed between the both side surfaces of the first protective layer 112a to be formed later and between the both side surfaces of the second protective layer 118a, and the conductive layer 114b is formed between the both side surfaces of the first protective layer 112b to be formed later and between the both side surfaces of the second protective layer 118b. As conditions for selectively etching the conductive film 114 without etching the first protective film 112, it is possible to appropriately use, for example, nitric acid, perchloric acid, phosphoric acid, a mixed solution of acetic acid and nitric acid (mixed acid aluminum solution), or the like as an etchant.

[0112] ​​​​​​​​​​​​​​​ Here, a wet etching method using a mixed solution of hydrogen peroxide, ammonium acetate, malonic acid, ethylenediaminetetraacetic acid, and 5-amino-1H-tetrazole monohydrate is used to selectively etch the conductive film 114.

[0113] Next, the masks 115a and 115b are removed. Here, the masks are decomposed in the gas phase by plasma (hereinafter referred to as ashing treatment) to facilitate the removal of the masks 115a and 115b, and then the masks 115a and 115b are removed using a stripping solution.

[0114] Note that the removal of the masks 115a and 115b can also be performed before the etching treatment of the conductive film 114. However, since the side surfaces of the pair of conductive layers 114a and 114b obtained by processing the conductive film 114 are located between the both side surfaces of the pair of second protective layers 113a and 113b, they are less likely to be exposed to the plasma (for example, oxygen plasma) applied to the ashing treatment of the masks 115a and 115b. When the pair of conductive layers 114a and 114b are irradiated with plasma, the metal elements and oxygen constituting the pair of conductive layers 114a and 114b react to form a compound (metal oxide). Since the compound has high reactivity and becomes an impurity when diffused into the semiconductor layer 110, it is more preferable to remove the masks 115a and 115b after processing the pair of conductive layers 114a and 114b.

[0115] Next, a third protective film 120 is formed so as to cover the exposed first protective film 112, the side surfaces of the pair of conductive layers 114a and 114b, and the pair of second protective layers 113a and 113b (see FIG. 3(B)).

[0116] The third protective film 120 is formed using a sputtering method, a CVD method, an evaporation method, or the like.

[0117] Here, as the third protective film 120, a silicon nitride film with a thickness of 230 nm is formed by plasma CVD method.

[0118] Next, the third protective film 120 and the first protective film 112 are etched by anisotropic etching to form a pair of second protective layers 118a, 118b, a pair of first protective layers 112a, 112b, and third protective layers 120a, 120b that cover the sides of the pair of second protective layers 118a, 118b and the sides of the pair of conductive layers 114a, 114b (see Fig. 3(C)). .

[0119] By the anisotropic etching process here, electrodes 116a composed of the first protective layer 112a and the conductive layer 114a, and electrodes 116b composed of the first protective layer 112b and the conductive layer 114b are formed.

[0120] The anisotropic etching process etches the third protective film 120 and the first protective film 112 by a thickness corresponding to the film thicknesses of the third protective film 120 and the first protective film 112 in a direction substantially perpendicular to the substrate 102. In this embodiment, dry etching using a chlorine-based gas such as chlorine, boron chloride, silicon chloride, carbon tetrachloride, etc. is used to etch the third protective film 120 and the first protective film 112.

[0121] In addition, in the etching process of the first protective film 112, since the pair of second protective layers 113a, 113b are also exposed to the etching gas, a part of the surfaces of the pair of second protective layers 113a, 113b is also etched to form a pair of second protective layers 118a, 118b with a reduced film thickness. The pair of second protective layers 118a, 118b are the bariers of the pair of conductive layers 114a, 114b. ​​​​​​​​​​​​ Since it functions as the A layer, it disappears during the etching process of the first protective film 112 In order not to, it is necessary to select the materials, film thicknesses, or etching conditions of the pair of second protective layers 113a and 113b. Specifically, let the etching rate of the first protective film 112 be ER1, the film thickness be t1, the etching rate of the second protective layers 113a and 113b be ER2, and the film thickness be t 2. Then, it is necessary to satisfy t1 / ER1 < t2 / ER2.

[0122] In the etching processes of the third protective film 120 and the first protective film 112, the upper surfaces of the pair of conductive layers 1 14a and 114b are covered by the pair of second protective layers 118a and 118b, and the side surfaces of the pair of conductive layers 114a and 114b are covered by the pair of third protective layers 120a and 120b. Therefore, the pair of conductive layers 114a and 114 b are not exposed to the plasma used in the etching process, and the formation of compounds of the metal elements constituting the pair of conductive layers 114a and 114b by the plasma is prevented. Thus, even if the surface of the semiconductor layer 110 is exposed by the etching process here, the diffusion of the metal elements (or their compounds) constituting the pair of conductive layers 114a and 114b into the semiconductor layer 110 can be suppressed. As a result, it is possible to reduce the impurity concentration of the semiconductor layer 110.

[0123] Also, in the etching process of the first protective film 112, a part of the semiconductor layer 110 and / or a part of the insulating film 108 (specifically, the region exposed from the pair of first protective layers 112a and 112b) may be etched, and the film thickness of the region may decrease.

[0124] In addition, the metal elements constituting the conductive film 114 scattered by the etching treatment of the conductive film 114​​​​​​ (For example, copper) remains on the surface of the first protective film 112, there is a risk that the metal element will adhere to the surface of the semiconductor layer 110 during the etching process of the first protective film 112. Therefore, after forming the pair of first protective layers 112a and 112b, it is preferable to perform a cleaning process on the semiconductor layer 110 exposed from the pair of first protective layers 112a and 11 2b.

[0125] The cleaning process can be performed, for example, with an alkaline solution such as a TMAH (Tetramethylammonium Hydr oxide) solution, an acidic solution such as dilute hydrofluoric acid, oxalic acid, or phosphoric acid, or by plasma treatment (such as oxygen plasma treatment). Note that due to the cleaning process, a part of the semiconductor layer 110 exposed from the pair of first protective layers 112a and 112b may be etched, and the film thickness of the region may decrease.

[0126] Also, when an oxide semiconductor layer is applied as the semiconductor layer 110, after the cleaning process, the semiconductor layer 1 10 may be exposed to plasma generated in an oxidizing atmosphere to supply oxygen to the semiconductor layer 110. As the oxidizing atmosphere, there are atmospheres such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. Further, in the plasma treatment, exposing the semiconductor layer 110 to the plasma generated without applying a bias to the substrate 102 side is preferable because it is possible to supply oxygen to the semiconductor layer 110 without damaging it. Also, the plasma treatment can remove etching residue (for example, halogens such as fluorine and chlorine) of the semiconductor film that may remain on the surface of the semiconductor layer 11 0. Also, when the plasma treatment is performed while heating at 300 °C or higher, oxygen in the plasma combines with hydrogen contained in the semiconductor layer 110 to form water and desorb. 0. As a result, the contents of hydrogen and water contained in the semiconductor layer 110 can be reduced.

[0127] Here, note that plasma treatment is used as the cleaning treatment or as the subsequent oxygen supply treatment. Even in this case, the lower surfaces, upper surfaces, and side surfaces of the pair of conductive layers 114a and 114b are respectively covered by a pair of first protective layers 112a and 112b, a pair of second protective layers 118a and 118b, and a pair of third protective layers 120a and 120b. Therefore, the surfaces of the pair of conductive layers 114a and 114 b are not exposed to the plasma. Thus, the contamination of impurities into the semiconductor layer 110 is prevented.

[0128] Next, an insulating film 122 and an insulating film 124 are formed on the semiconductor layer 110, the pair of electrodes 116a and 116b, and the pair of second protective layers 118 a and 118b (see Fig. 3(D)).

[0129] The insulating film 122 and the insulating film 124 can be formed by the plasma CVD method or the sputtering method.

[0130] When forming the insulating film 122 and the insulating film 124 provided on the pair of electrodes 116a and 116b, the lower surfaces, upper surfaces, and side surfaces of the pair of conductive layers 114a and 114b containing copper, aluminum, gold, or silver are covered by the first protective layer to the third protective layer. Therefore, even when plasma is used when forming the insulating film 122 and / or the insulating film 124, the surfaces of the pair of conductive layers 1 14a and 114b are not exposed to the plasma. As a result, the formation of compounds (for example, metal oxides) generated by the reaction between the metal elements constituting the pair of conductive layers 114a and 114 b and the plasma is suppressed, and the metal elements Mixing into or diffusion into the semiconductor layer 110 can be reduced.

[0131] As the insulating film 122 and the insulating film 124, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film or the like can be used alone or in a stacked manner. However, when an oxide semiconductor layer is applied, as the insulating film 122 in contact with the semiconductor layer 110, when an oxide insulating film is formed, oxygen can be supplied to the oxide semiconductor layer by the oxide insulating film, which is preferable.

[0132] For example, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is held at 180°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower. A source gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 30 Pa or higher and 250 Pa or lower, more preferably 40 Pa or higher and 200 Pa or lower. High-frequency power is supplied to an electrode provided in the processing chamber under such conditions, and a silicon oxide film or a silicon oxynitride film may be formed. By forming a film under the above conditions, an oxide insulating film that releases oxygen can be formed.

[0133] Further, after forming the oxide insulating film that releases oxygen, without exposing to the atmosphere, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is held at 180°C or higher and 250°C or lower, more preferably 180°C or higher and 230°C or lower. A source gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. 0.17 W / cm 2 or more and 0.5 W / cm 2 or less, more preferably Preferably 0.26 W / cm 2 or more 0.35 W / cm 2 under the condition of supplying high-frequency power below a silicon oxide film or a silicon oxynitride film may be formed. By forming a film under this condition, the decomposition efficiency of the source gas in the plasma increases, oxygen radicals increase, and the oxidation of the source gas proceeds, so that the oxygen content in the formed silicon oxide film or silicon oxynitride film becomes more than the stoichiometric composition. Also, when the substrate temperature is the above temperature, since the binding force between silicon and oxygen is weak, a part of oxygen desorbs by heating. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric ratio and having a part of oxygen desorbed by heating can be formed . .

[0134] As the insulating film 124 provided on the insulating film 122, it is preferable to use a nitride insulating film . By providing a nitride insulating film as the insulating film 124, the diffusion of oxygen from the semiconductor layer 110 to the outside and the intrusion of hydrogen, water, etc. from the outside into the semiconductor layer 110 can be prevented. As the nitride insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film, etc. can be used

[0135] In addition, when forming a nitride insulating film by the plasma CVD method, the substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus is set to 300°C or higher and 400°C or lower, more preferably 320 °C or higher and 370°C or lower, which is preferable because a dense nitride insulating film can be formed .

[0136] In addition, when an oxide semiconductor layer is applied as the semiconductor layer 110, a heat treatment may be performed after the formation of the insulating film 122 and before the formation of the insulating film 124. The temperature of the heat treatment is typically​ It is set to be 150°C or higher and 300°C or lower, preferably 200°C or higher and 250°C or lower. This heat treatment can be performed in the same manner as the first heat treatment. By this heat treatment, a part of the oxygen contained in the insulating film 122 is moved to the semiconductor layer 110, and it is possible to reduce the oxygen vacancies contained in the oxide semiconductor used as the semiconductor layer 110. As a result, the amount of oxygen vacancies contained in the semiconductor layer 110 can be reduced.

[0137] When water, hydrogen, etc. are contained, if a heat treatment is performed after forming the insulating film 124 having a function of blocking water, hydrogen, etc., the water, hydrogen, etc. contained in the insulating film 122 may move to the semiconductor layer 110, and defects may occur in the semiconductor layer 110. However, by performing the heat treatment before forming the insulating film 124, it is possible to desorb the water, hydrogen, etc. contained in the insulating film 122 and reduce the variation in the electrical characteristics of the transistor 200 and suppress the variation in the threshold voltage.

[0138] In addition, by forming the insulating film 122 while heating the substrate 102, it is possible to move oxygen to the semiconductor layer 110 and reduce the oxygen vacancies contained in the semiconductor layer 110. Therefore, this heat treatment may not be performed.

[0139] Also, by setting the heat treatment temperature to 150°C or higher and 300°C or lower, preferably 200°C or higher and 250°C or lower, it is possible to suppress the diffusion of copper, aluminum, gold, silver, etc.

[0140] Also, when forming the pair of electrodes 116a and 116b, the semiconductor layer 110 is damaged by the etching of the pair of first protective layers 112a and 11 2b, and the back of the semiconductor layer 110 Oxygen deficiency may occur on the channel side. However, by applying an oxide insulating film containing more oxygen than the stoichiometric composition of the insulating film 122, the oxygen deficiency generated on the back channel side can be repaired by heat treatment. As a result, the defects contained in the semiconductor layer 110 can be reduced, so that the reliability of the transistor 200 can be improved. In addition, heat treatment may be performed after the formation of the insulating film 124. The temperature of the heat treatment is typically 150 °C or higher and 300 °C or lower, preferably 200 °C or higher and 250 °C or lower. The transistor 200 can be manufactured by the above steps. FIG. 4 shows a partially enlarged view of a cross section in the channel length direction of the electrode 116a included in the transistor of the present embodiment. FIGS. 4(A) to 4(E) are enlarged views of the electrode 116a and the surrounding components in the vicinity of the channel region. In FIG. 4, although the electrode 116a and its surroundings are enlarged, it is assumed that the electrode 116b and its surroundings have the same configuration.

[0141] In FIG. 4(A), a case where the third protective layer 120a covering a part of the upper surface of the first protective layer 112a, the side surface of the conductive layer 114a, and the side surface of the second protective layer 118a has a film thickness difference for each region is shown as an example. Specifically, in the third protective layer 120a, in the region 50 overlapping the second protective layer 118a, the film thickness is smaller than that in other regions (for example, the region in contact with the side surface of the second protective layer 118a). Also, the third protective layer 120a is formed such that the film thickness gradually increases as it approaches the channel region.

[0142]

[0143]

[0144] ​​​​​​​​​​​​​

[0145] In terms of the cross-sectional shape, the side surface of the conductive layer 114a is positioned inside the side surface of the second protective layer 118a (the width of the conductive layer 114 is shorter than the width of the second protective layer 118a). Therefore, in the process of forming the third protective film 120, it is difficult to form the third protective film 120 in the region overlapping with the second protective layer 118a protruding from the side surface of the conductive layer 114a. Thus, as shown in FIG. 4(A), the third protective layer 120a having a film thickness difference for each region may be formed. In terms of the cross-sectional shape, the side surface of the conductive layer 114a is positioned inside the side surface of the second protective layer 118a (the width of the conductive layer 114 is shorter than the width of the second protective layer 118a). Therefore, in the process of forming the third protective film 120, it is difficult to form the third protective film 120 in the region overlapping with the second protective layer 118a protruding from the side surface of the conductive layer 114a. Thus, as shown in FIG. 4(A), the third protective layer 120a having a film thickness difference for each region may be formed. In the process of forming the third protective film 120, it is difficult to form the third protective film 120 in the region overlapping with the second protective layer 118a protruding from the side surface of the conductive layer 114a. Thus, as shown in FIG. 4(A), the third protective layer 120a having a film thickness difference for each region may be formed. In the process of forming the third protective film 120, it is difficult to form the third protective film 120 in the region overlapping with the second protective layer 118a protruding from the side surface of the conductive layer 114a. Thus, as shown in FIG. 4(A), the third protective layer 120a having a film thickness difference for each region may be formed. In the process of forming the third protective film 120, it is difficult to form the third protective film 120 in the region overlapping with the second protective layer 118a protruding from the side surface of the conductive layer 114a. Thus, as shown in FIG. 4(A), the third protective layer 120a having a film thickness difference for each region may be formed.

[0146] FIG. 4(B) shows a case where the side surface of the conductive layer 114a has a curved surface. Depending on the etching conditions of the conductive film 114, the side surface of the conductive layer 114a to be processed may have a curved surface. When the side surface of the conductive layer 114a has a curved surface, the coverage of the third protective layer 120a provided in contact with the side surface can be enhanced. Depending on the etching conditions of the conductive film 114, the side surface of the conductive layer 114a to be processed may have a curved surface. When the side surface of the conductive layer 114a has a curved surface, the coverage of the third protective layer 120a provided in contact with the side surface can be enhanced. Depending on the etching conditions of the conductive film 114, the side surface of the conductive layer 114a to be processed may have a curved surface. When the side surface of the conductive layer 114a has a curved surface, the coverage of the third protective layer 120a provided in contact with the side surface can be enhanced. Depending on the etching conditions of the conductive film 114, the side surface of the conductive layer 114a to be processed may have a curved surface. When the side surface of the conductive layer 114a has a curved surface, the coverage of the third protective layer 120a provided in contact with the side surface can be enhanced.

[0147] FIGS. 4(C) and 4(D) show an example in the case where materials with different etching rates are used for the second protective layer 118a and the third protective layer 120a. In FIG. 4(C), a case where a material with an etching rate greater than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a. FIGS. 4(C) and 4(D) show an example in the case where materials with different etching rates are used for the second protective layer 118a and the third protective layer 120a. In FIG. 4(C), a case where a material with an etching rate greater than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a. In FIGS. 4(C) and 4(D), an example in the case where materials with different etching rates are used for the second protective layer 118a and the third protective layer 120a is shown. In FIG. 4(C), a case where a material with an etching rate greater than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a. In FIGS. 4(C) and 4(D), an example in the case where materials with different etching rates are used for the second protective layer 118a and the third protective layer 120a is shown. In FIG. 4(C), a case where a material with an etching rate greater than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a. In the configuration shown in FIG. 4(C), since the third protective layer 120a is more easily etched than the second protective layer 118a, the upper surface of the third protective layer 120a is located closer to the surface of the substrate 102 than the upper surface of the second protective layer 118a.

[0148] Also, in FIG. 4(D), a case where a material with an etching rate smaller than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(D), Also, in FIG. 4(D), a case where a material with an etching rate smaller than the etching rate of the second protective layer 118a is applied as the third protective layer 120a is shown. In the configuration shown in FIG. 4(D), In this case, since the third protective layer 120a is more difficult to etch than the second protective layer 118a, the upper surface of the second protective layer 118a is closer to the surface of the substrate 102 than the upper surface of the third protective layer 120a. is located closer.

[0149] In FIG. 4(E), an example is shown in which, in the cross-sectional shape, the upper end portion of the side surface of the conductive layer 114a coincides with the lower end portion of the side surface of the second protective layer 118a. With this configuration, in the third protective layer 120a, the side surface on the side facing the second protective layer 118a and the conductive layer 114a may have a curved surface. Since the side surface of the third protective layer 120a has a curved surface, the covering property of the insulating film 122 provided in contact with the third protective layer 120a can be enhanced.

[0150] As described above, the configuration shown in FIG. 4 can be used in appropriate combination with other configurations in this specification. .

[0151] The semiconductor device shown in this embodiment contains a low-resistance material such as copper, aluminum, gold, or silver as wiring, so that wiring delay can be suppressed even when a large-area substrate is applied. Therefore, it is possible to enhance the functionality of the semiconductor device.

[0152] In addition, the semiconductor device shown in this embodiment has a protective layer that functions as a barrier layer so as to cover the lower surface, upper surface, and side surface of the conductive layer containing the low-resistance material. As a result, the mixing and diffusion of impurities into the semiconductor layer in contact with the wiring including the conductive layer can be suppressed. Therefore, it is possible to provide a highly reliable semiconductor device in which fluctuations in the electrical characteristics of the transistor are suppressed. is possible.

[0153] ​​Furthermore, the semiconductor device shown in this embodiment can self-alignedly form a protective layer provided on the lower surface, upper surface, and side surface of a conductive layer containing a low-resistance material without adding the number of photomasks as compared with the case where no protective layer is provided. Therefore, a semiconductor device having good functions can be produced at low cost with high yield. Also, since there is no need for a margin considering the alignment accuracy due to an increase in the number of photomasks, it is also possible to fabricate transistors with a short channel length.

[0154] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with those shown in other embodiments.

[0155] (Embodiment 2) In this embodiment, a semiconductor device according to an aspect of the present invention having a configuration different from that of Embodiment 1 will be described. For parts having the same configuration as in Embodiment 1, since it is possible to refer to Embodiment 1, detailed description thereof will be omitted.

[0156] Transistors 230 included in the semiconductor device of this embodiment are shown in FIGS. 5(A) to 5(C). FIG. 5(A) is a plan view of transistor 230, FIG. 5(B) is a cross-sectional view taken along the dashed-dotted line X4 - Y4 in FIG. 5(A), and FIG. 5(C) is a cross-sectional view taken along the dashed-dotted line V7 - W7 in FIG. 5(A). In FIG. 5(A), for clarity, some of the components of transistor 230 (for example, insulating film 124, etc.) are omitted from the illustration.

[0157] The transistor 230 shown in FIG. 5 is a channel-etch type transistor, and includes a gate electrode 104 formed on a substrate 102, an insulating film 106 on the gate electrode 104, and an insulating film 10 ​ 8 and a semiconductor layer 110 overlapping with the gate electrode 104 via the insulating films 106 and 108 and a pair of electrodes 116a and 116b in contact with the semiconductor layer 110, and in contact with the upper surfaces of the pair of electrodes a pair of second protective layers 118a and 118b, and a part of the side surfaces of the pair of electrodes 116a and 116b a pair of third protective layers 120a and 120b in contact with, and an insulating film 122 provided on the pair of electrodes 116a and 116b an insulating film 124 on the insulating film 122, and a gate electrode 126 overlapping with the semiconductor layer 110 on the insulating film 124. It includes.

[0158] In the transistor 230 of the present embodiment, a case where an oxide semiconductor layer is used as the semiconductor layer 110 will be described as an example. will be described.

[0159] In the transistor 230, the insulating films 106 and 108 function as a first gate insulating film. Further, the insulating films 122 and 124 function as a second gate insulating film. function.

[0160] The transistor 230 is different from the transistor 200 in that it has a gate electrode 126 on the insulating film 124. Other configurations are the same as those in the first embodiment, and the same effects can be achieved. That is, the transistor 230 has a pair of first to third protective layers functioning as barrier layers so as to cover the lower surfaces, upper surfaces, and side surfaces of a pair of conductive layers 114a and 114b including a low-resistance material. Thereby, it is possible to suppress the mixing and diffusion of impurities into the semiconductor layer 110 in contact with the wiring including the pair of conductive layers 114a and 114b. Therefore, the transistor 230 is a highly reliable transistor with suppressed fluctuations in electrical characteristics. That is, the transistor 230 has a pair of first to third protective layers functioning as barrier layers so as to cover the lower surfaces, upper surfaces, and side surfaces of a pair of conductive layers 114a and 114b including a low-resistance material. Thereby, it is possible to suppress the mixing and diffusion of impurities into the semiconductor layer 110 in contact with the wiring including the pair of conductive layers 114a and 114b. Therefore, the transistor 230 has a pair of first to third protective layers functioning as barrier layers so as to cover the lower surfaces, upper surfaces, and side surfaces of a pair of conductive layers 114a and 114b including a low-resistance material. Thereby, it is possible to suppress the mixing and diffusion of impurities into the semiconductor layer 110 in contact with the wiring including the pair of conductive layers 114a and 114b. Therefore, the transistor 230 has a pair of first to third protective layers functioning as barrier layers so as to cover the lower surfaces, upper surfaces, and side surfaces of a pair of conductive layers 114a and 114b including a low-resistance material. Thereby, it is possible to suppress the mixing and diffusion of impurities into the semiconductor layer 110 in contact with the wiring including the pair of conductive layers 114a and 114b. Therefore, the transistor 230 is a highly reliable transistor with suppressed fluctuations in electrical characteristics.

[0161] Also, in the transistor 230, as shown in FIG. 5(A), the gate electrode 126 overlaps the side surface of the semiconductor layer 110 through the insulating film 122 and the insulating film 124.

[0162] Also, as shown in the cross-sectional view of FIG. 5(C), the insulating film 124, the insulating film 122, the insulating film 108, and the insulating film 106 have an opening 52 provided outside one of the side surfaces of the semiconductor layer 110 in the channel width direction. In the opening 52, the gate electrode 104 and the gate electrode 126 are connected to each other. In this case, the gate electrode 126 in the opening 52 includes a region on the semiconductor layer 110 and a region under the semiconductor layer 110. Also, the gate electrode 126 overlaps from one end to the other end of the semiconductor layer 110 in the channel width direction.

[0163] Note that in FIG. 5, the case where the opening is provided outside one of the side surfaces of the semiconductor layer 110 in the channel width direction is shown as an example, but the present embodiment is not limited to this, and openings may be formed outside both of the side surfaces of the semiconductor layer 110 in the channel width direction. In this case, the gate electrode 126 includes a region on the semiconductor layer 110 and a region under the semiconductor layer 110 in the opening.

[0164] As shown in FIG. 5(C), when the distance d3 in the channel width direction between the end of the gate electrode 126 and the end of the semiconductor layer 110 is equal to or greater than one times the total film thickness of the first gate insulating film (the insulating film 106 and the insulating film 108) with a film thickness t1 and the second gate insulating film (the insulating film 122 and the insulating film 124) with a film thickness t2, since the electric field formed by the gate electrode 126 affects the side surface of the semiconductor layer 110 or the end portion including the side surface and its vicinity, the generation of parasitic channels at the side surface or the end portion including the side surface and its vicinity can be suppressed. On the other hand, when the distance d3 is less than the film thickness t1 When it is 7.5 times or less the total film thickness including the film thickness t2, the area of the transistor can be reduced. This is possible.

[0165] The transistor 230 shown in this embodiment has a channel length of 0.5 μm or more and 6 μm or less, preferably more preferably more than 1 μm and 4 μm or less, still more preferably more than 1 μm and 3.5 μm or less and still more preferably more than 1 μm and 2.5 μm or less. Since the on-current of the transistor increases as the ratio (L / W) of the channel length to the channel width decreases, by reducing the channel length of the transistor 230 to about the above range, the on-current can be improved. This is possible.

[0166] Also, as shown in Embodiment 1, the pair of first to third protective layers covering the pair of conductive layers 114a and 114b can be formed self-alignedly, and since there is no need for a margin considering the alignment accuracy due to an increase in the number of photomasks, even a transistor having a short channel length in the above range can be manufactured with a high yield.

[0167] The semiconductor layer 110 included in the transistor 230 has a configuration in which the side surfaces in the channel length direction overlap with the pair of electrodes 116a and 116b, and one of the side surfaces in the channel width direction overlaps with the gate electrode 126. When the end portion of the semiconductor layer 110 is exposed to plasma by an etching process for processing the semiconductor layer 110 into an island shape, it easily reacts with chlorine radicals, fluorine radicals, etc. generated from the etching gas. When an oxide semiconductor layer is applied as the semiconductor layer 110, the metal element constituting the oxide semiconductor easily binds to the above radicals. Therefore, at the end portion of the island-shaped oxide semiconductor layer, oxygen that was bound to the metal element is likely to be desorbed. ​ Therefore, oxygen deficiency may be formed, and n-type formation may be likely. However, in the case of transistor 2 30, since the side surface of the semiconductor layer 110 overlaps with a pair of electrodes 116a and 116b and the gate electrode 126 (including the gate electrode 104 having the same potential as the gate electrode 126 ), by controlling the potential of the gate electrode 126, the electric field applied to the end portion can be controlled. Thus, even if an oxide semiconductor layer is applied as the semiconductor layer 110 and the end portion of the oxide semiconductor layer is n-type formed, the current that can flow between the pair of electrodes 116a and 116b through the n-type formed region can be controlled by the potential applied to the pair of gate electrodes. Specifically, when a potential is applied to the pair of gate electrodes such that the transistor 230 is in a non-conducting state,

[0168] the off-current flowing between the pair of electrodes 116a and 116b through the end portion can be reduced. Therefore, in the transistor 230, in order to obtain a large on-current, the channel length is shortened. As a result, even if the length between the pair of electrodes 116a and 116b at the end portion of the semiconductor layer 110 becomes short, the off-current can be reduced. That is, the transistor 230 can obtain a large on-current in the conducting state and can reduce the off-current in the non-conducting state. state. That is, the transistor 230 is a transistor that can obtain a large on-current in the conducting state and can reduce the off-current in the non-conducting state. state.

[0169] In addition, the transistor 230 has the gate electrode 104 and the gate electrode 126, and the gate electrode 104 and the gate electrode 126 are at the same potential, and by making the side surface of the semiconductor layer 110 in the channel width direction face the gate electrode 126, carriers are generated not only at the interface between the first gate insulating film and the second gate insulating film and the semiconductor layer 110, but also in the bulk of the semiconductor layer 110. at the interface between the semiconductor layer 110 and the first gate insulating film and the second gate insulating film, but also in the bulk of the semiconductor layer 110. flows, the amount of carrier movement in the transistor 230 increases. As a result, the on-current of the transistor 230 increases and the field-effect mobility increases. Typically, the field-effect mobility is 10 cm 2 / V·s or more, or 20 cm 2 / V·s or more. Note that the field-effect mobility here is not an approximate value of the mobility as a physical property value of the oxide semiconductor film, but is the field-effect mobility in the saturation region of the transistor.

[0170] Also, in the transistor 230, by having the gate electrode 104 and the gate electrode 126, each having a function of shielding an external electric field, charges such as charged particles existing between the substrate 102 and the gate electrode 10 4, and / or on the gate electrode 126 do not affect the semiconductor layer 110. As a result, the characteristics in a stress test (for example, a -GBT (Gate Bias-Temperature) stress test in which a negative potential is applied to the gate electrode) are suppressed from deteriorating, and the change in the turn-on voltage of the on-current at different drain voltages can be suppressed. The BT stress test is a type of acceleration test and can evaluate the characteristic changes (i.e., aging changes) of the transistor that occur over a long period of use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is an important index

[0171] for examining reliability. The smaller the amount of change in the threshold voltage before and after the BT stress test, the higher the reliability of the transistor can be said to be.

[0172]

[0172] Note that in the transistor 230, the gate electrode 126 uses a conductive film having translucency It is possible. The conductive film having translucency can be formed using conductive materials such as ITO, indium zinc oxide, indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, indium oxide containing titanium, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide, etc.

[0173] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0174] (Embodiment 3) In this embodiment, when an oxide semiconductor layer is applied as the semiconductor layer, a semiconductor device having a transistor capable of further reducing the defect amount of the oxide semiconductor layer will be described with reference to the drawings. The transistor described in this embodiment is different in that it has a multilayer film including a plurality of oxide semiconductor layers as compared with Embodiment 1 or Embodiment 2. Here, the details of the transistor will be described using the semiconductor device shown in FIG. 1 of Embodiment 1.

[0175] FIGS. 6(A) to 6(D) show a plan view and a cross-sectional view of a transistor 210 included in the semiconductor device.

[0176] FIG. 6(A) is a top view of the transistor 210, FIG. 6(B) is a cross-sectional view taken along the dashed-dotted line X2 - Y2 in FIG. 6(A), FIG. 6(C) is a cross-sectional view taken along the dashed-dotted line V3 - W3 in FIG. 6(A), and FIG. 6(D) is a cross-sectional view taken along the dashed-dotted line V4 - W4 in FIG. 6(A). In FIG. 6(A), for clarity, some of the components of the transistor 210 (for example, the insulating film 124, etc.) are omitted from the illustration. ​​​​​​​​​​​​​

[0177] The transistor 210 included in the semiconductor device shown in FIG. 6 has a laminated structure with a semiconductor layer 110 provided between an insulating film 108 and an insulating film 122 and is different from the transistor 200 shown in FIG. 1 in this respect. Other configurations are the same as those in FIG. 1, and the previous description can be referred to .

[0178] In the transistor 210 shown in this embodiment, an oxide semiconductor layer is used as the semiconductor layer 110 , and the semiconductor layer 110 has an oxide semiconductor layer 107 and an oxide semiconductor layer 109 . Further, in the transistor 210, a channel region is formed in the oxide semiconductor layer 107

[0179] The oxide semiconductor layer 109 is an oxide semiconductor layer composed of one or more of the metal elements constituting the oxide semiconductor layer 107 in which the channel region is formed. Therefore, interface scattering hardly occurs at the interface between the oxide semiconductor layer 10 7 and the oxide semiconductor layer 109. Accordingly, carrier movement is not inhibited at this interface, so that the field-effect mobility of the transistor is increased .

[0180] The oxide semiconductor layer applied to the oxide semiconductor layer 109 is formed of a metal oxide containing at least In or Zn , and typically is In-Ga oxide, In-Zn oxide, In-M- Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd), and the energy of the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor layer applied to the oxide semiconductor layer 107 . Typically, the difference between the energy of the lower end of the conduction band of the oxide semiconductor layer 109 and the energy of the lower end of the conduction band of the oxide semiconductor layer 107 is 0.05 eV or more, 0.07 eV or more . ​​​0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less That is, the electron affinity of the oxide semiconductor layer 109 and the The difference between the electron affinity of the semiconductor layer 107 and the electron affinity of the semiconductor layer 107 is 0.05 eV or more, 0.07 eV or more, 0.1 e V or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or is less than 0.4 eV.

[0181] When the oxide semiconductor layer 109 contains In, the carrier mobility (electron mobility) is increased. In addition, the oxide semiconductor layer 109 is preferably made of Al, Ga, Y, Zr, La, Ce, or the like. Or, by having Nd in a higher atomic ratio than In, the following effects may be obtained. (1) To increase the energy gap of the oxide semiconductor layer 109. (2) To increase the energy gap of the oxide semiconductor layer 109. (3) To reduce the diffusion of impurities from the outside. (4) To reduce the amount of acid Compared to the compound semiconductor layer 107, the insulating property is higher.

[0182] In addition, Ga, Y, Zr, La, Ce, and Nd are metal elements that have strong bonding strength with oxygen. Therefore, the oxide semiconductor layer 109 contains Ga, Y, Zr, La, Ce, or Nd more than In. By having a high atomic ratio, oxygen deficiency is less likely to occur.

[0183] When the oxide semiconductor layer 109 is an In-M-Zn oxide, the In, Zn and O are not included. The atomic ratio of M is preferably less than 50 atomic % for In and less than 50 atomic % for M. % or more, more preferably, In is less than 25 atomic % and M is 75 atomic % or more. c% or more.

[0184] Also, when the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are In-M-Zn oxide (M is , Ga, Y, Zr, La, Ce, or Nd), compared with the oxide semiconductor layer 107 , the atomic ratio of M (Ga, Y, Zr, La, Ce, or Nd) contained in the oxide semiconductor layer 109 is large. Typically, compared with the above atoms contained in the oxide semiconductor layer 107, it is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher in atomic ratio. .5 times or more, preferably 2 times or more, more preferably 3 times or more higher in atomic ratio.

[0185] Also, when the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd), for the oxide semiconductor layer 109, In :M:Zn = x1:y1:z1 [atomic ratio], and for the oxide semiconductor layer 107, In:M:Zn = x2:y2:z2 [atomic ratio], then y1 / x1 is larger than y2 / x2, preferably y1 / x1 is 1.5 times or more than y2 / x2. More preferably, y1 / x 1 is more than 2 times larger than y2 / x2, and even more preferably, y1 / x1 is more than 3 times larger than y2 / x2. At this time, in the oxide semiconductor layer, when y2 is equal to or greater than x2, it is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor layer. However, when y2 becomes 3 times or more of x2, the field effect mobility of the transistor using the oxide semiconductor layer decreases. Therefore, it is preferable that y2 is less than 3 times of x2. when y2 becomes 3 times or more of x2, the field effect mobility of the transistor using the oxide semiconductor layer decreases. Therefore, it is preferable that y2 is less than 3 times of x2. when y2 becomes 3 times or more of x2, the field effect mobility of the transistor using the oxide semiconductor layer decreases. Therefore, it is preferable that y2 is less than 3 times of x2.

[0186] When the oxide semiconductor layer 107 is In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the oxide semiconductor layer 107, when the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2 、 x2 / y2 is 1 / It is 3 or more and 6 or less, further 1 or more and 6 or less, and z2 / y2 is 1 / 3 or more and 6 or less, further preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, it becomes easy to form a CAAC-OS film, which will be described later, as the oxide semiconductor layer 107. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:1:1, In:M: Zn = 1:1:1.2, In:M:Zn = 3:1:2, etc.

[0187] When the oxide semiconductor layer 109 is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the oxide semiconductor layer 109, when the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1, 、 x1 / y1 < x2 / y2, and z1 / y1 is preferably 1 / 3 or more and 6 or less, further preferably 1 or more and 6 or less. By setting z1 / y1 to 1 or more and 6 or less, a C AAC-OS film is easily formed as the oxide semiconductor layer 109. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1: 3:6, In:M:Zn = 1:3:8, etc.

[0188] Note that the atomic ratios of the oxide semiconductor layer 107 and the oxide semiconductor layer 109 each include fluctuations of plus or minus 40% of the above atomic ratios as errors.

[0189] The thickness of the oxide semiconductor layer 109 is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less.

[0190] In the transistor 210, the oxide semiconductor layer 107 in which the channel region is formed and the insulating film 12​​ By having the oxide semiconductor layer 109 between the oxide semiconductor layer 107 and the insulating film 122, even if trap levels are formed due to impurities and defects, there is a gap between the trap levels and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210. and the oxide semiconductor layer 107. As a result, electrons flowing through the oxide semiconductor layer 107 are less likely to be trapped by the trap levels, making it possible to increase the on-current of the transistor and enhance the field-effect mobility. Also, when electrons are trapped by the trap levels, these electrons become negative fixed charges, causing the threshold voltage of the transistor to fluctuate. However, by having the oxide semiconductor layer 109, it is possible to reduce the trapping of electrons at the trap levels and reduce the fluctuation of the threshold voltage in the transistor 210.

[0191] In addition, since the oxide semiconductor layer 109 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor layer 107. Also, the oxide semiconductor layer 109 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiencies in the oxide semiconductor layer 107. In addition, since the oxide semiconductor layer 109 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor layer 107. Also, the oxide semiconductor layer 109 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiencies in the oxide semiconductor layer 107. In addition, since the oxide semiconductor layer 109 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor layer 107. Also, the oxide semiconductor layer 109 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiencies in the oxide semiconductor layer 107. In addition, since the oxide semiconductor layer 109 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor layer 107. Also, the oxide semiconductor layer 109 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiencies in the oxide semiconductor layer 107.

[0192] Note that the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are fabricated such that a continuous junction (here, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the films. That is, at the interface of each film, a laminated structure is formed such that there are no impurities that form defect levels such as trap centers and recombination centers. If impurities are mixed between the laminated oxide semiconductor layer 107 and the oxide semiconductor layer 109, Note that the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are fabricated such that a continuous junction (here, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the films. That is, at the interface of each film, a laminated structure is formed such that there are no impurities that form defect levels such as trap centers and recombination centers. If impurities are mixed between the laminated oxide semiconductor layer 107 and the oxide semiconductor layer 109, Note that the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are fabricated such that a continuous junction (here, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the films. That is, at the interface of each film, a laminated structure is formed such that there are no impurities that form defect levels such as trap centers and recombination centers. If impurities are mixed between the laminated oxide semiconductor layer 107 and the oxide semiconductor layer 109, Note that the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are fabricated such that a continuous junction (here, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the films. That is, at the interface of each film, a laminated structure is formed such that there are no impurities that form defect levels such as trap centers and recombination centers. If impurities are mixed between the laminated oxide semiconductor layer 107 and the oxide semiconductor layer 109, Note that the oxide semiconductor layer 107 and the oxide semiconductor layer 109 are fabricated such that a continuous junction (here, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed, rather than simply laminating the films. That is, at the interface of each film, a laminated structure is formed such that there are no impurities that form defect levels such as trap centers and recombination centers. If impurities are mixed between the laminated oxide semiconductor layer 107 and the oxide semiconductor layer 109, Then, the continuity of the energy band is lost, carriers are trapped at the interface, or they recombine and disappear. Recombine and disappear.

[0193] To form a continuous junction, it is necessary to continuously stack each film without exposing it to the atmosphere using a multi-chamber film deposition apparatus (sputtering apparatus) equipped with a load lock chamber. (Sputtering apparatus) without exposing it to the atmosphere. Each chamber in the sputtering apparatus should be evacuated to a high vacuum (pressure of about 5×10 Pa to 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water that would be -7 impurities for the oxide semiconductor layer as much as possible. -4 Preferably. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas, especially gas containing carbon or hydrogen, from flowing back into the chamber from the exhaust system. Preferably. Preferably.

[0194] Another configuration example of a transistor having a semiconductor layer including a stacked structure is shown in FIG. 7.

[0195] FIG. 7(A) is a top view of the transistor 220, FIG. 7(B) is a cross-sectional view taken along the dashed line X3 - Y3 in FIG. 7(A), FIG. 7(C) is a cross-sectional view taken along the dashed line V5 - W5 in FIG. 7(A), and FIG. 7(D) is a cross-sectional view taken along the dashed line V6 - W6 in FIG. 7(A). In FIG. 7(A), for clarity, some components of the transistor 220 (for example, the insulating film 124, etc.) are omitted from the illustration. In FIG. 7(A), for clarity, some components of the transistor 220 (for example, the insulating film 124, etc.) are omitted from the illustration.

[0196] The transistor 220 included in the semiconductor device shown in FIG. 7 has a semiconductor layer 110 provided between an insulating film 108 and an insulating film 122, and the semiconductor layer 110 includes an oxide semiconductor layer 105, an oxide semiconductor layer 107, and and an oxide semiconductor layer 107, and It is different from the transistor in FIG. 6 in that it has a stacked structure including an oxide semiconductor layer 109. Other configurations are the same as those in FIG. 6, and the previous description can be referred to.

[0197] In the transistor 220, an oxide semiconductor layer 105, an oxide semiconductor layer 107, and an oxide semiconductor layer 109 are sequentially stacked on the insulating film 108. Further, in the transistor 220, a channel region is formed in the oxide semiconductor layer 107.

[0198] For the oxide semiconductor layer applied to the oxide semiconductor layer 105, the same materials and formation methods as those of the oxide semiconductor layer 109 can be appropriately used.

[0199] The oxide semiconductor layer 105 and the oxide semiconductor layer 109 sandwiching the oxide semiconductor layer 107 in which the channel region is formed are each preferably thinner than the oxide semiconductor layer 107. By setting the thicknesses of the oxide semiconductor layer 105 and the oxide semiconductor layer 109 to be 1 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less, it is possible to reduce the variation amount of the threshold voltage of the transistor.

[0200] In the transistor 220, an oxide semiconductor layer 105 is provided between the insulating film 108 and the oxide semiconductor layer 107, and an oxide semiconductor layer 109 is provided between the oxide semiconductor layer 107 and the insulating film 122. Therefore, the concentration of silicon or carbon in the vicinity of the interface of the oxide semiconductor layer 107 can be reduced.

[0201] The transistor according to the present embodiment having such a structure has extremely few defects in the multilayer film including the oxide semiconductor layer in which the channel region is formed, so the electrical characteristics of the transistor ​​​It is possible to improve, typically by increasing the on-current and improving the field-effect mobility. This is possible. Also, in a BT stress test and a photo BT stress test, which are examples of stress tests, the amount of variation in the threshold voltage is small and the reliability is high.

[0202] <Transistor band structure> Next, the band structure of the stacked structure included in the transistor 210 shown in FIG. 6 and the stacked structure included in the transistor 220 shown in FIG. 7 will be described with reference to FIG. 8.

[0203] Here, as an example, an In-Ga-Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor layer 107, and an In-Ga-Zn oxide having an energy gap of 3.5 eV is used as the oxide semiconductor layer 109. The energy gap was measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON's UT-300). The energy difference between the vacuum level and the upper end of the valence band of the oxide semiconductor layer 107 and the oxide semiconductor layer 109 (also referred to as the ionization potential) was 8 eV and 8.2 eV, respectively. Incidentally, the energy difference between the vacuum level and the upper end of the valence band was measured using an ultraviolet photoelectron spectroscopy (UPS)

[0204] apparatus (P HI's VersaProbe). Therefore, the energy difference between the vacuum level and the lower end of the conduction band of the oxide semiconductor layer 107 and the oxide semiconductor layer 109 (also referred to as the electron affinity) was 4.85 eV and 4.7 eV, respectively.

[0205]

[0206]

[0206] ​FIG. 8(A) schematically shows a part of the band structure of the stacked structure included in the transistor 210. Here, the insulating film 108 and the insulating film 122 are silicon oxide films, and the case where the semiconductor layer 1 10 is provided in contact with the silicon oxide film will be described. Note that EcI1 shown in FIG. 8(A) represents the energy at the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy at the lower end of the conduction band of the oxide semiconductor layer 1 07, EcS2 represents the energy at the lower end of the conduction band of the oxide semiconductor layer 109, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating film 108, and EcI2 corresponds to the insulating film 122.

[0207] As shown in FIG. 8(A), in the oxide semiconductor layer 107 and the oxide semiconductor layer 109, the energy at the lower end of the conduction band changes smoothly. In other words, it can also be said that it changes continuously. This is because the oxide semiconductor layer 107 and the oxide semiconductor layer 109 contain common elements, and oxygen moves mutually between the oxide semiconductor layer 107 and the oxide semiconductor layer 109, so that a mixed layer is formed.

[0208] From FIG. 8(A), the energy EcS1 at the lower end of the conduction band of the oxide semiconductor layer 107 of the semiconductor layer 110 becomes a well, and in the transistor using the semiconductor layer 110 of the stacked structure, it can be seen that the channel region is formed in the oxide semiconductor layer 107.

[0209] As shown in FIG. 8(A), although trap levels may be formed near the interface between the oxide semiconductor layer 109 and the insulating film 122 due to impurities and defects, since the oxide semiconductor layer 109 is provided, the oxide semiconductor layer 107 and the trap levels can be separated from each other. ​ It can be cut. However, when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor layer 10 7 may reach the trap level across the energy difference. When electrons are trapped at the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable. is captured, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable. value voltage shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable. difference is set to 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable. value voltage is reduced, and stable electrical characteristics are obtained, which is preferable.

[0210] FIG. 8(B) schematically shows a part of the band structure of the stacked structure included in the transistor 220. Here, the insulating film 108 and the insulating film 122 are silicon oxide films, and the case where the semiconductor layer 1 10 is provided in contact with the silicon oxide film will be described. Note that EcI1 shown in FIG. 8(B) represents the energy of the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 1 07, EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 109, EcS3 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 105, and EcI2 represents the energy of the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating film 07, EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 109, EcS3 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 105, and EcS3 represents the energy of the lower end of the conduction band of the oxide semiconductor layer 105. EcI2 represents the energy of the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating film 108, and EcI2 corresponds to the insulating film 122.

[0211] As shown in FIG. 8(B), in the oxide semiconductor layer 105, the oxide semiconductor layer 107, and the oxide semiconductor layer 109, the energy of the lower end of the conduction band changes gently. In other words, it can be said that it changes continuously. This is because the oxide semiconductor layer 105, the oxide semiconductor layer 107, and the oxide semiconductor layer 109 contain common elements, and oxygen is present in the stacked structure. 7 may reach the trap level across the energy difference. When electrons are trapped at the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is preferable. 107, and the oxide semiconductor layer 109 contain common elements, and oxygen is present in the stacked structure. It can be said that this is because a mixed layer is formed by moving relative to each other.

[0212] From FIG. 8(B), the energy EcS1 at the lower end of the conduction band of the oxide semiconductor layer 107 becomes a well (well door), and it can be seen that in the transistor 220, the channel region is formed in the oxide semiconductor layer 107. It can be seen that it is formed.

[0213] Note that although trap levels may be formed near the interfaces between the semiconductor layer 110 and the insulating films 108 and / or 122 due to impurities and defects, as shown in FIG. 8(B), the provision of the oxide semiconductor layers 105 and 109 allows the oxide semiconductor layer 107 and the trap levels to be separated from each other. However, when the energy difference between EcS1 and EcS2 and the energy difference between Ec S1 and EcS3 are small, electrons in the oxide semiconductor layer 107 may reach the trap levels across the energy difference. Therefore, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, resulting in stable electrical characteristics, which is preferable. electrical characteristics, which is preferable. electrical characteristics, which is preferable. electrical characteristics, which is preferable.

[0214] Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments. and used in appropriate combination.

[0215] (Embodiment 4) In this embodiment, in the transistor included in the semiconductor device described in the above embodiment, when an oxide semiconductor film is used as the semiconductor film, one aspect applicable to the oxide semiconductor film will be described.

[0216] In the following description, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, " perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, in this specification, when the crystal is trigonal crystal or rhombohedral crystal, it is expressed as a hexagonal crystal system.

[0217] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Non The single crystal oxide semiconductor film refers to a CAAC-OS film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semi conductor film, an amorphous oxide semiconductor film, etc.

[0218] <CAAC-OS film> First, the CAAC-OS film will be described.

[0219] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction.

[0220] By observing the bright field image and the composite analysis image of the diffraction pattern (also referred to as a high resolution TEM image) of the CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of crystal parts can be confirmed. On the one hand, the boundaries between the clear crystal parts, that is, the crystal grain boundaries (also referred to as grain boundaries ), cannot be confirmed by the high resolution TEM image. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to crystal grain boundaries. When observing the high resolution TEM image of the cross section of the CAAC-OS film from a direction roughly parallel to the sample surface,

[0221] it is possible to observe , in the crystalline part, it can be confirmed that metal atoms are arranged in layers. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0222] On the other hand, when observing the high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface , it can be confirmed that in the crystalline part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline parts.

[0223] Fig. 19(A) is a high-resolution TEM image of the cross-section of the CAAC-OS film. Also, Fig. 19(B ) is a high-resolution TEM image of the cross-section obtained by further magnifying Fig. 19(A), and the atomic arrangement is highlighted for easy understanding.

[0224] Fig. 19(C) is a local Fourier transform image of the region (diameter: about 4n m) surrounded by a circle between A-O-A' in Fig. 19(A). From Fig. 19(C), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between A-O and O-A', it is suggested that they are in different gray levels. Moreover, it can be seen that between A-O, the angle of the c-axis changes continuously little by little, such as 14.3°, 16.6 °, 26.4°. Similarly, between O-A', it can be seen that the angle of the c-axis changes continuously little by little, such as -18.3°, -17.6°, -15.9°.

[0225] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, with respect to the upper surface of the CAAC-OS film, for example, electrons in the range of 1 nm or more and 30 nm or less When electron diffraction (also referred to as nano-beam electron diffraction) is performed using a sub-beam, spots are observed (see Fig. 20(A)).

[0226] From the high-resolution TEM image of the cross-section and the high-resolution TEM image of the plane, it can be seen that the crystalline part of the CAAC-OS film has orientation.

[0227] Most of the crystalline parts contained in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm . Therefore, the crystalline parts contained in the CAAC-OS film also include cases where they are sized to fit within a cube with a side length of less than 10 nm , less than 5 nm or less than 3 nm. However, when a plurality of crystalline parts contained in the CAAC-OS film are connected, it may form one large crystal region . For example, in the high-resolution TEM image of the plane, crystal regions of 2500 nm 2 or more , 5 μm 2 or more or 1000 μm 2 or more may be observed.

[0228] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device , for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4 , peaks may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the crystals of InGaZnO4 , it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface . .

[0229] On the other hand, for the CAAC-OS film, in-pl where X-rays are incident from a direction approximately perpendicular to the c-axis In the analysis by the ane method, a peak may appear around 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor film of InGaZnO4, if 2θ is fixed around 56° and the sample is rotated while analyzing (φ scan) with the normal vector of the sample surface as the axis (φ axis), six peaks attributed to crystal planes equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed

[0230] around 56°. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it can be seen that it has c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer

[0231] of the metal atoms arranged in layers confirmed by the high-resolution TEM observation of the cross-section described above is a plane parallel to the ab plane of the crystal. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented

[0232] in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. The ratio may increase. In addition, in the CAAC-OS film doped with impurities, the region where the impurities are doped deteriorates, and regions with different ratios of partially c-axis oriented crystal parts are formed. This may also occur.

[0233] In addition, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0234] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, deprive the oxide semiconductor film of oxygen, disturbing the atomic arrangement of the oxide semiconductor film and reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), and when contained inside the oxide semiconductor film, they become factors that disturb the atomic arrangement of the oxide semiconductor film and reduce the crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

[0235] In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen vacancies in the oxide semiconductor film may become carrier traps or carrier generation sources by capturing hydrogen. ​​​​​​

[0236] Having a low impurity concentration and a low density of defect levels (with few oxygen deficiencies) is referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have an electrical characteristic (also called normally-off) in which the threshold voltage becomes negative. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0237] Also, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0238] <Polycrystalline Oxide Semiconductor Film> Next, the polycrystalline oxide semiconductor film will be described.

[0239] In a high-resolution TEM image, crystal grains can be confirmed in the polycrystalline oxide semiconductor film. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, in a particle size of 2 nm or more and 30 0 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in a high-resolution TEM image in many cases. Also, in a high-resolution TEM image, the grain boundaries of the polycrystalline oxide semiconductor film can be confirmed. ​​​​​​​ There is a combination.

[0240] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientations are different between the plurality of crystal grains. There may be cases where the crystal orientations are different between the plurality of crystal grains. Also, when performing structural analysis on the polycrystalline oxide semiconductor film using an XRD apparatus, for example, in the out-of-plane method analysis of a polycrystalline oxide semiconductor film having InGaZnO4 crystals, peaks near 2θ of 31°, peaks near 2θ of 36°, or other peaks may appear. Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the grain boundaries of the polycrystalline oxide semiconductor film. Also, the grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film.

[0241] Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the grain boundaries of the polycrystalline oxide semiconductor film. Also, the grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film. The grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film. Therefore, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film. become a less reliable transistor.

[0242] <Microcrystalline Oxide Semiconductor Film> Next, the microcrystalline oxide semiconductor film will be described.

[0243] The microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed in a high-resolution TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. An oxide semiconductor film having nanocrystals (nc) that are crystals is referred to as an nc -OS (nanocrystalline Oxide Semiconductor) film. Also, in, for example, a high-resolution TEM image, the grain boundaries of the nc-OS film may not be clearly recognized.

[0244] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film. Accordingly, depending on the analysis method, there are cases where the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of the crystal part, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, when performing electron diffraction (also referred to as limited-field electron diffraction) on the nc-OS film using an electron beam having a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam having a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, there may be cases where a region with high luminance is observed so as to draw a circle (ring-shaped). Also, when performing nano-beam electron diffraction on the nc-OS film, there may be cases where a plurality of spots are observed within the ring-shaped region (see Fig. 20(B)).

[0245] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Its Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However, the nc-OS film shows no regularity in crystal orientation between different crystal parts. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0246] Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore, a transistor using the nc-OS film may have a high field-effect mobility. Also, since the nc-OS film has a higher density of defect levels than the CAAC-OS film, there may be many carrier traps. Therefore, a transistor using the nc-OS film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using the CAAC-O S film. However, since the nc-OS film can be formed even when it contains relatively many impurities, it is easier to form than the CAAC-OS film and may be suitably used depending on the application. Therefore, a semiconductor device having a transistor using the nc-OS film may be manufactured with high productivity.

[0247]

[0248] <Amorphous oxide semiconductor film> Next, the amorphous oxide semiconductor film will be described.

[0248] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0249] ​In the high-resolution TEM image, the crystalline part cannot be confirmed in the amorphous oxide semiconductor film.

[0250] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-p lane method analysis. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. For the amorphous oxide semiconductor film, when performing nano-beam electron diffraction, no spot is observed and a halo pattern is observed.

[0251] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. Also, the amorphous oxide semiconductor film is an oxide semiconductor film with a high density of defect levels.

[0252] An oxide semiconductor film with a high impurity concentration and a high density of defect levels is an oxide semiconductor film with many carrier traps and carrier generation sources.

[0253] Therefore, the carrier density of the amorphous oxide semiconductor film may be even higher than that of the nc-OS film. For this reason, a transistor using the amorphous oxide semiconductor film tends to have the electrical characteristics of a normally-on transistor. Therefore, it may be suitably used for a transistor that requires the electrical characteristics of a normally-on transistor. Since the amorphous oxide semiconductor film has a high density of defect levels, the number of carrier traps may increase. Therefore, a transistor using the amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. The amorphous oxide semiconductor film has a high density of defect levels, so the number of carrier traps may increase. Therefore, a transistor using the amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. Therefore, a transistor using the amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. Therefore, a transistor using the amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. Therefore, a transistor using the amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film.

[0254] <Single-crystalline oxide semiconductor film> Next, the single-crystalline oxide semiconductor film will be described.

[0255] The single-crystalline oxide semiconductor film is an oxide semiconductor film with a low impurity concentration and a low density of defect levels (few oxygen deficiencies). Therefore, the carrier density can be lowered. Thus, transistors using the single-crystalline oxide semiconductor film are less likely to have normally-on electrical characteristics. In addition, since the single-crystalline oxide semiconductor film has a low impurity concentration and a low density of defect levels, the number of carrier traps may be reduced. Therefore, transistors using the single-crystalline oxide semiconductor film have small fluctuations in electrical characteristics and are highly reliable transistors. Note that when the oxide semiconductor film has few defects, its density increases. In addition, when the oxide semiconductor film has high crystallinity, its density increases.

[0256] In addition, when the impurity concentration such as hydrogen in the oxide semiconductor film is low, its density increases. The single-crystalline oxide semiconductor film has a higher density than the CAAC-OS film. In addition, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. In addition, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. In addition, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film. Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film.

[0257] An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (amorphous-like OS: amorphous-like Oxide Semiconductor) film. The amorphous-like OS film has a void (also called a void) in a high-resolution TEM image. ide Semiconductor) film.

[0258] In the high-resolution TEM image, the amorphous-like OS film has a void (also called a void). ​う。) may be observed. Also, in the high-resolution TEM image, a region where the crystalline part can be clearly confirmed and a region where the crystalline part cannot be confirmed are present. amor phous-like OS films may crystallize and crystal growth may be observed due to a very small amount of electron irradiation during observation by TEM. On the other hand, for a high-quality nc-OS film crystallization due to a very small amount of electron irradiation during observation by TEM is hardly seen.

[0259] The measurement of the size of the crystalline part of amorphous-like OS films and nc-OS films can be performed using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell of the crystal of InGaZnO4 has three In-O layers and six Ga-Zn-O layers, for a total of nine layers stacked in a layered manner in the c-axis direction. Therefore, the distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value). From crystal structure analysis, its value is determined to be 0.29 nm. Therefore, focusing on the lattice fringes in the high-resolution TEM image at positions where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe is regarded as corresponding to the a-b plane of the crystal of InGaZnO4. The maximum length in the region where the lattice fringes are observed is taken as the size of the crystalline part of amorphous-like OS films and nc-OS films. Note that the size of the crystalline part is selectively evaluated for those of 0.8 nm or more.

[0260] Fig. 21 shows amorphous-like OS films and nc by a high-resolution TEM image This is an example of investigating the change in the average size of the crystalline parts (from 20 to 40 locations) of the -OS film. As shown in Fig. 21, it can be seen that the amorphous-like OS film has crystalline parts that grow larger according to the cumulative electron irradiation dose. Specifically, at the initial stage of observation by TEM, the crystalline parts with a size of about 1. 8 e - / nm 2 become about 2.6 nm in size when the cumulative irradiation dose reaches 4.2×10 . On the other hand, for the high-quality nc-OS film, 8 e - / nm 2 it can be seen that there is no change in the size of the crystalline parts regardless of the cumulative electron irradiation dose within the range until the cumulative electron irradiation dose reaches 4.2×10

[0261] Also, by linearly approximating the change in the size of the crystalline parts of the amorphous-like OS film and nc-OS film shown in Fig. 21 and extrapolating to the cumulative electron irradiation dose of 0 e - / nm 2 , it can be seen that the average size of the crystalline parts takes a positive value. Therefore, it can be seen that the crystalline parts of the amorphous-li ke OS film and nc-OS film exist before observation by TEM.

[0262] Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CA AC-OS film.

[0263] When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction.

[0264] Figure 20(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 2010, an optical system 2012 below the electron gun chamber 2010, a sample chamber 2014 below the optical system 2012, an optical system 2 016 below the sample chamber 2014, an observation chamber 2020 below the optical system 2016, a camera 2018 installed in the observation chamber 2020, and a film chamber 2022 below the observation chamber 2020. The camera 2 018 is installed facing the inside of the observation chamber 2020. Note that the film chamber 2022 may not be provided.

[0265] Also, Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 2010 are irradiated onto a substance 2028 disposed in the sample chamber 2014 through the optical system 2012. The electrons that have passed through the substance 2028 enter a fluorescent plate 2032 installed inside the observation chamber 2020 through the optical system 2016. In the fluorescent plate 2032, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of the incident electrons.

[0266] The camera 2018 is installed facing the fluorescent plate 2032 and can photograph the pattern that appears on the fluorescent plate 2032. The angle formed by the straight line passing through the center of the lens of the camera 2018 and the center of the fluorescent plate 20 32 and the upper surface of the fluorescent plate 2032 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 2018. However, if the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. ​​​​​​​This is also possible. There are cases where the camera 2018 may be installed in the film chamber 2022. For example, the camera 2018 may be installed in the film chamber 2022 so as to face the incident direction of the electrons 2024. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 2032. In the sample chamber 2014, a holder for fixing the substance 2028 as the sample is installed. The holder has a structure that allows electrons passing through the substance 2028 to pass through. The holder may have a function of moving the substance 2028 in the X-axis, Y-axis, Z-axis, etc., for example. The moving function of the holder may have an accuracy of moving within a range such as 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc.

[0267] These ranges may be set to the most appropriate ranges according to the structure of the substance 2028. Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described. For example, as shown in Fig. 20(D), by changing (scanning) the irradiation position of the electrons 2024, which are nano-beams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 2028 is a CAAC-OS film, a diffraction pattern as shown in Fig. 20(A) will be observed. Or, if the substance 2028 is an nc-OS film, a diffraction pattern as shown in Fig. 20(B) will be observed.

[0268]

[0269]

[0270] ​​​​​​​​​Incidentally, even if the substance 2028 is a CAAC-OS film, a diffraction pattern similar to that of the nc-OS film may be observed in part. Therefore, the quality of the CAAC-OS film can be represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also referred to as the CAAC conversion rate). For example, in the case of a high-quality CAAC-OS film, the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Note that the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate. In some cases, a similar diffraction pattern may be observed. Therefore, the quality of the CAAC-OS film can be represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also referred to as the CAAC conversion rate). That is, it may be possible to represent it by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also called the CAAC conversion rate). For example, in the case of a high-quality CAAC-OS film, the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. In the case of a good-quality CAAC-OS film, the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Note that the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate. The area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate.

[0271] As an example, for the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered) or after heat treatment at 450 °C in an oxygen-containing atmosphere, a transmission electron diffraction pattern was obtained while scanning. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the CAAC conversion rate was derived by converting the observed diffraction pattern into a still image every 0.5 seconds. Note that a nano-beam with a probe diameter of 1 nm was used as the electron beam. The same measurement was performed on 6 samples. The average value of the 6 samples was used for calculating the CAAC conversion rate. For the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered) or after heat treatment at 450 °C in an oxygen-containing atmosphere, a transmission electron diffraction pattern was obtained while scanning. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the CAAC conversion rate was derived by converting the observed diffraction pattern into a still image every 0.5 seconds. The diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the CAAC conversion rate was derived by converting the observed diffraction pattern into a still image every 0.5 seconds. The CAAC conversion rate was derived by converting the observed diffraction pattern into a still image every 0.5 seconds while scanning at a speed of 5 nm / second for 60 seconds. Note that a nano-beam with a probe diameter of 1 nm was used as the electron beam. The same measurement was performed on 6 samples. The average value of the 6 samples was used for calculating the CAAC conversion rate. The average value of the 6 samples was used for calculating the CAAC conversion rate.

[0272] The CAAC conversion rate of each sample is shown in Fig. 22(A). The CAAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (the non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation. The CAAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (the non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation. That is, it can be seen that by heat treatment at a high temperature (for example, 400 °C or higher), the non-CAAC ratio is low (the CAAC ratio becomes high). Also, in the heat treatment below 500 °C it can be seen that a CAAC-OS film having a high CAAC ratio can be obtained.

[0273] Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as the diffraction patterns of the nc-OS film. Also, in the measurement region, the amorphous oxide semiconductor film could not be confirmed. Therefore, it is suggested that by heat treatment, the region having the same structure as the nc-OS film rearranges under the influence of the structure of the adjacent region and becomes CAAC.

[0274] FIGS. 22(B) and 22(C) are high-resolution TEM images of the plane of the CAAC-O S film immediately after film formation and after heat treatment at 450 °C. By comparing FIG. 22(B) with FIG. 22(C) it can be seen that the CAAC-OS film after heat treatment at 450 °C has a more homogeneous film quality. That is, it can be seen that by heat treatment at a high temperature, the film quality of the CAAC-OS film is improved.

[0275] By using such a measurement method, it may be possible to analyze the structure of an oxide semiconductor film having a plurality of structures.

[0276] Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0277] (Embodiment 5) In this embodiment, a semiconductor device which is one aspect of the present invention will be described with reference to the drawings. Note that in this embodiment, a semiconductor device which is one aspect of the present invention will be described by taking a display device as an example. Also, in this embodiment, an oxide semiconductor layer is used as the semiconductor layer for description.

[0278] FIG. 9(A) shows an example of a semiconductor device. The semiconductor device shown in FIG. 9(A) includes a pixel portion 401 , a scanning line driving circuit 404, a signal line driving circuit 406, m scanning lines 407 that are each arranged in parallel or substantially parallel and whose potential is controlled by the scanning line driving circuit 404, and n signal lines 409 that are each arranged in parallel or substantially parallel and whose potential is controlled by the signal line driving circuit 406. Further, the pixel portion 401 includes a plurality of pixels 301 arranged in a matrix. Also, along the scanning lines 407, there are capacitance lines 415 that are each arranged in parallel or substantially parallel. Note that the capacitance lines 415 may be each arranged in parallel or substantially parallel along the signal lines 409. Further, the scanning line driving circuit 404 and the signal line driving circuit 406 may be collectively referred to as a driving circuit portion.

[0279] Each scanning line 407 is electrically connected to n pixels 301 arranged in any one row among the pixels 301 arranged in m rows and n columns in the pixel portion 401. Also, each signal line 409 is electrically connected to m pixels 301 arranged in any one column among the pixels 301 arranged in m rows and n columns. m and n are both integers of 1 or more. Also, each capacitance line 415 is electrically connected to n pixels 301 arranged in any one row among the pixels 301 arranged in m rows and n columns. Note that when the capacitance lines 415 are each arranged in parallel or substantially parallel along the signal lines 409, they are electrically connected to m pixels 301 arranged in any one column among the pixels 301 arranged in m rows and n columns.

[0280] ​​​​ FIG. 9(B) and FIG. 9(C) show circuit configurations that can be used for the pixel 301 of the display device shown in FIG. 9(A).

[0281] The pixel 301 shown in FIG. 9(B) includes a liquid crystal element 132, a transistor 131_1, and a capacitor element 133_1.

[0282] One potential of a pair of electrodes of the liquid crystal element 132 is appropriately set according to the specifications of the pixel 301. The liquid crystal element 132 has its alignment state set according to the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 132 included in each of the plurality of pixels 301. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 132 for each pixel 301 in each row.

[0283] For example, as driving methods of a display device including the liquid crystal element 132, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode may be used. In addition, as driving methods of the display device, in addition to the driving methods described above, an ECB (Electric ​​​​​​​​​​​​​Vertically Controlled Birefringence mode, PDLC ( Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, etc. However, it is not limited to this, and various types can be used as the liquid crystal element and its driving method.

[0284] In addition, a liquid crystal element may be configured from a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal exhibiting a blue phase has a short response speed of 1 msec or less and is optically isotropic, so alignment treatment is unnecessary and the viewing angle dependence is small.

[0285] In the pixel 301 at the m-th row and n-th column, one of the source electrode and the drain electrode of the transistor 131_1 is electrically connected to the signal line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. Also, the gate electrode of the transistor 131_1 is electrically connected to the scanning line GL _m. The transistor 131_1 has a function of controlling the writing of data of the data signal by being turned on or off.

[0286] One of the pair of electrodes of the capacitor element 133_1 is electrically connected to a wiring (hereinafter referred to as a capacitor line CL) to which a potential is supplied, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. Note that the value of the potential of the capacitor line CL is appropriately set according to the specifications of the pixel 301. The capacitor element 133_1 has a function as a holding capacitor for holding the written data.

[0287] ​For example, in the display device having the pixel 301 in FIG. 9(B), each pixel 301 in a row is sequentially selected by the scanning line driving circuit 404, and the transistor 131_1 is turned on to write data of the data signal.

[0288] The pixel 301 in which data has been written enters a holding state when the transistor 131_1 is turned off. By sequentially performing this for each row, an image can be displayed.

[0289] Also, the pixel 301 shown in FIG. 9(C) includes a transistor 131_2, a capacitive element 133_2, a transistor 134, and a light-emitting element 135.

[0290] One of the source electrode and the drain electrode of the transistor 131_2 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 131_2 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0291] The transistor 131_2 has a function of controlling the writing of the data signal by being turned on or off.

[0292] One of the pair of electrodes of the capacitive element 133_2 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL_a) to which a potential is supplied, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 131_2.

[0293] The capacitive element 133_2 has a function as a holding capacitor for holding the written data.

[0294] One of the source electrode and the drain electrode of the transistor 134 is electrically connected to the potential supply line VL_a​​​​​​​​ is connected. Further, the gate electrode of transistor 134 is electrically connected to the other of the source electrode and the drain electrode of transistor 131_2 in addition to the source electrode and the drain electrode of transistor 131_2.

[0295] One of the anode and the cathode of the light-emitting element 135 is electrically connected to the potential supply line VL_b and the other is electrically connected to the other of the source electrode and the drain electrode of transistor 134. are connected.

[0296] As the light-emitting element 135, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 135 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

[0297] Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other.

[0298] In the display device having the pixel 301 in FIG. 9(C), the scanning line driving circuit 404 sequentially selects the pixels 301 in each row, turns on transistor 131_2, and writes the data of the data signal.

[0299] The pixel 301 in which the data has been written becomes a holding state when transistor 131_2 is turned off. Further, according to the potential of the written data signal, the amount of current flowing between the source electrode and the drain electrode of transistor 134 is controlled, and the light-emitting element 135 emits light with a luminance corresponding to the amount of current flowing. By sequentially performing this for each row, an image can be displayed.

[0300] Next, a specific example of a liquid crystal display device using a liquid crystal element for the pixel 301 will be described. ​​​​Here, a top view of the pixel 301 shown in FIG. 9(B) is shown in FIG. 10. In FIG. 10, the counter electrode, the liquid crystal element, and the first protective layers 314d and 314e are omitted.

[0301] In FIG. 10, the conductive layer 304c that functions as a scanning line extends in a direction substantially orthogonal to the signal line (the left - right direction in the figure ). The conductive layer 313d that functions as a signal line extends in a direction substantially orthogonal to the scanning line (the up - down direction in the figure). The conductive layer 313f that functions as a capacitance line extends in a direction parallel to the signal line. The conductive layer 304c that functions as a scanning line is electrically connected to the scanning line driving circuit 404 (see FIG. 9(A)). The conductive layer 313d that functions as a signal line and the conductive layer 31 3f that functions as a capacitance line are electrically connected to the signal line driving circuit 406 (see FIG. 9(A)). The transistor 403 is provided in a region where the scanning line and the signal line intersect. The transistor 403 is composed of a conductive layer 304c that functions as a gate electrode, a gate insulating film (not shown in FIG. 10), a semiconductor layer 308b in which a channel region is formed on the gate insulating film, and conductive layers 313d and 313e that function as source electrodes and drain electrodes. The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight

[0302] The transistor 403 is provided in a region where the scanning line and the signal line intersect. The transistor 403 is composed of a conductive layer 304c that functions as a gate electrode, a gate insulating film (not shown in FIG. 10), a semiconductor layer 308b in which a channel region is formed on the gate insulating film, and conductive layers 313d and 313e that function as source electrodes and drain electrodes. The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight The conductive layer 304c also functions as a scanning line, and the region overlapping with the semiconductor layer 308b functions as the gate electrode of the transistor 403. The conductive layer 313d also functions as a signal line, and the region overlapping with the semiconductor layer 308b functions as the source electrode or drain electrode of the transistor 403. In FIG. 10, the scanning line has an end portion located outside the end portion of the semiconductor layer 308b in the top surface shape. Therefore, the scanning line is a light source such as a backlight functions as a light-shielding film that blocks light from irradiating the semiconductor layer 30 included in the transistor, and as a result, the semiconductor layer 30 can be prevented from being irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed.

[0303] Further, the conductive layer 313e is electrically connected to a conductive layer 320b having translucency that functions as a pixel electrode at the opening 362c.

[0304] The capacitor element 405 is connected to a conductive layer 313f that functions as a capacitor line at the opening 362. Further, the capacitor element 405 includes a conductive layer 308c formed on the gate insulating film, a conductive layer 320b having translucency that functions as a pixel electrode, and a dielectric film formed of a nitride insulating film provided on the transistor 403. The conductive layer 308c formed on the gate insulating film has translucency. That is, the capacitor element 405 has translucency. Since the capacitor element 405 has translucency in this way, the capacitor element 405 can be formed large (with a large area) within the pixel 301. Therefore, it is possible to increase the aperture ratio, typically to 55% or more, preferably 60% or more, and to obtain a semiconductor device with an increased charge capacitance. For example, in a semiconductor device with high resolution, such as a liquid crystal display device, the area of the pixel becomes small, and the area of the capacitor element also becomes small. For this reason, in a semiconductor device with high resolution, the charge capacitance accumulated in the capacitor element becomes small. However, since the capacitor element 405 shown in this embodiment has translucency, by providing the capacitor element in the pixel, it is possible to increase the aperture ratio while obtaining a sufficient charge capacitance in each pixel. Typically

[0305] A high-resolution semiconductor device with a pixel density of 200 ppi or more, and further 300 ppi or more can be preferably used.

[0306] In addition, the pixel 301 shown in FIG. 10 has a shape in which the side parallel to the conductive layer 313d functioning as a signal line is shorter than the side parallel to the conductive layer 304c functioning as a scanning line, and the conductive layer 313f functioning as a capacitance line extends in a direction parallel to the conductive layer 313d functioning as a signal line. As a result, since the area of the conductive layer 313f in the pixel 301 can be reduced, the aperture ratio can be increased. Further, since the conductive layer 313f functioning as a capacitance line is in contact with the directly conductive layer 308c without using a connection electrode, the aperture ratio can be further increased. In comparison, the side parallel to the conductive layer 304c functioning as a scanning line is longer, and the conductive layer 313f functioning as a capacitance line extends in a direction parallel to the conductive layer 313d functioning as a signal line. In addition, the conductive layer 313f functioning as a capacitance line extends in a direction parallel to the conductive layer 313d functioning as a signal line. As a result, the area of the conductive layer 313f in the pixel 301 can be reduced, so that the aperture ratio can be increased. In addition, since the conductive layer 313f functioning as a capacitance line is in contact with the directly conductive layer 308c without using a connection electrode, the aperture ratio can be further increased. In addition, since the conductive layer 313f functioning as a capacitance line is in contact with the directly conductive layer 308c without using a connection electrode, the aperture ratio can be further increased. Furthermore, the aperture ratio can be increased.

[0307] In addition, one aspect of the present invention can increase the aperture ratio even in a high-resolution display device, so that the light of a light source such as a backlight can be efficiently used, and the power consumption of the display device can be reduced. Therefore, the light of a light source such as a backlight can be efficiently used, and the power consumption of the display device can be reduced. The power consumption of the display device can be reduced.

[0308] Next, a cross-sectional view between the dashed-dotted line C-D in FIG. 10 is shown in FIG. 11. In FIG. 11, a cross-sectional view of a drive circuit portion (the top view is omitted) including a scanning line drive circuit 404 and a signal line drive circuit 406 is shown at A-B. In the present embodiment, as an example of a semiconductor device having a display function, a vertical electric field type liquid crystal display device will be described. In the present embodiment, a cross-sectional view of a drive circuit portion (the top view is omitted) including a scanning line drive circuit 404 and a signal line drive circuit 406 is shown at A-B. In the present embodiment, as an example of a semiconductor device having a display function, a vertical electric field type liquid crystal display device will be described. In the display device shown in the present embodiment, a liquid crystal element 322 is sandwiched between a pair of substrates (substrate 302 and substrate 342).

[0309] In the display device shown in the present embodiment, a liquid crystal element 322 is sandwiched between a pair of substrates (substrate 302 and substrate 342). The liquid crystal element 322 is sandwiched between the pair of substrates.

[0310] The liquid crystal element 322 includes a conductive layer 320b having translucency above the substrate 302, a film for controlling the orientation (hereinafter referred to as alignment films 323 and 352), a liquid crystal layer 321, and a conductive layer 350. The conductive layer 320b having translucency functions as one electrode of the liquid crystal element 322, and the conductive layer 350 functions as the other electrode of the liquid crystal element 322. As described above, a liquid crystal display device refers to a device having a liquid crystal element. The liquid crystal display device includes a drive circuit for driving a plurality of pixels and the like. Further, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, a backlight module, etc. disposed on another substrate, and may also be referred to as a liquid crystal module. In the drive circuit unit, a transistor 402 is constituted by a conductive layer 304a functioning as a gate electrode, insulating films 305 and 306 functioning as a gate insulating film, a semiconductor layer 308a in which a channel region is formed, conductive layers 313a, 313b functioning as source electrodes and drain electrodes, and first protective layers 314a, 314b. The semiconductor layer 308a is provided on the gate insulating film. Second protective layers 312a, 312b are provided on the upper surfaces of the conductive layers 313a, 313b, and third protective layers 324a, 324b are provided on the side surfaces. When the second protective layers 312a, 312b and / or the third protective layers 324a, 324b are formed of a conductive layer having translucency, the second protective layers 312a, 312b and / or the third protective layers 324a, 324b function as source electrodes and drain electrodes and constitute the transistor 402.

[0311] As described above, a liquid crystal display device refers to a device having a liquid crystal element. The liquid crystal display device includes a drive circuit for driving a plurality of pixels and the like. Further, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, a backlight module, etc. disposed on another substrate, and may also be referred to as a liquid crystal module.

[0312] In the drive circuit unit, a conductive layer 304a functioning as a gate electrode, an insulating film 305 functioning as a gate insulating film, an insulating film 306, a semiconductor layer 308a in which a channel region is formed, conductive layers 313a, 313b functioning as source electrodes and drain electrodes, and first protective layers 314a, 314b constitute a transistor 402. The semiconductor layer 308a is provided on the gate insulating film. Second protective layers 312a, 312b are provided on the upper surfaces of the conductive layers 313a, 313b, and third protective layers 324a, 324b are provided on the side surfaces. When the second protective layers 312a, 312b and / or the third protective layers 324a, 324b are formed of a conductive layer having translucency, the second protective layers 312a, 312b and / or the third protective layers 324a, 324b function as source electrodes and drain electrodes, and constitute the transistor 402.

[0313] ​​​In the pixel portion, a conductive layer 304c that functions as a gate electrode, an insulating film 305 and an insulating film 306 that function as a gate insulating film, and a semiconductor layer 308b in which a channel region is formed on the gate insulating film constitute a transistor 403 together with a conductive layer 313d, 313e that functions as a source electrode and a drain electrode, and first protective layers 314d, 314e. The semiconductor layer 308b is provided on the gate insulating film. Second protective layers 312d, 312g are provided on the upper surfaces of the conductive layers 313d, 313e, and third protective layers 324d, 324e are provided on the side surfaces. Insulating films 316 and 318 are provided as protective layers on the second protective layers 312d, 312g. When the second protective layers 312d, 312g and / or the third protective layers 324d, 324e are formed of a conductive film having translucency, the second protective layers 312d, 312g and / or the third protective layers 324d, 324e function as source electrodes and drain electrodes and constitute the transistor 403. In addition, a translucent conductive layer 320b that functions as a pixel electrode is connected to the conductive layer 313e at openings provided in the second protective layer 312g, the insulating film 316, and the insulating film 318. Furthermore, a capacitive element 405 is constituted by a conductive layer 308c having conductivity that functions as one electrode, an insulating film 318 that functions as a dielectric film, and a translucent conductive layer 320b that functions as the other electrode. The conductive layer 308c having conductivity is provided on the gate insulating film. In the drive circuit portion, a conductive layer 304 formed simultaneously with the conductive layers 304a and 304c

[0314]

[0315]

[0316] ​​​​​​​​​​b and the conductive layer 313 formed simultaneously with the conductive layers 313a, 313b, 313d, 313e c is the light-transmissive conductive layer 320 formed simultaneously with the light-transmissive conductive layer 320b is connected by a

[0317] The conductive layer 304b and the light-transmissive conductive layer 320a are connected at the openings provided in the insulating film 306 and the insulating film 316. Also, the conductive layer 313c and the light-transmissive conductive layer 32 0a are connected at the openings provided in the second protective layer 312f, the insulating film 316, and the insulating film 318. Note that the side surface of the conductive layer 313c is covered with the third protective layer 324c .

[0318] Here, the components of the display device shown in FIG. 11 will be described below.

[0319] On the substrate 302, conductive layers 304a, 304b, and 304c are formed. The conductive layer 30 4a functions as a gate electrode of a transistor in the drive circuit section. Also, the conductive layer 3 04c is formed in the pixel section 401 and functions as a gate electrode of a transistor in the pixel section . Also, the conductive layer 304b is formed in the scanning line drive circuit 404 and is connected to the conductive layer 313c .

[0320] As the substrate 302, the material of the substrate 102 shown in Embodiment 1 can be appropriately used.

[0321] As the conductive layers 304a, 304b, and 304c, the material and manufacturing method of the gate electrode 104 shown in Embodiment 1 can be appropriately used.

[0322] On the substrate 302 and the conductive layers 304a, 304c, 304b, insulating films 305, 3 ​​​06 is formed. The insulating films 305 and 306 function as gate insulating films for the transistors in the drive circuit section and the gate insulating films for the transistors in the pixel section 401.

[0323] As the insulating film 305, it is preferable to use the nitride insulating film described for the insulating film 106 shown in Embodiment 1. As the insulating film 306, it is preferable to use the oxide insulating film described for the insulating film 108 shown in Embodiment 1.

[0324] On the insulating film 306, semiconductor layers 308a, 308b, and a conductive layer 308c are formed. The semiconductor layer 308a is formed at a position overlapping with the conductive layer 304a and functions as the channel region of the transistor in the drive circuit section. Also, the semiconductor layer 308b is formed at a position overlapping with the conductive layer 304c and functions as the channel region of the transistor in the pixel section. The conductive layer 308c functions as one electrode of the capacitor element 405.

[0325] For the semiconductor layers 308a, 308b, and the conductive layer 308c, the materials and manufacturing methods of the semiconductor layer 110 shown in Embodiment 1 can be appropriately used.

[0326] The conductive layer 308c is a layer having the same metal elements as the semiconductor layers 308a and 308b, and is characterized by containing impurities. As the impurities, there is hydrogen. In addition, instead of hydrogen, impurities such as boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc. may be contained.

[0327] The semiconductor layers 308a, 308b, and the conductive layer 308c are all on the gate insulating film. are formed, but the impurity concentrations are different. Specifically, compared with the semiconductor layers 308a and 308b the impurity concentration of the conductive layer 308c is high. For example, the hydrogen concentration contained in the semiconductor layers 308a and 308 b is 5×10 19 atoms / cm 3 less than, preferably 5×10 1 8 atoms / cm 3 less than, preferably 1×10 18 atoms / cm 3 or less, more preferably preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less, and the hydrogen concentration contained in the conductive layer 308c is 8×10 19 a toms / cm 3 or more, preferably 1×10 20 atoms / cm 3 or more, more preferably is 5×10 20 atoms / cm 3 or more. Also, compared with the semiconductor layers 308a and 308b the hydrogen concentration contained in the conductive layer 308c is 2 times, preferably 10 times or more more.

[0328] Also, the conductive layer 308c has a lower resistivity than the semiconductor layers 308a and 308b. The resistivity of the conductive layer 308c is 1×10 - 8 times or more and 1×10 -1 times or less of the resistivity of the semiconductor layers 308a and 308b, preferably, typically 1×10 -3 Ωcm or more 1×10 4 Ωcm less than, even more preferably, the resistivity is 1×10 -3 Ωcm or more and 1×10 - 1 It is preferably less than Ωcm.

[0329] The semiconductor layers 308a and 308b are in contact with a film formed of a material capable of improving the interface characteristics with the semiconductor layer, such as the insulating film 306 and the insulating film 316. Therefore, since the semiconductor layers 308a and 308b are in contact with a film formed of a material capable of improving the characteristics, the semiconductor layers 308a , 308b function as semiconductors, and the transistor having the semiconductor layers 308a and 308b has excellent electrical characteristics.

[0330] On the other hand, the conductive layer 308c is in contact with the insulating film 318 at the opening 362 (see FIG. 14(A)). The insulating film 318 is a film formed of a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the semiconductor layer, and further contains hydrogen. Therefore, when hydrogen in the insulating film 318 diffuses into the semiconductor layer formed simultaneously with the semiconductor layers 308a and 308b, hydrogen combines with oxygen in the semiconductor layer to generate carriers, electrons. In addition, when the insulating film 318 is formed by plasma CVD method or sputtering method, the semiconductor layers 308a and 308b are exposed to plasma and oxygen deficiency is generated. When hydrogen contained in the insulating film 318 enters the oxygen deficiency, carriers, electrons, are generated. As a result, the conductivity of the semiconductor layer increases and it becomes the conductive layer 308c. That is, the conductive layer 308c can also be said to be an oxide semiconductor layer with high conductivity. Also, the conductive layer 308c can be said to be a metal oxide film with high conductivity.

[0331] However, one aspect of the embodiment of the present invention is not limited to this, and the conductive layer 308c may not be in contact with the insulating film 318 in some cases.

[0332] ​​​​​​ In addition, in one aspect of the embodiment of the present invention, without being limited thereto, the conductive layer 308c may be formed in a process separate from the semiconductor layer 308a or 308b, depending on the case. In that case, the conductive layer 308c may have a different material from the semiconductor layers 308a and 308b. For example, the conductive layer 308c may contain indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide containing silicon oxide, or the like. ium zinc oxide, indium tin oxide containing silicon oxide, or the like. It may be formed using, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide containing silicon oxide, or the like.

[0333] The semiconductor device shown in this embodiment forms an electrode that also serves as one of the electrodes of the capacitor element simultaneously with the semiconductor layer of the transistor. Further, a light-transmissive conductive film that functions as a pixel electrode is used as the other electrode of the capacitor element. For these reasons, in order to form the capacitor element, a step of newly forming a conductive film is unnecessary, and the manufacturing process of the semiconductor device can be reduced. In addition, since the pair of electrodes has light-transmittance, the capacitor element has light-transmittance. As a result, while increasing the occupied area of the capacitor element, the aperture ratio of the pixel can be increased.

[0334] The first protective layers 314a, 314b, 314c, 314d, 314e can appropriately use the materials and manufacturing methods of the first protective layers 112a, 112b shown in Embodiment 1.

[0335] The conductive layers 313a, 313b, 313c, 313d, 313e can appropriately use the materials and manufacturing methods of the conductive layers 114a, 114b that constitute the pair of electrodes 116a, 116b shown in Embodiment 1. ​​​​​​​​​

[0336] The second protective layers 312a, 312b, 312f, 312d, 312g can appropriately use the materials and manufacturing methods of the second protective layers 118a, 118b shown in Embodiment 1.

[0337] The third protective layers 324a, 324b, 324c, 324d, 324e can appropriately use the materials and manufacturing methods of the third protective layers 120a, 120b shown in Embodiment 1.

[0338] On the insulating film 306, semiconductor layers 308a, 308b, a conductive layer 308c, the first protective layers 314a, 314b, 314c, 314d, 314e, conductive layers 313a, 313b, 31 3c, 313d, 313e, the second protective layers 312a, 312b, 312f, 312d, 3 12g, and the third protective layers 324a, 324b, 324c, 324d, 324e, an insulating film 316 and an insulating film 318 are formed. The insulating film 316 is preferably made of a material capable of improving the interface characteristics with the semiconductor layers 308a, 308b, and at least the same materials and manufacturing methods as the oxide insulating film shown in Embodiment 1 can be appropriately used.

[0339] The insulating film 318, similar to the insulating film 305, preferably uses a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the semiconductor layer. Silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. nitride insulating films can be appropriately used. The thickness of the insulating film 318 is 30 nm or more and 200 nm or less, preferably 50 nm or more and 150 nm or less. The insulating film 318 can be formed by appropriately using a sputtering method, a CVD method, etc.

[0340] In addition, conductive layers 320a and 320b having translucency are formed on the insulating film 318. The conductive layer 320a having translucency is electrically connected to the conductive layer 313a at the opening 364a (see Fig. 15(A)), and is electrically connected to the conductive layer 313c at the opening 364b (see Fig. 15(A)). That is, it functions as a connecting electrode connecting the conductive layer 304a and the conductive layer 313c. The conductive layer 320b having translucency is electrically connected to the conductive layer 313e at the opening 364c (see Fig. 15(A)), and functions as a pixel electrode of a pixel. In addition, the conductive layer 320b having translucency can function as one of a pair of electrodes of a capacitive element.

[0341] To form a connection structure in which the conductive layer 304a and the conductive layer 313c are in direct contact, it is necessary to perform patterning to form openings in the insulating films 305 and 306 and form a mask before forming the conductive layer 313c. However, in the connection structure of Fig. 11, such a photomask is unnecessary. However, as shown in Fig. 11, by connecting the conductive layer 304a and the conductive layer 313c with the conductive layer 320a having translucency, it becomes unnecessary to fabricate a connection portion where the conductive layer 304a and the conductive layer 313c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device.

[0342] Examples of the conductive layers 320a and 320b having translucency include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, and silicon oxide. ​​​​​​​​​​​​​​A conductive material having translucency such as indium tin oxide containing silicon can be used.

[0343] Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, on the colored film 346 An adjacent light-shielding film 344 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 does not necessarily have to be provided. For example, when the display device is black and white, etc., a configuration in which the colored film 346 is not provided may be adopted.

[0344] The colored film 346 may be a colored film that transmits light in a specific wavelength band. For example, a red (R) color filter that transmits light in the red wavelength band, a green (G) color filter that transmits light in the green wavelength band, a blue (B) color filter that transmits light in the blue wavelength band, etc. can be used.

[0345] The light-shielding film 344 only needs to have a function of blocking light in a specific wavelength band, and a metal film or an organic insulating film containing a black pigment or the like can be used.

[0346] Also, an insulating film 348 is formed on the colored film 346. The insulating film 348 has a function as a planarization layer or a function of suppressing the diffusion of impurities that the colored film 346 may contain to the liquid crystal element side.

[0347] Also, a conductive layer 350 is formed on the insulating film 348. The conductive layer 350 functions as the other of a pair of electrodes that the liquid crystal element in the pixel portion has. Note that on the translucent conductive layers 320a, 320b, and the conductive layer 350, an insulating film having a function as an alignment film is separately ​ It may be formed by a process.

[0348] Further, between the conductive layers 320a and 320b having translucency and the conductive layer 350, a liquid crystal layer 32 1 is formed. Also, the liquid crystal layer 321 is sealed between the substrate 30 2 and the substrate 342 using a sealing material (not shown). Note that the sealing material preferably has a configuration that contacts an inorganic material in order to suppress the entry of moisture or the like from the outside.

[0349] Further, a spacer for maintaining the thickness (also referred to as cell gap) of the liquid crystal layer 321 may be provided between the conductive layers 320a and 320b having translucency and the conductive layer 350.

[0350] A method for manufacturing an element portion provided on the substrate 302 shown in the semiconductor device shown in FIG. 11 will be described with reference to FIGS. 12 to 15.

[0351] First, the substrate 302 is prepared. Here, a glass substrate is used as the substrate 302.

[0352] Next, a conductive film is formed on the substrate 302, and by processing the conductive film into a desired shape, conductive layers 304a, 304b, and 304c are formed. Note that the formation of the conductive layers 304a, 304b, and 304c can be performed by forming a mask by first patterning in a desired region and etching a region not covered by the mask (see FIG. 12(A)).

[0353] Also, as the conductive layers 304a, 304b, and 304c, typically, they can be formed using a vapor deposition method, a CVD method, a sputtering method, a spin coating method, or the like.

[0354] Next, an insulating film 305 is formed on the substrate 302 and the conductive layers 304a, 304b, and 304c Next, an insulating film 306 is formed on the insulating film 305 (see Fig. 12(A)).

[0355] The insulating film 305 and the insulating film 306 can be formed by a sputtering method, a CVD method, or the like. Note that it is preferable to form the insulating film 305 and the insulating film 306 continuously in a vacuum to suppress the inclusion of impurities.

[0356] Next, a semiconductor film 307 is formed on the insulating film 306 (see Fig. 12(B)).

[0357] The semiconductor film 307 can be formed using a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

[0358] Next, by processing the semiconductor film 307 into a desired shape, island-shaped semiconductor layers 308a, 308b, and 308d are formed. Note that the formation of the semiconductor layers 308a, 308b, and 308d can be achieved by forming a mask by second patterning in a desired region and etching a region not covered by the mask. As the etching, dry etching, wet etching, or a combination of both can be used (see Fig. 12(C)).

[0359] Next, a first heat treatment may be performed. The first heat treatment uses the same conditions as the first heat treatment shown in Embodiment 1. By the first heat treatment, impurities such as hydrogen and water can be removed from the insulating film 306 and the semiconductor layers 308a, 308b, and 308d. Note that the first heat treatment may be performed before etching the semiconductor film.

[0360] Next, a first protective film 3 09, a conductive film 310, and a second protective film 311 are sequentially formed (see Fig. 13(A)).

[0361] The first protective film 309 and the conductive film 310 can be formed, for example, by using a sputtering method . Also, the second protective film 311 can be formed, for example, by using a CVD method, a sputtering ring method, or the like.

[0362] Next, by processing the second protective film 311 into a desired shape, second protective layers 312a, 31 2b, 312c, 312d, 312e are formed. Note that the formation of the second protective layers 312a, 312 b, 312c, 312d, 312e can be performed by forming a mask by a third patterning in a desired region and etching a region not covered by the mask. After that, the mask is removed (see Fig. 13(B)).

[0363] Next, by processing the conductive film 310 into a desired shape, conductive layers 313a, 313b, 313 c, 313d, 313e are formed. Here, the second protective layers 312a, 312b , 312c, 312d, 312e function as a mask, and the regions not covered by the mask are etched to form the conductive layers 313a, 313b, 313c, 313d, 313e.

[0364] Subsequently, a third protective film is formed (not shown) on the second protective layers 312a, 312b, 312c, 312d, 312e so as to cover the sides of the conductive layers 313a, 313b, 313c, 313d, 313e, and the third protective film and the first protective film 309 are processed by anisotropic etching to form third protective layers 324a, 324b, 324c, 324d, 324e and a first protective layer 324a, 324b, 324c, 324d, 324e and a first Form the protective layers 314a, 314b, 314c, 314d, 314e (see Fig. 13(C)) Note that by the anisotropic etching here, the surfaces of the second protective layers 312a, 312b, 312c, 312d, 312e are also etched simultaneously, and the film thickness becomes smaller.

[0365] The third protective film can be formed, for example, using the CVD method, the sputtering method, or the like. .

[0366] Next, an insulating film 315 is formed so as to cover the insulating film 306, the semiconductor layers 308a, 308b, 308d, the first protective layers 314a, 314b, 314c, 314d, 314e, the conductive layers 313a, 313b, 313c, 31 3d, 313e, the second protective layers 312a, 312b, 312c, 312d, 312e, and also the third protective layers 324a, 324b, 324c, 324d, 324e (see Fig. 14(A)).

[0367] As the insulating film 315, a configuration similar to the insulating film 122 shown in Embodiment 1 can be applied, and an oxide insulating film can be preferably applied.

[0368] Next, by processing the insulating film 315 into a desired shape, an insulating film 316 and an opening 362 are formed. Note that the formation of the insulating film 315 and the opening 362 is performed by forming a mask by a fourth patterning in a desired region and etching a region not covered by the mask. This can be done (see Fig. 14(B)).

[0369] Note that the opening 362 is formed so that the surface of the semiconductor layer 308d is exposed. As a method for forming the opening 36 2, for example, a dry etching method can be used. However, for the opening The method for forming the mouth portion 362 is not limited to this, and it may be a wet etching method, or a forming method combining a dry etching method and a wet etching method.

[0370] After that, a second heat treatment may be performed. A part of the oxygen contained in the insulating film 315 is moved to the semiconductor layers 308a and 308b, and it is possible to reduce the oxygen vacancies contained in the semiconductor layers 308a and 308b. As a result, the amount of oxygen vacancies contained in the semiconductor layers 308a and 308b can be reduced.

[0371] Next, an insulating film 317 is formed on the insulating film 316 and the semiconductor layer 308d (see Fig. 14(C)).

[0372] As the insulating film 317, it is preferable to use a material that prevents impurities from the outside, such as oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc., from diffusing into the multilayer film. Furthermore, it is preferable to contain hydrogen. Typically, an inorganic insulating material containing nitrogen, such as a nitride insulating film, can be used. As the insulating film 317, for example, it can be formed by using a CVD method, a sputtering method, or the like.

[0373] When the insulating film 317 is formed by using a CVD method, a sputtering method, or the like, the semiconductor layer 308d is exposed to plasma, and oxygen vacancies are generated in the semiconductor layer 308d. In addition, the insulating film 317 is a film formed of a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the semiconductor layer, and further contains hydrogen. For these reasons, when the hydrogen in the insulating film 317 diffuses into the semiconductor layer 308d, in the semiconductor layer 308d, hydrogen combines with oxygen vacancies, and carriers, electrons, are generated. Or, the hydrogen in the insulating film 317 diffuses into the semiconductor layer When diffusing into the semiconductor layer 308d, hydrogen combines with oxygen in the semiconductor layer 308d, and electrons, which are carriers, are generated. As a result, the semiconductor layer 308d becomes a layer 308c having high conductivity.

[0374] In addition, the insulating film 317 is preferably formed at a high temperature in order to enhance the blocking property. For example, it is preferably formed by heating at a temperature of 100°C or higher and lower than the distortion point of the substrate, more preferably 300°C or higher and lower than 400°C. When forming the film at a high temperature, oxygen may desorb from the semiconductor layers 308a and 308b, and a phenomenon in which the carrier concentration increases may occur. Therefore, the temperature is set so that such a phenomenon does not occur.

[0375] Before forming the insulating film 317, by exposing the semiconductor layer 308d to plasma containing a rare gas and hydrogen, oxygen vacancies are formed in the semiconductor layer 308d, and hydrogen can be added to the semiconductor layer 308d. As a result, electrons, which are carriers, can be further increased in the semiconductor layer 308d, and the conductivity of the layer 308c having conductivity can be further enhanced.

[0376] Next, by processing the insulating film 317, the second protective layers 312c and 312e into a desired shape, an insulating film 318, the second protective layers 312f and 312g, and openings 364a, 364b, and 364c are formed. The insulating film 318 and the openings 364a, 364b, and 364c can be formed by forming a mask by fifth patterning in a desired region and etching a region not covered by the mask (see Fig. 15(A)). When the protective layers 312c and 312e are formed of a conductive film having translucency, in this step, the protective layers 312c and 312e of No. 2 do not need to be etched.

[0377] Further, the opening 364a is formed so that the surface of the conductive layer 304a is exposed. Also, the opening 364b is formed so that the conductive layer 313c is exposed. Also, the opening 364c is formed so that the conductive layer 313e is exposed.

[0378] Note that as a method for forming the openings 364a, 364b, and 364c, for example, a dry etching method can be used. However, the method for forming the openings 364a, 364b, and 364c is not limited to this, and a wet etching method, or a method combining a dry etching method and a wet etching method may also be used.

[0379] Next, a conductive film 319 is formed on the insulating film 318 so as to cover the openings 364a, 364b, and 364c (see Fig. 15(B)).

[0380] As the conductive film 319, for example, it can be formed using a sputtering method.

[0381] Next, by processing the conductive film 319 into a desired shape, conductive layers 320a and 3 20b having translucency are formed. Note that the formation of the conductive layers 320a and 320b having translucency can be performed by forming a mask by sixth patterning in a desired region and etching the region not covered by the mask (see Fig. 15(C)).

[0382] In the above steps, a pixel portion and a drive circuit portion having transistors are formed on the substrate 302. It is possible. In the manufacturing process shown in this embodiment, the first to sixth patterning, that is, transistors and capacitive elements can be formed simultaneously with six masks. It is possible.

[0383] In this embodiment, hydrogen contained in the insulating film 318 is diffused into the semiconductor layer 308d to increase the conductivity of the semiconductor layer 308d. However, the semiconductor layers 308a and 308b are covered with a mask, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc. may be added to the semiconductor layer 308d to increase the conductivity of the semiconductor layer 308d. As a method of adding hydrogen, boron, phosphorus, tin, antimony, noble gas elements, etc. to the semiconductor layer 308d, there are an ion doping method, an ion implantation method, etc. On the other hand, as a method of adding an alkali metal, an alkaline earth metal, etc. to the semiconductor layer 308d, there is a method of applying a solution containing the impurity to the semiconductor layer 308d.

[0384] Next, the structure formed on the substrate 342 provided facing the substrate 302 will be described below.

[0385] First, the substrate 342 is prepared. As the substrate 342, the materials shown for the substrate 302 can be used. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (see Fig. 16(A)).

[0386] The light-shielding film 344 and the colored film 346 are formed at desired positions using various materials by printing, inkjet, an etching method using photolithography technology, etc.

[0387] Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see Fig. 16(B)).​​​​​​​​​​​ )

[0388] As the insulating film 348, for example, an organic insulating film such as an acrylic resin, an epoxy resin, or a polyimide can be used. By forming the insulating film 348, for example, diffusion of impurities contained in the colored film 346 to the liquid crystal layer 321 side can be suppressed. However, the insulating film 348 does not necessarily have to be provided, and a structure in which the insulating film 348 is not formed may be adopted.

[0389] Next, a conductive layer 350 is formed on the insulating film 348 (see FIG. 16(C)). As the conductive layer 350, the materials shown in the conductive film 319 can be used.

[0390] The structure formed on the substrate 342 in the above steps can be formed.

[0391] Next, alignment films 323 and 352 are formed on the substrate 302 and on the substrate 342, more specifically, on the insulating film 318 formed on the substrate 302, the conductive layers 320a and 320b having translucency, and on the conductive layer 350 formed on the substrate 342. The alignment films 323 and 352 can be formed using, for example, the rubbing method, the photo-alignment method, or the like. Thereafter, a liquid crystal layer 321 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 321, the dispensing method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used.

[0392] The display device shown in FIG. 11 can be manufactured through the above steps.

[0393] Note that this embodiment can be appropriately combined with other embodiments described in this specification. .

[0394] (Embodiment 6) In this embodiment, an electronic device capable of mounting a semiconductor device according to one aspect of the present invention will be described.

[0395] Examples of electronic devices to which a semiconductor device according to one aspect of the present invention is applied include, for example, a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a pachinko machine, and other large game machines. Specific examples of these electronic devices are shown in FIG. 17.

[0396] FIG. 17(A) shows an example of a television device. The television device 7100 has a display unit 7103 incorporated in a housing 7101. The display unit 7103 can display video, and a semiconductor device can be used for the display unit 7103. Also, here a configuration in which the housing 7101 is supported by a stand 7105 is shown.

[0397] The operation of the television device 7100 can be performed by an operation switch provided in the housing 7101 or by a separate remote controller 7110. Channel and volume operations can be performed by operation keys 7109 provided on the remote controller 7110, and the video displayed on the display unit 710 3 can be operated. Also, the remote controller 7110 may be configured to be provided with a display unit 7107 for displaying information output from the remote controller.

[0398] ​​​​​​​​Note that the television device 7100 is configured to include a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can further be connected to a communication network via a modem, either wired or wirelessly, to enable one-way (sender to receiver) or two-way information communication (between the sender and the receiver, or between receivers, etc.).

[0399] Figure 17(B) shows a computer, which includes a main body 7201, a housing 7202, a display unit 7203, a keyboard 7204, an external connection port 7205, a pointing device 7206, etc. Note that the computer can be manufactured by using semiconductor devices, for example, in the display unit 7203.

[0400] Figure 17(C) shows a portable gaming machine, which is composed of two housings, a housing 7301 and a housing 7302, and is connected in an openable and closable manner by a connecting portion 7303. A display unit 7304 is incorporated in the housing 7301, and a display unit 7305 is incorporated in the housing 7302. In addition, the portable gaming machine shown in Figure 17(C) further includes a speaker unit 7306, a recording medium insertion portion 7307, an LED lamp 7308, input means (operation keys 7309, connection terminals 7310, a sensor 7311 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 7312), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it is sufficient if a display device is used in at least both or one of the display unit 7304 and the display unit 7305. ​​​​​​​​​​​​​​It can be configured with appropriate auxiliary equipment. The portable gaming machine shown in Fig. 17(C) has a function of reading programs or data recorded on a recording medium and displaying them on a display unit and a function of sharing information by performing wireless communication with other portable gaming machines. Note that the functions of the portable gaming machine shown in Fig. 17 (C) are not limited to this, and it can have various functions .

[0401] Fig. 17(D) shows an example of a mobile phone. The mobile phone 7400 includes a display unit 7402 incorporated in a housing 7401 , as well as operation buttons 7403, an external connection port 7404, a speaker 7405, a microphone 7406, etc. Note that the mobile phone 7400 is manufactured by using a semiconductor device for the display unit 7402 .

[0402] For the mobile phone 7400 shown in Fig. 17(D), information can be input by touching the display unit 7402 with a finger or the like . Also, operations such as making a phone call or creating an email can be performed by touching the display unit 7402 with a finger or the like .

[0403] The screen of the display unit 7402 mainly has three modes. The first is a display mode mainly for displaying images , the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the two modes of the display mode and the input mode are mixed .

[0404] For example, when making a phone call or creating an email, the display unit 7402 can be set to the character input mode mainly for character input, and an input operation of the characters displayed on the screen can be performed . In this case , it is preferable to display a keyboard or number buttons on most of the screen of the display unit 7402 .​

[0405] In addition, a sensor for detecting the inclination such as a gyro or an acceleration sensor is installed inside the mobile phone 7400. By providing a detection device having the above configuration, the orientation of the mobile phone 7400 (vertical or horizontal) can be determined and the display The screen display of the display unit 7402 can be automatically switched.

[0406] The screen mode can be changed by touching the display portion 7402 or by operating the housing 7401. The type of image displayed on the display unit 7402 can be selected by operating the operation button 7403. For example, the image signal to be displayed on the display unit may be changed by If the data is text data, the mode switches to input mode.

[0407] In the input mode, the optical sensor of the display unit 7402 detects a signal and displays If there is no input by touch operation of the part 7402 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0408] The display portion 7402 can also function as an image sensor. By touching the palm or fingers of the user on the sensor 02 and capturing an image of the palm print or fingerprint, the user can be authenticated. In addition, a backlight that emits near-infrared light to the display unit or a sensing light that emits near-infrared light By using a source, it is also possible to image finger veins, palm veins, etc.

[0409] FIG. 17(E) shows an example of a folding computer. Computer 7450 includes housing 7451L and housing 7451R connected by hinge 7454. In addition, the operation button 7453, the left speaker 7455L and the right speaker 74 In addition to 55R, an external connection port 7456 (not shown) is provided on the side of the computer 7450. It is provided with. When the hinge 7454 is folded so that the display unit 7452L provided on the housing 7451L and the display unit 7452R provided on the housing 7451R face each other, the display unit can be protected by the housing.

[0410] In addition to displaying an image, the display unit 7452L and the display unit 7452R can input information when touched with a finger or the like. For example, an icon indicating an installed program can be touched with a finger to select and start the program. Or, by changing the distance between the fingers touching two locations on the displayed image, the image can be enlarged or reduced. Or, by moving the finger touching one location on the displayed image, the image can be moved. Also, an image of a keyboard can be displayed, and the displayed characters and symbols can be touched with a finger to select and input information.

[0411] In addition, the computer 7450 can be equipped with a gyro, an acceleration sensor, a GPS (Global Positioning System) receiver, a fingerprint sensor, and a video camera. For example, by providing a detection device having sensors for detecting the inclination of a gyro, an acceleration sensor, etc., the orientation (vertical or horizontal) of the computer 7450 can be determined, and the orientation of the displayed screen can be automatically switched.

[0412] In addition, the computer 7450 can be connected to a network. The computer 7450 can display information on the Internet and, in addition, can be used as a terminal for remotely operating other electronic devices connected to the network.

[0413] Note that this embodiment can be appropriately combined with other embodiments described in this specification. .

Example

[0414] In this example, an example of manufacturing a conductive layer covered with a first protective layer, a second protective layer, and a third protective layer using the manufacturing method shown in Embodiment 1 is shown.

[0415] In this example, by the steps shown in FIGS. 2(C) to 3(C), an electrode composed of a first protective layer and a conductive layer, a second protective layer covering the upper surface of the conductive layer, and a third protective layer covering the side surfaces of the second protective layer and the conductive layer and the upper surface of the first protective layer exposed from the conductive layer were manufactured. The details of the manufacturing method of the sample manufactured in this example are shown below. First, an In-Ga-Zn oxide film with a thickness of 100 nm was formed as a semiconductor film on a substrate.

[0416] The In-Ga-Zn oxide film was formed by a sputtering method using an oxide target with In:Ga:Zn = 1:1:1 [atomic ratio]. The film formation conditions were an oxygen partial pressure of 50% atmosphere, a pressure of 0.6 Pa, a power supply power (AC) of 2.5 kW, and a substrate temperature of 170°C. Next, a titanium film with a thickness of 35 nm was formed as the first protective film by a sputtering method.

[0417] The film formation conditions were an argon atmosphere (flow rate 100 sccm), a pressure of 0.3 Pa, a power supply power (DC) of 58 kW, and a substrate temperature of 100°C.

[0418] On the first protective film, a copper film with a thickness of 200 nm was formed as a conductive film by a sputtering method. . The film formation conditions were an argon atmosphere (flow rate 150 sccm), a pressure of 0.9 Pa, a power supply power ( DC) The power was set to 20 kW and the substrate temperature was set to 80°C.

[0419] After that, as the second protective film, a silicon nitride film was formed on the conductive film by CVD method. The film formation of the silicon nitride film was carried out at a pressure of 200 Pa and a power supply power of 1000 W. As the supply gas, silane (flow rate 50 sccm), nitrogen (flow rate 5000 sccm), and ammonia (flow rate 100 scc m) mixed gas was used.

[0420] Similar to the process of Fig. 2(D), a resist mask was formed on the second protective film, and a part of the second protective film was selectively etched using the resist mask to form the second protective layer. Similar to the process of Fig. 3 (A), using the second protective layer as a mask, a part of the copper film, which is the conductive film, was selectively etched to form the conductive layer (copper layer in this example). Wet etching was used for the etching of the conductive film.

[0421] By the processes up to here, the cross-sectional photographs of the sample of this example obtained are shown in Fig. 18(A1) and Fig. 18 (A2).

[0422] Note that the cross-sectional photographs shown in Fig. 18(A1) to Fig. 18(C2) are STEM images taken by a scanning transmission electron microscope (Sc anning Transmission Electron Microscope; STEM). Also, Fig. 18(A1), Fig. 18(B1) , Fig. 18(C1) are phase contrast images (TE images), Fig. 18(A2) is the Z contrast image (ZC image) of Fig. 18(A 1), Fig. 18(B2) is the Z contrast image (ZC image) of Fig. 18(B1), and Fig. 18(C2) is the Z contrast image (ZC image) of Fig. 18(C1).

[0423] As shown in Fig. 18(A2), on the copper layer provided as the conductive layer, the film thickness of the silicon nitride layer is 198 nm, and the distance between the side surface of the copper layer and the side surface of the silicon nitride layer was confirmed to be 217 nm.

[0424] Next, in the same manner as the process of Fig. 3(B), a silicon nitride film was formed by CVD as the third protective film covering the upper surface of the first protective film, the side surface of the conductive layer, and the upper surface and side surface of the second protective layer. The silicon nitride film was formed under a pressure of 200 Pa and a power supply power of 1000 W, and as the supply gas, silane (flow rate 50 sccm), nitrogen (flow rate 5000 sccm), and ammonia (flow rate 100 s ccm) mixed gas was used.

[0425] Cross-sectional photographs of the sample of this example after the formation of the silicon nitride film used as the third protective film are shown in Figs. 18 (B1) and 18(B2).

[0426] In this example, since silicon nitride films with the same film formation conditions were formed as the second protective film and the third protective film, in Figs. 18(B1) and 18(B2), the interface between the two layers is not clear. However, in Fig. 18(B2), the film thickness of the silicon nitride layer (the second protective layer and the third protective film) provided on the copper layer is 288 nm, and since the distance between the side surface of the copper layer and the side surface of the silicon nitride layer is 266 nm, by comparison with Fig. 18(A2), it was confirmed that the third protective film was formed with good coverage so as to cover the side surface and the upper surface of the copper layer provided as the conductive layer.

[0427] Next, in the same manner as the process of Fig. 3(C), the first protective film and the third protective film were anisotropically etched Self-aligned etching was performed to form the first protective layer and the third protective layer.

[0428] Here, dry etching by the ICP (Inductively Coupled Plasma a: Inductively Coupled Plasma) etching method was applied. The etching conditions were as follows: a mixed gas of boron trichloride and chlorine (BCl3:Cl2 = 75 0 sccm:150 sccm) was used as the etching gas, the power supply power was 0 W, the bias power was 1500 W, the pressure was 2 .0 Pa, the lower electrode temperature was 20 °C, and the treatment was performed for 270 seconds. Under the above etching conditions the etching rate was 86.1 nm / min for the titanium film used as the first protective film and 31.4 nm / min for the silicon nitride film used as the third protective film.

[0429] Cross-sectional photographs of the sample of this example obtained are shown in FIGS. 18(C1) and 18(C2).

[0430] From FIGS. 18(C1) and 18(C2), a silicon nitride layer used as the second protective layer and the third protective layer was formed so as to cover the side surface and the upper surface of the copper layer used as the conductive layer, and a titanium layer used as the first protective layer was formed on the lower surface of the copper layer. It was confirmed that an electrode structure according to one aspect of the present invention was obtained. The upper surface of the titanium layer exposed from the copper layer was covered with the silicon nitride layer.

[0431] In FIG. 18(C2), the thickness of the silicon nitride layer (the second protective layer and the third protective layer) provided on the copper layer was 129 nm, and the distance between the side surface of the copper layer and the side surface of the silicon nitride layer was 260 nm.

[0432] The electrode structure of this example shown above was applied as a pair of electrodes in contact with the semiconductor layer of the transistor. By using this, it is possible to form a highly reliable transistor.

Explanation of Signs

[0433] 50 Region 52 Opening 102 Substrate 105 Oxide semiconductor layer 104 Gate electrode 104a Gate electrode 104b Gate electrode 106 Insulating film 107 Oxide semiconductor layer 108 Insulating film 109 Oxide semiconductor layer 110 Semiconductor layer 112 Protective film 112a Protective layer 112b Protective layer 113 Protective film 113a Protective layer 113b Protective layer 114 Conductive film 114a Conductive layer 114b Conductive layer 115a Mask 115b Mask 116a Electrode 116b Electrode 118a Protective layer 118b Protective layer 120 Protective film 120a Protective layer 120b Protective layer 122 Insulating film 124 Insulating film 126 Gate electrode 131_1 Transistor 131_2 Transistor 132 Liquid crystal element 133_1 Capacitor element 133_2 Capacitor element 134 Transistor 135 Light emitting element 200 Transistor 210 Transistor 220 transistor 230 transistor 301 pixel 302 substrate 304a conductive layer 304b conductive layer 304c conductive layer 305 insulating film 306 insulating film 307 semiconductor film 308a semiconductor layer 308b semiconductor layer 308c layer 308d semiconductor layer 309 protective film 310 conductive film 311 protective film 312a protective layer 312b protective layer 312c protective layer 312d protective layer 312e protective layer 312f protective layer 312g protective layer 313a conductive layer 313b conductive layer 313c conductive layer 313d conductive layer 313e conductive layer 313f conductive layer 314a protective layer 314b protective layer 314c protective layer 314d protective layer 314e protective layer 315 insulating film 316 insulating film 317 insulating film 318 insulating film 319 conductive film 320a conductive layer 320b conductive layer 321 liquid crystal layer 322 liquid crystal element 323 alignment film 324a protective layer 324b protective layer 324c protective layer 324d protective layer 324e protective layer 342 substrate 344 light-shielding film 346 colored film 348 insulating film 350 conductive layer 352 alignment film 362 opening 362c opening 364a opening 364b opening 364c opening 401 pixel section 402 transistor 403 transistor 404 scanning line drive circuit 405 capacitive element 406 signal line drive circuit 407 scanning line 409 signal line 415 capacitive line 7100 television apparatus 7101 housing 7103 display section 7105 stand 7107 display section 7109 operation key 7110 remote controller 7201 main body 7202 housing 7203 display section 7204 keyboard 7205 external connection port 7206 pointing device 7301 housing 7302 housing 7303 connecting section 7304 display section 7305 display section 7306 speaker section 7307 recording medium insertion section 7308 LED lamp 7309 operation key 7310 connection terminal 7311 sensor 7312 Microphone 7400 Mobile Phone 7401 Housing 7402 Display Unit 7403 Operation Button 7404 External Connection Port 7405 Speaker 7406 Microphone 7450 Computer 7451L Housing 7451R Housing 7452L Display Unit 7452R Display Unit 7453 Operation Button 7454 Hinge 7455L Left Speaker 7455R Right Speaker 7456 External Connection Port

Claims

1. A display device including a plurality of pixels each including a transistor and a capacitor electrically connected to the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating film having a region located above the first conductive layer and including silicon nitride; a second insulating film having a region located above the first insulating film and including silicon oxide; an oxide semiconductor film having a region in contact with a top surface of the second insulating film and including a channel formation region of the transistor; a second conductive layer having a region in contact with an upper surface of the second insulating film and functioning as an electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a third insulating film having a region in contact with a top surface of the oxide semiconductor film, a region in contact with a top surface of the second conductive layer, and a region in contact with a top surface of the third conductive layer, the third insulating film including silicon oxide; a fourth insulating film having a region located above the third insulating film and a region in contact with an upper surface of the second conductive layer, the fourth insulating film having silicon nitride; a fourth conductive layer having a region located above the second conductive layer with the fourth insulating film interposed therebetween and having a function as a pixel electrode; the third conductive layer has a stacked structure of a first film having a region in contact with a top surface of the oxide semiconductor film, a second film having a region located above the first film, and a third film having a region located above the second film; When viewed in cross section, the first film has a region that protrudes beyond an end of the second film, In a cross-sectional view, the third film has a region that protrudes beyond an end of the second film, The thickness of the second film is greater than the thickness of the first film, A display device, wherein the second film has a thickness greater than the thickness of the third film.

2. A display device including a plurality of pixels each including a transistor and a capacitor electrically connected to the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating film having a region located above the first conductive layer and including silicon nitride; a second insulating film having a region located above the first insulating film and including silicon oxide; an oxide semiconductor film having a region in contact with a top surface of the second insulating film and including a channel formation region of the transistor; a second conductive layer having a region in contact with an upper surface of the second insulating film and functioning as an electrode of the capacitor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor film and functioning as one of a source electrode and a drain electrode of the transistor; a third insulating film having a region in contact with a top surface of the oxide semiconductor film, a region in contact with a top surface of the second conductive layer, and a region in contact with a top surface of the third conductive layer, the third insulating film including silicon oxide; a fourth insulating film having a region located above the third insulating film and a region in contact with an upper surface of the second conductive layer, the fourth insulating film having silicon nitride; a fourth conductive layer having a region located above the second conductive layer with the fourth insulating film interposed therebetween and having a function as a pixel electrode; the third conductive layer has a stacked structure of a first film having a region in contact with a top surface of the oxide semiconductor film, a second film having a region located above the first film, and a third film having a region located above the second film; When viewed in cross section, the first film has a region that protrudes beyond an end of the second film, In a cross-sectional view, the third film has a region that protrudes beyond an end of the second film, The thickness of the second film is greater than the thickness of the first film, The thickness of the second film is greater than the thickness of the third film, A display device, wherein the third insulating film has a thickness greater than a thickness of the fourth insulating film.

3. In claim 1 or 2, A display device, wherein the first insulating film has a thickness greater than a thickness of the second insulating film.

Images