Semiconductor device

Abstract

To provide a semiconductor device with high reliability including an oxide semiconductor, and a semiconductor device that has achieved miniaturization while keeping excellent electric characteristics using an oxide semiconductor.SOLUTION: A semiconductor device includes a first protection insulating layer 111, an oxide semiconductor layer 102 on the first protection insulating layer, a source electrode and a drain electrode 103 electrically connected to the oxide semiconductor layer, a gate insulating layer 104 existing on the source electrode and the drain electrode and overlapping with the oxide semiconductor layer, a gate electrode 105 overlapping with the oxide semiconductor layer through the gate insulating layer, and a second protection insulating layer 112 covering the source electrode, the drain electrode, and the gate electrode. In addition, the first protection insulating layer and the second protection insulating layer include an aluminum oxide film including an oxygen-excessive region, and include a region where these layers are in contact with each other in a region where the source electrode, the drain electrode, or the gate electrode does not exist.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] In this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. It refers to all devices, and transistors, semiconductor circuits, arithmetic units, storage devices, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are one aspect of semiconductor devices.

Background Art

[0003] Techniques for constructing transistors using semiconductor thin films formed on substrates having insulating surfaces have been attracting attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. For example, techniques for manufacturing transistors using zinc oxide or In-Ga-Zn-based oxide semiconductors as oxide semiconductors have been disclosed (see Patent Document 1 and Patent Document 2).

[0004] For example, techniques for manufacturing transistors using zinc oxide or In-Ga-Zn-based oxide semiconductors as oxide semiconductors have been disclosed (see Patent Document 1 and Patent Document 2).

[0005] Also, techniques for laminating oxide semiconductor layers having different electron affinities (or conduction band lower levels) for the purpose of improving the carrier mobility of transistors have been disclosed (see Patent Document 3 and Patent Document 4).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] In a semiconductor device having a transistor using an oxide semiconductor, achieving high reliability is an important matter for commercialization. In particular, fluctuations and degradation of the electrical characteristics of the semiconductor device are one of the factors leading to low reliability.

[0008] In view of such problems, one aspect of the present invention is a semiconductor device using an oxide semiconductor and has an object of providing a highly reliable semiconductor device.

[0009] In addition, in order to achieve high-speed operation, low power consumption, low cost, high integration of the transistor, etc., miniaturization of the transistor is essential.

[0010] Therefore, one aspect of the present invention is a semiconductor device using an oxide semiconductor, and has an object of providing a semiconductor device that achieves miniaturization while maintaining good electrical characteristics.

[0011] Note that the description of these problems does not prevent the existence of other problems. One aspect of the present invention is not required to solve all of these problems. Also, problems other than the above will be apparent from the description in the specification and the like, and it is possible to extract problems other than the above from the description in the specification and the like. ​

Means for Solving the Problem

[0012] A semiconductor device according to one aspect of the present invention includes a first protective insulating layer, an oxide semiconductor layer on the first protective insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer located on the source electrode and the drain electrode and overlapping the oxide semiconductor layer, and a gate electrode overlapping the oxide semiconductor layer through the gate insulating layer, and a second protective insulating layer covering the source electrode, the drain electrode, and the gate electrode. Further, the first protective insulating layer and the second protective insulating layer include an aluminum oxide film having an oxygen-excess region, and have a region where they are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode do not exist. Also, the gate electrode preferably has a configuration that covers the upper surface and the side surface of the oxide semiconductor layer through the gate insulating layer. Further, the thickness of the oxide semiconductor layer is preferably 0.1 times or more and 10 times or less with respect to the channel width. In addition, a first oxide layer provided between the first protective insulating layer and the oxide semiconductor layer and composed of at least one of the metal elements of the oxide semiconductor layer, and a second oxide layer provided between the oxide semiconductor layer and the gate insulating layer and composed of at least one of the metal elements of the oxide semiconductor layer may be provided. Here, the energy of the lower end of the conduction band of the first oxide layer and the second oxide layer is preferably in the range of 0.05 eV or more and 2 eV or less closer to the vacuum level than the energy of the lower end of the conduction band of the oxide semiconductor layer.

[0013]

[0014]

[0015]

[0016] ​​​​​​​​​​​​​ Further, the upper surface of the second oxide layer may be configured to contact the lower surface of the source electrode, the lower surface of the drain electrode, and the lower surface of the gate insulating layer. Or, the lower surface of the second oxide layer may be configured to contact the upper surface of the source electrode, the upper surface of the drain electrode, and the upper surface and side surface of the oxide semiconductor layer in a region where the source electrode and the drain electrode are not provided.

[0017] Also, another aspect of the semiconductor device of the present invention includes an insulating layer having a groove, a first protective insulating layer provided so as to cover the side surface and the bottom surface of the groove, and an oxide semiconductor layer provided so as to be embedded in the groove on the first protective insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer located on the source electrode and the drain electrode and overlapping the oxide semiconductor layer, a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer, and a second protective insulating layer covering the source electrode, the drain electrode, and the gate electrode. Furthermore, the first protective insulating layer and the second protective insulating layer include an aluminum oxide film having an oxygen-excess region and have a region where they contact each other in a region where the source electrode, the drain electrode, and the gate electrode do not exist.

Advantages of the Invention

[0018] According to one aspect of the present invention, a semiconductor device using an oxide semiconductor can be provided, which is a highly reliable semiconductor device. Also, according to one aspect of the present invention, a semiconductor device using an oxide semiconductor can be provided, which achieves miniaturization while maintaining good electrical characteristics.

[0019]

[0020] ​​​​​​​​​​​​

Brief Description of the Drawings

[0021]

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Mode for Carrying Out the Invention

[0022] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and various changes can be made to its form and details without departing from the spirit and scope of the present invention. This will be readily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the embodiments

[0023] shown below. In the configuration of the invention described below, the same part or parts having the same function are commonly denoted by the same reference numerals in different drawings, and the repeated description thereof will be omitted. Also, when referring to similar functions, the hatch patterns may be the

[0024] same, and in some cases, no specific reference numerals may be attached. The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0025] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0026] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0027] (Embodiment 1) In this embodiment, examples of the structure of a transistor and a semiconductor device according to one embodiment of the present invention will be described. An example of a manufacturing method thereof will be described with reference to the drawings.

[0028] When a transistor is manufactured using an oxide semiconductor, a carrier source of the oxide semiconductor One of the causes is oxygen vacancy. If there are many oxygen vacancies in the conductor, electrons are generated in the channel formation region, Normally-on transistors, increased leakage current, and threshold voltage fluctuations due to stress application This can cause defects in electrical characteristics such as shift.

[0029] In addition, in the oxide semiconductor layer, hydrogen, silicon, nitrogen, carbon, and a metal element other than the main component For example, some of the hydrogen in the oxide semiconductor layer forms a donor level, and Increase carrier density.

[0030] Therefore, in order to obtain stable electrical characteristics in a semiconductor device using an oxide semiconductor, measures are required to reduce oxygen vacancies by supplying sufficient oxygen to the oxide semiconductor layer and to reduce the concentration of impurities such as hydrogen.

[0031] Thus, in the semiconductor device according to one aspect of the present invention, a protective insulating layer including an aluminum oxide film having an oxygen-excess region is provided so as to surround the oxide semiconductor layer, and oxygen is supplied from the protective insulating layer to the channel formation region to compensate for oxygen vacancies that may be formed in the channel formation region. Further, the protective insulating layer suppresses the release of oxygen from the oxide semiconductor layer and suppresses the formation of oxygen vacancies.

[0032] In one aspect of the present invention, as the protective insulating layer for supplying oxygen to the channel formation region, an insulating layer having an aluminum oxide film containing excess oxygen is applied. Here, the excess oxygen refers to, for example, oxygen contained in excess of the stoichiometric composition or oxygen that can be released by heating at a temperature equal to or lower than the heat treatment temperature applied during the manufacturing process of the semiconductor device. For example, as the aluminum oxide film containing excess oxygen, an AlO (where x is greater than 3 / 2) film can be used. x Since the excess oxygen contained in the aluminum oxide film can be released by heating and supplied to the oxide semiconductor layer, by providing such an insulating layer containing an aluminum oxide film on the lower side and the upper side of the oxide semiconductor layer, oxygen can be effectively supplied to the channel formation region.

[0033] Note that the aluminum oxide film containing excess oxygen is formed, for example, by sputtering in an oxygen-containing atmosphere. It can be formed by film formation using the ring method or the like.

[0034] In addition, the aluminum oxide film is an insulating layer such as a silicon oxide film or a silicon oxynitride film, and is an insulating layer with low permeability to oxygen and hydrogen compared to the oxide semiconductor layer. In other words, it is an insulating layer having a barrier property against oxygen and hydrogen. Therefore, by providing an insulating layer containing an aluminum oxide film, formation of oxygen vacancies due to desorption of oxygen in the region surrounded by the insulating layer can be suppressed, and mixing of hydrogen or hydrogen compounds can be suppressed.

[0035] In one aspect of the present invention, the protective insulating layers provided on the upper and lower sides of the oxide semiconductor layer have regions in contact with each other in a region where there are no oxide semiconductor layers, source electrodes, and drain electrodes that are electrically connected to the oxide semiconductor layers. That is, a semiconductor device according to one aspect of the present invention has a configuration in which an aluminum oxide film is provided so as to wrap the oxide semiconductor layer. By having such a configuration, in addition to the front channel side and back channel side interfaces of the oxide semiconductor layer, desorption of oxygen and / or mixing of impurities such as hydrogen on the side surface of the oxide semiconductor layer can be suppressed, and supply of oxygen can be performed. Therefore, fluctuations in the electrical characteristics of a transistor in which a channel is formed in the oxide semiconductor layer can be suppressed, and a highly reliable semiconductor device can be formed. Therefore, in a semiconductor device according to one aspect of the present invention, by reducing oxygen vacancies in the channel formation region, a highly reliable semiconductor device having good electrical characteristics and suppressed fluctuations in electrical characteristics can be realized.

[0036]

[0037]

[0037] The effects of the configuration according to one aspect of the present invention can be described as follows, for example.

[0038] A semiconductor device according to one aspect of the present invention includes an insulating layer containing an aluminum oxide film having excess oxygen, which is provided so as to wrap an oxide semiconductor layer. The excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer in which a channel is formed by heat treatment in the manufacturing process of the semiconductor device. Furthermore, since the aluminum oxide film has a barrier property against oxygen and hydrogen, desorption of oxygen from the oxide semiconductor layer wrapped with the insulating layer containing the aluminum oxide film and mixing of impurities such as hydrogen into the oxide semiconductor layer can be suppressed. The oxide semiconductor layer sufficiently supplied with oxygen and having suppression of mixing of impurities such as hydrogen is an oxide semiconductor layer that is highly purified and made intrinsic.

[0039] Also, in the above semiconductor device, a gate electrode overlapping the oxide semiconductor layer via a gate insulating layer is preferably provided so as to overlap the side surface and the upper surface of the channel formation region of the oxide semiconductor layer. With such a configuration, an electric field is applied to the oxide semiconductor layer from a direction perpendicular to the side surface and a direction perpendicular to the upper surface, so that the threshold voltage of the transistor can be favorably controlled and the subthreshold swing (also referred to as S value) can be improved.

[0040] Here, in order to achieve high density (high integration) of the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor may deteriorate due to miniaturization of the transistor.

[0041] For example, in a transistor using silicon, when the channel length is shortened, the subthreshold It is known that short-channel effects such as deterioration of the Yold coefficient (S value) and fluctuations in the threshold voltage occur. It is known.

[0042] However, since a transistor using an oxide semiconductor is an accumulation-type transistor with electrons as majority carriers, Drain-Induced Barrier Lowering (DIBL) in a short channel is less likely to occur compared to an inversion-type transistor such as silicon. In other words, a transistor using an oxide semiconductor has resistance to short-channel effects. However, since a transistor using an oxide semiconductor is an accumulation-type transistor with electrons as majority carriers, Drain-Induced Barrier Lowering (DIBL) in a short channel is less likely to occur compared to an inversion-type transistor such as silicon. In other words, a transistor using an oxide semiconductor has resistance to short-channel effects. Drain-Induced Barrier Lowering (DIBL) in a short channel is less likely to occur compared to an inversion-type transistor such as silicon. In other words, a transistor using an oxide semiconductor has resistance to short-channel effects. However, since a transistor using an oxide semiconductor is an accumulation-type transistor with electrons as majority carriers, Drain-Induced Barrier Lowering (DIBL) in a short channel is less likely to occur compared to an inversion-type transistor such as silicon. In other words, a transistor using an oxide semiconductor has resistance to short-channel effects. In other words, a transistor using an oxide semiconductor has resistance to short-channel effects.

[0043] In addition, when the channel width of a transistor is reduced, a decrease in the on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is known. However, since the surface area where the channel is formed increases, carrier scattering at the interface between the channel formation region and the gate insulating layer increases, and it is not easy to expect sufficient improvement in the on-current. In addition, when the channel width of a transistor is reduced, a decrease in the on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is known. However, since the surface area where the channel is formed increases, carrier scattering at the interface between the channel formation region and the gate insulating layer increases, and it is not easy to expect sufficient improvement in the on-current. In addition, when the channel width of a transistor is reduced, a decrease in the on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is known. However, since the surface area where the channel is formed increases, carrier scattering at the interface between the channel formation region and the gate insulating layer increases, and it is not easy to expect sufficient improvement in the on-current. In addition, when the channel width of a transistor is reduced, a decrease in the on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is known. However, since the surface area where the channel is formed increases, carrier scattering at the interface between the channel formation region and the gate insulating layer increases, and it is not easy to expect sufficient improvement in the on-current. In addition, when the channel width of a transistor is reduced, a decrease in the on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is known. However, since the surface area where the channel is formed increases, carrier scattering at the interface between the channel formation region and the gate insulating layer increases, and it is not easy to expect sufficient improvement in the on-current.

[0044] However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed. However, in the transistor according to one aspect of the present invention, by having an insulating layer including an aluminum oxide film containing excess oxygen in a manner that wraps the oxide semiconductor layer where the channel is formed, the excess oxygen contained in the aluminum oxide film can be supplied to the oxide semiconductor layer, and desorption of oxygen from the oxide semiconductor layer and incorporation of impurities such as hydrogen can be suppressed. Since oxygen deficiency and hydrogen are factors for generating carriers in the oxide semiconductor layer, by providing an aluminum oxide film containing excess oxygen, carrier scattering that may occur at the interface of the oxide semiconductor layer where the channel is formed can be suppressed.

[0045] Therefore, even when the channel width is reduced, by increasing the film thickness of the oxide semiconductor layer and increasing the surface area overlapping with the gate electrode, it becomes possible to sufficiently improve the on-current. In order to sufficiently apply an electric field from the gate electrode in the lateral direction of the oxide semiconductor layer, it is preferable that the film thickness of the oxide semiconductor layer be equal to or greater than the channel width. Moreover, by providing an oxide layer containing at least one of the metal elements of the oxide semiconductor layer in contact with the oxide semiconductor layer, the above-described carrier scattering can be further suppressed, which is effective. When the channel length and channel width of the transistor are miniaturized, the end faces of wirings, semiconductor layers, etc. that are processed using a resist mask may become rounded (have a curved surface). When forming a thin film insulating layer (for example, a gate insulating layer) so as to cover the thick film oxide semiconductor layer, shape defects may occur due to a decrease in the covering property, and stable electrical characteristics may not be obtained. However, since the end face of the oxide semiconductor layer has a curved surface, the covering property of the insulating layer provided on the oxide semiconductor layer can be improved, which is preferable. Also, a part of the hydrogen in the oxide semiconductor layer is trapped by oxygen vacancies and n-type dopes the oxide semiconductor layer, so that the Fermi level (Ef) approaches the lower end of the conduction band (Ec). Therefore, while the oxide semiconductor layer containing a large amount of hydrogen is concerned about fluctuations in electrical characteristics, an improvement in the field-effect mobility of the transistor is expected. On the other hand, when the oxide semiconductor layer is intrinsic or substantially intrinsic, the Fermi energy of the oxide semiconductor layer is at the mid-gap (the energy of the oxide semiconductor layer).

[0046]

[0047]

[0048] ​​​​​​​​​​​​​​In this case, the oxide semiconductor There is concern that a decrease in the number of carriers contained in the semiconductor layer may result in a decrease in field effect mobility.

[0049] However, in the transistor of one embodiment of the present invention, In addition to the gate field from the top, a gate field is applied from the side. A gate electric field is applied to the entire semiconductor layer, and the current flows through the bulk of the oxide semiconductor layer. This allows the suppression of fluctuations in electrical characteristics by using highly pure intrinsic material while also reducing the This makes it possible to improve the field effect mobility of the transistor.

[0050] More specifically, for example, the following configuration can be adopted.

[0051] [Configuration example 1] FIG. 1A is a schematic top view of a transistor 100 illustrated in this configuration example. (B) and (C) are schematic cross-sectional views taken along lines AB and CD in FIG. 1(A), respectively. In FIG. 1(A), some components are not shown for clarity.

[0052] The transistor 100 is provided on a substrate 101, and includes an island-shaped semiconductor layer 102 and a semiconductor layer A pair of electrodes 103 electrically connected to the semiconductor layer 102 and a semiconductor layer A gate insulating layer 104 overlapping the semiconductor layer 102 and a semiconductor layer 102 disposed on the gate insulating layer 104. and a gate electrode 105 overlapping the gate electrode 103 .

[0053] In addition, a first protective insulating layer 111 is provided between the substrate 101 and the semiconductor layer 102. In addition, a second protective insulating layer 112 is formed on the pair of electrodes 103 and the gate electrode 105. is provided. Further, the first protective insulating layer 111 and the second protective insulating layer 112 are provided in contact with each other in a region where the pair of electrodes 103 and the gate electrode 105 are not provided.

[0054] The semiconductor layer 102 contains an oxide semiconductor. The semiconductor layer 102 preferably contains at least indium (In) or zinc (Zn). Or, it preferably contains both In and Zn. More preferably, it contains an oxide represented by an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf).

[0055] Of the pair of electrodes 103, one functions as the source electrode of the transistor 100 and the other functions as the drain electrode. Also, in FIG. 1(B), the pair of electrodes 103 are each provided in contact with the upper surface and the side surface of the semiconductor layer 102.

[0056] The gate electrode 105 is provided so as to surround the upper surface and the side surface of the semiconductor layer 102 via the gate insulating layer 104.

[0057] Here, the channel length (L length) of the transistor is defined as the distance between the opposing source and drain. Also, the channel width (W length) of the transistor is defined as the width of the semiconductor layer in a direction orthogonal to the channel length direction. Note that depending on the shapes of the source electrode, drain electrode, gate electrode, and semiconductor layer of the transistor, the channel length and channel width may vary depending on the region (position). In that case, the average value, or the minimum value, etc. thereof can be applied as the channel length or channel width of the transistor.

[0058] ​​​​​​​​​Since the gate electrode 105 is provided so as to surround also the side surface of the semiconductor layer 102, the side surface of the semiconductor layer 10 2 can also function as a channel formation region. At this time, with respect to the channel width of the semiconductor layer 102, the thickness of the semiconductor layer 102 is 0.05 times or more and 20 times or less, preferably 0.1 times or more and 10 times or less. By adopting such a shape, even when the channel width is reduced, a decrease in the on-current is suppressed, and a more fine and high-speed operating transistor can be realized. Even when the channel width is reduced, a decrease in the on-current is suppressed, and a more fine and high-speed operating transistor can be realized.

[0059] As described above, a transistor structure in which a gate electrode is provided so as to surround the upper surface and the side surface of the semiconductor layer of the transistor, and the on-current is increased by actively using a channel formed in the vicinity of the side surface of the semiconductor layer, is also called a Surrounded Channel (S-C hannel) structure. hannel) structure. hannel) structure.

[0060] The first protective insulating layer 111 and the second protective insulating layer 112 can be made of an insulating material having an oxygen-excess region and having a function of suppressing oxygen diffusion (also referred to as blocking property against oxygen). For example, as the first protective insulating layer 111 and the second protective insulating layer 112, a layer containing an aluminum oxide film can be used. In addition, aluminum oxide aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia ( YSZ), and other insulating films containing an oxygen-containing insulating material can also be applied. aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia ( YSZ), and other insulating films containing an oxygen-containing insulating material can also be applied. YSZ), and other insulating films containing an oxygen-containing insulating material can also be applied.

[0061] As the insulating film having an oxygen-excess region, for example, more oxygen than that satisfying the stoichiometric composition It is preferable to use an oxide insulating film containing oxygen. An oxide insulating film containing more oxygen than the stoichiometric composition has some oxygen desorbed by heating. An oxide insulating film containing more oxygen than the stoichiometric composition has some oxygen desorbed by heating.

[0062] Also, for the first protective insulating layer 111 and the second protective insulating layer 112, it is preferable to use an insulating material with an extremely low hydrogen content. For example, the hydrogen content detected by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is less than 5×10 atoms / cm and preferably less than 2×10 21 atoms / cm 3 and more preferably less than 1×10 21 atoms / cm 3 and an insulating material including a region less than this can be used. 21 atoms / cm 3

[0063] Also, as the insulating material applied to the first protective insulating layer 111 and the second protective insulating layer 112, a material in which silicon oxide is contained in the above-mentioned oxide can also be used. For example, aluminum oxide containing silicon oxide in the range of 0.1 wt% to 30 wt% (for example, 5 wt% or 10 wt%, etc.)

[0064]

[0064]

[0065]

[0065] As the oxide semiconductor contained in the semiconductor layer 102, an oxide semiconductor having a wider band gap than silicon 、 When using an oxide semiconductor with a small carrier density, it is preferable because the current in the off state of the transistor can be reduced.

[0066] Also, as the crystallinity of the semiconductor used for the semiconductor layer 102, any of an amorphous semiconductor, a semiconductor having crystallinity (microcrystalline semiconductor, polycrystalline semiconductor, single crystal semiconductor, or a semiconductor having crystal portions partially or entirely) may be used. When using a semiconductor having crystallinity for the semiconductor layer 102, it is preferable because deterioration of the characteristics of the transistor is suppressed.

[0067] In particular, as the semiconductor layer 102, it is preferable to use a layer having a plurality of crystal portions, wherein the c-axis of the crystal portions is oriented substantially perpendicular to the surface to be formed of the semiconductor layer 102 (the upper surface of the first protective insulating layer 111 in FIG. 1) or the upper surface of the semiconductor layer 102, and there is no grain boundary between adjacent crystal portions.

[0068] By using such a material as the semiconductor layer 102, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor 100 can be realized.

[0069] Also, the semiconductor layer 102 may have a single-layer structure or a laminated structure of two or more layers. In the case of a laminated structure, two or more oxide semiconductor films having different compositions may be combined.

[0070] Note that preferred forms of the oxide semiconductor applicable to the semiconductor layer 102 and methods for forming the same will be described in detail in later embodiments.

[0071] [Substrate] There is no significant limitation on the material of the substrate 101, etc., but a material having heat resistance sufficient to withstand at least the heat treatment during the process is used. For example, a glass substrate, a ceramic substrate, a quartz substrate, a s ​ A fire substrate, a yttria-stabilized zirconia (YSZ) substrate, etc. may be used as the substrate 101. Also, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate such as silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. may be applied. It is also possible.

[0072] Also, those in which semiconductor elements are provided on various semiconductor substrates or SOI substrates may be used as the substrate 101. In that case, the transistor 100 is formed on the substrate 101 via an interlayer insulating layer. At this time, at least one of the gate electrode 105 of the transistor 100 and one of the pair of electrodes 103 may be configured to be electrically connected to the semiconductor element by a connection electrode embedded in the interlayer insulating layer. By providing the transistor 100 on the semiconductor element via an interlayer insulating layer, it is possible to suppress an increase in area due to adding the transistor 100.

[0073] 〔Gate Electrode〕 The gate electrode 105 can be formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metals as components, or an alloy obtained by combining the above-described metals. Also, a metal selected from any one or more of manganese and zirconium may be used. A semiconductor typified by doped polycrystalline silicon, a silicide such as nickel silicide, etc. may be used. Also, the gate electrode 105 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a titanium film on the aluminum film ​​​​​​​​​​A two-layer structure in which they are laminated, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and on the titanium nitride film There is a two-layer structure in which a tungsten film is laminated, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a titanium film, and an aluminum film is laminated on the titanium film and a titanium film is further formed thereon, and there are three-layer structures and the like. Further, for aluminum, one or a plurality of metals selected from titanium tantalum, tungsten, molybdenum, chromium, neodymium, scandium may be used in combination as an alloy film, or these nitride films may be used.

[0074] Further, the gate electrode 105 can also be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Also a laminated structure of the above-mentioned translucent conductive material and the above-mentioned metal can also be used.

[0075] When using a conductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration of at least higher than that of the semiconductor layer 102, specifically 7 atomic% or higher is used.

[0076] 〔Gate insulating layer〕 The gate insulating layer 104 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide or a Ga-Zn-based metal oxide, nitride silicon, etc., and may be provided in a laminated or single-layer structure.

[0077] Also, as the gate insulating layer 104, hafnium silicate (HfSiO x ), hafnium silicate with nitrogen added (HfSi O x O y N z ), hafnium aluminate with nitrogen added (HfAl O x O y N z ), high- k materials such as hafnium oxide and yttrium oxide can be used to reduce the gate leakage of the transistor.

[0078] 〔Pair of electrodes〕 The pair of electrodes 103 can be used as a single-layer structure or a laminated structure of a simple metal composed of aluminum, titanium, chromium, nickel, copper , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and a copper film or a titanium nitride film is superimposed on the titanium film or the titanium nitride film or a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a titanium film or a titanium nitride film and a copper film or a titanium nitride film are superimposed on the titanium film or the titanium nitride film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a titanium film or a titanium nitride film and a copper film or a titanium nitride film are superimposed on the titanium film or the titanium nitride film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a titanium film or a titanium nitride film and a copper film or a titanium nitride film are superimposed on the titanium film or the titanium nitride film Stack an aluminum film or a copper film, and further form a titanium film or a titanium nitride film thereon A three-layer structure, a molybdenum film or a molybdenum nitride film, and the molybdenum film or the nitride Stack an aluminum film or a copper film on top of the molybdenum film or the molybdenum nitride film, and further form a molybdenum film or a molybdenum nitride film thereon. There is also a three-layer structure or the like. In addition, a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

[0079] The above is a configuration example of the transistor 100 and an explanation of each component.

[0080] [Example of manufacturing method 1] Hereinafter, an example of the manufacturing method of the transistor 100 illustrated in FIG. 1 will be described with reference to the drawings FIG. 2 is a schematic cross-sectional view of each step in the manufacturing method illustrated below.

[0081] [Formation of the first protective insulating layer] First, form the first protective insulating layer 111 on the substrate 101 (FIG. 2(A)).

[0082] The first protective insulating layer 111 can be formed by, for example, sputtering in an atmosphere containing oxygen or the like. In addition, in an atmosphere containing oxygen, CVD (Chemical Vapor Deposition) method, MBE (Molecular Beam Epitaxy) method, ALD (Atomic Layer Deposition) method or PLD (Pulsed Laser Deposition) method or the like may be used to form the film thereof.

[0083] For example, when an aluminum oxide film is used as the first protective insulating layer 111, oxidation Aluminum can be used as a sputtering target to form a film in an atmosphere containing oxygen. The film-forming gas may contain an inert gas such as a noble gas. For example, the flow rate of oxygen with respect to the total flow rate of the film-forming gas is 20% or more, preferably 30% or more, more preferably 40% or more. It is preferable. In addition, an aluminum oxide film may be formed by a reactive sputtering method using aluminum as a sputtering target. However, it is more preferable to use aluminum oxide as a sputtering target because more oxygen can be contained in the film. Although an aluminum oxide film may be formed by a reactive sputtering method using aluminum as a sputtering target, it is more preferable to use aluminum oxide as a sputtering target because more oxygen can be contained in the film. For this reason, it is preferable.

[0084] 〔Formation of Semiconductor Layer〕 Subsequently, a semiconductor film is formed on the first protective insulating layer 111. Then, a resist mask is formed on the semiconductor film using a photolithography method or the like, and unnecessary portions of the semiconductor film are removed by etching. Then, by removing the resist mask, island-shaped semiconductor layers 102 can be formed (FIG. 2(B)). The semiconductor film can be formed by using a sputtering method, a CVD method, an MBE method, an ALD method, a PLD method, or the like. Alternatively, a thin film forming technique using a liquid material such as a sol-gel method, a spray method, or a mist method can also be used. It is preferable to use a sputtering method for forming the semiconductor film. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. In particular, since the generation of dust during film formation can be reduced and the film thickness distribution is also uniform, it is preferable to use the DC sputtering method.

[0085] In particular, since the generation of dust during film formation can be reduced and the film thickness distribution is also uniform, it is preferable to use the DC sputtering method.

[0086] ​​​​​​​​​​After forming the semiconductor film, heat treatment may be performed. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower , preferably at a temperature of 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Further, the atmosphere for the heat treatment may be an inert gas atmosphere, and after heat treatment in the inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas may be used to supplement the desorbed oxygen. By the heat treatment, oxygen is supplied from the first protective insulating layer 111 to the semiconductor film ( or semiconductor layer 102), and oxygen vacancies in the oxide semiconductor contained in the semiconductor layer 102 can be reduced. Note that the heat treatment may be performed immediately after forming the semiconductor film, or after processing the semiconductor film to form the island-shaped semiconductor layer 102.

[0087] The light used for forming the resist mask can be, for example, i-line (wavelength 365 nm), g-line (wavelength 43 6 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Further, exposure may be performed by the liquid immersion exposure technique. Also, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also , instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays or an electron beam is preferable because extremely fine processing becomes possible. Note that when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0088] Here, as shown in FIG. 2(B), when etching the semiconductor film, a part of the first protective insulating layer 111 may be etched and thinned in a region that does not overlap with the semiconductor layer 102. Semi Above the first protective insulating layer 111 around the semiconductor layer 102 rather than the lower surface of the conductor layer 102 By making the upper surface lower, the gate electrode 105 formed later can be configured to surround the lower part of the side surface of the semiconductor layer 102. As a result, an electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 100 can be increased. Similarly, as shown in FIG. 26, when a part of the first protective insulating layer 111 is etched so that the lower surface of the gate electrode 105 is lower than the lower surface of the semiconductor layer 102, it is preferable because the on-current of the transistor 100 can be further increased. Also, depending on the material used for the first protective insulating layer 111 and the etching conditions of the semiconductor film, the first protective insulating layer 111 may not be etched. At this time, it is preferable because the coating property of the film formed on the semiconductor layer 102 is improved.

[0089]

[0090] Also, as shown in FIG. 2(B), the semiconductor layer 102 is preferably processed so that the upper corner portions thereof become gentle curved surfaces. Particularly when the semiconductor layer 102 is finely processed, it often has such a shape. By making the semiconductor layer 102 have such a shape, the coating property of the film provided on the upper part thereof is improved, so that variations and fluctuations in the electrical characteristics of the transistor 100 can be suppressed, which is preferable.

[0091] 〔Formation of a pair of electrodes〕 Subsequently, a conductive film is formed on the first protective insulating layer 111 and the semiconductor layer 102. Then, a resist mask is formed on the conductive film using a photolithography method or the like, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask, a pair of ​​​​​​​​​​​​ The electrode 103 can be formed (Fig. 2(C)).

[0092] The conductive film can be formed by, for example, sputtering, vapor deposition, CVD method, etc. and so on.

[0093] Here, as shown in Fig. 2(C), when etching the conductive film, a part of the upper portion of the semiconductor layer 102 may be etched, and the portion that does not overlap with the pair of electrodes 103 may be thinned. Therefore, it is preferable to form the semiconductor film that will become the semiconductor layer 102 in advance with a thickness considering the etching depth. In addition, although not shown in the figure, also during the etching of the conductive film, a part of the first protective insulating layer 111 may be etched and thinned in the same manner as above.

[0094]

[0095] 〔Formation of Gate Insulating Layer and Gate Electrode〕 Subsequently, an insulating film is formed on the semiconductor layer 102, the pair of electrodes 103, and the first protective insulating layer 111. Further, a conductive film is formed on the insulating film. Then, a resist mask is formed on the conductive film using photolithography or the like, and unnecessary portions of the conductive film and the insulating film are removed by etching. Then, by removing the resist mask, the gate electrode 105 and the gate insulating layer 104 can be formed (Fig. 2(D)).

[0096] The insulating film that will become the gate insulating layer 104 can be formed using sputtering, CVD, MBE, ALD method or PLD method, etc. In particular, when the insulating film is formed by CVD method, preferably by plasma CVD method, the coating property can be improved, so it is preferable.

[0097] ​​​​​​​​​ Also, the conductive film serving as the gate electrode 105 can be formed by, for example, sputtering, vapor deposition, CVD method and the like.

[0098] Here, the gate insulating layer 104 is etched simultaneously when forming the gate electrode 105 and the case where the gate insulating layer 104 is processed to have the same upper surface shape as the gate electrode 105 will be described. However, the gate insulating layer 104 extends outside the gate electrode 105 Each may be processed individually so as to have an upper surface shape. At this time, a multi-tone mask such as a grayscale mask or a halftone mask is used as the exposure mask used in the photolithography method or the like and the like, which is preferable because the process can be simplified.

[0099] 〔Formation of the second protective insulating layer〕 Subsequently, a second protective insulating layer 112 is formed on the first protective insulating layer 111, the pair of electrodes 103, the gate insulating layer 104, and the gate electrode 105 (Fig. 2(E)).

[0100] The second protective insulating layer 112 can be formed in the same manner as the first protective insulating layer 111.

[0101] Here, the second protective insulating layer 112 is provided in a region where the pair of electrodes 103 and the gate electrode 105 are not provided and is in contact with the first protective insulating layer 111. Therefore, the semiconductor layer 102 can be surrounded by the first protective insulating layer 111 and the second protective insulating layer 112.

[0102]

[0103] Through the above steps, the transistor 100 can be manufactured.

[0103] 〔Heat treatment〕 After forming the second protective insulating layer 112, a heat treatment may be performed. By the heat treatment, oxygen is supplied to the semiconductor layer 102 from the first protective insulating layer 111 and the second protective insulating layer 112, and oxygen vacancies in the semiconductor layer 102 can be reduced. At this time, the first protective insulating layer 111 and the second protective insulating layer 112 can suppress the release of oxygen from the semiconductor layer 102 and suppress the formation of oxygen vacancies in the semiconductor layer 102.

[0104] The above is the description of the manufacturing process example of the transistor 100.

[0105] [Modification Example 1 of Configuration Example 1] Hereinafter, a configuration example of a transistor having a partially different configuration from the transistor exemplified in the above Configuration Example 1 will be described. Note that descriptions of overlapping parts with the above will be omitted, and only the differences will be described in detail. Also, even if the components have different positions and shapes, if their functions are the same, they may be given the same reference numerals and the descriptions may be omitted.

[0106] 〔Modification Example 1〕 Cross-sectional schematic views of the transistor exemplified below are shown in FIGS. 3(A) and (B). Note that the top schematic view can refer to FIG. 1(A). The transistor shown in FIG. 3 is mainly different in that it has an insulating layer 106 between the semiconductor layer 102 and the first protective insulating layer 111.

[0107] The insulating layer 106 provided under the semiconductor layer 102 preferably contains an oxide insulating material that releases oxygen by heating. By providing the insulating layer 106 under the semiconductor layer 102 , more oxygen can be supplied to the semiconductor layer 102 by the heat generated during the manufacturing process of the transistor, such as heat treatment. Also, the structure including the insulating layer 106 and the semiconductor layer 102 and the structure including the insulating layer 106 and the semiconductor layer 102 can be used. By adopting a configuration in which the [object] is surrounded by a first protective insulating layer 111 and a second protective insulating layer 112, oxygen released from the insulating layer 106 is suppressed from being released to the outside (the substrate 101 side or above the second protective insulating layer 112), and oxygen can be more effectively supplied to the semiconductor layer 102. This is possible.

[0108] Also, the insulating layer 106 can be provided so as to cover the upper surface of the first protective insulating layer 111. However, as shown in FIG. 3, it is preferable that the upper surface shapes of the semiconductor layer 102 and the insulating layer 106 are substantially the same and are processed by the same resist mask. With such a configuration, the first protective insulating layer 111 and the second protective insulating layer 112 are in contact with each other in a region where the gate electrode 105 and the pair of electrodes 103 are not provided, thereby blocking the diffusion path of oxygen and effectively supplying oxygen to the semiconductor layer 102.

[0109] The insulating layer 106 preferably uses an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. In the oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition, some oxygen desorbs upon heating. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition is an oxide insulating film in which the desorption amount of oxygen in terms of oxygen atoms is 1 .0×10 . 18 atoms / cm 3 or more, preferably 3.0×10 20 atoms / cm 3 or more as analyzed by temperature programmed desorption spectroscopy (TDS: Thermal Desorption

[0110] As the insulating layer 106, a silicon oxide film or a silicon oxynitride film is formed by plasma CVD method. When forming, as the source gas, a depositable gas containing silicon and an oxidizing gas are preferably used. Representative examples of the depositable gas containing silicon include silane, disilane, tri silane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, di nitrogen oxide, etc.

[0111] For example, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is maintained at 180°C or higher and 260°C or lower, more preferably 200°C or higher and 240°C or lower. Source gas is introduced into the processing chamber to make the pressure in the processing chamber 100 Pa or higher and 250 Pa or lower, more preferably 100 Pa or higher and 200 Pa or lower. High-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied to the electrode provided in the processing chamber, and a silicon oxide film or a silicon oxynitride film is formed under these conditions.

[0112] As the film formation conditions, by supplying high-frequency power with the above power density in the processing chamber with the above pressure, the decomposition efficiency of the source gas increases in the plasma, the oxygen radicals increase, and the oxidation of the source gas proceeds, so that the oxygen content in the oxide insulating film becomes more than the stoichiometric ratio. However, when the substrate temperature is the above temperature, since the bonding force between silicon and oxygen is weak, a part of oxygen desorbs due to heating. As a result, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and from which a part of oxygen desorbs due to heating can be formed.

[0113] 〔Modification Example 2〕 FIG. 4 shows an example in which a capacitive element 120 is formed adjacent to the transistor 100.

[0114] The capacitive element 120 has a dielectric layer 124 formed by processing the same insulating film as the gate insulating layer 104 between one of the pair of electrodes 103 of the transistor 100 and an electrode 125 formed by processing the same conductive film as the gate electrode 10 5.

[0115] Thus, by forming the capacitive element 120 by processing the film used for manufacturing the transistor 100, the capacitive element 120 can be manufactured simultaneously with the manufacturing of the transistor 100 without increasing the number of steps.

[0116] In FIG. 4, a configuration is shown in which one of the pair of electrodes 103 of the transistor 100 is used as one of the electrodes of the capacitive element 120. However, the present invention is not limited to this, and a different electrode formed by processing the same conductive film as the pair of electrodes 103 of the transistor 100 may be used as one of the electrodes of the capacitive element 120. Further, at least one of the gate electrode 105 and the electrode 125, and at least one of the gate insulating layer 1 04 and the dielectric layer 124 may be formed as a continuous integral body and used in common.

[0117] Here, as the material used for the insulating film constituting the gate insulating layer 104 and the dielectric layer 124, it is preferable to use a high dielectric constant material such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate, barium titanate, etc. Further, a material containing a metal such as lanthanum, aluminum, yttrium, or tungsten, or an oxide of these metals may be used. Further, a film containing the above-described material may be laminated and used.

[0118] Further, it is preferable to use an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. By using such an insulating film, oxygen can be supplied from the gate insulating layer 104 to the semiconductor layer 102 by heat such as heat treatment in the manufacturing process of the transistor.

[0119] The above is the description of the modified example.

[0120] [Configuration Example 2] Hereinafter, a configuration example of a transistor having a configuration partially different from that of the above Configuration Example 1 and the like will be described. Note that the description may be omitted for parts overlapping with the above.

[0121] FIG. 5(A) shows a schematic top view of a transistor 200 illustrated in this configuration example. FIGS. 5(B) and 5(C) show schematic cross-sectional views taken along cutting lines E-F and G-H in FIG. 5(A), respectively. Note that some components are not explicitly shown in FIG. 5(A) for clarity.

[0122] The transistor 200 includes an insulating layer 207 having a groove provided on a substrate 201, a semiconductor layer 202 provided on the insulating layer 207 and provided so as to fill the groove, a pair of electrodes 203 provided on the semiconductor layer 202 and electrically connected to the semiconductor layer 202, a gate insulating layer 204 located on the pair of electrodes 203 and overlapping the semiconductor layer 202, and a gate electrode 205 located on the gate insulating layer 204 and overlapping the semiconductor layer 202.

[0123] Further, a first protective insulating layer 211 is provided below the semiconductor layer 202 so as to cover the side surface and the bottom surface of the groove of the insulating layer 207. The first protective insulating layer 211 is as shown in FIG. 5. ​​​​​​​​​​​It is preferably provided so as to cover the upper surface in a region where the groove portion of the sea urchin insulating layer 207 is not provided. Also, a second protective insulating layer 212 is provided so as to cover the pair of electrodes 203 and the gate electrode 205. Furthermore, the first protective insulating layer 211 and the second protective insulating layer 212 are provided in contact with each other in a region where the pair of electrodes 203 and the gate electrode 205 are not provided. The semiconductor layer 202, the pair of electrodes 203, the gate insulating layer 204, the gate electrode 205, etc. can each use the same materials as the semiconductor layer 102, the pair of electrodes 103, the gate insulating layer 104, the gate electrode 105, etc. in Configuration Example 1. Also, the first protective insulating layer 211 and the second protective insulating layer 212 can use the same materials as the first protective insulating layer 111 and the second protective insulating layer 112 in Configuration Example 1.

[0124] The first protective insulating layer 211 is provided so as to cover the side surface and the bottom surface of the groove portion provided in the insulating layer 207, and is further provided so that the semiconductor layer 202 is embedded in the groove portion. Since the side surface and the lower surface of the semiconductor layer 202 are surrounded by the first protective insulating layer 211, diffusion of impurities such as hydrogen from the insulating layer 207 to the semiconductor layer 202 is suppressed, and at the same time, oxygen is released from the semiconductor layer 202 toward the insulating layer 207. This is suppressed.

[0125]

[0126] Also, by adjusting the depth of the groove portion, the thickness of the semiconductor layer 202 can be increased, so that it becomes easy to increase the on-current of the transistor 200 and improve the breakdown voltage between the source and the drain. For example, when a thick semiconductor layer is formed on a flat surface, it is provided on the upper layer thereof. The film may have difficulty covering the semiconductor layer, and the film may be broken or a low-density region may be formed in the film. On the other hand, in this configuration example, the semiconductor layer 202 is provided so as to fill the groove portion, and the height of its upper surface and the height of the upper surface of the first protective insulating layer 211 are formed to be substantially the same. Therefore, the semiconductor layer 202 can be formed thick without adversely affecting the covering property of the film provided in the upper layer thereof. The above is the description of the configuration example of the transistor 200. In the above, the semiconductor layer 202 is provided so as to fill the groove portion, and the height of its upper surface and the height of the upper surface of the first protective insulating layer 211 are formed to be substantially the same. Therefore, the semiconductor layer 202 can be formed thick without adversely affecting the covering property of the film provided in the upper layer thereof. The above is the description of the configuration example of the transistor 200. In the above, the semiconductor layer 202 is provided so as to fill the groove portion, and the height of its upper surface and the height of the upper surface of the first protective insulating layer 211 are formed to be substantially the same. Therefore, the semiconductor layer 202 can be formed thick without adversely affecting the covering property of the film provided in the upper layer thereof.

[0127] The above is the description of the configuration example of the transistor 200.

[0128] [Manufacturing Method Example 2] Hereinafter, an example of the manufacturing method of the transistor 200 illustrated in FIG. 5 will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view in each step of the manufacturing method illustrated below. The above is the description of the configuration example of the transistor 200.

[0129] [Formation of Insulating Layer] First, an insulating layer 207 is formed on the substrate 201.

[0130] The insulating layer 207 can be formed by a sputtering method, a CVD method, an evaporation method, or the like. The above is the description of the configuration example of the transistor 200.

[0131] As the insulating layer 207, an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. The above is the description of the configuration example of the transistor 200. As the insulating layer 207, a film made of different insulating materials may be laminated and used. By making the insulating layer 207 have a laminated structure, the film provided below can be protected from the etching during the formation of the groove portion later. The above is the description of the configuration example of the transistor 200.

[0132] Also, as the insulating layer 207, a film made of different insulating materials may be laminated and used. By making the insulating layer 207 have a laminated structure, the film provided below can be protected from the etching during the formation of the groove portion later. The above is the description of the configuration example of the transistor 200. It can function as an etching stopper.

[0133] 〔Formation of groove portion〕 Subsequently, a resist mask is formed on the insulating layer 207 using a photolithography method or the like. The upper portion of the insulating layer 207 is removed by etching. Then, the resist mask is removed. By doing so, a groove portion can be formed in the insulating layer 207.

[0134] Here, as described above, by making the insulating layer 207 a multilayer structure made of different materials, etching can be made easier. Furthermore, it is preferable to use the layer provided below as an etching stopper, because the bottom surface of the groove portion can be made flat.

[0135] Also, when the depth of the groove portion is made large, there is a risk that the resist mask will disappear during etching. In that case, a thin film made of a material that is difficult to etch (that is, a material having a large selectivity of the insulating layer 207 with respect to the thin film) is formed in advance, and the thin film is etched with a resist mask. Then, the groove portion may be formed by etching the upper portion of the insulating layer 207 using the thin film as a hard mask. When the thin film used as the hard mask is insulating, the hard mask may be left as it is after the formation of the groove portion.

[0136] 〔Formation of first protective insulating layer〕 Subsequently, a first protective insulating layer 211 is formed on the insulating layer 207 so as to cover the side surface and the bottom surface of the groove portion (Fig. 6(A)).

[0137] The film formation of the first protective insulating layer 211 is performed in the same manner as the first protective insulating layer 111 in Production Method Example 1. ​​​​​​​​​​

[0138] [Formation of Semiconductor Layer] Subsequently, a semiconductor film is formed on the first protective insulating layer 211. When the groove portion is completely filled with the semiconductor film, it is preferable to form the film so that the height of the upper surface of the portion of the semiconductor film overlapping the groove portion is equal to or higher than the height of the portion of the first protective insulating layer 211 that does not overlap the groove portion.

[0139] The semiconductor film can be formed in the same manner as in Production Method Example 1 described above.

[0140] After forming the semiconductor film, a heat treatment may be performed. The heat treatment can be performed in the same manner as in Production Method Example 1 described above. By the heat treatment, oxygen is supplied from the first protective insulating layer 211 to the semiconductor film (or semiconductor layer 202), and oxygen deficiencies in the oxide semiconductor contained in the semiconductor layer 202 can be reduced. Note that the heat treatment may be performed immediately after forming the semiconductor film, or may be performed after processing the semiconductor film to form island-shaped semiconductor layers 202.

[0141] Subsequently, a planarization process is performed to process the upper surface of the semiconductor film so that it coincides with the upper surface of the portion of the first protective insulating layer 211 that does not overlap the groove portion, thereby forming island-shaped semiconductor layers 202 embedded in the groove portion (FIG. 6(B)).

[0142] As the planarization process, for example, a polishing process such as CMP (Chemical Mechanical Polishing) or an etching process may be used.

[0143] Here, when aluminum oxide or the like is used as the first protective insulating layer 211 and a polishing process such as CMP is used as the planarization process, the first protective insulating layer 211 serves as an etching stopper. It can be made to function. Therefore, the thickness reduction of the semiconductor layer 202 due to the planarization process can be suppressed, and furthermore, the variation in its thickness can also be reduced. It can be suppressed that the thickness becomes thinner, and furthermore, the variation in the thickness can also be reduced.

[0144] 〔Formation of a pair of electrodes〕 Subsequently, a conductive film is formed on the first protective insulating layer 211 and the semiconductor layer 202. Then Using a photolithography method or the like, a resist mask is formed on the conductive film, and unnecessary parts of the conductive film are removed by etching. Then, by removing the resist mask, a pair of electrodes 203 can be formed (Fig. 6(C)).

[0145] The conductive film can be formed by, for example, a sputtering method, an evaporation method, a CVD method, etc. It can be formed.

[0146] Here, as shown in Fig. 6(C), during the etching of the conductive film, a part of the upper portion of the semiconductor layer 202 may be etched, and the portion that does not overlap with the pair of electrodes 203 may be thinned. Thus it is preferable to form the thickness of the semiconductor film that becomes the semiconductor layer 202 (i.e., the depth of the groove portion) thicker in advance in consideration of the depth to be etched.

[0147] Also, although not shown in the figure, during the etching of the conductive film, a part of the first protective insulating layer 211 may also be etched and thinned.

[0148] 〔Formation of the gate insulating layer and the gate electrode〕 Subsequently, an insulating film is formed on the semiconductor layer 202, the pair of electrodes 203, and the first protective insulating layer 211. Furthermore, a conductive film is formed on the insulating film. Then, using a photolithography method or the like a resist mask is formed on the conductive film, and unnecessary parts of the conductive film and the insulating film are etched ​Remove it. Then, by removing the resist mask, the gate electrode 205 and the gate insulating layer 204 can be formed (Fig. 6(D)).

[0149] The insulating film that becomes the gate insulating layer 204 and the conductive film that becomes the gate electrode 205 can be formed by the same method as in the above manufacturing method example 1.

[0150] Here, the gate insulating layer 204 is etched simultaneously when the gate electrode 205 is formed, and the case where the gate insulating layer 204 is processed so as to have the same upper surface shape as the gate electrode 205 will be described. However, they may be individually processed so that the gate insulating layer 204 has an upper surface shape that extends outside the gate electrode 205. At this time, as an exposure mask used in the photolithography method or the like, a multi-tone mask such as a grayscale mask or a halftone mask is preferably used because the process can be simplified.

[0151] 〔Formation of the second protective insulating layer〕 Subsequently, a second protective insulating layer 212 is formed on the first protective insulating layer 211, the pair of electrodes 203, the gate insulating layer 204, and the gate

[0152] electrode 205 (Fig. 6(E)). The second protective insulating layer 212 can be formed by the same method as the first protective insulating layer 211.

[0153] Here, the second protective insulating layer 212 is provided so as to be in contact with the first protective insulating layer 211 in a region where the pair of electrodes 203 and the gate electrode 205 are not provided. Therefore, the semiconductor layer 202 can be surrounded by the first protective insulating layer 211 and the second protective insulating layer 212.

[0154] ​​​​​ Through the above steps, the transistor 200 can be fabricated.

[0155] 〔Heat treatment〕 After the formation of the second protective insulating layer 212, heat treatment may be performed. By the heat treatment, oxygen can be supplied to the semiconductor layer 202 from the first protective insulating layer 211 and the second protective insulating layer 212, and oxygen deficiency in the semiconductor layer 202 can be reduced. Also at this time, the first protective insul ating layer 211 and the second protective insulating layer 212 can suppress the release of oxygen from the semiconductor layer 202 and suppress the formation of oxygen deficiency in the semiconductor layer 202.

[0156] The above is the description of an example of the manufacturing process of the transistor 200.

[0157] [Modification example of Configuration example 2] Hereinafter, a configuration example of a transistor having a partially different configuration from the transistor exemplified in the above Configuration example 2 will be described. Note that descriptions of parts overlapping with the above will be omitted, and only the differences will be described in detail. Also, even for constituent elements having different positions and shapes, if their functions are the same, they may be given the same reference numerals and the description may be omitted.

[0158] 〔Modification example 1〕 FIGS. 7(A) and (B) show schematic cross-sectional views of the transistor exemplified below. Note that the top surface schematic view can refer to FIG. 5(A). The transistor shown in FIG. 7 is different mainly in that an insulating layer 206 is provided between the semiconductor layer 202 and the first protective insulating layer 211.

[0159] In the groove provided in the insulating layer 207, the insulating layer 206 is provided so as to cover the side surface and the top surface of the first protective insulating layer 211. Also, the insulating layer 206 is on the side surface of the semiconductor layer 202 and ​​​​ It is provided so as to cover the upper surface and the lower surface.

[0160] As the insulating layer 206 provided below the semiconductor layer 202, it preferably contains an oxide insulating material that releases oxygen by heating. By providing the insulating layer 206 below the semiconductor layer 202, more oxygen can be supplied to the semiconductor layer 202 by the heat generated during the heat treatment or the like in the manufacturing process of the transistor. Also, by configuring to surround the structure including the insulating layer 206 and the semiconductor layer 202 with the first protective insulating layer 211 and the second protective insulating layer 212, the oxygen released from the insulating layer 206 is suppressed from being released to the outside (above the insulating layer 207 side or above the second protective insulating layer 212), and oxygen can be supplied to the semiconductor layer 202 more effectively.

[0161] Also, the insulating layer 206 can be provided so as to cover the upper surface of the region that does not overlap with the groove portion of the first protective insulating layer 211, but it is preferably processed to be provided inside the groove portion by a planarization process. With such a configuration, the first protective insulating layer 211 and the second protective insulating layer 212 are in contact with each other in the region where the gate electrode 205 and the pair of electrodes 203 are not provided, thereby blocking the diffusion path of oxygen and effectively supplying oxygen to the semiconductor layer 202.

[0162] Similar to the insulating layer 106, it is preferable to use an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition for the insulating layer 206.

[0163] [Modification Example 2] FIG. 8 shows an example in which a capacitor element 220 is formed adjacent to the transistor 200.

[0164] The capacitive element 220 has a dielectric layer 224 formed by processing an insulating film identical to the gate insulating layer 204 between one of the pair of electrodes 203 of the transistor 200 and an electrode 225 formed by processing the same conductive film as the gate electrode 20 5. Thus, by forming the capacitive element 220 by processing the film used for manufacturing the transistor 200, the capacitive element 220 can be manufactured simultaneously with the manufacturing of the transistor 200 without increasing the number of processes.

[0165] In FIG. 8, a configuration is shown in which one of the pair of electrodes 203 of the transistor 200 is used as one of the capacitive element 220. However, the present invention is not limited to this, and as one of the electrodes of the capacitive element 220, a different electrode formed by processing the same conductive film as the pair of electrodes 203 of the transistor 200 may be used. Further, at least one of the gate electrode 205 and the electrode 225, and at least one of the gate insulating layer 204 and the dielectric layer 224 may be used in common as a continuous integral body.

[0166] Here, as the material used for the insulating film constituting the gate insulating layer 204 and the dielectric layer 224, it is preferable to use a high dielectric constant material such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate, or barium titanate. Further, a material containing a metal such as lanthanum, aluminum, yttrium, or tungsten, or an oxide of these metals may be used. Further, a film containing the above-described material may be laminated and used.

[0167] Further, the insulating film is an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition.

[0168] It is preferable to use a film. By using such an insulating film, oxygen can be supplied from the gate insulating layer 204 to the semiconductor layer 202 due to the heat generated during the heat treatment in the manufacturing process of the transistor. During the heat treatment in the manufacturing process of the transistor, oxygen can be supplied from the gate insulating layer 204 to the semiconductor layer 202 due to the heat generated. It is possible to supply oxygen.

[0169] 〔Modification Example 3〕 When arranging a plurality of transistors on a substrate, instead of providing one groove for each transistor, a configuration is adopted in which one groove is provided for a plurality of transistors, so that the transistors can be integrated at a higher density. By adopting a configuration in which one groove is provided for a plurality of transistors instead of providing one groove for each transistor, the transistors can be integrated at a higher density. It is possible to integrate the transistors at a higher density.

[0170] As an example, in FIG. 9, when four transistors 200 are connected in series, a case is shown where four transistors 200 are formed on top of one groove provided in the insulating layer 207. FIG. 9(A) is a top schematic view, and FIG. 9(B) is a cross-sectional schematic view taken along the cutting line I-J in FIG. 9(A). As shown in FIG. 9(B), four transistors 200 are formed on top of one groove formed in the insulating layer 207. Also, in two adjacent transistors 200, a common electrode 203 is provided, so that the two transistors 200 are connected in series. On the other hand, the gate electrodes 205 are provided independently for each transistor 200. FIG. 9(B) shows a cross-sectional schematic view taken along the cutting line I-J in FIG. 9(A). It is a cross-sectional schematic view taken along the cutting line I-J in FIG. 9(A).

[0171] As shown in FIG. 9(B), four transistors 200 are formed on top of one groove formed in the insulating layer 207. In two adjacent transistors 200, a common electrode 203 is provided, so that the two transistors 200 are connected in series. By providing a common electrode 203, the two transistors 200 are connected in series. On the other hand, the gate electrodes 205 are provided independently for each transistor 200. They are provided independently for each transistor 200.

[0172] The first protective insulating layer 211 and the second protective insulating layer 212 are in contact with each other in a region outside the electrodes 203 provided at both ends, and are provided so as to surround the four transistors 200. The first protective insulating layer 211 and the second protective insulating layer 212 are in contact with each other in a region outside the electrodes 203 provided at both ends, and are provided so as to surround the four transistors 200.

[0173] An example of a circuit configuration to which such transistors 200 connected in series can be applied is shown in FIG. 9( It is shown in FIG. 9(C). The circuit shown in FIG. 9(C) has four transistors and three capacitive elements. In two adjacent transistors, one of the source or drain of one transistor is electrically connected to the source or drain of the other transistor to form a node, and one electrode of the capacitive element is electrically connected to the node. For example, in two adjacent transistors, one of the source or drain of one transistor is electrically connected to the source or drain of the other transistor to form a node, and one electrode of the capacitive element is electrically connected to the node. For example, in two adjacent transistors, one of the source or drain of one transistor is electrically connected to the source or drain of the other transistor to form a node, and one electrode of the capacitive element is electrically connected to the node. For example, in two adjacent transistors, one of the source or drain of one transistor is electrically connected to the source or drain of the other transistor to form a node, and one electrode of the capacitive element is electrically connected to the node.

[0174] For example, the capacitive element can apply the configuration of the capacitive element 220 exemplified in the above Modification 2. For example, the capacitive element can apply the configuration of the capacitive element 220 exemplified in the above Modification 2.

[0175] The circuit shown in FIG. 9(C) can function as, for example, a shift register by applying the following potentials. The circuit shown in FIG. 9(C) can function as, for example, a shift register by applying the following potentials.

[0176] A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right. A common potential is applied to the other electrode of each of the three capacitive elements. Among the four transistors, the same clock signal (CLK1) is applied to the gates of the first and third transistors from the left, and the same clock signal (CLK2) is applied to the gates of the second and fourth transistors. Also, an input terminal to which an input potential (IN) is applied to one of the source or drain of the first transistor, and an output terminal from which an output potential (OUT) is output to one of the source or drain of the fourth transistor. By using clock signals CLK1 and CLK2 as potentials (for example, high-level potentials) that alternately turn on the transistors without overlapping, the information of the potential applied to the input terminal can be shifted from left to right.

[0177] Also, the configuration shown in FIG. 9(D) is a configuration in which a plurality of reading transistors 260 are serially connected to the circuit of FIG. 9(C). Each of the transistors 260 is a capacitive element. Also, the configuration shown in FIG. 9(D) is a configuration in which a plurality of reading transistors 260 are serially connected to the circuit of FIG. 9(C). Each of the transistors 260 is a capacitive element. It is electrically connected to the node of one electrode. Also, on the other electrode of each capacitive element, a potential for reading is applied. By adopting such a configuration, the circuit shown in FIG. 9(D) can function as a NAND-type memory device that can read at any time the information of the potential held at the node to which one electrode of the capacitive element is connected. Here, for example, transistor 26 0 may be a transistor to which an oxide semiconductor is applied in the same manner as transistor 200, and as exemplified in the following embodiments, a transistor to which a different semiconductor is applied may be used.

[0178] The above is the description of the modification.

[0179] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0180] (Embodiment 2) In this embodiment, a configuration example of a transistor that is partially different in configuration from the transistor exemplified in Embodiment 1 will be described. For parts that overlap with the above, the description will be omitted, and only the differences will be described in detail. Also, even for components that are different in position and shape, if their functions are the same, they may be given the same reference numerals and the description may be omitted.

[0181] A semiconductor device according to one aspect of the present invention preferably has an oxide layer containing at least one metal element among the metal elements constituting the oxide semiconductor layer between the oxide semiconductor layer and the gate insulating layer and the protective insulating layer overlapping the oxide semiconductor layer. Thereby, trap levels are formed at the interface between the oxide semiconductor layer and the insulating layer overlapping the oxide semiconductor layer. Since the above-mentioned problem can be prevented, deterioration of the electrical characteristics of the transistor can be prevented. .

[0182] That is, in one embodiment of the present invention, at least the upper surface and the lower surface of the oxide semiconductor layer are made of an oxide semiconductor. The oxide layer acts as a barrier to prevent the formation of interface states in the carbon nanotube layer. The top and side surfaces of the oxide semiconductor layer in the panel width direction are connected to the gate electrode via the gate insulating layer. an insulating layer including an aluminum oxide film so as to cover the oxide semiconductor layer and to enclose the oxide semiconductor layer; In the above-described structure, the oxide semiconductor layer The formation of oxygen vacancies and the inclusion of impurities, which are factors that cause carrier generation in the semiconductor and at the interface, are suppressed. Since the oxide semiconductor layer can be highly purified and intrinsic, The term "oxidizing" refers to making the oxide semiconductor layer intrinsic or substantially intrinsic. This suppresses fluctuations in the electrical characteristics of transistors that include an organic semiconductor layer, thereby providing highly reliable semiconductor devices. It will be possible to provide

[0183] Note that in the case of being substantially intrinsic in this specification and the like, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 By making the oxide semiconductor layer highly intrinsic, the transistor has stable electrical characteristics. It is possible to give the

[0184] More specifically, for example, the following configuration can be adopted.

[0185] [Configuration example 1] FIG. 10(A) and (B) show schematic cross-sectional views of the transistor 150 exemplified below. Note that for the top view, FIG. 1(A) can be cited. The transistor 150 shown in FIG. 10 is different from the transistor 100 exemplified in Embodiment 1 in that it mainly has a first oxide layer 151 and a second oxide layer 152.

[0186] The first oxide layer 151 is provided between the first protective insulating layer 111 and the semiconductor layer 102. Also, the second oxide layer 152 is provided between the semiconductor layer 102 and the gate insulating layer 104.

[0187] More specifically, the upper surface of the second oxide layer 152 is provided in contact with the lower surfaces of the pair of electrodes 103 and also the lower surface of the gate insulating layer 104.

[0188] The first oxide layer 151 and the second oxide layer 152 each contain an oxide containing one or more of the same metal elements as the semiconductor layer 102.

[0189] Note that the boundary between the semiconductor layer 102 and the first oxide layer 151 or the boundary between the semiconductor layer 102 and the second oxide layer 152 may be unclear.

[0190] For example, the first oxide layer 151 and the second oxide layer 152 contain In or Ga, and typically, In-Ga-based oxides, In-Zn-based oxides, In-M-Zn-based oxides ( M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), and a material whose energy at the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 102 is used. Typically, the energy at the lower end of the conduction band of the first oxide layer 151 or the second oxide layer 152 and the semiconductor ​​​​The difference from the energy at the lower end of the conduction band of layer 102 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, which is preferable.

[0191] By using the first oxide layer 151 and the second oxide layer 1 provided so as to sandwich the semiconductor layer 102 52, an oxide having a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 can suppress the release of oxygen from the semiconductor layer 102.

[0192] When using an In-Ga-Zn-based oxide with an atomic ratio of, for example, In:Ga:Zn = 1:1:1 or 3:1:2 as the semiconductor layer 102, the first oxide layer 151 or the second oxide layer 152 can use an In-Ga-Zn-based oxide with an atomic ratio of, for example, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1 :6:4, 1:6:8, 1:6:10, or 1:9:6. Note that the atomic ratios of the semiconductor layer 102, the first oxide layer 151, and the second oxide layer 152 each include a fluctuation of plus or minus 20% of the above atomic ratio as an error. Also, the first oxide layer 151 and the second oxide layer 152 may use the same material in terms of composition or materials with different compositions.

[0193] Also, when using an In-M-Zn-based oxide as the semiconductor layer 102, the target used to form the semiconductor film that becomes the semiconductor layer 102 has an atomic ratio of the metal elements contained in the target of In:M:Zn = x1:y1:z1. When this is the case, the value of x1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, preferably It is preferable to use an oxide having an atomic ratio of 1 or more and 6 or less. Note that by setting z1 / y1 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, and the like.

[0194] In addition, when an In-M-Zn-based oxide is used as the first oxide layer 151 and the second oxide layer 152, to form an oxide film that becomes the first oxide layer 151 and the second oxide layer 152, the target used has an atomic ratio of the metal elements contained in the target of In:M:Zn = x2:y2:z2, when x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio of z2 / y2 of 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. Note that by setting z2 / y2 to 6 or less, it becomes easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, and the like.

[0195] In addition, by using a material having an energy at the lower end of the conduction band closer to the vacuum level for the first oxide layer 151 and the second oxide layer 152 than for the semiconductor layer 102, a channel is mainly formed in the semiconductor layer 102, and the semiconductor layer 102 becomes the main current path. In this way, by sandwiching the semiconductor layer 102 in which the channel is formed with the first oxide layer 151 and the second oxide layer 152 containing the same metal element, the generation of these interface levels is suppressed, and the reliability of the electrical characteristics of the transistor is improved. Note that the present invention is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect characteristics) of the transistor, ...

[0196] However, it is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect ​Depending on the fruit mobility, threshold voltage, etc., a material with an appropriate composition may be used. Also, to obtain the semiconductor characteristics of the required transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer 102, the first oxide layer 151, and the second oxide layer 152 are preferably made appropriate.

[0197] Here, the thickness of the semiconductor layer 102 is preferably formed to be at least thicker than the first oxide layer 151. The thicker the semiconductor layer 102, the higher the on-current of the transistor can be increased. Also, the first oxide layer 151 may have a thickness such that the effect of suppressing the generation of interface levels in the semiconductor layer 102 is not lost. For example, the thickness of the semiconductor layer 102 is greater than 1 times, preferably 2 times or more, more preferably 4 times or more, more preferably 6 times or more, the thickness of the first oxide layer 151.

[0198] Also, the second oxide layer 152 may have a thickness such that the effect of suppressing the generation of interface levels in the semiconductor layer 102 is not lost, similar to the first oxide layer 151. For example, it may have a thickness equal to or less than that of the first oxide layer 151. If the second oxide layer 152 is thick, there is a risk that the electric field by the gate electrode 105 may not easily reach the semiconductor layer 102. Therefore, the second oxide layer 152 is preferably formed thin. Note that this is not limited thereto, and the thickness of the second oxide layer 152 may be appropriately set according to the voltage for driving the transistor 150 in consideration of the breakdown voltage of the gate insulating layer 104.

[0199] Also, as shown in FIG. 10(B), from the lower surface of the oxide layer 151, around the oxide layer 151 Lower the upper surface of the first protective insulating layer 111 in the enclosure so that the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102 It is preferable to adopt a configuration in which the lower part of the side surface of the semiconductor layer 102 is sufficiently affected by the electric field of the gate electrode 105, and the on-current of the transistor 150 can be increased Similarly, as shown in FIG. 27, if the lower surface of the gate electrode 105 is lower than the lower surface of the oxide layer 151, the on-current of the transistor 150 can be further increased which is preferable.

[0200] Here, the band structure in the channel formation region of the transistor 150 will be described .

[0201] FIGS. 11(A) and (B) schematically show the energy band structure in the thickness direction of the channel formation region.

[0202] In FIGS. 11(A) and (B), EcI1, EcS1, EcS2, EcS3, EcI2 respectively schematically show the energies of the lower ends of the conduction bands of the first protective insulating layer 111, the first oxide layer 151, the semiconductor layer 102, the second oxide layer 152, and the gate insulating layer 104. Here, for the sake of convenience, the thicknesses of the respective layers are not considered .

[0203] Here, the difference between the vacuum level and the energy of the lower end of the conduction band (also called electron affinity) is the value obtained by subtracting the energy gap from the difference between the vacuum level and the energy of the upper end of the valence band (also called ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (for example HORIBA JOBIN YVON's UT-300). Also, the energy difference between the vacuum level and the upper end of the valence band can be measured by ultraviolet photoelectron spectroscopy (UPS: Ultrav ​​​​iolet Photoelectron Spectroscopy (e.g. Measurements can be performed using a HI VersaProbe.

[0204] As shown in FIG. 11A, a first oxide layer 151, a semiconductor layer 102, a second oxide layer In 152, the energy of the conduction band minimum changes continuously with no barrier between them. This is because the compositions of the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are similar to each other. This allows oxygen to easily diffuse between the two layers, forming what may be called a mixed layer between the two layers. This is understandable.

[0205] In FIG. 11A, the first oxide layer 151 and the second oxide layer 152 are formed in the same energy state. The case of oxide layers with different energy gaps has been shown. For example, EcS3 is higher than EcS1. At higher energies, a portion of the band structure is shown in FIG. 11(B). Although not shown, EcS1 may have higher energy than EcS3.

[0206] 11A and 11B, the semiconductor layer 102 forms a well in the channel formation region. ), and it can be seen that a channel is formed in the semiconductor layer 102. 151, the semiconductor layer 102, and the second oxide layer 152 have a continuous conduction band minimum energy. Since the well is gradually changing, it can also be called a U Shape Well. A channel formed in this manner can also be called a buried channel.

[0207] The first oxide layer 151 and the second oxide layer 152 are formed of metal elements constituting the semiconductor layer 102. Since it is an oxide containing one or more elements, the stacked structure in which the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked can also be said to be an oxide stack in which the main components are stacked in common. (Hereinafter, the stacked structure in which the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked is also referred to as an oxide stack.) The oxide stack in which the main components are stacked in common is not simply stacked with each layer, but is produced so that a continuous junction (here, in particular, a U-shaped well structure in which the energy of the lower end of the conduction band changes continuously between the layers) is formed. This is because if impurities that form defect levels such as trap centers or recombination centers are mixed at the interface of each layer, the continuity of the energy band is lost, and carriers disappear due to trapping or recombination at the interface. To form a continuous junction, it is preferable to continuously stack each layer without exposing it to the atmosphere using a multi-chamber film-forming apparatus (for example, a sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump in order to remove water and the like that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow back into the chamber from the exhaust system. In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas. Oxygen gas or argon gas used as the sputtering gas Since it is an oxide containing one or more elements, the stacked structure in which the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked can also be said to be an oxide stack in which the main components are stacked in common. (Hereinafter, the stacked structure in which the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked is also referred to as an oxide stack.) The oxide stack in which the main components are stacked in common is not simply stacked with each layer, but is produced so that a continuous junction (here, in particular, a U-shaped well structure in which the energy of the lower end of the conduction band changes continuously between the layers) is formed.

[0208] To form a continuous junction, it is preferable to continuously stack each layer without exposing it to the atmosphere using a multi-chamber film-forming apparatus (for example, a sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is evacuated to a high vacuum (up to about 5×10 Pa to 1×10 Pa) using an adsorption-type vacuum exhaust pump such as a cryopump in order to remove water and the like that become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow back into the chamber from the exhaust system. In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas. Oxygen gas or argon gas used as the sputtering gas Since it is an oxide containing one or more elements, the stacked structure in which the first oxide layer 151, the semiconductor layer 102, and the second -7 Pa~1×10 -4 Pa degree) is preferably done. Or, it is preferable to combine a turbo molecular pump and a cold trap so that gas does not flow back into the chamber from the exhaust system. In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas. Oxygen gas or argon gas used as the sputtering gas

[0209] In order to obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas. Oxygen gas or argon gas used as the sputtering gas should be highly purified. By using a gas purified to a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor as much as possible.

[0210] The first oxide layer 151 and the second oxide layer 152 provided on the upper layer or the lower layer of the semiconductor layer 102 function as barrier layers, and the influence of trap levels formed at the interface between the oxide stack and the insulating layers (the first protective insulating layer 111 and the gate insulating layer 104) in contact with the oxide stack can be suppressed from reaching the semiconductor layer 102, which is the main path (carrier path) of carriers in the transistor.

[0211] For example, oxygen deficiencies contained in the semiconductor layer manifest as localized levels existing at deep energy positions within the energy gap of the oxide semiconductor. When carriers are trapped at such localized levels, the reliability of the transistor decreases, so it is necessary to reduce the oxygen deficiencies contained in the semiconductor layer. In the oxide stack, by providing oxide layers that are less likely to generate oxygen deficiencies in contact with the upper and lower sides of the semiconductor layer 102, the oxygen deficiencies in the semiconductor layer 102 can be reduced. For example, the semiconductor layer 102 can have an absorption coefficient due to localized levels measured by the constant photocurrent method (CPM) of less than 1×10 02. / cm, preferably less than 1×10 -3 -4 / cm.

[0212] In addition, when the semiconductor layer 102 is an insulating layer having different constituent elements (for example, an insulating layer including a silicon oxide film) When it is in contact with the (layer), an interface level is formed at the interface between the two layers, and the interface level forms a channel which may occur. In such a case, a second transistor with a different threshold voltage appears, and the apparent threshold voltage of the transistor may vary. However, in the oxide stack, since the first oxide layer 151 contains one or more metal elements constituting the semiconductor layer 102 and has it, it is difficult to form an interface level at the interface between the first oxide layer 151 and the semiconductor layer 102 . Therefore, by providing the first oxide layer 151, the variation in the threshold voltage and other electrical characteristics of the transistor can be reduced .

[0213] Also, when a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, interface scattering occurs at the interface , and the field-effect mobility of the transistor decreases. However, in the oxide stack, since the second oxide layer 152 contains one or more metal elements constituting the semiconductor layer 102 and has it, carrier scattering hardly occurs at the interface between the semiconductor layer 102 and the second oxide layer 152, and the field-effect mobility of the transistor can be increased .

[0214] [Configuration Example 2] FIGS. 12(A) and (B) show schematic cross-sectional views of the transistor 160 exemplified below. Note that for the top view, FIG. 1(A) can be cited. The transistor 160 shown in FIG. 12 differs from the above-described transistor 150 mainly in that the shape of the second oxide layer 152 is different .

[0215] In the transistor 160, the lower surface of the second oxide layer 152 is provided in contact with the upper surfaces of the pair of electrodes 103 respectively. Further, the pair of electrodes 103 are not provided ​​In the i-region, it is provided in contact with the upper surface and the side surface of the semiconductor layer 102.

[0216] In the configuration shown in FIG. 12, the upper surface shapes of the second oxide layer 152 and the gate insulating layer 104 are processed using the same photomask so as to substantially coincide with the upper surface shape of the gate electrode 105. Also, the second protective insulating layer 112 is provided in contact with each end of the second oxide layer 152 and the gate insulating layer 104. By adopting such a configuration, desorption of elements from the semiconductor layer 102 can be suppressed via the ends of the second oxide layer 152 and the gate insulating layer 104.

[0217] Also, as shown in FIG. 12(B), the semiconductor layer 102 of the transistor 160 is provided in contact with the second oxide layer 152 not only on its upper surface but also on its side surface. That is, the channel formation region of the semiconductor layer 102 is configured to be surrounded by the first oxide layer 151 and the second oxide layer 152.

[0218] By adopting such a configuration, the formation of interface states can be suppressed also on the side surface of the semiconductor layer 102 by the second oxide layer 152 provided in contact with the side surface of the semiconductor layer 102. As a result, even when the channel formed near the side surface of the semiconductor layer 102 is actively used, fluctuations in the electrical characteristics of the transistor can be suppressed, and a transistor having a high on-current and high reliability can be realized.

[0219] Also, as shown in FIG. 12(B), the upper surface of the first protective insulating layer 111 in the periphery of the oxide layer 151 is made lower than the lower surface of the oxide layer 151, and the gate electrode 105 is formed on the semiconductor layer 102. ​​​​​It is preferable to adopt a configuration that surrounds the lower part of the side surface. As a result, an electric field generated by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 160 can be increased. Similarly, as shown in FIG. 28, if the lower surface of the gate electrode 105 is made lower than the lower surface of the oxide layer 151, it is preferable because the on-current of the transistor 160 can be further increased. In addition, the insulating layer 106 that releases oxygen by heating, as exemplified in Embodiment 1, can also be applied. FIGS. 13(A) and 13(B) show schematic cross-sectional views of a transistor 170 having a configuration different from that of the transistor 160. The transistor 170 is different from the transistor 160 mainly in that it has an insulating layer 106 between the first oxide layer 151 and the first protective insulating layer 111.

[0220] As shown in FIGS. 13(A) and 13(B), the semiconductor layer 102, the first oxide layer 151, and the insulating layer 106 are processed into an island shape, a second oxide layer 152 is provided so as to cover them, and further, by providing the first protective insulating layer 111 on the lower side, oxygen released from the insulating layer 106 can be more effectively supplied to the semiconductor layer 102 through the first oxide layer 151. Also, as shown in FIG. 13(B), it is preferable that the upper surface of the first protective insulating layer 111 around the insulating layer 106 is made lower than the lower surface of the insulating layer 106, and the gate electrode 105 is configured to surround the lower part of the side surface of the semiconductor layer 102. As a result, an electric field is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 160 can be increased.

[0221]

[0222]

[0223]

[0224] ​​​​​​​​​​​The electric field by the gate electrode 105 is sufficiently applied, and the on-current of the transistor 170 can be increased. Similarly, as shown in FIGS. 29(A) and (B), if the lower surface of the gate electrode 105 is made lower than the lower surface of the oxide layer 151, it is preferable because the on-current of the transistor 170 can be further increased. Similarly, as shown in FIGS. 29(A) and (B), if the lower surface of the gate electrode 105 is made lower than the lower surface of the oxide layer 151, it is preferable because the on-current of the transistor 170 can be further increased. Similarly, as shown in FIGS. 29(A) and (B), if the lower surface of the gate electrode 105 is made lower than the lower surface of the oxide layer 151, it is preferable because the on-current of the transistor 170 can be further increased.

[0225] Also, FIGS. 13(C) and (D) show schematic cross-sectional views of a transistor 180 having a configuration partially different from that of the transistor 170. The transistor 180 has an insulating layer 106 that is not processed into an island shape, a first oxide layer 151, and a second oxide layer 152. Such a configuration can be realized by using a material having a sufficiently large bandgap as the first oxide layer 151 and the second oxide layer 152. Also, FIGS. 13(C) and (D) show schematic cross-sectional views of a transistor 180 having a configuration partially different from that of the transistor 170. The transistor 180 has an insulating layer 106 that is not processed into an island shape, a first oxide layer 151, and a second oxide layer 152. Such a configuration can be realized by using a material having a sufficiently large bandgap as the first oxide layer 151 and the second oxide layer 152. Also, FIGS. 13(C) and (D) show schematic cross-sectional views of a transistor 180 having a configuration partially different from that of the transistor 170. The transistor 180 has an insulating layer 106 that is not processed into an island shape, a first oxide layer 151, and a second oxide layer 152. Such a configuration can be realized by using a material having a sufficiently large bandgap as the first oxide layer 151 and the second oxide layer 152. Also, FIGS. 13(C) and (D) show schematic cross-sectional views of a transistor 180 having a configuration partially different from that of the transistor 170. The transistor 180 has an insulating layer 106 that is not processed into an island shape, a first oxide layer 151, and a second oxide layer 152. Such a configuration can be realized by using a material having a sufficiently large bandgap as the first oxide layer 151 and the second oxide layer 152. Also, FIGS. 13(C) and (D) show schematic cross-sectional views of a transistor 180 having a configuration partially different from that of the transistor 170. The transistor 180 has an insulating layer 106 that is not processed into an island shape, a first oxide layer 151, and a second oxide layer 152. Such a configuration can be realized by using a material having a sufficiently large bandgap as the first oxide layer 151 and the second oxide layer 152.

[0226] When the configuration of the transistor 180 is adopted, in a region not shown, the insulating layer 106, the first oxide layer 151, and the second oxide layer 152 are etched, and it is preferable to provide a region where the first protective insulating layer 111 and the second protective insulating layer 112 are in contact. For example, a configuration in which a plurality of transistors are provided in a region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112 may be adopted. When the configuration of the transistor 180 is adopted, in a region not shown, the insulating layer 106, the first oxide layer 151, and the second oxide layer 152 are etched, and it is preferable to provide a region where the first protective insulating layer 111 and the second protective insulating layer 112 are in contact. For example, a configuration in which a plurality of transistors are provided in a region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112 may be adopted. When the configuration of the transistor 180 is adopted, in a region not shown, the insulating layer 106, the first oxide layer 151, and the second oxide layer 152 are etched, and it is preferable to provide a region where the first protective insulating layer 111 and the second protective insulating layer 112 are in contact. For example, a configuration in which a plurality of transistors are provided in a region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112 may be adopted. When the configuration of the transistor 180 is adopted, in a region not shown, the insulating layer 106, the first oxide layer 151, and the second oxide layer 152 are etched, and it is preferable to provide a region where the first protective insulating layer 111 and the second protective insulating layer 112 are in contact. For example, a configuration in which a plurality of transistors are provided in a region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112 may be adopted. When the configuration of the transistor 180 is adopted, in a region not shown, the insulating layer 106, the first oxide layer 151, and the second oxide layer 152 are etched, and it is preferable to provide a region where the first protective insulating layer 111 and the second protective insulating layer 112 are in contact. For example, a configuration in which a plurality of transistors are provided in a region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112 may be adopted.

[0227] Also, as shown in FIG. 13(D), it is preferable that the upper surface of the first protective insulating layer 111 in the periphery of the semiconductor layer 102 is made lower than the lower surface of the semiconductor layer 102, and the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102. As a result, the electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 180 can be increased. Similarly, as shown in FIGS. 29(C) and (D), below the semiconductor layer 102 Also, as shown in FIG. 13(D), it is preferable that the upper surface of the first protective insulating layer 111 in the periphery of the semiconductor layer 102 is made lower than the lower surface of the semiconductor layer 102, and the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102. As a result, the electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 180 can be increased. Similarly, as shown in FIGS. 29(C) and (D), below the semiconductor layer 102 Also, as shown in FIG. 13(D), it is preferable that the upper surface of the first protective insulating layer 111 in the periphery of the semiconductor layer 102 is made lower than the lower surface of the semiconductor layer 102, and the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102. As a result, the electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 180 can be increased. Similarly, as shown in FIGS. 29(C) and (D), below the semiconductor layer 102 Also, as shown in FIG. 13(D), it is preferable that the upper surface of the first protective insulating layer 111 in the periphery of the semiconductor layer 102 is made lower than the lower surface of the semiconductor layer 102, and the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102. As a result, the electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 180 can be increased. Similarly, as shown in FIGS. 29(C) and (D), below the semiconductor layer 102 Also, as shown in FIG. 13(D), it is preferable that the upper surface of the first protective insulating layer 111 in the periphery of the semiconductor layer 102 is made lower than the lower surface of the semiconductor layer 102, and the gate electrode 105 surrounds the lower part of the side surface of the semiconductor layer 102. As a result, the electric field by the gate electrode 105 is sufficiently applied to the lower part of the side surface of the semiconductor layer 102, and the on-current of the transistor 180 can be increased. Similarly, as shown in FIGS. 29(C) and (D), below the semiconductor layer 102 Lowering the lower surface of the gate electrode 105 below the surface is preferable because the on-current of the transistor 180 can be further increased.

[0228] [Configuration Example 3] FIGS. 14(A) and (B) show schematic cross-sectional views of the transistor 250 exemplified below. Note that FIG. 1(A) can be used as the schematic top view. The transistor 250 shown in FIG. 14 is different from the transistor 200 exemplified in Embodiment 1 in that it mainly has a first oxide layer 251 and a second oxide layer 252.

[0229] The first oxide layer 251 is provided between the first protective insulating layer 211 and the semiconductor layer 202. The second oxide layer 252 is provided between the semiconductor layer 202 and the gate insulating layer 204.

[0230] More specifically, in the groove provided in the insulating layer 207, the first oxide layer 251 is provided so as to cover the side surface and the upper surface of the first protective insulating layer 211. The first oxide layer 251 is provided in contact with the lower surface and the side surface of the semiconductor layer 202.

[0231] The lower surface of the second oxide layer 252 is provided in contact with the upper surface of each of the pair of electrodes 203. Further, in a region where the pair of electrodes 203 is not provided, it is provided in contact with the upper surface of the semiconductor layer 202.

[0232] The first oxide layer 251 and the second oxide layer 252 each contain an oxide containing one or more of the same metal elements as the semiconductor layer 202.

[0233] Note that at the boundary between the semiconductor layer 202 and the first oxide layer 251, or between the semiconductor layer 202 and the second​​​​​​​​​​​ The boundary with the oxide layer 252 may be unclear.

[0234] As the first oxide layer 251 and the second oxide layer 252, for example, the same materials as the above-described first oxide layer 151 and the second oxide layer 152 can be used.

[0235] In the configuration shown in FIG. 14, the upper surface shapes of the second oxide layer 252 and the gate insulating layer 204 are , processed using the same photomask so as to substantially coincide with the upper surface shape of the gate electrode 205. Also, the second protective insulating layer 212 is provided in contact with each end of the second oxide layer 252 and the gate insulating layer 204. By adopting such a configuration, desorption of elements from the semiconductor layer 202 can be suppressed via the ends of the second oxide layer 252 and the gate insulating layer 204.

[0236] Further, as shown in FIG. 14(B), the semiconductor layer 202 of the transistor 250 is provided in contact with the first oxide layer 251 not only on its lower surface but also on its side surface, and the upper surface of the semiconductor layer 202 is provided in contact with the second oxide layer 252. That is, the channel formation region of the semiconductor layer 202 is configured to be surrounded by the first oxide layer 251 and the second oxide layer 252.

[0237] By adopting such a configuration, formation of interface levels on the surface in the channel formation region of the semiconductor layer 202 can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and a highly reliable transistor can be realized.

[0238] Here, the thickness of the semiconductor layer 202 is formed to be at least thicker than the first oxide layer 251.​​​ is preferred. The thicker the semiconductor layer 202, the higher the on-current of the transistor can be . Also, the first oxide layer 251 may have a thickness such that the effect of suppressing the generation of interface levels in the semiconductor layer 202 is not lost. For example, the thickness of the semiconductor layer 202 may be greater than 1 times, preferably 2 times or more, more preferably 4 times or more, and even more preferably 6 times or more the thickness of the first oxide layer 251.

[0239] Also, the depth of the groove provided in the insulating layer 207 may be appropriately set in consideration of the processed thicknesses of the first protective insulating layer 211, the first oxide layer 251, and the semiconductor layer 202, respectively. Also, the width of the groove may be appropriately set according to the channel length and channel width of the transistor 250.

[0240] Also, similar to the first oxide layer 251, the second oxide layer 252 may have a thickness such that the effect of suppressing the generation of interface levels in the semiconductor layer 202 is not lost. For example, it may have a thickness equal to or less than that of the first oxide layer 251. If the second oxide layer 252 is thick, there is a possibility that the electric field by the gate electrode 205 may not easily reach the semiconductor layer 202. Therefore, it is preferable to form the second oxide layer 252 thinly. Note that this is not limiting, and the thickness of the second oxide layer 25 2 may be appropriately set according to the voltage for driving the transistor 250, taking into account the breakdown voltage of the gate insulating layer 204.

[0241]

[0242] Also, the insulating layer 206 that releases oxygen by heating, exemplified in Modification 1 of Embodiment 1, can also be applied.

[0242] In FIGS. 14(C) and (D), a transistor 27 having a configuration different from that of the transistor 250 It shows a schematic cross-sectional view of 0.

[0243] The transistor 270 is mainly between the first oxide layer 251 and the first protective insulating layer 211 in that it has the insulating layer 206, and the semiconductor layer 202 is provided covering the groove portion, which is different from the transistor 250.

[0244] Thus, by providing the first oxide layer 251 so as to fill the groove portion, in the channel formation region, the physical distance between the semiconductor layer 202 and the insulating layer 206 can be increased. Therefore, in the channel formation region, the interface level formed at the interface of the semiconductor layer 202 can be further reduced.

[0245] FIG. 15 shows the case where transistors 280 having a configuration different from the above-described transistors 250 and 270 are connected in series. The transistor 280 is mainly different from the transistor 270 in that the first oxide layer 251 is provided covering the groove portion.

[0246] Thus, by adopting a configuration in which the insulating layer 206 is embedded in the groove portion and the first oxide layer 251 and the semiconductor layer 202 are provided on the upper layer thereof, the volume of the insulating layer 206 can be easily increased, and as a result, the amount of oxygen supplied to the semiconductor layer 202 can be increased. Furthermore, by adopting such a configuration, no step is formed on the upper surface of the insulating layer 206, so that the covering properties of the first oxide layer 251, the semiconductor layer 202, etc. provided on the upper layer thereof are not deteriorated, and the thickness of the insulating layer 206 can be increased.

[0247] This embodiment can be appropriately combined with at least a part of other embodiments described in this specification. They can be implemented in combination.

[0248] (Embodiment 3) In this embodiment, an oxide semiconductor that can be suitably used for a semiconductor device according to an aspect of the present invention will be described.

[0249] The oxide semiconductor has a large energy gap of 3.0 eV or more, and an oxide semiconductor film obtained by processing the oxide semiconductor under appropriate conditions and sufficiently reducing its carrier density is applied. In a transistor, the leakage current (off-current) between the source and the drain in the off state can be made extremely low compared to a conventional transistor using silicon. .

[0250] As an applicable oxide semiconductor, it is preferably included at least indium (In) or zinc (Zn ). In particular, it is preferably included In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of a transistor using the oxide semiconductor, in addition to them, gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanoids (for example , cerium (Ce), neodymium (Nd), gadolinium (Gd)) are preferably included one kind, or a plurality of kinds.

[0251] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide , Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide ​(also referred to as), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc-Zn -based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide , In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide , In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, I n-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I n-Hf-Al-Zn-based oxide can be used.

[0252] Here, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, metal elements other than In, Ga, and Zn may be included.

[0253] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer ) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co, or the elements as the above stabilizer . Also, as the oxide semiconductor, In2SnO5(ZnO) . n (n > 0, and n is an integer) A material represented by may be used.

[0254] For example, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:3:2, In:Ga :Zn = 1:3:4, In:Ga:Zn = 1:3:6, In:Ga:Zn = 3:1:2 or an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn = 2:1:3 or an oxide in the vicinity of its composition may be used.

[0255] When a large amount of hydrogen is contained in the oxide semiconductor film, by bonding with the oxide semiconductor, a part of hydrogen becomes a donor and generates electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film and purify it to a high purity so that impurities are not contained as much as possible.

[0256] Note that, by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may simultaneously decrease from the oxide semiconductor film. Therefore, in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide semiconductor film. In this specification and the like, the case of supplying oxygen to the oxide semiconductor film may be described as an oxygen addition treatment, or the case of making the oxygen contained in the oxide semiconductor film more than the stoichiometric composition may be described as a peroxygenation treatment. In this way, the oxide semiconductor film is i-type (intrinsic) by removing hydrogen or moisture by the dehydration treatment (dehydrogenation treatment) and compensating for the oxygen deficiency by the oxygen addition treatment.

[0257] Thus, the oxide semiconductor film is dewatered (dehydrogenated) to remove hydrogen or moisture, and oxygen deficiency is compensated by oxygen addition treatment, thereby achieving i-type (intrinsic) conversion or ​​​​​It is possible to use an oxide semiconductor film that is substantially of type I (intrinsic) and infinitely close to type I. Note that being substantially intrinsic means that carriers derived from donors in the oxide semiconductor film are extremely few (close to zero), and the carrier density is 1×10 17 / cm 3 or less, 1×10 16 / cm 3 or less, 1×10 15 / cm 3 or less, 1×10 14 / cm 3 or less, 1×10 13 / cm 3 or less, which means.

[0258] Also, a transistor including an oxide semiconductor film that is of type I or substantially of type I can achieve extremely excellent off-current characteristics. For example, when a transistor using an oxide semiconductor film is in the off state, the drain current is 1×10 -18 A or less at room temperature (about 25°C), preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1×10 A or less at 85 -15 °C, preferably 1×10 -18 A or less, more preferably 1× 10 -21 A or less. Note that when the transistor is in the off state, for an n-channel type transistor, it means a state where the gate voltage is sufficiently smaller than the threshold voltage. Specifically speaking, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage , the transistor is in the off state.

[0259] Hereinafter, the structure of the oxide semiconductor film will be described.

[0260] Oxide semiconductor films are roughly classified into non-single crystal oxide semiconductor films and single crystal oxide semiconductor films. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, etc.

[0261] First, the CAAC-OS film will be described.

[0262] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, " perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0263] In this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. That is.

[0264] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction. .

[0265] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Elec tron Microscope), clear boundaries between crystal parts, that is, grain boundaries (also referred to as grain boundaries) cannot be confirmed. Therefore, C AAC-OS film can be said to be less likely to cause a decrease in electron mobility due to grain boundaries.

[0266] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation Upon observation, it can be confirmed that in the crystal part, metal atoms are arranged in layers. Metal atoms Each layer of the atoms has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0267] On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0268] Fig. 23(a) is a cross-sectional TEM image of the CAAC-OS film. Fig. 23(b) is a cross-sectional TEM image obtained by further magnifying Fig. 23(a), and the atomic arrangement is emphasized and displayed for easy understanding.

[0269] Fig. 23(c) is a local Fourier transform image of the region (with a diameter of about 4 nm) surrounded by a circle between A-O-A' in Fig. 23(a). From Fig. 23(c), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between A-O and O-A', it is suggested that they are different grains. Also, between A-O, it can be seen that the angle of the c-axis changes continuously little by little, such as 14.3°, 16. 6°, 26.4°. Similarly, between O-A ', it can be seen that the angle of the c-axis changes continuously little by little, such as -18.3°, -17.6°, -15.9°.

[0270] Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, with respect to the upper surface of the CAAC-OS film, for example, within a range of 1 nm or more and 30 nm or less.​​​​​​​ When performing electron diffraction using an electron beam (also referred to as nano-beam electron diffraction), spots can be observed (see Fig. 24(A)). (See Fig. 24(A).)

[0271] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystalline portions of the CAAC-OS film have orientation. (It can be seen that.)

[0272] Most of the crystalline portions contained in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystalline portions contained in the CAAC-OS film also include cases where the size fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline portions contained in the CAAC-OS film are connected, they may form one large crystalline region. For example, in a planar TEM image, a crystalline region of 2500 nm or more, 5 μm or more, or 1000 μm or more may be observed. nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline portions contained in the CAAC-OS film are connected, they may form one large crystalline region. For example, in a planar TEM image, a crystalline region of 2500 nm or more, 5 μm or more, or 1000 μm or more may be observed. nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline portions contained in the CAAC-OS film are connected, they may form one large crystalline region. For example, in a planar TEM image, a crystalline region of 2500 nm or more, 5 μm or more, or 1000 μm or more may be observed. nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline portions contained in the CAAC-OS film are connected, they may form one large crystalline region. For example, in a planar TEM image, a crystalline region of 2500 nm or more, 5 μm or more, or 1000 μm or more may be observed. nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystalline portions contained in the CAAC-OS film are connected, they may form one large crystalline region. For example, in a planar TEM image, a crystalline region of 2500 nm or more, 5 μm or more, or 1000 μm or more may be observed. 2 or more, 5 μm 2 or more or 1000 μm 2 or more may be observed.

[0273] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface. When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, for example, in the analysis of the out-of-plane method of a CAAC-OS film having crystals of InGaZnO4, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the formed surface or the upper surface.

[0274] On the other hand, when X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, in-p In the analysis by the lane method, a peak may appear around 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. For a single crystal oxide semiconductor film of InGaZnO4, if 2θ is fixed around 56° and the sample is rotated while analyzing (φ scan) with the normal vector of the sample surface as the axis (φ axis), six peaks attributed to crystal planes equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film,

[0275] even when φ scan is performed with 2θ fixed around 56°, no distinct peak appears. From the above, it can be seen that in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has

[0276] c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the deposition surface or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0277] Note that the crystal part is formed when the CAAC-OS film is deposited or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel The proportion of the part may increase. In addition, in the CAAC-OS film to which impurities are added, the region where the impurities are added deteriorates, and regions with different proportions of the crystal part partially oriented in the c-axis may be formed .

[0278] In addition, in the out-of-plane analysis by the method of the CAAC-OS film having the crystal of InGaZnO4, in addition to the peak where 2θ is around 31°, a peak may also appear where 2θ is around 36° . The peak where 2θ is around 36° indicates that a crystal having no c-axis orientation property is included in a part of the CAAC-OS film. It is preferable that the CAAC-OS film shows a peak where 2θ is around 31° and does not show a peak where 2θ is around 36°.

[0279] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon , silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity . In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when they are contained inside the oxide semiconductor film, they disrupt the atomic arrangement of the oxide semiconductor film, resulting in a decrease in crystallinity. Note that impurities contained in the oxide semiconductor film may be carrier traps or carrier generation sources.

[0280] In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiency in the oxide semiconductor film may become a carrier trap or a carrier generation source by capturing hydrogen . ​​​​​​​

[0281] The fact that the impurity concentration is low and the density of defect levels is low (with few oxygen deficiencies) is called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have electrical characteristics (also called normally-off) in which the threshold voltage becomes negative. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0282] Also, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0283] Next, the microcrystalline oxide semiconductor film will be described.

[0284] In the observation image by TEM, it may not be possible to clearly confirm the crystalline part in the microcrystalline oxide semiconductor film. The crystalline part contained in the microcrystalline oxide semiconductor film is often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, nanocrystals (nc: nanocrys) that are microcrystals of 1 nm or more and 10n m or less, or 1 nm or more and 3 nm or less. m or less, or 1 nm or more and 3 nm or less. An oxide semiconductor film having (tal) is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in the observation image by TEM, for example, grain boundaries may not be clearly confirmed. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole film. Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method.

[0285] Also, when performing electron diffraction (also referred to as limited-field electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, a region with high brightness may be observed as drawing a circle (ring-shaped). Also, when performing nano-beam electron diffraction on the nc-OS film, a plurality of spots may be observed within the ring-shaped region. The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film.

[0286]

[0286]

[0286] Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However , the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher density of defect levels than the CAAC-OS film.

[0287] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0288] When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction.

[0289] FIG. 24(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, a camera 18 installed in the observation chamber 20, and a film chamber 22 below the observation chamber 20. The camera 18 is installed facing the inside of the observation chamber 20. Note that the film chamber 22 may not be provided.

[0290] Further, FIG. 24(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 24(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 10 are irradiated onto a substance 28 disposed in the sample chamber 14 through the optical system 12. The electrons that have passed through the substance 28 enter a fluorescent plate 32 installed inside the observation chamber 20 through the optical system 16. In the fluorescent plate 32, a transmission electron diffraction pattern can be measured by a pattern corresponding to the intensity of the incident electrons appearing.

[0291] The camera 18 is installed facing the fluorescent plate 32 and can capture the pattern appearing on the fluorescent plate 32. The angle formed by the straight line passing through the center of the lens of the camera 18 and the center of the fluorescent plate 32, and the upper surface of the fluorescent plate 32 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern imaged by the camera 18. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. In addition, the camera 18 may be installed in the film chamber 22. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with less distortion can be captured from the back surface of the fluorescent plate 32. In the sample chamber 14, a holder for fixing the substance 28 as the sample is installed. The holder has a structure that allows electrons passing through the substance 28 to pass through. The holder may, for example, have a function of moving the substance 28 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have an accuracy of moving, for example, in a range of 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 n

[0292] m or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc. These ranges may be set to an optimal range depending on the structure of the substance 28. Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described. For example, as shown in Fig. 24(D), the irradiation position of the electrons 24, which are nano-beams in the substance

[0293]

[0294] ​​​​​​​ By changing (scanning) , it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in Fig. 24(A) is observed. Or, if the substance 28 is an nc-OS film, a diffraction pattern as shown in Fig. 24(B) is observed.

[0295] Incidentally, even if the substance 28 is a CAAC-OS film, a diffraction pattern similar to that of an nc-OS film, etc. may be observed in part. Therefore, the quality of the CAAC-OS film can sometimes be represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also referred to as the CAAC conversion rate). For example, for a high-quality CAAC-OS film the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Note that the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate.

[0296] As an example, for each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered), or after heat treatment at 450 °C in an oxygen-containing atmosphere, a transmission electron diffraction pattern was obtained while scanning the upper surface. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the observed diffraction pattern was converted into still images every 0.5 seconds to derive the CAAC conversion rate. Note that a nano-beam with a probe diameter of 1n m was used as the electron beam. The same measurement was performed on 6 samples. And for the calculation of the CAAC conversion rate, the average value of the 6 samples was used. m. The same measurement was performed on 6 samples. And for the calculation of the CAAC conversion rate, the average value of the 6 samples was used.

[0297] The CAAC conversion rates for each sample are shown in Fig. 25(A). The C AAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (the non-CAAC conversion rate was 14.7%) . It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation. That is, it can be seen that by heat treatment at a high temperature (for example, 400 °C or higher), the non-CAAC conversion rate decreases (the CAAC conversion rate increases). Also, it can be seen that a CAAC-OS film having a high CAAC conversion rate can be obtained even with heat treatment below 500 °C. Here, most of the diffraction patterns different from those of the CAAC-OS film were the same as those of the nc-OS film. Also, in the measurement region, the amorphous oxide semiconductor film could not be confirmed. Therefore, it is suggested that the region having the same structure as the nc-OS film is rearranged under the influence of the structure of the adjacent region and CAACified by heat treatment.

[0298] .

[0299] Figs. 25(B) and 25(C) are plan-view TEM images of the CAAC- OS film immediately after film formation and after heat treatment at 450 °C. By comparing Fig. 25(B) and Fig. 25(C), it can be seen that the CAAC-OS film after heat treatment at 4 50 °C has a more homogeneous film quality. That is, it can be seen that the film quality of the CAAC-OS film is improved by heat treatment at a high temperature.

[0300] Using such a measurement method, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.

[0301] (Embodiment 4) ​​​​​​​​In this embodiment, an example of a circuit using a transistor according to one aspect of the present invention will be described with reference to the drawing plane.

[0302] FIG. 16(A) shows a circuit diagram of a semiconductor device, and FIGS. 16(C) and (D) show cross-sectional views of the semiconductor device respectively. FIGS. 16(C) and (D) each show a cross-sectional view in the channel length direction of the transistor 100 on the left side and a cross-sectional view in the channel width direction on the right side. In the circuit diagram, in order to clearly indicate that the transistor is one to which an oxide semiconductor is applied, the description "OS" is attached.

[0303] The semiconductor device shown in FIGS. 16(C) and (D) has a transistor 2200 using a first semiconductor material at the lower part and has a transistor using a second semiconductor material at the upper part. Here, as the transistor using the second semiconductor material, an example in which the transistor 100 exemplified in Embodiment 1 is applied will be described.

[0304] Note that FIGS. 17(A) and (B) show an example of a cross-sectional configuration when the transistor 200 exemplified in Embodiment 1 is applied as the transistor using the second semiconductor material.

[0305] Here, it is desirable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc.), and the second semiconductor material can be the oxide semiconductor described in Embodiment 1. A transistor using single-crystalline silicon or the like as a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor has a low off-current. ​

[0306] Here, the transistor 2200 will be described as a p-channel transistor. However, it goes without saying that different circuits can be configured using n-channel transistors. In addition to using the transistors as shown in Embodiment 1 using an oxide semiconductor, the specific configuration of the semiconductor device, such as the materials used for the semiconductor device and the structure of the semiconductor device, need not be limited to what is shown here.

[0307] The configurations shown in FIGS. 16(A), (C), and (D) are examples of the configuration of a so-called CMOS circuit in which a p-channel transistor and an n-channel transistor are connected in series and their gates are connected. transistor are connected in series, and their gates are connected, which shows an example of the configuration of a so-called CMOS circuit.

[0308] In the transistor to which the oxide semiconductor of one aspect of the present invention is applied, the on-current is increased, so that the circuit can operate at high speed.

[0309] In the configuration shown in FIG. 16(C), the transistor 100 is provided above the transistor 2200 with an insulating layer 2201 interposed therebetween. Also, a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 100. Also, a plurality of plugs 2203 embedded in various insulating layers electrically connect the wirings and electrodes provided in the upper layer and the lower layer, respectively. Further, an insulating layer 2204 covering the transistor 100, a wiring 2205 on the insulating layer 2204, and a wiring 2206 formed by processing the same conductive film as the pair of electrodes of the transistor are provided. 00, and a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 1 00. Also, a plurality of plugs 2203 embedded in various insulating layers electrically connect the wirings and electrodes provided in the upper layer and the lower layer, respectively. are electrically connected. Also, an insulating layer 2204 covering the transistor 100, a wiring 2205 on the insulating layer 2204, and a wiring 220 6 formed by processing the same conductive film as the pair of electrodes of the transistor are provided. 2205 and a wiring 220 formed by processing the same conductive film as the pair of electrodes of the transistor 6 are provided.

[0310] In this way, by stacking two transistors, the occupied area of the circuit is reduced. A plurality of circuits can be arranged with higher density.

[0311] In FIG. 16(C), one of the source or drain of transistor 100 and one of the source or drain of transistor 2200 are electrically connected by wiring 2202 or plug 2203. Also, the gate of transistor 100 is electrically connected to the gate of transistor 2200 via wiring 2205, wiring 220 6, plug 2203, wiring 2202, etc.

[0312] In the configuration shown in FIG. 16(D), an opening for embedding plug 2203 is provided in the gate insulating layer of transistor 100, and the gate of transistor 100 and plug 2203 are in contact with each other. By adopting such a configuration, in addition to facilitating circuit integration, the number and length of the wirings and plugs to be passed through can be reduced as compared with the configuration shown in FIG. 16(C), so that the circuit can operate at a higher speed.

[0313] Here, in the configurations shown in FIGS. 16(C) and (D), by varying the connection configurations of the electrodes of transistor 100 and transistor 2200, various circuits can be configured For example, as shown in FIG. 16(B), by adopting a circuit configuration in which the sources and drains of the respective transistors are connected to each other, it can function as a so-called analog switch

[0314] Also, using the transistor shown as an example in any one of Embodiment 1 or 2, a semiconductor device having an image sensor function for reading information of an object can be manufactured.

[0315] ​​​​Fig. 18 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0316] One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the gate of the transistor 640. One of the source or drain of the transistor 64 0 is electrically connected to the photosensor reference signal line 672, and the other of the source or drain is electrically connected to one of the source or drain of the transistor 656. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source or drain is electrically connected to the photosensor output signal line 671.

[0317] For the photodiode 602, for example, a pin-type photodiode in which a semiconductor layer having a p-type conductivity type, a semiconductor layer having a high resistance ( having an i-type conductivity type), and a semiconductor layer having an n-type conductivity type are stacked can be applied. The information of the object to be detected can be read by detecting the light incident on the photodiode 602. Note that a light source such as a backlight can be used when reading the information of the object to be detected.

[0318] The information of the object to be detected can be read by detecting the light incident on the photodiode 602. Note that a light source such as a backlight can be used when reading the information of the object to be detected.

[0319] Note that for the transistor 640 and the transistor 656, the transistor in which a channel is formed in an oxide semiconductor, which was shown as an example in any of the first or second embodiments, can be used. In Fig. 18, in order to clearly show that the transistor 640 and the transistor 656 include an oxide semiconductor, "OS" is added to the symbol of the transistor. In Fig. 18, in order to clearly show that the transistor 640 and the transistor 656 include an oxide semiconductor, "OS" is added to the symbol of the transistor.

[0320] The transistor 640 and the transistor 656 are the transistors shown as an example in the above embodiment.​​ It is a resistor, and an oxide semiconductor layer in which a channel is formed is wrapped with an insulating layer including an aluminum oxide film containing excess oxygen. Further, it preferably has a configuration in which the oxide semiconductor layer is electrically surrounded by a gate electrode. Therefore, the transistor 640 and the transistor 656 are electrically stable transistors with suppressed electrical characteristic variations. By including the transistor, a highly reliable semiconductor device having the image sensor function shown in FIG. 18 can be provided.

[0321] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0322] (Embodiment 5) In this embodiment, an example of a semiconductor device (memory device) that can hold stored contents even in a situation where no power is supplied and has no limit on the number of write operations will be described with reference to the drawings, using a transistor which is an aspect of the present invention.

[0323] FIG. 19 shows a circuit diagram of the semiconductor device.

[0324] The semiconductor device shown in FIG. 19 has a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that, as the transistor 3300, the transistor described in the above embodiment can be used.

[0325] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 3300 has a small off-current, using this It is possible to retain memory contents for a longer period. That is, it is possible to provide a semiconductor memory device that does not require a refresh operation or requires a very low frequency of refresh operations, so that power consumption can be sufficiently reduced.

[0326] In FIG. 19, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. Then, the gate electrode of the transistor 3200 and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400.

[0327] In the semiconductor device shown in FIG. 19, by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read as follows.

[0328] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, and the transistor 3300 is turned on. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, two different potential levels are applied. ​​​​​​​​​​​​​​Either a charge (hereinafter referred to as Low - level charge or High - level charge) is given to it. Then, the potential of the fourth wiring 3004 is set to the potential at which the transistor 3300 is turned off, and by turning off the transistor 3300, the charge applied to the gate electrode of the transistor 3200 is held (retained). Since the off - current of the transistor 3300 is extremely small, the charge on the gate electrode of the transistor 3200 is retained for a long time.

[0329]

[0330] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring 3001 and an appropriate potential (reading potential) is applied to the fifth wiring 3005, the second wiring 3002 takes different potentials according to the amount of charge held on the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n - channel type, the apparent threshold voltage V when a High - level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold voltage V when a Low - level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to turn the transistor 3200 into the "on state". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between V and V th_ H the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, when a High - level charge was applied, the potential of the fifth wiring 3005 is V0 (> V th_L th_H and V th_L the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, when a High - level charge was applied, the potential of the fifth wiring 3005 is V0 (> V th_H ​​​​​​​​), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". The potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0331] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0332] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. That is, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0333] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem of element degradation. For example, unlike conventional non-volatile memories, there is no need to inject electrons into the floating gate or extract electrons from the floating gate , so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories , and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor , high-speed operation can be easily realized .

[0334] This embodiment can be implemented in appropriate combination with other embodiments described in this specification .

[0335] (Embodiment 6) In this embodiment, at least the transistor described in the embodiment can be used , and a CPU including the storage device described in the previous embodiment will be described .

[0336] FIG. 20 is a block diagram showing an example of the configuration of a CPU using at least a part of the transistor described in Embodiment 1 .

[0337] The CPU shown in FIG. 20 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) . The substrate 1190 is a semiconductor substrate, SOI . ​​​​​​​​​​​​​A substrate, such as a glass substrate, is used. ROM 1199 and ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 20 is only an example with its configuration simplified and actual CPUs have various configurations depending on their applications. For example a configuration including the CPU or arithmetic circuit shown in FIG. 20 may be regarded as one core, and a configuration including a plurality of such cores where each core operates in parallel may be adopted. Also, the number of bits that the CPU can handle with its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 6 4 bits, etc.

[0338] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

[0339] Based on the decoded instructions, the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program based on their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU

[0340] ​​​​​​​​​Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 11 92, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above-mentioned various circuits. In the CPU shown in FIG. 20, memory cells are provided in the register 1196. As the memory cells of the register 11 96, the transistors shown in the previous embodiment can be used.

[0341] In the CPU shown in FIG. 20, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cells included in the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed. When holding data in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0342]

[0343] FIG. 21 is an example of a circuit diagram of a storage element that can be used as the register 1196. The storage element 700 includes a circuit 701 in which stored data is volatile when the power supply is cut off, and a circuit 702 in which stored data is non-volatile when the power supply is cut off. A circuit 702 in which data does not volatilize, a switch 703, a switch 704, and a logic element 706 and a capacitive element 707 and a circuit 720 having a selection function. The circuit 702 includes a capacitive element 708, a transistor 709, and a transistor 710. Note that the storage element 700 may further include other elements such as a diode, a resistive element, and an inductor as necessary.

[0344] Here, the storage device described in the previous embodiment can be used for the circuit 702. When the supply of the power supply voltage to the storage element 700 is stopped, the gate of the transistor 709 in the circuit 702 continues to receive the ground potential (0 V) or a potential at which the transistor 709 turns off. For example, the gate of the transistor 709 is grounded via a load such as a resistor.

[0345] The switch 703 is configured using a transistor 713 of one conductivity type (for example, an n-channel type), and the switch 704 is configured using a transistor 714 of a conductivity type opposite to that of the one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 703 corresponds to one of the source and drain of the transistor 713, the second terminal of the switch 703 corresponds to the other of the source and drain of the transistor 713, and the switch 703 is controlled by a control signal RD input to the gate of the transistor 713 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 713). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714, and the switch 704 is controlled by a control signal WR input to the gate of the transistor 714 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 714). to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 713). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714, and the switch 704 is controlled by a control signal WR input to the gate of the transistor 714 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 714). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714, and the switch 704 is controlled by a control signal WR input to the gate of the transistor 714 ​​The switch 704 is controlled by a control signal RD input to the gate of the transistor 714, and the conduction or non-conduction between the first terminal and the second terminal (i.e., the on-state or off-state of the transistor 714) is selected.

[0346] One of the source and drain of the transistor 709 is electrically connected to one of the pair of electrodes of the capacitive element 708 and to the gate of the transistor 710. Here, the connection part is designated as node M2. One of the source and drain of the transistor 710 is electrically connected to a wiring (e.g., GND line) that can supply a low-potential power supply , and the other is electrically connected to the first terminal of the switch 703 (one of the source and drain of the transistor 713). The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is electrically connected to the first terminal of the switch 704 (one of the source and drain of the transistor 714). The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 703 (the other of the source and drain of the transistor 713), the first terminal of the switch 704 (one of the source and drain of the transistor 714), the input terminal of the logic element 706 and one of the pair of electrodes of the capacitive element 707 are electrically connected. Here, the connection part is designated as node M1. The other of the pair of electrodes of the capacitive element 707 can be configured to have a constant potential input . For example, it can be configured to input a low power supply potential (such as GND) or a high power supply potential ( VDD, etc.). The other of the pair of electrodes of the capacitive element 707 is electrically connected to a wiring (e.g., GND line) that can supply a low-potential power supply ​ Of the pair of electrodes of the capacitive element 708, the other is configured to receive a constant potential. This makes it possible. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. Of the pair of electrodes of the capacitive element 708, the other is electrically connected to a wiring (for example, a GND line) capable of supplying a low potential power supply.

[0347] Note that the capacitive elements 707 and 708 can also be omitted by positively using the parasitic capacitances of transistors and wirings, etc.

[0348] A control signal WE is input to the first gate (first gate electrode) of the transistor 709. The switches 703 and 704 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

[0349] A signal corresponding to the data held in the circuit 701 is input to the other of the source and drain of the transistor 709. In FIG. 21, an example is shown in which the signal output from the circuit 701 is input to the other of the source and drain of the transistor 709. The signal output from the second terminal of the switch 703 (the other of the source and drain of the transistor 713) becomes an inverted signal whose logical value is inverted by the logic element 706 and is input to the circuit 701 via the circuit 720.

[0350] Note that in FIG. 21, the second terminal of the switch 703 (the source and drain of the transistor 713 The signal output from the other side of the inductor) is input to circuit 701 via logic element 706 and circuit 720. Although an example of inputting to circuit 701 via the second terminal of switch 703 (the other side of the source and drain of transistor 713) has been shown, it is not limited to this. The signal output from the second terminal of switch 703 (the other side of the source and drain of transistor 713) may be input to circuit 701 without inverting the logical value. For example, when there is a node in circuit 701 that holds a signal whose logical value is inverted from the input signal, the signal output from the second terminal of switch 703 (the other side of the source and drain of transistor 713) can be input to the node. The signal output from the other side of the source and drain of the transistor 713) may be input to circuit 701 without inverting the logical value. For example, in circuit 701, if there is a node that holds a signal whose logical value is inverted from the input signal, the signal output from the second terminal of switch 703 (the other side of the source and drain of transistor 713) can be input to the node. Although an example of inputting to circuit 701 via the second terminal of switch 703 (the other side of the source and drain of transistor 713) has been shown, it is not limited to this. The signal output from the second terminal of switch 703 (the other side of the source and drain of transistor 713) can be input to the node.

[0351] The transistor 709 in FIG. 21 can use the transistor described in Embodiment 1. Further, it is preferable to have a configuration having a second gate (second gate electrode) provided on the side opposite to the first gate with a semiconductor layer interposed therebetween. A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a certain potential. For the certain potential, for example, a ground potential GND or a potential lower than the source potential of transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of transistor 709, and can further reduce the Icut of transistor 709. Note that as transistor 709, a transistor without a second gate can also be used. The transistor 709 in FIG. 21 can use the transistor described in Embodiment 1. Also, it is preferable to have a configuration having a second gate (second gate electrode) provided on the side opposite to the first gate with a semiconductor layer interposed therebetween. A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a certain potential. For the certain potential, for example, a ground potential GND or a potential lower than the source potential of transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of transistor 709, and can further reduce the Icut of transistor 709. Note that as transistor 709, a transistor without a second gate can also be used. Among the transistors used in the memory element 700 in FIG. 21, the transistors other than transistor 709 can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon-based semiconductor layer can be used.

[0352] Among the transistors used in the memory element 700 in FIG. 21, the transistors other than transistor 709 can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon-based semiconductor layer can be used. silicon-based semiconductor layer can be used. A transistor in which a channel is formed in a recon substrate can be used. Also, all the transistors used in the memory element 7 00 can also be transistors in which the channel is formed of an oxide semiconductor layer. Alternatively, the memory element 700 may include, in addition to the transistor 709, a transistor in which the channel is formed of an oxide semiconductor layer, and the remaining transistors can also be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. In the circuit 701 in FIG. 21, for example, a flip-flop circuit can be used. Also, as the logic element 706, for example, an inverter, a clocked inverter, or the like can be used. In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to the memory element 700,

[0353] the data stored in the circuit 701 can be held by the capacitor element 708 provided in the circuit 702.

[0354]

[0355] Also, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using such a transistor as the transistor 709, the signal held in the capacitor element 708 can be maintained for a long time even while the power supply voltage is not supplied to the memory element 7

[0356] 00. Thus, the memory element 700 can hold the memory content (data) even while the supply of the power supply voltage is stopped. 00. Thus, the memory element 700 can hold the memory content (data) even while the supply of the power supply voltage is stopped. Thus, the memory element 700 can hold the memory content (data) even while the supply of the power supply voltage is stopped. is possible.

[0356] Also, by providing switches 703 and 704, a precharge operation is performed, and since it is a memory element, after the power supply voltage supply resumes, the circuit 701 can shorten the time until it resumes holding the original data.

[0357] Also, in circuit 702, the signal held by capacitor element 708 is input to the gate of transistor 7 10. Therefore, after the supply of the power supply voltage to the memory element 700 resumes, the signal held by the capacitor element 708 can be converted into the state (on state or off state) of transistor 710 and read out from circuit 702. Therefore, even if the potential corresponding to the signal held by the capacitor element 708 fluctuates somewhat, the original signal can be accurately read out. By using such a memory element 700 in a memory device such as a register or cache memory that a processor has, it is possible to prevent the loss of data in the memory device due to the supply stop of the power supply voltage.

[0358] Also, after the supply of the power supply voltage resumes, it can return to the state before the power supply stop in a short time. Therefore, in the entire processor, or in one or a plurality of logic circuits constituting the processor, the power supply can be stopped even for a short time, so the power consumption can be suppressed.

[0359] In this embodiment, the memory element 700 has been described as an example used in a CPU, but the memory element 7 00 is an LSI such as a DSP (Digital Signal Processor), custom LS I, PLD (Programmable Logic Device), or RF ​​​​-Applicable to ID (Radio Frequency Identification) as well It is possible.

[0360] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. It can be done.

[0361] (Embodiment 7) In this embodiment, examples of electronic devices that can be made using semiconductor devices such as the transistor, memory device, or CPU (including DSP, custom LSI, PLD, RF-ID, etc.) described in the above embodiment will be described. The transistor, memory device, or CPU, etc. exemplified in the above embodiment can be applied to various electronic devices (including gaming machines). Examples of electronic devices include display devices such as televisions and monitors, lighting devices, personal computers, word processors, image playback devices, portable audio players, radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones, transceivers, radios, gaming machines, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as IC chips and microwave ovens, rice cookers, washing machines,

[0362] vacuum cleaners, air conditioning equipment such as air conditioners, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, freezers, refrigerator-freezers, freezers for DNA storage, radiation measuring instruments, medical devices such as dialysis devices and X-ray diagnostic devices, and so on. Also included are alarm devices such as smoke sensors, thermal sensors, gas alarm devices, and crime prevention alarm devices. Furthermore, induction lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems Industrial equipment such as turbines can also be mentioned. In addition, engines using fuel, and moving bodies propelled by an electric motor using power from a non-aqueous secondary battery are also included in the category of electronic devices. As such moving bodies, for example, electric vehicles (EVs), hybrid vehicles (HEVs) having both an internal combustion engine and an electric motor, plug-in hybrid vehicles (PHEVs), rail vehicles with their tire wheels changed to endless tracks, motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, airplanes, rockets, artificial satellites, space exploration vehicles and planetary exploration vehicles, and spaceships can be mentioned. Specific examples of some of these electronic devices are shown in Fig. 22. The television device 8000 shown in Fig. 22(A) has a display unit 8002 incorporated in a housing 8001, and can display an image by the display unit 8002 and output sound from a speaker unit 8003. The transistor exemplified in the previous embodiment can be used for a drive circuit or a pixel for operating the display unit 8002 incorporated in the housing 8001. The display unit 8002 can use a liquid crystal display device, a light emitting device having a light emitting element such as an organic EL element in each pixel, an electrophoretic display device, a semiconductor display device such as a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), etc. The television device 8000 may be provided with a receiver, a modem, etc. The television device 8000 can receive general television broadcasts by the receiver, and further, a modem

[0363]

[0364]

[0365] ​​​​​​​​​​​​​​By connecting to a wired or wireless communication network, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can be performed.

[0366] Also, the television device 8000 may include a CPU 8004 and a memory for performing information communication. Power saving can be achieved by using the transistor, storage device, or CPU shown in the previous embodiment in the CPU 8004 and the memory.

[0367] The alarm device 8100 shown in FIG. 22(A) is a residential fire alarm and is an example of an electronic device using a smoke or heat detection unit 8102 and a microcomputer 8101. The microcomputer 8101 includes the transistor, storage device, or CPU shown in the previous embodiment. U.

[0368] Also, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. 22(A) is an example of an electronic device including the transistor, storage device, or CPU, etc. shown in the previous embodiment. Specifically, the indoor unit 8200 has a housing 8201, an air outlet 8202, a CPU 8203, etc. In FIG. 22(A), the case where the CPU 8203 is provided in the indoor unit 8200 is illustrated, but the CPU 8203 may be provided in the outdoor unit 8204. Or, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. Power saving can be achieved by using the transistor shown in the previous embodiment in the CPU of the air conditioner.

[0369] ​​In addition, the electric refrigerator 8300 shown in Fig. 22(A) is an example of an electronic device including a transistor, a storage device, a CPU, or the like shown in the previous embodiment. Specifically, the electric refrigerator 8300 has a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, etc. In Fig. 22(A), the CPU 8304 is provided inside the housing 8301. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved. Examples of electronic devices include a transistor, a storage device, or a CPU shown in the previous embodiment. Specifically, the electric refrigerator 8300 has a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, etc. In Fig. 22(A), the CPU 8304 is provided inside the housing 8301. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved. The electric refrigerator 8300 has a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, etc. In Fig. 22(A), the CPU 8304 is provided inside the housing 8301. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved. In Fig. 22(A), the CPU 8304 is provided inside the housing 8301. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved. By using the transistor shown in the previous embodiment for the CPU 8304 of the electric refrigerator 8300, power saving can be achieved.

[0370] Figs. 22(B) and (C) show an example of an electric vehicle, which is an example of an electronic device. The electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved. The electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved. The circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved. By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved. By using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700, power saving can be achieved.

[0371] The drive device 9703 is composed of a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 outputs a control signal to the circuit 9702 based on input information such as the operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and the information during driving (information such as uphill and downhill, load information applied to the drive wheels, etc.). The circuit 9702 controls the output of the drive device 9703 by adjusting the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. The drive device 9703 is composed of a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 outputs a control signal to the circuit 9702 based on input information such as the operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and the information during driving (information such as uphill and downhill, load information applied to the drive wheels, etc.). The circuit 9702 controls the output of the drive device 9703 by adjusting the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. The processing device 9704 outputs a control signal to the circuit 9702 based on input information such as the operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and the information during driving (information such as uphill and downhill, load information applied to the drive wheels, etc.). The circuit 9702 controls the output of the drive device 9703 by adjusting the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. The circuit 9702 controls the output of the drive device 9703 by adjusting the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. The circuit 9702 controls the output of the drive device 9703 by adjusting the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated. When an AC motor is mounted, an inverter (not shown) for converting DC to AC is also incorporated.

[0372] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. This can be done.

Explanation of Reference Numerals

[0373] 100 Transistor 101 Substrate 102 Semiconductor layer 103 Electrode 104 Gate insulating layer 105 Gate electrode 106 Insulating layer 111 Protection insulating layer 112 Protection insulating layer 120 Capacitor element 124 Dielectric layer 125 Electrode 150 Transistor 151 Oxide layer 152 Oxide layer 160 Transistor 170 Transistor 180 Transistor 200 Transistor 201 Substrate 202 Semiconductor layer 203 Electrode 204 Gate insulating layer 205 Gate electrode 206 Insulating layer 207 Insulating layer 211 Protection insulating layer 212 Protection insulating layer 220 Capacitor element 224 Dielectric layer 225 Electrode 250 Transistor 251 Oxide layer 252 Oxide layer 260 Transistor 270 Transistor 280 Transistor 602 Photodiode 640 Transistor 656 Transistor 658 Photo Diode Reset Signal Line 659 Gate Signal Line 671 Photo Sensor Output Signal Line 672 Photo Sensor Reference Signal Line 700 Memory Element 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Element 707 Capacitor Element 708 Capacitor Element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 1189 ROM Interface 1190 Substrate 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 Transistor 2201 Insulation Layer 2202 Wiring 2203 Plug 2204 Insulation Layer 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitor Element 8000 Television device 8001 Housing 8002 Display unit 8003 Speaker unit 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detection unit 8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Door for refrigerator compartment 8303 Door for freezer compartment 8304 CPU 9700 Electric vehicle 9701 Secondary battery 9702 Circuit 9703 Driving device 9704 Processing device

Claims

1. a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; the oxide semiconductor layer has a region disposed above a first insulating layer; the oxide semiconductor layer has a channel formation region of a transistor, the first conductive layer has a region disposed above the oxide semiconductor layer; the first conductive layer functions as a source electrode or a drain electrode of the transistor; the second insulating layer has a region disposed above the oxide semiconductor layer; the second insulating layer functions as a gate insulating layer of the transistor; the second conductive layer overlaps with the oxide semiconductor layer via the second insulating layer; the second conductive layer functions as a gate electrode of the transistor; The third insulating layer has a region disposed above the second conductive layer, the third insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the second insulating layer, a region in contact with an upper surface of the first conductive layer, a region in contact with a side surface of the first conductive layer, and a region in contact with an upper surface of the first insulating layer; a surface of the first insulating layer having a recess, the oxide semiconductor layer having a region disposed inside the recess, in a cross-sectional view taken along a channel length direction of the transistor.

2. a first insulating layer, an oxide semiconductor layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer; the oxide semiconductor layer has a region disposed above a first insulating layer; the oxide semiconductor layer has a channel formation region of a transistor, the first conductive layer has a region disposed above the oxide semiconductor layer; the first conductive layer functions as a source electrode or a drain electrode of the transistor; the second insulating layer has a region disposed above the oxide semiconductor layer; the second insulating layer functions as a gate insulating layer of the transistor; the second conductive layer overlaps with the oxide semiconductor layer via the second insulating layer; the second conductive layer functions as a gate electrode of the transistor; The third insulating layer has a region disposed above the second conductive layer, the third insulating layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the second insulating layer, a region in contact with an upper surface of the first conductive layer, a region in contact with a side surface of the first conductive layer, and a region in contact with an upper surface of the first insulating layer; In a cross-sectional view of a cross section cut along a channel length direction of the transistor, a surface of the first insulating layer has a recess, and the oxide semiconductor layer has a region disposed inside the recess, a top surface of the oxide semiconductor layer in contact with the second insulating layer is located lower than a top surface of the first insulating layer in contact with the first conductive layer in the cross-sectional view.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor layer contains indium.

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