Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device, capable of improving a yield.SOLUTION: After a top-surface element structure 2 is formed to a top-surface 1a side of a semiconductor wafer 1, a back surface element structure 4 containing a diffusion region by an ion implantation is formed onto a back surface 1b side of the semiconductor wafer 1, and thus a heat processing by a furnace is performed under a temperature of 450°C or more to execute an impurity activation of the back surface element structure 4. After that, a back surface protection film 14 formed by a closed-ring polyimide system of a higher heat resistance than that of a passivation film 5 is formed to a back surface 1b of the semiconductor wafer 1. By a spin coating method, a polyimide is coated to the top-surface 1a of the semiconductor wafer 1, and the passivation film 5 is formed and hardened. Since the back surface 1b of the semiconductor wafer 1 is protected by the back surface protection film 14 during a formation of the passivation film 5, defected or scattered polyimide due to a foreign material on a stage of a spin coating device does not occur on the back surface 1b of the semiconductor wafer 1.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] Patent Document 1 describes a technique for suppressing the adhesion of polyimide to the back surface of a wafer by using a rod-shaped member erected around the wafer to entangle and capture the polyimide that has scattered and misted around the wafer due to centrifugal force when forming a polyimide-based resin film on the front surface of the wafer using a spin coating device. Patent Document 2 describes a technique for preventing damage and adhesion of foreign substances to the metal layer on the back surface of a wafer by covering the metal layer on the back surface of the wafer with a protective film when cutting the wafer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in Patent Document 1 above, since the back surface of the wafer is exposed when applying polyimide to the front surface of the wafer, it is impossible to completely prevent the adhesion of polyimide to the back surface of the wafer. In addition, since the back surface of the wafer directly contacts the support base of the spin coating device, there is a risk of defects such as scratches and contamination on the back surface of the wafer. Foreign substances adhering to the back surface of the wafer can cause thermal breakdown during device operation, and defects such as scratches and contamination on the back surface of the wafer can cause leakage (current leakage) failures. Therefore, foreign substances and defects on the back surface of the wafer are likely to have an adverse effect on the yield of the product and cause a decrease in the yield of the product.

[0005] This disclosure aims to provide a method for manufacturing a semiconductor device capable of improving the yield.

Means for Solving the Problems

[0006] A method for manufacturing a semiconductor device according to one aspect of this disclosure is a method for manufacturing a semiconductor device having a predetermined front surface element structure and a predetermined back surface element structure on both main surfaces, and is as follows. A back surface process for forming the back surface element structure on the back surface side of the semiconductor wafer is performed. After the back surface process, a heat process for heating the semiconductor wafer in a furnace is performed. After the heat process, a back surface protection process for protecting the back surface of the semiconductor wafer with a back surface protection film is performed. With the back surface of the semiconductor wafer protected by the back surface protection film, a front surface process for performing a predetermined process having a heat treatment of 200°C or higher is performed at least on the front surface side of the semiconductor wafer. After the front surface process, a removal process for removing the back surface protection film is performed. In the back surface protection process, the back surface protection film having heat resistance of 200°C or higher is formed using a non-photosensitive resin material.

Effects of the Invention

[0007] According to the method for manufacturing a semiconductor device according to this disclosure, there is an effect that the yield can be improved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] <Summary of Embodiments of the Present Disclosure> (1) A method for manufacturing a semiconductor device according to one aspect of this disclosure is a method for manufacturing a semiconductor device having a predetermined front surface element structure and a predetermined back surface element structure on both main surfaces, and is as follows. A back surface process for forming the back surface element structure on the back surface side of the semiconductor wafer is performed. After the back surface process, a heat process for heating the semiconductor wafer in a furnace is performed. After the heat process, a back surface protection process for protecting the back surface of the semiconductor wafer with a back surface protection film is performed. In a state where the back surface of the semiconductor wafer is protected with the back surface protection film, a front surface process for performing a predetermined process having a heat treatment of 200°C or higher is performed on at least the front surface side of the semiconductor wafer. After the front surface process, a removal process for removing the back surface protection film is performed. In the back surface protection process, the back surface protection film having heat resistance of 200°C or higher is formed using a non-photosensitive resin material.

[0010] According to the above-described disclosure, since the back surface of the semiconductor wafer is protected by the back surface protection film during the front surface process, it is possible to suppress the occurrence of defects (scratches, contamination) that cause leakage defects on the back surface of the semiconductor wafer. In addition, it is possible to suppress the adhesion of foreign substances that cause thermal breakdown during device operation to the back surface of the semiconductor wafer. Therefore, the yield of the product (semiconductor device) can be improved.

[0011] (2) Also, in the method for manufacturing a semiconductor device according to this disclosure, in the above-described (1), in the back surface protection step, the back surface protection film may be formed using a non-photosensitive resin material soluble in an organic solvent.

[0012] According to the above-described disclosure, an organic solvent containing a material for the back surface protection film can be applied to the back surface of the semiconductor wafer, and the back surface protection film can be formed by vaporizing the organic solvent by heat treatment at a relatively low temperature.

[0013] (3) Also, in the method for manufacturing a semiconductor device according to this disclosure, in the above-described (1) or (2), in the back surface protection step, the back surface protection film may be formed using a closed-ring polyimide-based material.

[0014] According to the above-described disclosure, a back surface protection film having a heat resistance temperature higher than that of the resist and mechanical properties (elongation) comparable to those of the polyimide material used for the passivation film can be formed.

[0015] (4) Also, in the method for manufacturing a semiconductor device according to this disclosure, in any one of the above-described (1) to (3), in the back surface protection step, the thickness of the back surface protection film may be 1 μm or more.

[0016] According to the above-described disclosure, the effect of suppressing the occurrence of defects on the back surface of the semiconductor wafer during the front surface process is enhanced.

[0017] (5) Also, in the method for manufacturing a semiconductor device according to this disclosure, in any one of the above-described (1) to (4), the front surface process may include a step of applying polyimide to the front surface of the semiconductor wafer by spin coating to form a passivation film, and the heat treatment for curing the passivation film.

[0018] According to the above-described disclosure, a heat process can be performed at a temperature exceeding the heat resistance temperature of the passivation film. Also, when forming the passivation film, it is possible to prevent the material of the passivation film from adhering to the back surface of the semiconductor wafer.

[0019] (6) Further, in any one of (1) to (5) described above, the method for manufacturing a semiconductor device according to this disclosure includes, before the back surface process, a process of forming the front surface element structure on the front surface side of the semiconductor wafer. The front surface process may include a process of forming a front surface electrode electrically connected to the front surface element structure on the front surface of the semiconductor wafer, and the heat treatment for baking the front surface electrode.

[0020] According to the above-described disclosure, a heat process can be performed at a temperature exceeding the heat resistance temperature of the front surface electrode.

[0021] (7) Further, in any one of (1) to (6) described above, in the back surface process, a diffusion region of a predetermined conductivity type constituting the back surface element structure is formed by ion-implanting impurities from the back surface of the semiconductor wafer, and in the heat process, the impurities may be activated.

[0022] According to the above-described disclosure, impurity activation of the back surface element structure can be performed at a temperature exceeding the heat resistance temperature of the passivation film or the front surface electrode.

[0023] (8) Further, in any one of (1) to (7) described above, in the removal process, the back surface protective film may be dissolved and removed with an organic solvent.

[0024] According to the above-described disclosure, the back surface protective film can be removed without applying a stress load to the semiconductor wafer or leaving deposits such as an adhesive on the back surface of the semiconductor wafer.

[0025] (9) Further, in any one of (1) to (8) described above, after the removal process, a back surface electrode electrically connected to the back surface element structure may be formed on the back surface of the semiconductor wafer.

[0026] According to the above disclosure, even if warpage occurs in the semiconductor wafer due to the formation of the back electrode, the number of processes performed after the formation of the back electrode in all the manufacturing process steps can be reduced. Therefore, cracking of the semiconductor wafer in the manufacturing process can be suppressed. In addition, leakage defects caused by the diffusion of metal atoms in the back electrode into the semiconductor wafer can be suppressed.

[0027] <The knowledge on which the present disclosure is based> For example, in vertical semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and RC-IGBTs (Reverse Conducting IGBTs) in which diodes are built in the same semiconductor substrate as IGBTs, and surface electrodes and element structures are formed on both main surfaces of semiconductor chips, generally, after performing the front surface side process of the semiconductor wafer in a state where the thickness is thick (for example, 600 μm or more), the semiconductor wafer is thinned by grinding from the back surface side, and then the back surface side process of the semiconductor wafer is performed. As a manufacturing method of the semiconductor device of Reference Example 1, a manufacturing method of a general vertical semiconductor device will be described.

[0028] FIG. 18 is a flowchart showing an outline of a manufacturing method of a semiconductor device of Reference Example 1. Specifically, a semiconductor wafer made of silicon (Si) is prepared, and an element structure on the front surface side of the semiconductor wafer (hereinafter referred to as the front surface element structure) is formed (step S101). Next, a surface electrode on the front surface side of the semiconductor wafer (hereinafter referred to as the front surface electrode) is deposited (formed) and sintered (step S102). Next, after a passivation film is formed and cured on the front surface of the semiconductor wafer (steps S103, S104), the front surface of the semiconductor wafer is covered and protected with a protective film (hereinafter referred to as the front surface protective film) (step S105). Next, the semiconductor wafer is thinned by back grinding (step S106).

[0029] Next, an element structure on the back side of the semiconductor wafer (hereinafter referred to as the back-side element structure) is formed by ion implantation or the like (step S107). Next, a heat treatment is performed to activate the impurities ion-implanted to form the back-side element structure (hereinafter referred to as impurity activation of the back-side element structure) (step S108). In the heat treatment of step S108, only the back side of the semiconductor wafer is heated by laser irradiation or the like. Then, the front-side protective film is removed (step S109). Next, a surface electrode on the back side of the semiconductor wafer (hereinafter referred to as the back-side electrode) is formed (step S110). Thereafter, the semiconductor wafer is diced (cut) into individual chips (step S111), and the semiconductor device (semiconductor chip) is completed.

[0030] On the other hand, depending on the product (semiconductor device), it is necessary to perform the heat treatment for impurity activation of the back-side element structure of the semiconductor wafer using a furnace. The temperature of the heat treatment by the furnace at this time is 450°C or higher, and may be about 500°C to 800°C. Since the entire semiconductor wafer is heated in the heat treatment by the furnace, among the respective structural parts of the front-side element structure and the front-side electrode, the structural parts that cannot withstand the temperature of the heat treatment by the furnace need to be formed after the heat treatment by the furnace. For example, the heat resistance temperature of polyimide, which is the material of the passivation film, is about 350°C to 400°C, and may be even lower. The heat resistance temperature of aluminum (Al), which is the material of the front-side electrode, is about 500°C.

[0031] As a method for manufacturing the semiconductor device of Reference Example 2, the case of performing heat treatment at a temperature of about 450°C using a furnace will be described. FIG. 19 is a flowchart showing an outline of another example of the method for manufacturing the semiconductor device of Reference Example 2. FIGS. 20 to 24 are cross-sectional views schematically showing the states during the manufacturing of the semiconductor device of Reference Example 2. The method for manufacturing the semiconductor device of Reference Example 2 is different from the method for manufacturing the semiconductor device of Reference Example 1 (see FIG. 18) in that the heat treatment for impurity activation of the back-side element structure 104 is performed using a furnace and the timing of forming and curing the passivation film 105. Specifically, first, a semiconductor wafer 101 is prepared, and a front-side element structure 102 is formed on the front side 101a of the semiconductor wafer 101 (step S121).

[0032] Next, a front surface electrode 103 is formed on the front surface 101a of the semiconductor wafer 101 and sintered (step S122). Next, the front surface 101a of the semiconductor wafer 101 is covered and protected with a front surface protective film 111 (step S123). The state up to this point is shown in FIG. 20. Next, the semiconductor wafer 101 is thinned by back grinding (step S124; FIG. 21). Next, the semiconductor wafer 101 is placed with the front surface 101a side down (on the stage 112 side) on the stage 112 of the semiconductor manufacturing apparatus via the front surface protective film 111, and a back surface element structure 104 of the semiconductor wafer 101 is formed by ion implantation or the like (step S125: FIG. 22). Then, the front surface protective film 111 is removed (step S126).

[0033] Next, the semiconductor wafer 101 is inserted into a furnace (heat treatment furnace) 113, and heat treatment for impurity activation of the back surface element structure 104 is performed at a temperature of about 450°C (step S127: FIG. 23). The semiconductor wafer 101 is supported from below by a plurality of wafer support portions 113a in the furnace 113, for example, and held at a predetermined position. When the semiconductor wafer 101 has a rib shape in which the outer peripheral portion remains thicker than the central portion, the semiconductor wafer 101 may be inserted into the furnace 113 with the back surface 101b side down, and the process of step S127 may be performed in a state where the rib portion (outer peripheral portion protruding more than the central portion) on the back surface 101b side is held by the wafer support portion 113a.

[0034] Next, place the semiconductor wafer 101 on the stage 114 of the spin coater with the back surface 101b side facing down (towards the stage 114), and apply polyimide 105a (the hatched portion with diagonal lines) to the front surface 101a of the semiconductor wafer 101 to form the passivation film 105 (step S128: FIG. 24). In the process of step S128, the passivation film 105 may be patterned by photolithography and etching. By patterning the passivation film 105, openings may be formed to expose the scribe region, electrode pads, etc., respectively. Next, cure the passivation film 105 by heat treatment (step S129). Thereafter, form a back electrode (not shown) (step S130), and singulate the semiconductor wafer 101 by dicing (step S131), thereby completing the semiconductor device.

[0035] The chip region 110a of the semiconductor wafer 101 is the portion that is singulated in the process of step S131 to become a semiconductor chip (semiconductor device). Note that the arrangement, shape, and size of each structural part (front surface element structure 102, front surface electrode 103, back surface element structure 104, passivation film 105) inside the semiconductor wafer 101 and on the main surfaces (front surface 101a and back surface 101b) in FIGS. 20 to 24, and the shape and size of the foreign matter 114a (shown as a triangle) on the stage 114 and the misty polyimide 105a (shown as a circular shape with diagonal hatching) floating around the stage 114 in FIG. 24 are simplified for explaining the manufacturing method of the semiconductor device of Reference Example 2 and are different from the actual shape and size.

[0036] When a predetermined process is performed on the front surface 101a (processing surface) side of the semiconductor wafer 101 while exposing the back surface 101b (non-processing surface) of the semiconductor wafer 101 as described above, the back surface 101b of the semiconductor wafer 101 comes into contact with the stage 114 of the semiconductor manufacturing apparatus (see FIG. 24). For this reason, defects such as scratches and contamination are likely to occur on the back surface 101b of the semiconductor wafer 101 due to foreign matter 114a (shown in a triangular shape) on the stage 114. In particular, when polyimide is applied to the front surface 101a of the semiconductor wafer 101 by the spin coating method, there is a risk that the misted polyimide 105a (shown in a circular shape) adheres to the back surface 101b of the semiconductor wafer 101. The polyimide 105a adhering to the back surface 101b of the semiconductor wafer 101 cannot be easily removed.

[0037] Furthermore, in order to expose the polyimide film applied to the front surface 101a of the semiconductor wafer 101 and transfer a predetermined pattern of the passivation film 105, it is necessary to transport the semiconductor wafer 101 to an exposure apparatus (not shown) and place it on the stage of the exposure apparatus with the back surface 101b side facing down. Therefore, it is inevitable that foreign matter adheres to and defects occur on the back surface 101b of the semiconductor wafer 101. Foreign matter adhering to the back surface of the semiconductor chip separated from the semiconductor wafer 101 causes thermal destruction during device operation, and defects such as scratches and contamination occurring on the back surface of the semiconductor chip cause leakage (current leakage) defects. For this reason, foreign matter and defects on the back surface 101b of the semiconductor wafer 101 are likely to have an adverse effect on the product yield and cause a decrease in the product yield.

[0038] The problem to be solved in the present embodiment is a manufacturing method of a vertical semiconductor device having element structures (front surface element structure and back surface element structure) on both main surface sides of a semiconductor chip, and by suppressing the adhesion of foreign matter and the occurrence of defects (scratches, contamination) on the back surface of the semiconductor wafer, improving the product yield.

[0039] With reference to the accompanying drawings, preferred embodiments of a method for manufacturing a semiconductor device according to this disclosure will be described in detail. In this specification and the accompanying drawings, for layers and regions preceded by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0040] (Details of Embodiment 1) The method for manufacturing a semiconductor device according to Embodiment 1 for solving the above problems will be described below by taking the case of manufacturing an IGBT as an example. FIG. 1 is a flowchart showing an outline of the method for manufacturing a semiconductor device according to Embodiment 1. FIGS. 2 to 13 are cross-sectional views schematically showing the states during the manufacture of the semiconductor device according to Embodiment 1. In FIGS. 2 to 13 and FIG. 14 to be described later, each part is shown in a simplified manner. First, as shown in FIG. 2, a semiconductor wafer 1 is prepared, and an element structure (front surface element structure) 2 on the front surface 1a side is formed in each chip region 10a of the semiconductor wafer 1 (step S1). Next, as shown in FIG. 3, a surface electrode (front surface electrode) 3 on the front surface 1a side of the semiconductor wafer 1 is deposited (formed) and sintered (step S2).

[0041] The diameter and thickness of the semiconductor wafer 1 are, for example, about 8 inches and 725 μm, respectively. As the semiconductor material of the semiconductor wafer 1, silicon (Si) or silicon carbide (SiC) can be used. The front surface element structure 2 is a MOS gate (Metal Oxide Semiconductor Field Effect Transistor: an insulating gate composed of a three-layer structure of metal - oxide film - semiconductor) structure and an interlayer insulating film. The front surface element structure 2 reaches a depth of, for example, less than about 10 μm from the front surface 1a of the semiconductor wafer 1. The chip region 10a is a region that is cut from the semiconductor wafer 1 and separated into chips (semiconductor chips 10: see FIG. 13).

[0042] The front surface electrode 3 is an emitter electrode. The front surface electrode 3 is, for example, an aluminum (Al) layer or an Al alloy layer. Note that the arrangement, shape, and size of each structural part (front surface element structure 2, front surface electrode 3, back surface element structure 4 described later, passivation film 5 described later, and back surface electrode 6 described later) inside and on the main surfaces (front surface 1a and back surface 1b) of the semiconductor wafer 1 in FIGS. 2 to 13, and the shape and size of the foreign matter 15a (illustrated as a triangle) on the stage 15 and the misty polyimide 5a (illustrated as a circular shape with diagonal hatching) floating around the stage 15 in FIG. 9 are simplified for explaining the manufacturing method of the semiconductor device according to Embodiment 1 and are different from the actual shape and size.

[0043] Next, as shown in FIG. 4, the front surface 1a of the semiconductor wafer 1 is covered and protected with a protective film (front surface protective film) 11 (step S3). The front surface protective film 11 is, for example, a resist film. Next, as shown in FIG. 5, the semiconductor wafer 1 is ground from the back surface 1b side (back surface grinding), and thinned to a product thickness (for example, about 50 μm or more and 300 μm or less) to be used as a semiconductor device (semiconductor chip 10) (step S4). In the process of step S4, the semiconductor wafer 1 may be made into a flat plate shape that is uniformly thinned to the product thickness over the entire surface (not shown), or the semiconductor wafer 1 may be made into a rib shape in which only the central portion 1b-1 is thinned to the product thickness and the outer peripheral portion 1b-2 remains thicker than the central portion 1b-1 along the outer periphery with a predetermined width (FIG. 5).

[0044] Next, as shown in FIG. 6, an element structure (back surface element structure) 4 on the back surface 1b side of the semiconductor wafer 1 is formed (step S5: back surface process). The back surface element structure 4 is a p +It is a p-type collector region or an n-type field stop (FS) layer. Specifically, in the process of step S5, the semiconductor wafer 1 is placed on the stage 12 of the ion implantation apparatus via the front surface protective film 11 with the front surface 1a side facing down (towards the stage 12), and impurities are ion-implanted from the back surface 1b of the semiconductor wafer 1 to form a diffusion region of a predetermined conductivity type that constitutes the back surface element structure 4. The back surface element structure 4 may reach a depth of up to, for example, about 30 μm from the back surface 1b of the semiconductor wafer 1. Then, the front surface protective film 11 is removed (step S6).

[0045] Next, as shown in FIG. 7, the semiconductor wafer 1 is inserted into a furnace (heat treatment furnace) 13 and held so as not to contact the inner wall of the furnace 13, and heat treatment for activating the impurities ion-implanted in the process of step S5 (activating the impurities in the back surface element structure 4), thermal diffusion of the impurities, and recovery of crystal defects generated by the ion implantation is performed at a high temperature of, for example, about 450 °C or higher (step S7: heat process). At this time, the semiconductor wafer 1 is inserted into the furnace 13 with, for example, the back surface 1b side facing down, and may be supported from below by a plurality (for example, four) of wafer support portions 13a in the furnace 13 and held at a predetermined position. Thereby, the wafer support portions 13a do not contact the front surface element structure 2 and the front surface electrode 3 on the front surface 1a of the semiconductor wafer 1.

[0046] Also, the plurality of wafer support portions 13a may each contact different portions of the rib portion (outer peripheral portion 1b-2 protruding from the central portion 1b-1) of the back surface 1b of the semiconductor wafer 1 to hold the semiconductor wafer 1. Thereby, the wafer support portions 13a also do not contact the back surface element structure 4 on the back surface 1b of the semiconductor wafer 1. Further, since the heat treatment by the furnace 13 in step S7 heats the entire semiconductor wafer 1, a structural portion that cannot withstand the temperature of the heat treatment by this furnace 13 is formed after the process of step S7. For example, the heat resistance temperature of polyimide, which is the material of the passivation film 5 (see FIG. 9 described later), is about 350 °C to 400 °C, or may be even lower. Note that the heat resistance temperature of the resist, which is the material of the front surface protective film 11 removed before the process of step S7, is about 150 °C to 200 °C.

[0047] For example, when impurity activation of the backside element structure is performed by laser irradiation as in the method for manufacturing a semiconductor device of Reference Example 1 (see FIG. 18), only a shallow region about 1 μm deep (up to about 2 μm at maximum) from the backside of the semiconductor wafer is heated. For this reason, it is only possible to form the backside element structure in a shallow region up to about 2 μm or less in depth from the backside of the semiconductor wafer, or a region with insufficient impurity activation is formed. On the other hand, in Embodiment 1, since the entire semiconductor wafer 1 is heated by the heat treatment in the furnace 13, it is possible to form a backside element structure 4 in which a region of a predetermined conductivity type is arranged up to a depth of, for example, about 30 μm at maximum from the backside 1b of the semiconductor wafer 1.

[0048] Next, as shown in FIG. 8, after taking out the semiconductor wafer 1 from the furnace 13, the backside 1b of the semiconductor wafer 1 is covered and protected with a protective film (hereinafter referred to as the backside protective film) 14 by the spin coating method using a spin coater (step S8: backside protection step). Specifically, the outer peripheral portion 1b-2 of the semiconductor wafer 1 is clamped (held by being sandwiched by a jig) with the backside 1b (processing surface) of the semiconductor wafer 1 facing upward. The semiconductor wafer 1 is held at a predetermined height position without contacting a stage or the like. Then, while rotating the semiconductor wafer 1 around an axis perpendicular to the backside 1b of the semiconductor wafer 1 passing through the approximate center of the semiconductor wafer 1, the material of the backside protective film 14 is dropped onto the backside 1b of the semiconductor wafer 1 and spread to form the backside protective film 14 (hatched portion).

[0049] The material of the back surface protective film 14 uses a non-photosensitive resin material soluble in an organic solvent. Specifically, as the material of the back surface protective film 14, for example, a polymer compound having a molecular structure containing a polyimide that has already undergone imide ring closure, a thermal crosslinking component, and a photosensitizer as repeating units (groups) in the molecular chain is used, such as a polyimide-based material dissolved in a solvent having a boiling point of about 200 °C or lower, such as propylene glycol monomethyl ether, which is used in a photoresist. The polyimide-based material that has already undergone imide ring closure has mechanical properties (elongation) similar to those of the polyimide material used for the passivation film 5. Since the back surface protective film 14 has a heat resistance temperature of, for example, about 200 °C or higher and less than 400 °C, it can withstand the heat treatment performed during the formation of the passivation film 5.

[0050] That is, in the process of step S8, a polyimide-based material that has already undergone imide ring closure is applied to the back surface 1b of the semiconductor wafer 1 by the spin coating method, and the solvent (organic solvent) in the polyimide-based material that has already undergone imide ring closure is vaporized by heat treatment. Since the polyimide-based material that has already undergone imide ring closure contains polyimide that has already been imidized in the solvent, by simply vaporizing and sintering the solvent in the polyimide-based material, a back surface protective film 14 having mechanical properties similar to those of the passivation film 5 can be formed by heat treatment at a relatively low temperature. The sintered body of the polyimide that has already undergone imide ring closure and remains attached to the back surface 1b of the semiconductor wafer 1 becomes the back surface protective film 14. The back surface protective film 14 is formed at least in the central portion 1b-1 of the back surface 1b of the semiconductor wafer 1 so as to cover all the chip regions 10a of the semiconductor wafer 1.

[0051] The back surface element structure 4 of the back surface 1b of the semiconductor wafer 1 is protected by the back surface protective film 14. The back surface protective film 14 has a function of suppressing the adhesion of foreign substances and the occurrence of defects (scratches, contamination) on the back surface 1b of the semiconductor wafer 1 during the process of step S9 described later. The thickness of the back surface protective film 14 is equal to or greater than the height of foreign substances 15a such as particles existing on the stage 15 (see FIG. 19) of the spin coater used in the process of step S9 described later. Specifically, for example, it is about 1 μm or more, preferably about 2 μm or more. Since the back surface protective film 14 is soluble in an organic solvent, it can be dissolved and removed by the organic solvent without applying a stress load to the semiconductor wafer 1 or leaving deposits such as adhesives on the back surface 1b of the semiconductor wafer 1.

[0052] Next, as shown in FIG. 9, the semiconductor wafer 1 is placed on the stage 15 of the spin coater through the back surface protective film 14 with the back surface 1b side facing down (toward the stage 15), and polyimide 5a (hatched portion with diagonal lines) is applied to the front surface 1a of the semiconductor wafer 1 by the spin coating method to form a passivation film 5 (step S9: front surface process). In the process of step S9, the passivation film 5 may be patterned by photolithography and etching. The passivation film 5 may be patterned to form openings that expose the scribe region and electrode pads (front surface electrodes 3), etc., respectively. The scribe region is the portion between adjacent chip regions 10a and surrounds the periphery of the chip region 10a. Since the back surface 1b of the semiconductor wafer 1 is protected by the back surface protective film 14, it does not come into direct contact with the stage 15. Even if foreign substances 15a are present on the stage 15, the foreign substances 15a do not reach the back surface 1b of the semiconductor wafer 1 due to the back surface protective film 14. Therefore, defects such as scratches and contamination (contamination) caused by the foreign substances 15a on the stage 15 do not occur on the back surface 1b of the semiconductor wafer 1.

[0053] Also, during the process of step S9, the misted polyimide 5a wraps around from the front surface 1a side to the back surface 1b side of the semiconductor wafer 1. However, since the back surface 1b of the semiconductor wafer 1 is covered with the back surface protective film 14, the polyimide 5a does not adhere to the back surface 1b of the semiconductor wafer 1. The foreign matter 15a on the stage 15 and the misted polyimide 5a floating around the stage 15 adhere to the back surface protective film 14 and are removed together with the back surface protective film 14. Note that since the outer peripheral portion 1b-2 of the semiconductor wafer 1 is an invalid region where the chip region 10a is not arranged, the polyimide 5a may adhere thereto. As the material of the passivation film 5, for example, polyamic acid (polyamide acid), which is a precursor of polyamide, can be used.

[0054] The process of step S9 includes pre-curing (temporary curing) of the passivation film 5 by heat treatment at about 200°C and forming the passivation film 5 into a predetermined pattern by photolithography and etching with an alkaline solvent. For example, when the back surface 1b of the semiconductor wafer 1 is protected with a resist film, if the heat treatment is performed at a temperature equal to or higher than the heat resistance temperature of the resist film (about 150°C to 200°C), the resist film may not be peeled off, so it is required to perform the subsequent processes at a temperature lower than the heat resistance temperature of the resist film. On the other hand, in the first embodiment, since the back surface protective film 14 having a higher heat resistance temperature than the pre-curing temperature of the passivation film 5 is used, the manufacturing method of the semiconductor device in Reference Example 2 (see FIG. 19) can be applied with almost no design change.

[0055] Next, as shown in FIG. 10, the back surface protective film 14 is dissolved and removed by the chemical solution 16a dropped from the nozzle 16 positioned above the back surface 1b of the semiconductor wafer 1 using a single-wafer spin stripping apparatus (step S10: removal step). Specifically, the outer peripheral portion 1b-2 of the semiconductor wafer 1 is clamped with the back surface 1b of the semiconductor wafer 1 facing upward. The semiconductor wafer 1 is held at a predetermined height position without contacting a stage or the like. Then, while rotating the semiconductor wafer 1 around an axis perpendicular to the back surface 1b of the semiconductor wafer 1 passing through the approximate center of the semiconductor wafer 1, the chemical solution 16a is dropped onto the back surface 1b of the semiconductor wafer 1. The back surface protective film 14 is dissolved by the chemical solution 16a, and the dissolved portion 14a of the back surface protective film 14 is flung outward of the semiconductor wafer 1 by centrifugal force.

[0056] The chemical solution 16a is flung from the outer periphery of the semiconductor wafer 1 to the outside of the semiconductor wafer 1 at an angle substantially parallel to the back surface 1b of the semiconductor wafer 1 by centrifugal force spreading over the back surface 1b of the semiconductor wafer 1. The dissolved portion 14a of the back surface protective film 14 by the chemical solution 16a is also flung from the outer periphery of the semiconductor wafer 1 to the outside of the semiconductor wafer 1 at an angle substantially parallel to the back surface 1b of the semiconductor wafer 1 in the same manner as the chemical solution 16a. For this reason, the chemical solution 16a has no adverse effect on the passivation film 5 on the front surface 1a of the semiconductor wafer 1. As the chemical solution 16a, for example, an alkaline (basic) organic solvent can be used. Specifically, as the chemical solution 16a, for example, an alkanolamine-based (alcoholamine-based, ethanolamine-based) organic solvent can be used.

[0057] Next, as shown in FIG. 11, the semiconductor wafer 1 is inserted into the furnace 17 and held so as not to contact the inner wall of the furnace 17. Then, the passivation film 5 is cured (the polyimide 5a is dehydrated and undergoes ring closure to be cured) by heat treatment at a high temperature of, for example, 350° C. or higher (preferably 370° C. or higher) (step S11). By curing the passivation film 5, cracking of the passivation film 5 can be suppressed when the semiconductor device is used in a harsh environment with a thermal load. Note that the heat treatment in the furnace (this treatment and the treatment in step S7 described above) can be performed without bringing the central portion 1b-1 (the effective region where the chip region 10a is disposed) of the back surface 1b of the semiconductor wafer 1 into contact with a stage or a jig by clamping the outer peripheral portion 1b-2 of the semiconductor wafer 1 or the like.

[0058] Next, as shown in FIG. 12, a surface electrode (back surface electrode) 6 on the back surface 1b side of the semiconductor wafer 1 is formed (step S12). The back surface electrode 6 is preferably formed at a timing as close as possible to the end of the manufacturing process of the semiconductor device. The reason is as follows. If the back surface electrode 6 is formed on the back surface 1b of the semiconductor wafer 1 whose thickness has been reduced by back grinding, the semiconductor wafer 1 is likely to warp. When each process of the manufacturing process is performed on the warped semiconductor wafer 1 or the semiconductor wafer 1 is transported, there is a risk that the semiconductor wafer 1 will crack. For this reason, it is preferable to perform each process of the manufacturing process before forming the back surface electrode 6 as much as possible.

[0059] Also, when the back electrode 6 contains heavy metals, if heat treatment is performed after the formation of the back electrode 6, the heavy metals in the back electrode 6 will diffuse into the semiconductor wafer 1. This is because the heavy metals diffused into the semiconductor chip 10 (semiconductor wafer 1) will increase the leakage current at the pn junction of the semiconductor device. The back electrode 6 is formed by laminating, for example, an Al alloy film or an Al film, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film or a silver (Ag) film in this order. The thickness of the back electrode 6 is, for example, about 2 μm or less, which is thinner than the height of the rib portion on the back surface 1b of the semiconductor wafer 1. The height of the rib portion on the back surface 1b of the semiconductor wafer 1 is the height difference between the central portion 1b-1 and the outer peripheral portion 1b-2 of the back surface 1b of the semiconductor wafer 1, and is, for example, about 500 μm or less. Thereafter, as shown in FIG. 13, the semiconductor wafer 1 is diced (cut) along the scribe region by the dicing blade 18, and each chip region 10a of the semiconductor wafer 1 is separated into individual semiconductor chips 10 (step S13), thereby completing the semiconductor device (semiconductor chip 10).

[0060] There are approximately 70 processes performed on the front surface 1a side of the semiconductor wafer 1. Compared with the processes performed on the back surface 1b side of the semiconductor wafer 1 (about 30 processes), the proportion of the number of processes in the total number of processes of the semiconductor device manufacturing process is larger, and the stress load on the semiconductor wafer 1 is relatively large. Therefore, as many processes as possible among all the processes performed on the front surface 1a side of the semiconductor wafer 1 should be performed on the semiconductor wafer 1 in a thick state before thinning (the process of step S4). Also, since the process of forming the front surface element structure 2 (the process of step S1) includes heat treatment at about 1200 °C or higher, it is preferably performed before the process performed on the back surface 1b side of the semiconductor wafer 1 (the maximum temperature of heat treatment is about 800 °C).

[0061] Also, when the heat-resistant temperature of the back surface protective film 14 is higher than the curing temperature of the passivation film 5, the passivation film 5 may be cured while the back surface 1b of the semiconductor wafer 1 is protected by the back surface protective film 14. In this case, after curing the passivation film 5 (the process of step S11), the back surface protective film 14 may be removed before forming the back surface electrode 6 (the process of step S12). Further, when the semiconductor device is used in an environment where no thermal load is applied, since diffusion of metal atoms in the front surface electrode 3 and cracking of the passivation film 5 are less likely to occur, sintering of the front surface electrode 3 and curing of the passivation film 5 may be omitted.

[0062] Note that the method for manufacturing a semiconductor device according to Embodiment 1 can be realized, for example, by executing a program prepared in advance on a computer such as a personal computer or a workstation, a database server, or a web server. Further, a program for realizing the method for manufacturing a semiconductor device according to Embodiment 1 is recorded on a computer-readable recording medium such as a solid state drive (SSD), a hard disk, or a Blu-ray (registered trademark) disc, and is executed by being read from the recording medium by a computer or a server. Further, this program may be a transmission medium that can be distributed via a network such as the Internet.

[0063] A structural example of a semiconductor device (semiconductor chip 10) manufactured by the method for manufacturing a semiconductor device according to Embodiment 1 will be described by taking an RC-IGBT as an example. FIG. 14 is a cross-sectional view showing a structural example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to Embodiment 1. The semiconductor device 20 according to Embodiment 1 shown in FIG. 14 is an RC-IGBT in which an IGBT region 21 serving as an operation region of an IGBT and an FWD region 22 serving as an operation region of a FWD (Free Wheeling Diode) are provided adjacent to each other in the active region of the semiconductor chip 10. When the semiconductor device 20 is applied to an IGBT, the FWD region 22 may be omitted.

[0064] The active region is the region where the main current flows when the device is on, and is arranged approximately at the center of the semiconductor chip 10. The region between the active region and the edge of the semiconductor chip 10 is the edge termination region. The edge termination region surrounds the periphery of the active region and has a function of relaxing the electric field on the front surface side of the semiconductor chip 10 and maintaining the breakdown voltage. In the edge termination region, breakdown voltage structures such as a guard ring, a field limiting ring (FLR), and a junction termination extension (JTE) structure are arranged. The breakdown voltage is the upper limit voltage at which the device does not malfunction or break down at the operating voltage.

[0065] In the IGBT region 21, a plurality of unit cells (functional units of the device) of the IGBT are arranged adjacent to each other. In the FWD region 22, a plurality of unit cells of the FWD are arranged adjacent to each other. The IGBT in the IGBT region 21 and the FWD in the FWD region 22 are connected in anti-parallel. The IGBT region 21 and the FWD region 22 are, for example, alternately arranged adjacent to each other in a direction parallel to the front surface of the semiconductor chip 10. The front surface and the back surface of the semiconductor chip 10 respectively correspond to the front surface 1a and the back surface 1b (see FIG. 13) of the above-described semiconductor wafer 1. Inside the semiconductor chip 10, an n - -type drift region 31 is provided.

[0066] The portion of the semiconductor chip 10 excluding the front surface element structure 2 and the back surface element structure 4 is the n - -type drift region 31. The n - -type drift region 31 reaches from the active region to the edge of the semiconductor chip 10. The front surface element structure 2 is composed of a p-type base region 32, an n + -type emitter region 33, a p ++ -type contact region 34, a trench 36, a gate insulating film 37, and a gate electrode 38. The back surface element structure 4 is composed of an n-type FS layer 41, a p + -type collector region 42, and an n +It is composed of the type - cathode region 43. The front - side element structure 2 and the back - side element structure 4 are formed by the processes of steps S1 and S5 of the manufacturing method of the semiconductor device according to the first embodiment, respectively.

[0067] The p - type base region 32 is located between the front - side of the semiconductor chip 10 and the n - - type drift region 31, and is provided in contact with the n - - type drift region 31. The p - type base region 32 is provided over the entire active region from the IGBT region 21 to the FWD region 22. The p - type base region 32 functions as the p - type anode region of the FWD in the FWD region 22. The n + - type emitter region 33 and the p ++ - type contact region 34 are selectively provided in contact with the p - type base region 32 between the front - side of the semiconductor chip 10 and the p - type base region 32 in the IGBT region 21, respectively.

[0068] The p ++ - type contact region 34 may not be provided. In this case, instead of the p ++ - type contact region 34, the p - type base region 32 reaches the front - side of the semiconductor chip 10. In the IGBT region 21, an n - type accumulation layer 35 may be provided in contact with these regions between the n - - type drift region 31 and the p - type base region 32 between adjacent trenches 36. The n - type accumulation layer 35 serves as a barrier for minority carriers in the n - - type drift region 31 during the turn - on of the IGBT, and functions as a carrier storage (CS: Carrier Storage) layer for accumulating minority carriers in the n - - type drift region 31.

[0069] A plurality of trenches 36 extend linearly in the same direction parallel to the front - side of the semiconductor chip 10 over the entire active region to form a stripe shape. In the IGBT region 21, the trench 36 penetrates the n + - type emitter region 33, the p - type base region 32, and the n - type accumulation layer 35 from the front - side of the semiconductor chip 10 in the depth direction to the n -It terminates inside the type drift region 31. The trench 36 penetrates the p-type base region 32 from the front surface of the semiconductor chip 10 in the depth direction in the FWD region 22 and reaches n - It terminates inside the type drift region 31. Inside the trench 36, a gate electrode 38 is provided via a gate insulating film 37.

[0070] The p-type base region 32, n + type emitter region 33 and n-type accumulation layer 35 are in contact with the gate insulating film 37 on the side walls of the trench 36. A unit cell of the IGBT is formed at the portion between the centers of the trenches 36 adjacent to each other in the IGBT region 21. A unit cell of the FWD is formed at the portion between the centers of the trenches 36 adjacent to each other in the FWD region 22. The interlayer insulating film 39 is provided on substantially the entire front surface of the semiconductor chip 10 and covers the gate electrode 38. The interlayer insulating film 39 is, for example, BPSG (Boron Phosphorus Silicon Glass) or PSG (Phosphorus Silicon Glass).

[0071] The emitter electrode 40 is provided on the interlayer insulating film 39 over substantially the entire active region and fills the contact holes 39a, 39b of the interlayer insulating film 39. The emitter electrode 40 is the front surface electrode 3 formed in the process of step S2 of the manufacturing method of the semiconductor device according to Embodiment 1. The emitter electrode 40 makes an ohmic contact with the front surface of the semiconductor chip 10 via the contact holes 39a, 39b. The emitter electrode 40 is electrically connected to the p-type base region 32, n + type emitter region 33 and p ++ type contact region 34 in the IGBT region 21.

[0072] The emitter electrode 40 is electrically connected to the p-type base region 32 through the contact hole 39b in the FWD region 22 and also serves as the anode electrode. Although not shown in FIG. 14, the front surface of the semiconductor chip 10 is covered with a passivation film 5 (see FIG. 13). The emitter electrode 40 exposed at the opening (not shown) of the passivation film 5 functions as an emitter pad (electrode pad). Between the back surface of the semiconductor chip 10 and the n - -type drift region 31, an n-type FS layer 41, p + -type collector region 42 and an n + -type cathode region 43 are respectively provided.

[0073] The n-type FS layer 41, p + -type collector region 42 and n + -type cathode region 43 are diffusion regions formed by ion implantation from the back surface of the semiconductor chip 10. The n-type FS layer 41 is provided at a deep position away from the back surface of the semiconductor chip 10 over the entire active region. The n-type FS layer 41 may not be provided. p + -type collector region 42 is provided over the entire area between the back surface of the semiconductor chip 10 and the n-type FS layer 41 in the IGBT region 21. n + -type cathode region 43 is provided over the entire area between the back surface of the semiconductor chip 10 and the n-type FS layer 41 in the FWD region 22.

[0074] p + -type collector region 42 and n + -type cathode region 43 are adjacent to each other in a direction parallel to the back surface of the semiconductor chip 10. The collector electrode 44 is provided on the entire back surface of the semiconductor chip 10. The collector electrode 44 is the back surface electrode 6 formed by the process of step S12 in the manufacturing method of the semiconductor device according to Embodiment 1. The collector electrode 44 is in electrical contact with the p + -type collector region 42 on the back surface of the semiconductor chip 10. The collector electrode 44 is in electrical contact with the n + -type cathode region 43 on the back surface of the semiconductor chip 10 and also serves as the cathode electrode.

[0075] As described above, according to Embodiment 1, after forming the backside element structure and performing heat treatment in a furnace, the backside (non-processed surface) of the semiconductor wafer is protected with a backside protective film, and then a predetermined process is performed on the front side (processed surface) of the semiconductor wafer. In the predetermined process performed on the front side of the semiconductor wafer after heat treatment in the furnace, a structure portion having a heat resistance temperature lower than the temperature of the heat treatment in the furnace is formed among the structure portions on the front side of the semiconductor wafer. At this time, since the backside of the semiconductor wafer is protected by the backside protective film, it is possible to suppress the occurrence of defects (scratches, contamination) that cause leakage defects on the backside of the semiconductor wafer.

[0076] Also, when a predetermined process is performed on the front side of the semiconductor wafer, since the backside of the semiconductor wafer is protected by the backside protective film, it is possible to suppress the attachment of foreign substances that cause thermal breakdown during device operation to the backside of the semiconductor wafer. For example, the backside protective film is made of a closed-loop polyimide-based material, and its heat resistance temperature is relatively high. Therefore, a passivation film can be formed on the front side of the semiconductor wafer while the backside of the semiconductor wafer is protected by the backside protective film. It is possible to suppress the misted polyimide from adhering to the backside of the semiconductor wafer when polyimide is applied to the front side of the semiconductor wafer by the spin coating method.

[0077] Foreign substances present on the stage of the semiconductor manufacturing apparatus and materials scattered to the backside of the semiconductor wafer during the predetermined process on the front side of the semiconductor wafer adhere to the backside protective film, and thus can be removed together with the backside protective film. Also, according to Embodiment 1, although the process of forming and removing the backside protective film is added compared to the method of manufacturing a semiconductor device in Reference Example 2 (see FIG. 19), as described above, the adhesion of foreign substances and the occurrence of defects on the backside of the semiconductor wafer are suppressed, so that the generation rate of defective chips is reduced and the product yield is improved. Therefore, it is presumed that the product cost can be suppressed to be almost the same as that of the method of manufacturing a semiconductor device in Reference Example 2.

[0078] (Details of Embodiment 2) The manufacturing method of the semiconductor device according to Embodiment 2 for solving the above problems will be described below. FIG. 15 is a flowchart showing an outline of the manufacturing method of the semiconductor device according to Embodiment 2. The manufacturing method of the semiconductor device according to Embodiment 2 is different from the manufacturing method of the semiconductor device according to Embodiment 1 (see FIG. 1) in the timing of forming the front surface electrode 3, and is useful when the temperature of the heat treatment by the furnace exceeds the heat-resistant temperature (about 500° C.) of aluminum (Al), which is the material of the front surface electrode 3.

[0079] Specifically, in Embodiment 2, first, similar to the process of step S1 in Embodiment 1, a semiconductor wafer 1 is prepared, and a front surface element structure 2 is formed (step S31). Next, similar to Embodiment 1, formation of the front surface protective film 11 (step S32), back grinding (step S33), formation of the back surface element structure 4 (step S34), removal of the front surface protective film 11 (step S35), heat treatment by the furnace (step S36), and formation of the back surface protective film 14 (step S37) are performed in order.

[0080] Next, similar to the process of step S2 in Embodiment 1, a front surface electrode 3 is formed and sintered (step S38: front surface process). In the process of step S38, the semiconductor wafer 1 is placed on the stage of, for example, a sputtering apparatus via the back surface protective film 14 with the back surface 1b side down (stage side). Since the back surface 1b of the semiconductor wafer 1 does not come into direct contact with the stage during the process of step S38, it is possible to suppress the adhesion of foreign matter and the occurrence of defects on the back surface 1b of the semiconductor wafer 1 due to foreign matter on the stage of the sputtering apparatus.

[0081] The higher the film formation temperature of the front surface electrode 3, the more the crystal grains grow, and the crystallinity of the front surface electrode 3 improves. The film formation temperature of the front surface electrode 3 is preferably about 250°C or higher. Further, the formation of the front surface electrode 3 includes patterning of the front surface electrode 3 by photolithography and etching, and a resist film is used as an etching mask during patterning. Since the heat resistance temperature of the back surface protective film 14 is equal to or higher than the sintering temperature of the resist, the front surface electrode 3 can be patterned while the back surface 1b of the semiconductor wafer 1 is protected by the back surface protective film 14.

[0082] By sintering the front surface electrode 3, the movement (recrystallization) of metal atoms in the front surface electrode 3 proceeds, so that additional stress applied by metal atoms such as Al in the front surface electrode 3 to the passivation film 5 during the operation of the semiconductor device can be reduced. The sintering temperature of the front surface electrode 3 is preferably equal to or higher than the cure temperature of the passivation film 5, for example, 380°C or higher. By sintering the front surface electrode 3, it is possible to suppress the passivation film 5 from cracking due to the movement (recrystallization) and stress relaxation of metal atoms from the front surface electrode 3 when the semiconductor device is used in a harsh environment with a heat load.

[0083] Thereafter, in the same manner as in the first embodiment, the formation of the passivation film 5 (step S39), the removal of the back surface protective film 14 (step S40), the cure of the passivation film 5 (step S41), the formation of the back surface electrode 6 (step S42), and the dicing of the semiconductor wafer 1 (step S43) are sequentially performed, whereby the semiconductor device is completed. The same back surface protective film 14 can be used in the processes of steps S38 and S39. The semiconductor device manufactured by the manufacturing method of the semiconductor device according to the second embodiment is the same as that in FIG. 14.

[0084] In the processes of steps S32 to S37, the same processes as those of steps S3 to S8 in Embodiment 1 are performed on the semiconductor wafer 1 on which the front surface electrode 3 is not formed. The heat treatment in the furnace in step S36 can be performed at a temperature exceeding the heat resistance temperature of the front surface electrode 3. The processes of steps S39 to S43 are the same as those of steps S9 to S13 in Embodiment 1 respectively. The states during the processes of steps S39 to S43 are the same as those in FIGS. 9 to 13 respectively.

[0085] As described above, according to Embodiment 2, even when the front surface electrode is formed after the heat treatment in the furnace, by protecting the back surface of the semiconductor wafer with the back surface protective film when forming the front surface electrode, the same effects as those in Embodiment 1 can be obtained.

[0086] (Regarding the generation rate of defective chips) FIG. 16 is a characteristic diagram schematically showing the relationship between the occurrence rate of scratches on the back surface of the semiconductor wafer and the thickness of the back surface protective film. FIG. 17 is a characteristic diagram schematically showing the occurrence rate of defective chips per semiconductor wafer. The examples in FIGS. 16 and 17 are data estimated based on the inventor's empirical rule. The reference example 2 in FIG. 17 is data obtained from the inventor's experiment. When the back surface 1b of the semiconductor wafer 1 is protected with a resist film, the inventor has confirmed that by setting the thickness of the resist film to about 2 μm, when the semiconductor wafer 1 is placed on a general stage of a semiconductor manufacturing apparatus with the back surface 1b side down (stage side) through the resist film, the back surface 1b of the semiconductor wafer 1 can be protected from foreign substances on the stage.

[0087] Also, when the depth of the backside element structure 4 of the IGBT is relatively shallow (e.g., about 2 μm or less) from the backside 1b of the semiconductor wafer 1, when the thickness of the backside electrode 6 is increased to about 2 μm, even if the semiconductor wafer 1 or the semiconductor chip 10 is placed with the backside electrode 6 side down and the backside electrode 6 contacts the stage during the electrical test, the inventors have confirmed that no defective chips are generated. From these facts, if the thickness of the backside protective film 14 is about 2 μm, it is sufficient to protect the backside 1b of the semiconductor wafer 1 from foreign matter on the stage, and it is presumed that when the thickness of the backside protective film 14 is about 1 μm, scratches caused by foreign matter on the stage are less likely to occur on the backside 1b of the semiconductor wafer 1 (Fig. 16).

[0088] From these facts, it can be said that the defective chip generation rate per semiconductor wafer 1 in the manufacturing method of the semiconductor device according to Embodiment 1 (see Fig. 1) is obtained by subtracting the number of defective chips caused by foreign matter adhesion and defect generation that occurred on the exposed backside 101b of the semiconductor wafer 101 during the formation of the passivation film 105 in the manufacturing method of the semiconductor device of Reference Example 2 (see Figs. 19 and 24). Based on the inventor's rule of thumb, it is presumed that the defective chip generation rate per semiconductor wafer 1 in the manufacturing method of the semiconductor device according to Embodiment 1 (illustrated as an example in Fig. 17) can be reduced to about 1 / 10 of the defective chip generation rate per semiconductor wafer 101 in the manufacturing method of the semiconductor device of Reference Example 2 (see Fig. 17).

[0089] Regarding the manufacturing method of the semiconductor device according to Embodiment 2 (see Fig. 15) as well, since the backside 1b of the semiconductor wafer 1 is protected by the backside protective film 14 during the formation of the passivation film 5 in the same manner as the manufacturing method of the semiconductor device according to Embodiment 1, it is presumed that the same effects as those of the manufacturing method of the semiconductor device according to Embodiment 1 can be obtained.

[0090] As described above, the present disclosure is not limited to each of the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, the present disclosure is applicable not only to IGBTs and RC-IGBTs, but also to vertical semiconductor devices having surface electrodes on both main surfaces of a semiconductor chip, and semiconductor devices provided with a diffusion region that requires impurity activation by heat treatment in a furnace as a back surface element structure. Therefore, the present disclosure is applicable to, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors having an insulating gate composed of a three-layer structure of metal-oxide-semiconductor) and FWDs (Free Wheeling Diodes).

[0091] When applying the present disclosure to a MOSFET, in the structural example of the semiconductor device according to Embodiment 1 shown in FIG. 14, the FWD region is omitted, and an n + type drain region is provided instead of the p + type collector region, so that the entire active region may be a MOS region. In this case, the n + type emitter region, emitter electrode, and collector electrode in FIG. 14 may be read as an n + type source region, source electrode, and drain electrode, respectively. When applying the present disclosure to an FWD, the IGBT region may be omitted. In this case, the trench, gate insulating film, and gate electrode can also be omitted. Further, the present disclosure is not limited to the processing on the front surface side of the semiconductor wafer, and various processes involving heat treatment at 200° C. or higher performed on the semiconductor wafer may be performed with the back surface of the semiconductor wafer protected by a back surface protective film. Also, in each embodiment, the first conductivity type is an n-type and the second conductivity type is a p-type, but the present disclosure also holds true when the first conductivity type is a p-type and the second conductivity type is an n-type.

Industrial Applicability

[0092] As described above, the method for manufacturing a semiconductor device according to the present disclosure is useful for vertical semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Reference Numerals

[0093] 1,101 semiconductor wafer 1a,101a front surface of semiconductor wafer 1b,101b back surface of semiconductor wafer 1b-1 central part of semiconductor wafer 1b-2 outer peripheral part of semiconductor wafer 2,102 front surface element structure 3,103 front surface electrode 4,104 back surface element structure 5,105 passivation film 5a,105a polyimide material 6 back surface electrode 10 semiconductor chip 10a,110a chip region of semiconductor wafer 11,111 front surface protective film 12,15,112,114 stages of semiconductor manufacturing equipment 13,17,113 furnace 14 back surface protective film 14a dissolution part of back surface protective film 15a,114a foreign matter on the stage of semiconductor manufacturing equipment 16 nozzle 16a chemical solution 18 dicing blade 20 semiconductor device 21 IGBT region 22 FWD region 31 n - -type drift region 32 p-type base region 33 n + -type emitter region 34 p ++ -type contact region 35 n-type accumulation layer 36 trench 37 gate insulating film 38 gate electrode 39 interlayer insulating film 39a,39b contact hole 40 emitter electrode 41 n-type FS layer 42 p + Type collector region 43 n + Type cathode region 44 Collector electrode

Claims

1. A method for manufacturing a semiconductor device having a predetermined front surface element structure and a predetermined back surface element structure on both main surfaces, respectively, comprising: a back surface process of forming the back surface element structure on the back surface side of the semiconductor wafer; a heat process of heating the semiconductor wafer in a furnace after the back surface process; a back surface protection process of protecting the back surface of the semiconductor wafer with a back surface protection film after the heat process; a front surface process of performing a predetermined process having a heat treatment of 200 °C or higher on at least the front surface side of the semiconductor wafer while the back surface of the semiconductor wafer is protected with the back surface protection film; a removal process of removing the back surface protection film after the front surface process; and including In the back surface protection process, the back surface protection film having heat resistance of 200 °C or higher is formed using a non-photosensitive resin material. A method for manufacturing a semiconductor device characterized by this.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in the back surface protection process, the back surface protection film is formed using a non-photosensitive resin material soluble in an organic solvent.

3. The method for manufacturing a semiconductor device according to claim 1, wherein in the back surface protection process, the back surface protection film is formed using a polyimide-based material that has already been ring-closed.

4. The method for manufacturing a semiconductor device according to claim 1, wherein in the back surface protection process, the thickness of the back surface protection film is 1 μm or more.

5. The front surface process includes a step of applying polyimide to the front surface of the semiconductor wafer by a spin coating method to form a passivation film; and the heat treatment for curing the passivation film. The method for manufacturing a semiconductor device according to claim 1, characterized by this.

6. Before the back surface process, it includes a step of forming the front surface element structure on the front surface side of the semiconductor wafer. The front surface process includes a step of forming a front surface electrode electrically connected to the front surface element structure on the front surface of the semiconductor wafer; and the heat treatment for sintering the front surface electrode. The method for manufacturing a semiconductor device according to claim 1, characterized by this.

7. In the back surface process, a diffusion region of a predetermined conductivity type constituting the back surface element structure is formed by ion implanting impurities from the back surface of the semiconductor wafer. In the heat process, the impurities are activated. The method for manufacturing a semiconductor device according to claim 1, characterized by this.

8. The method for manufacturing a semiconductor device according to claim 1, wherein in the removal step, the back surface protective film is dissolved and removed by an organic solvent.

9. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a back surface electrode electrically connected to the back surface element structure on the back surface of the semiconductor wafer after the removal step.

Images