Semiconductor device

Abstract

To provide a semiconductor device comprising a plurality of guard rings capable of mitigating impact of an external electric charge of a load in a terminal end region of a semiconductor layer.SOLUTION: Each of a plurality of guard rings 16, includes: a guard ring lower part 162; and a guard ring upper part 164. The guard ring upper part 164 includes an outer peripheral wall 166 that extends upward from an upper surface an outer peripheral side of the guard ring lower part 162. An n-type region 12 is provided above the guard ring lower part 162, in a part adjacent to the outer peripheral wall 166 of the guard ring upper part 164.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

[0002] Patent Documents 1 to 3 disclose a semiconductor device in which a plurality of p-type guard rings are provided in a termination region of a semiconductor layer. When the semiconductor device is turned off, a depletion layer spreads from the element region toward the termination region. The depletion layer spreads toward the outer peripheral side of the termination region while passing through the plurality of guard rings. By providing the plurality of guard rings, the depletion layer spreading from the element region spreads toward the outer peripheral side of the termination region, and the breakdown voltage of the semiconductor device can be improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Generally, each of the plurality of guard rings is often formed to protrude from the upper surface of the semiconductor layer toward the deep part when the semiconductor layer is viewed in cross section. Also, the impurity concentration of each of the plurality of guard rings is often uniform in the depth direction of the semiconductor layer. In such a plurality of guard rings, due to the influence of negative external charges present on the upper surface of the semiconductor layer, the effective impurity concentration of the upper part of each of the plurality of guard rings increases, and there is a problem that the depletion layer spreading from the element region spreads excessively. In order to address such a problem, it is necessary to optimize the shape of the plurality of guard rings. This specification provides a semiconductor device including a plurality of guard rings capable of mitigating the influence of negative external charges in a termination region of a semiconductor layer.

Means for Solving the Problem

[0005] The semiconductor device (1) disclosed in this specification may include a semiconductor layer (10) having an element region (101) in which an element structure is formed and a termination region (102) located around the element region. The semiconductor layer may have a p-type region (13) provided in the upper portion of the element region and a plurality of p-type guard ring regions (16) provided in the upper portion of the termination region. Here, the p-type region has different names depending on the element structure formed in the element region. For example, when the element structure is a MOSFET structure, it is called a body region; when the element structure is an IGBT structure, it is called a base region; and when the element structure is a diode structure, it is called an anode region. Each of the plurality of guard rings may surround the element region and be arranged at intervals along the inside-outside direction of the semiconductor layer. Each of the plurality of guard rings may have a guard ring lower portion and a guard ring upper portion. The guard ring upper portion may have an outer peripheral wall extending upward from the upper surface on the outer peripheral side of the guard ring lower portion. An n-type region may be provided in a portion above the guard ring lower portion and adjacent to the outer peripheral wall of the guard ring upper portion.

[0006] In the above semiconductor device, an n-type region is provided above the guard ring lower portion. In other words, in the structure of a general guard ring, a part of the guard ring upper portion is replaced by an n-type region. Therefore, an increase in the effective impurity concentration of each of the plurality of guard rings due to the influence of negative external charges is suppressed. Also, in the above semiconductor device, the guard ring upper portion has an outer peripheral wall. Therefore, when the semiconductor device is off, the equipotential lines distributed in the termination region of the semiconductor layer can be arranged substantially parallel in the vertical direction and at intervals along the inside-outside direction. Therefore, since the concentration of the electric field in the termination region of the semiconductor layer is suppressed, the above semiconductor device can have high breakdown voltage characteristics.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0008] Hereinafter, the semiconductor device according to this embodiment will be described with reference to the drawings. For the purpose of clarity of illustration, some of the repeatedly arranged components may be labeled only partially.

[0009] As shown in FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor layer 10. The semiconductor layer 10 is not particularly limited, but is, for example, a semiconductor layer made of silicon carbide (SiC). The semiconductor layer 10 has an element region 101 and a termination region 102. As shown in FIG. 1, the element region 101 is disposed at the center of the semiconductor layer 10 when viewed from a direction (Z direction) orthogonal to the upper surface 10A of the semiconductor layer 10 (hereinafter referred to as "when the semiconductor layer 10 is viewed in plan view"), and is partitioned within the semiconductor layer 10 as a range where an element structure (in this example, a MOSFET structure) is formed. The termination region 102 is disposed at the peripheral portion of the semiconductor layer 10 and around the element region 101 when the semiconductor layer 10 is viewed in plan view, and is partitioned within the semiconductor layer 10 as a range where a breakdown voltage holding structure (in this example, a plurality of guard rings 16 described later) is formed.

[0010] The semiconductor device 1 further includes a source electrode 22 that covers at least a part of the element region 101 on the upper surface 10A of the semiconductor layer 10, an interlayer insulating film 24 that covers at least a part of at least the termination region 102 on the upper surface 10A of the semiconductor layer 10, a drain electrode 26 that covers the entire lower surface 10B of the semiconductor layer 10, and a plurality of trench-type insulating gates 30. The semiconductor device 1 of the present embodiment is a vertical MOSFET and is used as a semiconductor device for power. As shown in FIG. 2, the source electrode 22 and the interlayer insulating film 24 are provided on the upper surface 10A of the semiconductor layer 10. However, in FIG. 1, these components are omitted, and the layout of the plurality of trench-type insulating gates 30 and the breakdown voltage holding structure (in this example, a plurality of guard rings 16 described later) is illustrated.

[0011] As shown in FIG. 2, the semiconductor layer 10 has an n + -type drain region 11, an n - -type drift region 12, a p-type body region 13, and a plurality of n + -type source regions 14, a p +It has a plurality of body contact regions 15 of the n-type and a plurality of guard rings 16 of the p-type. In this embodiment, a case where the guard ring 16 is composed of four guard rings 16a, 16b, 16c, and 16d is illustrated, but it may be composed of a different number. Also, the guard ring 16 is also referred to as an FLR (Field Limiting Ring). The body region 13, the plurality of source regions 14, and the plurality of body contact regions 15 are selectively formed on the upper layer of the element region 101. The plurality of guard rings 16 are selectively formed on the upper layer of the termination region 102. In this embodiment, the boundary between the element region 101 and the termination region 102 is defined by the periphery of the body region 13.

[0012] The drain region 11 is disposed in the lower layer of the semiconductor layer 10 in both the element region 101 and the termination region 102, and is provided at a position exposed to the lower surface 10B of the semiconductor layer 10. The drain region 11 contains a high concentration of an n-type impurity (for example, nitrogen or phosphorus, etc.), and is in ohmic contact with a drain electrode 26 that coats the lower surface 10B of the semiconductor layer 10.

[0013] The drift region 12 is provided on the drain region 11 in both the element region 101 and the termination region 102. The n-type impurity concentration of the drift region 12 is lower than the n-type impurity concentration of the drain region 11.

[0014] The body region 13 is disposed on the drift region 12 located in the element region 101, and is provided in the upper layer of the semiconductor layer 10. The body region 13 is formed by introducing a p-type impurity (for example, aluminum or boron, etc.) into the upper layer of the semiconductor layer 10 using ion implantation technology.

[0015] The source region 14 is disposed on the body region 13 located in the element region 101 and is provided at a position exposed on the upper surface 10A of the semiconductor layer 10. The source region 14 is separated from the drift region 12 by the body region 13. The source region 14 is formed by introducing n-type impurities into the surface layer portion of the semiconductor layer 10 using ion implantation technology. The source region 14 contains a high concentration of n-type impurities and makes an ohmic contact with the source electrode 22 covering the upper surface 10A of the semiconductor layer 10.

[0016] The body contact region 15 is disposed on the body region 13 located in the element region 101 and is provided at a position exposed on the upper surface 10A of the semiconductor layer 10. The body contact region 15 is formed by introducing p-type impurities into the upper layer portion of the semiconductor layer 10 using ion implantation technology. The body contact region 15 contains a high concentration of p-type impurities and makes an ohmic contact with the source electrode 22 covering the upper surface 10A of the semiconductor layer 10.

[0017] As shown in FIG. 1, a plurality of trench-type insulated gates 30 arranged in a stripe shape are formed on the upper surface 10A of the semiconductor layer 10 in the range corresponding to the element region 101 when the semiconductor layer 10 is viewed in plan. Each of the plurality of trench-type insulated gates 30 extends along one direction (Y direction). As shown in FIG. 2, the trench-type insulated gate 30 has a gate insulating film 32 of silicon oxide and a gate electrode 34 of polysilicon. The gate electrode 34 faces the body region 13 in the portion separating the drift region 12 and the source region 14 with the gate insulating film 32 interposed therebetween. Thereby, the body region 13 in the portion separating the drift region 12 and the source region 14 can function as a channel region.

[0018] Thus, an MOSFET structure composed of a drain region 11, a drift region 12, a body region 13, a source region 14, a body contact region, and a trench-type insulated gate 30 is formed in the element region 101 of the semiconductor layer 10. On the other hand, a breakdown voltage holding structure composed of a plurality of guard rings 16 is formed in the termination region 102 of the semiconductor layer 10.

[0019] As shown in FIG. 3, each of the plurality of guard rings 16 is disposed on the upper portion of the terminal region 102 of the semiconductor layer 10 and is provided so as to be surrounded by the drift region 12. The potential of each of the plurality of guard rings 16 is floating. As shown in FIG. 1, each of the plurality of guard rings 16 surrounds the periphery of the element region 101 when the semiconductor layer 10 is viewed in plan, and is arranged at intervals along the inner and outer directions of the semiconductor layer 10. Each of the plurality of guard rings 16 is a concentric similar shape with respect to other guard rings. Thus, the plurality of guard rings 16 are laid out such that the individual guard rings repeatedly appear from the inner peripheral side to the outer peripheral side of the terminal region 102.

[0020] As shown in FIG. 3, each of the plurality of guard rings 16 has a guard ring lower portion 162 located on the lower side in the vertical direction of the semiconductor layer 10 and a guard ring upper portion 164 located on the upper side in the vertical direction of the semiconductor layer 10.

[0021] The under-guard-ring portion 162 has an inner peripheral side surface 162a located on the inner peripheral side of the semiconductor layer 10, an outer peripheral side surface 162b located on the outer peripheral side of the semiconductor layer 10, a bottom surface 162c extending between the inner peripheral side surface 162a and the outer peripheral side surface 162b and located on the lower surface side of the semiconductor layer 10, and a top surface 162d extending between the inner peripheral side surface 162a and the outer peripheral side surface 162b and located on the upper surface side of the semiconductor layer 10. Here, a guard-ring width W16 is defined as the length measured between the inner peripheral side surface 162a and the outer peripheral side surface 162b of the under-guard-ring portion 162 along the inner and outer direction of the semiconductor layer 10, and a guard-ring center line C16 is defined as the line bisecting the space between the inner peripheral side surface 162a and the outer peripheral side surface 162b of the under-guard-ring portion 162. The guard-ring width W16 is common among the plurality of guard rings 16. The distance between the guard rings 16 measured along the inner and outer direction of the semiconductor layer 10 is defined as the distance between the guard-ring center line C16 of one guard ring 16 and the guard-ring center line C16 of the other guard ring 16. In the semiconductor device 1, the distance between the guard rings 16 adjacent to each other on the outer peripheral side of the semiconductor layer 10 is larger than the distance between the guard rings 16 adjacent to each other on the inner peripheral side of the semiconductor layer 10 among the plurality of guard rings 16.

[0022] The over-guard-ring portion 164 has an outer peripheral wall 166 extending upward from the outer peripheral top surface 162d of the under-guard-ring portion 162 and an inner peripheral wall 168 extending upward from the inner peripheral top surface 162d of the under-guard-ring portion 162. The p-type impurity concentration of the outer peripheral wall 166 and the inner peripheral wall 168 of the over-guard-ring portion 164 is smaller than the p-type impurity concentration of the under-guard-ring portion 162. The outer peripheral wall 166 and the inner peripheral wall 168 of the over-guard-ring portion 164 are arranged at intervals in the inner and outer direction of the semiconductor layer 10. For this reason, a recess 167 is defined by the outer peripheral wall 166 and the inner peripheral wall 168 of the over-guard-ring portion 164 and the top surface 162d of the under-guard-ring portion 162, and an n-type region (a part of the drift region 12 in this example) is provided in the recess 167.

[0023] In this example, the outer peripheral side surface of the outer peripheral wall 166 of the upper part 164 of the guard ring is flush with the outer peripheral side surface 162b of the lower part 162 of the guard ring, and the inner peripheral side surface of the inner peripheral wall 168 of the upper part 164 of the guard ring is flush with the inner peripheral side surface 162a of the lower part 162 of the guard ring. Instead of this example, the outer peripheral wall 166 of the upper part 164 of the guard ring may protrude to the outer peripheral side more than the outer peripheral side surface 162b of the lower part 162 of the guard ring, and the inner peripheral wall 168 of the upper part 164 of the guard ring may protrude to the inner peripheral side more than the inner peripheral side surface 162a of the lower part 162 of the guard ring (see FIG. 4). In such an example, in the inner and outer direction of the semiconductor layer 10, the width by which the outer peripheral wall 166 of the upper part 164 of the guard ring protrudes to the outer peripheral side from the outer peripheral side surface 162b of the lower part 162 of the guard ring is equal to or less than half of the guard ring width W16. Similarly, in the inner and outer direction of the semiconductor layer 10, the width by which the inner peripheral wall 168 of the upper part 164 of the guard ring protrudes to the inner peripheral side from the inner peripheral side surface 162a of the lower part 162 of the guard ring is equal to or less than half of the guard ring width W16.

[0024] In this example, the upper ends of the outer peripheral wall 166 and the inner peripheral wall 168 of the upper portion 164 of the guard ring are separated from the upper surface 10A of the semiconductor layer 10. Also, in this example, the upper ends of the outer peripheral wall 166 and the inner peripheral wall 168 of the upper portion 164 of the guard ring are located at the same depth. However, considering the effects described later, the upper end of the outer peripheral wall 166 may be located above the upper end of the inner peripheral wall 168. Further, the upper portion 164 of the guard ring may be provided with only the outer peripheral wall 166 without the inner peripheral wall 168. Here, a guard ring depth D16 is defined as the distance measured between the guard ring 16 and the upper surface 10A of the semiconductor layer 10 along the vertical direction of the semiconductor layer 10. The guard ring depth D16 can be described by the ratio to the body depth D13 of the body region 13 measured along the vertical direction of the semiconductor layer 10. The guard ring depth D16 may be less than or equal to half of the body depth D13 (D16 < D13 / 2), the guard ring depth D16 may be less than or equal to one-third of the body depth D13 (D16 < D13 / 3), the guard ring depth D16 may be less than or equal to one-fourth of the body depth D13 (D16 < D13 / 4). Note that the guard ring depth D16 may be zero, that is, the upper end of the guard ring 16 may reach the upper surface 10A of the semiconductor layer 10. Note that the guard ring depth D16 may be 1 μm or less.

[0025] Next, the operation of the semiconductor device 1 will be described. During the operation of the semiconductor device 1, a voltage is applied between the drain and source such that the potential of the drain electrode 26 becomes higher than the potential of the source electrode 22. When the potential of the gate electrode 34 becomes higher than the threshold value, a channel is formed in the body region 13 in the range in contact with the gate insulating film 32. Then, electrons flow from the source electrode 22 through the source region 14, the channel, the drift region 12, and the drain region 11 to the drain electrode 26. On the other hand, when the potential of the gate electrode 34 becomes lower than the threshold value, the channel disappears and the flow of electrons stops. In this way, the semiconductor device 1 can control the current flowing between the source electrode 22 and the drain electrode 26 based on the potential of the gate electrode 34.

[0026] When the semiconductor device 1 is turned off, a depletion layer spreads from the pn junction surface between the drift region 12 and the body region 13 into the drift region 12. In the drift region 12 of the element region 101, the depletion layer spreads from the upper surface 10A side toward the lower surface 10B side. In the drift region 12 of the termination region 102, the depletion layer spreads from the inner peripheral side toward the outer peripheral side. The depletion layer spreading from the element region 101 can spread greatly toward the outer peripheral side of the termination region 102.

[0027] Negative external charges may enter the interface between the upper surface 10A of the semiconductor layer 10 and the interlayer insulating film 24. Such negative external charges increase the effective impurity concentration of each of the plurality of guard rings 16. When the effective impurity concentration of each of the plurality of guard rings 16 increases, there is a problem that the depletion layer spreading from the element region 101 spreads excessively. The excessive progress of the depletion layer causes the electric field to concentrate in the guard ring 16 located at the outermost periphery among the plurality of guard rings 16. In the semiconductor device 1, a recess 167 is formed in the upper portion 164 of the guard ring, and an n-type region is provided in the recess 167. In other words, in the structure of a general guard ring, a part of the upper portion of the guard ring is replaced with an n-type region. For this reason, an increase in the effective impurity concentration of each of the plurality of guard rings 16 due to negative external charges is suppressed. For this reason, in the semiconductor device 1, excessive progress of the depletion layer is suppressed, so that electric field concentration in the guard ring 16 located at the outermost periphery can be suppressed.

[0028] In order to obtain the above-described effects, it is also conceivable not to form the portion 164 above the guard ring. However, such a structure has a problem in that the withstand voltage decreases. FIG. 5 shows the potential line distribution when the semiconductor device 1 is turned off. FIG. 6 shows the equipotential line distribution when a semiconductor device of a comparative example in which the portion 164 above the guard ring is not formed is turned off. In the comparative example, equipotential lines enter inward toward the inner peripheral side in the vicinity of the upper surface 10A of the semiconductor layer 10, and the electric field concentrates in the vicinity of the upper surface 10A of the semiconductor layer 10 and at the corner portion of the guard ring. Such electric field concentration reduces the withstand voltage of the semiconductor device of the comparative example. On the other hand, in the semiconductor device 1 of the present embodiment, since the outer peripheral wall 166 of the portion 164 above the guard ring is provided, the equipotential lines can be arranged substantially parallel in the vertical direction and at intervals along the inner and outer directions. For this reason, since the concentration of the electric field is suppressed in the terminal region 102 of the semiconductor layer 10, the semiconductor device 1 can have a high withstand voltage characteristic.

[0029] As described above, in order to realize suppression of the influence of the negative external electric field and optimization of the equipotential line distribution, it is sufficient that the portion 164 above the guard ring has at least the outer peripheral wall 166. When the portion 164 above the guard ring further has the inner peripheral wall 168, the effective concentration of the drift region 12 in the vicinity of the interface due to the influence of the positive charges present at the interface between the semiconductor layer 10 and the interlayer insulating film 24 becomes high, and the progress of the depletion layer is suppressed and the withstand voltage decreases. Such an event can be suppressed. Thus, the semiconductor device 1 can have a high withstand voltage characteristic by the portion 164 above the guard ring having the outer peripheral wall 166 and the inner peripheral wall 168.

[0030] Next, a method for manufacturing the semiconductor device 1 will be described. Since the method for manufacturing the semiconductor device 1 is characterized by the step of forming a plurality of guard rings 16, the step of forming a plurality of guard rings 16 will be described below, and the description of other steps will be omitted.

[0031] First, as shown in FIG. 7, a mask 42 that opens corresponding to the formation range of the plurality of lower guard ring portions 162 is formed on the upper surface 10A of the semiconductor layer 10. Next, using ion implantation technology, p-type impurities are implanted into the semiconductor layer 10 through the mask 42 to form the plurality of lower guard ring portions 162. The implantation energy of the p-type impurities (i.e., the implantation depth of the impurities) is adjusted to implant p-type impurities into the interior of the semiconductor layer 10. After ion implantation, the mask 42 is removed.

[0032] Next, as shown in FIG. 8, a mask 44 that opens corresponding to the formation range of the outer peripheral wall 166 of the plurality of upper guard ring portions 164 is formed on the upper surface 10A of the semiconductor layer 10. Next, using ion implantation technology, p-type impurities are implanted into the semiconductor layer 10 through the mask 44 to form the outer peripheral wall 166 of the plurality of upper guard ring portions 164. The implantation energy of the p-type impurities (i.e., the implantation depth of the impurities) is adjusted to implant p-type impurities into the interior of the semiconductor layer 10. After ion implantation, the mask 44 is removed.

[0033] Next, as shown in FIG. 9, a mask 46 that opens corresponding to the formation range of the inner peripheral wall 168 of the plurality of upper guard ring portions 164 is formed on the upper surface 10A of the semiconductor layer 10. Next, using ion implantation technology, p-type impurities are implanted into the semiconductor layer 10 through the mask 46 to form the inner peripheral wall 168 of the plurality of upper guard ring portions 164. The implantation energy of the p-type impurities (i.e., the implantation depth of the impurities) is adjusted to implant p-type impurities into the interior of the semiconductor layer 10. Through these steps, the plurality of guard rings 16 can be formed.

[0034] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Numerals

[0035] 1: Semiconductor device, 10: Semiconductor layer, 11: Drain region, 12: Drift region, 13: Body region, 14: Source region, 15: Body contact region, 16: Guard ring, 22: Source electrode, 24: Interlayer insulating film, 26: Drain electrode, 30: Trench-type insulated gate, 101: Element region, 102: Termination region, 162: Portion under the guard ring, 164: Portion above the guard ring, 166: Outer peripheral wall, 168: Inner peripheral wall

Claims

1. A semiconductor device (1), comprising: a semiconductor layer (10) having an element region (101) in which an element structure is formed and a termination region (102) located around the element region; The semiconductor layer has a p-type region (13) provided in an upper portion of the element region, and a plurality of p-type guard ring regions (16) provided in an upper portion of the termination region; Each of the plurality of guard rings surrounds the element region and is arranged at intervals along the inner and outer directions of the semiconductor layer; Each of the plurality of guard rings has a guard ring lower portion (162) and a guard ring upper portion (164); The guard ring upper portion has an outer peripheral wall (166) extending upward from an upper surface on an outer peripheral side of the guard ring lower portion; An n-type region (12) is provided in a portion above the guard ring lower portion and adjacent to the outer peripheral wall of the guard ring upper portion.

2. The guard ring upper portion further has an inner peripheral wall (168) extending upward from an upper surface on an inner peripheral side of the guard ring lower portion; The semiconductor device according to claim 1, wherein the n-type region is provided in a recess (167) between the outer peripheral wall and the inner peripheral wall of the guard ring upper portion.

3. The distance between the guard rings measured along the inner and outer directions of the semiconductor layer is larger for the guard rings adjacent to each other on the outer peripheral side of the semiconductor layer than for the guard rings adjacent to each other on the inner peripheral side of the semiconductor layer among the plurality of guard rings.

4. The semiconductor device according to any one of claims 1 to 3, wherein the material of the semiconductor layer is silicon carbide.

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