Semiconductor device and manufacturing method thereof

Abstract

To simultaneously process a contact in a first semiconductor element made of a thin polysilicon film and a contact in a second semiconductor element.SOLUTION: A semiconductor device 100 includes an insulating film 30 and a polysilicon film 40 formed on the insulating film 30. In a plan view, the semiconductor device 10 includes a first region including a first semiconductor element configured with the polysilicon film 40, and a second region including a second semiconductor element. A first contact hole H1 formed in the first region penetrates the polysilicon film 40. An ohmic contact is formed between the metal embedded in the first contact hole H1 and the polysilicon film 40 on the side surface of the first contact hole H1.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a polysilicon film and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a temperature detection diode formed of a polysilicon film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] There is a problem that it is difficult to simultaneously process a contact in a semiconductor element formed of a thin polysilicon film and a contact in a semiconductor element such as a transistor.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment includes an insulating film and a polysilicon film formed on the insulating film. In a plan view, the semiconductor device includes a first region including a first semiconductor element formed of the polysilicon film and a second region including a second semiconductor element. A first contact hole formed in the first region penetrates the polysilicon film, and an ohmic contact is formed on a side surface of the first contact hole between the metal embedded in the first contact hole and the polysilicon film.

[0007] In a method of manufacturing a semiconductor device according to an embodiment, the semiconductor device includes an insulating film and a polysilicon film formed on the insulating film. In a plan view, the semiconductor device includes a first region including a first semiconductor element formed of the polysilicon film and a second region including a second semiconductor element. The method of manufacturing the semiconductor device includes forming a first contact hole penetrating the polysilicon film in the first region and forming a second contact hole in the second region, and performing oblique ion implantation so that an ion implantation region is formed in a cross section of the polysilicon film by the first contact hole.

Effects of the Invention

[0008] According to the above embodiment, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device capable of simultaneously processing contacts in a first semiconductor element formed of a thin polysilicon film and contacts in a second semiconductor element.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Mode for Carrying Out the Invention

[0010] For the sake of clarity of explanation, the following descriptions and drawings have been appropriately omitted and simplified. In each drawing, the same reference numerals are assigned to the same elements, and duplicate explanations are omitted as necessary.

[0011] Considerations Leading to the Embodiment FIG. 1 is an equivalent circuit diagram of a semiconductor device 10 according to a comparative example. The semiconductor device 10 includes a main IGBT 11m, a sub-IGBT 11s, a temperature detection diode 12, and a built-in gate resistor 13. The main IGBT 11m and the sub-IGBT 11s include protection diodes 111.

[0012] The collector of the main IGBT 11m and the collector of the sub-IGBT 11s are connected to each other. The emitter of the main IGBT 11m is connected to the main emitter terminal, and the emitter of the sub-IGBT 11s is connected to the sub-emitter terminal. The main emitter terminal is connected to the Kelvin emitter terminal. When the main IGBT 11m and the sub-IGBT 11s are not distinguished from each other, they may simply be referred to as IGBT11.

[0013] The protection diode 111 is disposed between the gate and the emitter of the IGBT11. The protection diode 111 protects the gate insulating film of the IGBT 11 by discharging the instantaneous high voltage (surge) generated between the gate and the emitter of the IGBT 11.

[0014] The temperature detection diode 12 is used to detect the temperature of the semiconductor device 10. The temperature is detected by utilizing the temperature dependence of the forward voltage (VF) of the temperature detection diode 12. The temperature detection diode 12 is composed of a polysilicon film. Four diode elements are arranged in series between the anode terminal and the cathode terminal.

[0015] The built-in gate resistor 13 adjusts the rising and falling speeds of the gate voltage of the IGBT 11.

[0016] When the semiconductor device 10 is viewed in plan view, the IGBT 11, the temperature detection diode 12, and the built-in gate resistor 13 are arranged in mutually different regions. In particular, the region where the temperature detection diode 12 is arranged (also referred to as the diode region) is different from the region where the IGBT 11 is arranged (also referred to as the cell region). FIG. 2 shows an arrangement example of the diode region A1 and the cell region A2.

[0017] Referring to FIG. 3, a method for manufacturing a semiconductor device according to a first comparative example will be described.

[0018] Referring to the upper diagram, the left diagram shows a schematic cross-sectional view of the cell region, and the right diagram shows a schematic cross-sectional view of the diode region. Referring to the left diagram, an n-type semiconductor region 21, a p-type semiconductor region 22, and a trench gate electrode 23 are formed in the silicon substrate 20. The trench gate electrode is embedded in the trench via a gate insulating film. An oxide film 50 is formed on the silicon substrate 20, and the oxide film 50 is covered with a resist 60. A pattern is formed in the resist 60 by photolithography technology, and the oxide film 50 is etched using the resist pattern as an etching mask, and an opening is formed in the oxide film 50. The oxide film 50 may be, for example, a TEOS (Tetraethyl orthosilicate) film.

[0019] Referring to the right figure, an insulating film 30 is formed on a silicon substrate 20. A polysilicon film 40 is formed on the insulating film 30. By performing ion implantation, a p-type semiconductor region 41 and an n+-type semiconductor region 42 are formed in the polysilicon film. For example, boron is implanted into the p-type semiconductor region 41. An oxide film 50 is formed on the polysilicon film, and the oxide film 50 is covered with a resist 60. A pattern is formed in the resist 60 by photolithography technology, and the oxide film 50 is etched using the resist pattern as an etching mask, and an opening is formed in the oxide film 50.

[0020] Referring to the middle figure, the silicon substrate 20 exposed at the opening of the oxide film 50 is etched (e.g., dry etching), so that a contact hole H2 is formed in the cell region, and contact holes H11 and H12 are formed in the diode region. Referring to the left figure, the contact hole H2 reaches the p-type semiconductor region 22. Referring to the right figure, since the polysilicon film 40 is thick enough, the contact holes H11 and H12 do not penetrate the polysilicon film 40.

[0021] Referring to the lower figure, by ion implantation, a p+-type ion implantation region I2 is formed in the p-type semiconductor region 22 of the cell region, and p+-type ion implantation regions I11 and I12 are formed in the diode region. The ion implantation regions I11 and I12 are formed in the p-type semiconductor region 41 and the n+-type semiconductor region 42, respectively.

[0022] Thus, when the contact hole H2 does not penetrate the polysilicon film 40, an ion implantation region I2 can be formed in the cell region and an ion implantation region I11 can be formed in the diode region at the same time, which has the advantage of fewer process steps.

[0023] Referring to FIG. 4, a method for manufacturing a semiconductor device according to a second comparative example will be described. The polysilicon film 40 according to the second comparative example is thinner than the polysilicon film 40 according to the first comparative example. The upper, middle, and lower diagrams in FIG. 4 respectively correspond to the upper, middle, and lower diagrams in FIG. 3. Referring to the middle diagram, the contact hole H11 in the diode region penetrates the polysilicon film 40. Referring to the lower diagram, the implanted ions pass through the polysilicon film 40 and reach the insulating film 30. Therefore, the contact between the metal formed (embedded) in the contact hole H11 and the p-type semiconductor region 41 of the polysilicon film 40 does not become an ohmic contact. In this case, there is a problem that the forward voltage (VF) variation of the temperature detection diode formed by the polysilicon film 40 occurs. And in order to avoid the occurrence of VF variation, it is necessary to separate the step of forming the contact hole H2 in the cell region and the step of forming the contact hole H11 in the diode region, and there is a problem that the number of steps increases.

[0024] Embodiment 1 FIG. 5 shows a schematic cross-sectional view of the diode region of the semiconductor device 100 according to Embodiment 1. Note that the semiconductor device 100 further includes a cell region, similar to the semiconductor device 10.

[0025] The semiconductor device 100 includes a silicon substrate 20, an insulating film 30, a polysilicon film 40, an oxide film 50, a barrier metal layer 70, and a wiring layer 80.

[0026] In the silicon substrate 20, a p-type well region 25 is formed on the n-type semiconductor region 24.

[0027] The insulating film 30 is formed on the well region 25. Specifically, the insulating film 30 includes an insulating region of a LOCOS (LOCal Oxidation of Silicon) structure formed on the well region 25 and an LPTEOS (Low Pressure TetraEthyl OrthoSillicate) film formed on the insulating region.

[0028] The polysilicon film 40 is formed on the insulating film 30. The polysilicon film 40 includes a p-type semiconductor region 41 and an n+-type semiconductor region 42.

[0029] The oxide film 50 is formed on the polysilicon film 40. The oxide film 50 is, for example, a PECVD film.

[0030] The barrier metal layer 70 is formed on the oxide film 50. The barrier metal layer 70 is composed of a material such as titanium tungsten (TiW), for example.

[0031] The wiring layer 80 is formed on the barrier metal layer 70. The wiring layer 80 is composed of a material such as Al or Cu, for example.

[0032] Contact holes H11 and H12 penetrating the oxide film 50 and the polysilicon film 40 are formed. And a p+-type ion implantation region I11 is formed on the side wall of the p-type semiconductor region 41. The side wall means the cross section of the p-type semiconductor region 41 by the contact hole H11. A metal such as tungsten (W) is formed (embedded) in the contact hole H11. A titanium nitride (TiN) film may be laid under the tungsten.

[0033] By forming the ion implantation region I11, the contact between the metal embedded in the contact hole H11 and the polysilicon film 40 becomes an ohmic contact. In the cell region, an ohmic contact is formed at the bottom surface of the contact hole H2.

[0034] FIG. 6 is an explanatory diagram showing a method of manufacturing the semiconductor device 100. The upper diagram and the lower diagram of FIG. 6 respectively correspond to the middle diagram and the lower diagram of FIG. 4.

[0035] Referring to the upper diagram of FIG. 6, a contact hole H2 is formed in the cell region, and contact holes H11 and H12 are formed in the diode region. Contact hole H1 penetrates the polysilicon film 40. By ion implantation, an ion implantation region I2 is formed in the p-type semiconductor region 22 of the cell region. At this time, in the diode region, ions are implanted into the insulating film 30.

[0036] Referring to the lower diagram, ions are implanted in the direction indicated by the arrow by oblique implantation. Thereby, ion implantation regions I11 and I12 are formed on the sidewalls of the polysilicon film 40 in the diode region. The sidewall means the cross section of the polysilicon film 40 by the contact holes H11 and H12. At this time, the aspect ratio (W / H) of the contact hole H2 may be appropriately set so that ions are not implanted into the silicon substrate 20 in the cell region. The aspect ratio is defined, for example, as the minimum value of the width of the contact hole with respect to the depth of the contact hole.

[0037] FIG. 7 is an explanatory diagram showing a first configuration example of the semiconductor device 100. The upper diagram is a schematic plan view of the semiconductor device 100, and the lower diagram is a schematic cross-sectional view. In the upper diagram, the illustration of the oxide film 50 is partially omitted. The thickness direction of the silicon substrate 20 is defined as the Z direction. The left-right direction in the upper diagram is defined as the Y direction, and the up-down direction in the upper diagram is defined as the X direction.

[0038] A contact hole H11 penetrating the p-type semiconductor region 41 of polysilicon is formed, a contact hole H12 penetrating the n+-type semiconductor region 42 of polysilicon is formed, and a contact hole H2 penetrating the n-type semiconductor region 21 of the cell region is formed. The contact holes H11, H12, and H2 extend in the X direction. The width of the contact hole H11 in the X direction is larger than the width of the contact hole H12 in the X direction. The width of the contact hole H11 in the X direction is larger than the width of the contact hole H2 in the X direction. That is, the aspect ratio of the contact hole H11 is smaller than the aspect ratio of the contact hole H2. The aspect ratio of the contact hole H11 is smaller than the aspect ratio of the contact hole H12.

[0039] When manufacturing the semiconductor device 100, first, ions are implanted in the -Z direction as shown by "1". Next, as shown by "2", ions are implanted in a direction having a negative Z component and a positive Y component, and then, as shown by "3", ions are implanted in a direction having a negative Z component and a negative Y component. Thereby, an ion implantation region I is formed. By "2" and "3", ions are implanted in the sidewalls of the p-type semiconductor region 41.

[0040] Since the aspect ratio of the contact hole H2 is high, ions are not implanted in the n-type semiconductor region 21 of the cell region. Also, since the aspect ratio of the contact hole H12 is high, ions are not implanted in the n+-type semiconductor region 42 of polysilicon.

[0041] Also, the contact hole H11 may be formed such that the inclination angle of the sidewall becomes gentle. When the sidewall is gentle, there is an advantage that ions H11 are easily implanted in the sidewall.

[0042] FIG. 8 is an explanatory diagram showing a second configuration example of the semiconductor device 100. The contact hole H11 extends in the Y direction, and the contact holes H2 and H12 extend in the X direction. In the step of "2", ions are implanted in a direction having a negative Z component and a negative X component, and in the step of (3), ions are implanted in a direction having a negative Z component and a positive X component. The step of (1) may be further executed.

[0043] In the steps of (2) and (3), ions are implanted into the sidewalls of the p-type semiconductor region 41. Since the contact holes H2 and H12 extend in the X direction, it is possible to prevent ions from being implanted into the sidewalls of the n-type semiconductor region 21 and the n+-type semiconductor region 42.

[0044] FIG. 9 is a graph showing the electrical characteristics of the temperature detection diode. The horizontal axis represents the forward voltage, and the vertical axis represents the forward current. Curve 91 shows the electrical characteristics of the semiconductor device according to the first comparative example, curve 92 shows the electrical characteristics of the semiconductor device according to the second comparative example, and curve 93 shows the electrical characteristics of the semiconductor device 100 according to Embodiment 1. In Comparative Example 2, since the contact between the temperature detection diode and the contact is not an ohmic contact, the value of the forward current in Comparative Example 2 is smaller than the value of the forward current in Comparative Example 1. It has been found that when Embodiment 1 is used, electrical characteristics equivalent to those of Comparative Example 1 can be obtained.

[0045] The upper diagram of FIG. 10 shows the variation in the electrical characteristics of the semiconductor device according to the second comparative example, the middle diagram shows the variation in the electrical characteristics of the semiconductor device according to the first comparative example, and the lower diagram shows an overview of the variation in the electrical characteristics of the semiconductor device according to the embodiment. The horizontal axis represents the forward voltage, and the vertical axis represents the forward current. In the second comparative example, the variation in the electrical characteristics is large, but by using Embodiment 1, the variation in the electrical characteristics can be suppressed.

[0046] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

[0047] For example, in the IGBT according to the above embodiment, the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. may be inverted. Therefore, when one of the n-type and p-type conductivity types is the first conductivity type and the other is the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0048] The semiconductor element composed of the polysilicon film 40 is not limited to the diode for temperature detection, and the semiconductor element may be a diode (e.g., protection diode) used for other applications or a fuse (e.g., e-Fuse).

Description of Reference Numerals

[0049] 10, 100 Semiconductor device 11m Main IGBT 11s Sub IGBT 111 Protection diode 12 Diode for temperature detection 13 Built-in gate resistor 20 Silicon substrate 21, 24 n-type semiconductor regions 22 p-type semiconductor region 23 Trench gate electrode 30 Insulating film 40 Polysilicon film 41 p-type semiconductor region 42 n+-type semiconductor region 50 Oxide film 60 Resist 70 Barrier metal layer 80 Wiring layer 91, 92, 93 Curves H11, H12, H2 Contact holes I1, I2, I Ion implantation regions

Claims

1. An insulating film, A polysilicon film formed on the insulating film, A semiconductor device comprising: In plan view, the semiconductor device includes a first region including a first semiconductor element formed of the polysilicon film and a second region including a second semiconductor element, A first contact hole formed in the first region penetrates the polysilicon film, An ohmic contact is formed on a side surface of the first contact hole between the metal embedded in the first contact hole and the polysilicon film. Semiconductor device.

2. An ion implantation region is formed in a cross section of the polysilicon film by the first contact hole. The semiconductor device according to claim 1.

3. An ohmic contact is formed on a bottom surface of the second contact hole between the metal embedded in the second contact hole formed in the second region and the substrate on which the second semiconductor element is formed. The semiconductor device according to claim 2.

4. The aspect ratio of the first contact hole is larger than the aspect ratio of the second contact hole. The semiconductor device according to claim 3.

5. The first contact hole extends in a first width direction orthogonal to the thickness direction of the substrate on which the second semiconductor element is formed, The second contact hole extends in a second width direction orthogonal to the first width direction. The semiconductor device according to claim 3.

6. The semiconductor element is a temperature sensing diode. The semiconductor device according to claim 1.

7. A method for manufacturing a semiconductor device, comprising: The semiconductor device includes an insulating film and a polysilicon film formed on the insulating film, In plan view, the semiconductor device includes a first region including a first semiconductor element formed of the polysilicon film and a second region including a second semiconductor element, Forming a first contact hole penetrating the polysilicon film in the first region and forming a second contact hole in the second region; Performing oblique ion implantation so that an ion implantation region is formed in a cross section of the polysilicon film by the first contact hole. A method for manufacturing a semiconductor device.

Images