Semiconductor element and optical sensor

Abstract

To provide a semiconductor element reduced in parasitic capacitance.SOLUTION: A semiconductor element 1 has a main surface 11. The semiconductor element 1 includes a first N-type region N1, a first P-type region P1 and a second P-type region P2. The first N-type region N1 is formed inside the semiconductor element 1. The first P-type region P1 is formed on the main surface 11. The concentration of impurities contained in the second P-type region P2 is less than the concentration of impurities contained in the first P-type region P1. In plan view of the main surface 11, the first P-type region P1 is formed so as to overlap with the first N-type region N1. The second P-type region P2 is formed between the first N-type region N1 and the first P-type region P1. In plan view, the area of the first P-type region P1 is smaller than the area of the second P-type region P2.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an optical sensor.

Background Art

[0002] International Publication No. 2020 / 137967 (Patent Document 1) discloses an optical sensor having a semiconductor device. The semiconductor device is a photodiode in which a photocurrent flows when irradiated with light.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] A semiconductor device according to an aspect of the present disclosure has a main surface. The semiconductor device includes a first N-type region, a first P-type region, and a second P-type region. The first N-type region is formed inside the semiconductor device. The first P-type region is formed on the main surface. The concentration of impurities contained in the second P-type region is smaller than the concentration of impurities contained in the first P-type region. In a plan view of the main surface, the first P-type region is formed so as to overlap the first N-type region. The second P-type region is formed between the first N-type region and the first P-type region. In a plan view, the area of the first P-type region is smaller than the area of the second P-type region.

[0005] A semiconductor device according to one aspect of the present disclosure has a main surface. The semiconductor device includes a first N-type region, a plurality of first P-type regions, and a second P-type region. The first N-type region is formed inside the semiconductor device. The first P-type regions are formed on the main surface. The concentration of impurities contained in the second P-type region is smaller than the concentration of impurities contained in the first P-type regions. In a plan view of the main surface, the first P-type regions are formed so as to overlap the first N-type region. The second P-type region is formed between the first N-type region and the first P-type regions.

Brief Description of the Drawings

[0006]

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[0007] (Embodiment 1) FIG. 1 is a schematic plan view of the semiconductor element 1 according to Embodiment 1. FIG. 2 is a schematic cross-sectional view of the semiconductor element 1 along line segment II-II in FIG. 1. In FIG. 1, the outer shape of the second P-type region P2 is indicated by a dotted line.

[0008] The semiconductor element 1 is, for example, a photodiode in which a photocurrent flows when irradiated with light. The semiconductor element 1 has a main surface 11. The semiconductor element 1 is a semiconductor element in which an element region is formed in the vicinity of the main surface 11, and mainly includes an N-type region N, a P-type region P, a first P-type region P1, and an insulating region 3. The N-type region N, the P-type region P, the first P-type region P1, and the insulating region 3 are formed inside a second layer 1b having a conductive type of P-type. The portion including at least the N-type region N, the P-type region P, and the first P-type region P1 corresponds to a light receiving portion.

[0009] The semiconductor element 1 may be a semiconductor element 1 formed by laminating a plurality of layers. As shown in FIG. 2, the semiconductor element 1 may have a two-layer structure composed of a first layer 1a and a second layer 1b. The first layer 1a may be, for example, a silicon substrate.

[0010] The conductivity type of the second layer 1b may be P-type. The second layer 1b may be, for example, an epitaxial layer. The epitaxial layer is formed by epitaxial growth on the surface of the first layer 1a. The second layer 1b may be, for example, a well layer formed by adding impurities on the surface of the first layer 1a. The surface of the second layer 1b constitutes the main surface 11.

[0011] When the conductivity type of the first layer 1a is P-type, the semiconductor element 1 may have a one-layer structure composed of the first layer 1a. The surface of the first layer 1a constitutes the main surface 11. When the semiconductor element 1 has a one-layer structure, the N-type region N, the P-type region P, the first P-type region P1, and the insulating region 3 may be formed inside the first layer 1a having a P-type conductivity type.

[0012] The conductivity type of the second layer 1b is P-type. Therefore, a P-type region P is formed inside the semiconductor element 1. That is, the conductivity type of the P-type region P is P-type. The impurity contained in the P-type region P may be of P-type, and may be, for example, any one of boron (B), aluminum (Al), and gallium (Ga).

[0013] The P-type region P includes a second P-type region P2 and a third P-type region P3. The concentration of the impurity contained in the second P-type region P2 may be the same as the concentration of the impurity contained in the third P-type region P3.

[0014] Taking the direction perpendicular to the main surface 11 as the z direction. The second P-type region P2 is formed at a distance in the z direction from the main surface 11 via the first P-type region P1. The second P-type region P2 is surrounded by the first P-type region P1, the N-type region N, and the first insulating region 3a. The second P-type region P2 is formed between the first N-type region N1 and the first P-type region P1.

[0015] The third P-type region P3 is formed to be spaced apart in the z direction from the main surface 11 with the N-type region N and the second insulating region 3b therebetween. The third P-type region P3 is formed to be spaced apart in the z direction from the second P-type region P2 through the first N-type region N1. The third P-type region P3 is connected to the first layer 1a on the surface opposite to the surface connected to the first N-type region N1 in the z direction.

[0016] The N-type region N is a diffusion region having an N-type conductivity type. The impurity contained in the N-type region N may be any one of phosphorus (P), arsenic (As), and antimony (Sb). A part of the N-type region N is formed on the main surface 11. Specifically, the N-type region N includes a first N-type region N1 and a second N-type region N2. The first N-type region N1 is formed between the second P-type region P2 and the third P-type region P3 in the z direction. The second N-type region N2 is formed on the main surface 11. The first N-type region N1 and the second N-type region N2 are connected on the outer periphery of the second P-type region P2. The concentration of the impurity contained in the first N-type region N1 may be the same as the concentration of the impurity contained in the second N-type region N2.

[0017] As shown in FIG. 2, the first P-type region P1 is formed on the main surface 11. In a plan view of the main surface 11, the first P-type region P1 is formed so as to overlap the first N-type region N1 and the second P-type region P2.

[0018] The first P-type region P1 is a diffusion region having a P-type conductivity type. The impurity contained in the first P-type region P1 may be any one of boron (B), aluminum (Al), and gallium (Ga). The impurity contained in the first P-type region P1 may be the same as the impurity contained in the P-type region P. That is, the impurity contained in the first P-type region P1 may be the same as the impurity contained in the second layer 1b. The concentration of the impurity contained in the first P-type region P1 is greater than the concentration of the impurity contained in the P-type region P. That is, each of the concentrations of the impurities contained in the second P-type region P2 and the third P-type region P3 is smaller than the concentration of the impurity contained in the first P-type region P1.

[0019] As shown in FIG. 2, the insulating region 3 is formed on the main surface 11. The material constituting the insulating region 3 is, for example, silicon dioxide (SiO2). The insulating region 3 includes a first insulating region 3a and a second insulating region 3b.

[0020] As shown in FIG. 1, in a plan view of the main surface 11, the first insulating region 3a is formed so as to surround the first P-type region P1. From a different perspective, on the main surface 11, the second N-type region N2 is formed at a distance from the first P-type region P1 via the first insulating region 3a. In this way, the first insulating region 3a insulates the first P-type region P1 and the second N-type region N2.

[0021] In a plan view of the main surface 11, the second insulating region 3b is formed at the outer peripheral portion of the semiconductor element 1. As shown in FIG. 1, in a plan view of the main surface 11, the second insulating region 3b surrounds the first P-type region P1 and the second P-type region P2.

[0022] The semiconductor element 1 may further include a metal wiring 2. The metal wiring 2 includes a first electrode 2a and a second electrode 2b. The first electrode 2a is connected to the first P-type region P1 on the main surface 11. The second electrode 2b is connected to the second N-type region N2 on the main surface 11.

[0023] The operation of the semiconductor element 1 of the present embodiment will be described. A reverse bias voltage is applied between the first electrode 2a and the second electrode 2b. The second electrode 2b is connected to, for example, ground. That is, a bias voltage is applied between the first electrode 2a and the second electrode 2b so that the potential of the second electrode 2b becomes higher than the potential of the first electrode 2a. Here, a depletion layer is formed in the second P-type region P2.

[0024] When light irradiates the semiconductor element 1, electrons are excited. Due to the reverse bias voltage, carriers (electrons and holes) move according to the electric field in the depletion layer. Due to the movement of these carriers, a photocurrent flows in the semiconductor element 1. As a result, the intensity of the light irradiating the semiconductor element 1 is detected. The region where the depletion layer is formed contributes to the light sensitivity of the semiconductor element 1.

[0025] On the other hand, the connection interfaces between the depletion layer and the first P-type region P1, and between the depletion layer and the N-type region N act as electrodes of the depletion layer. The area of both ends of the depletion layer contributes to the parasitic capacitance in the semiconductor element 1. That is, when the electrode of the depletion layer is large, the parasitic capacitance in the semiconductor element 1 becomes large. When the parasitic capacitance is large, the noise becomes large.

[0026] Here, the feature of the semiconductor element 1 according to the first embodiment is that, as shown in FIGS. 1 and 2, the region where the first P-type region P1 is formed is smaller than the region where the second P-type region P2 is formed. In a conventional semiconductor element, the first P-type region P1 is formed over substantially the entire main surface 11. Specifically, in a conventional semiconductor element, the area of the first P-type region P1 in a plan view of the main surface 11 is the same as the area of the second P-type region P2.

[0027] On the other hand, in the semiconductor element 1 according to the first embodiment, in a plan view of the main surface 11, the area of the first P-type region P1 is smaller than the area of the second P-type region P2. By doing so, the connection interface between the depletion layer and the first P-type region P1 can be reduced. As a result, one of the electrodes of the depletion layer becomes smaller. By making one of the electrodes of the depletion layer smaller, the parasitic capacitance in the semiconductor element 1 can be greatly reduced while suppressing the reduction in the light sensitivity of the semiconductor element 1. In a plan view of the main surface 11, the area of the first P-type region P1 may be smaller than the area of the first N-type region N1.

[0028] (Method for manufacturing a semiconductor element) Hereinafter, the method for manufacturing the semiconductor element 1 of the present embodiment will be described. FIG. 3 is a flowchart in the method for manufacturing the semiconductor element 1 of the first embodiment.

[0029] First, a step (S1) of preparing the first layer 1a is performed. FIG. 4 is a schematic cross-sectional view showing one step in the manufacturing method of the semiconductor element 1 of Embodiment 1. In this step (S1), as shown in FIG. 4, the first layer 1a having a surface 1s is prepared. The first layer 1a is, for example, a silicon substrate.

[0030] Next, a step (S2) of forming the second layer 1b is performed. FIG. 5 is a schematic cross-sectional view showing the next step of the step shown in FIG. 5 in the manufacturing method of the semiconductor element 1 of Embodiment 1. In this step (S2), the second layer 1b is formed on the surface 1s of the first layer 1a. The second layer 1b is, for example, an epitaxial layer. The epitaxial layer is formed by epitaxial growth. The conductivity type of the second layer 1b formed by epitaxial growth is P-type.

[0031] Next, a step (S3) of forming the insulating region 3 is performed. FIG. 6 is a schematic cross-sectional view showing the next step of the step shown in FIG. 5 in the manufacturing method of the semiconductor element 1 of Embodiment 1. In this step (S3), as shown in FIG. 6, the insulating region 3 is formed on the main surface 11. Specifically, a first insulating region 3a is formed at the center of the second layer 1b in a plan view of the main surface 11. A second insulating region 3b is formed at the outer peripheral portion of the second layer 1b in a plan view of the main surface 11. The insulating region 3 may be formed by thermal oxidation or by plasma CVD (Chemical Vapor Deposition).

[0032] Next, a step (S4) of forming the first N-type region N1 is performed. FIG. 7 is a schematic cross-sectional view showing the next step of the step shown in FIG. 6 in the manufacturing method of the semiconductor element 1 of Embodiment 1. In this step (S4), as shown in FIG. 7, the first N-type region N1 is formed inside the second layer 1b. Specifically, an N-type impurity such as phosphorus (P) is implanted. The region where the first N-type region N1 is formed is spaced apart from the main surface 11 in the z direction.

[0033] Next, a step (S5) of forming the first P-type region P1 is performed. FIG. 8 is a schematic plan sectional view showing the next step of the step shown in FIG. 7 in the manufacturing method of the semiconductor element 1 of the first embodiment. In this step (S5), as shown in FIG. 8, the first P-type region P1 is formed on the main surface 11. Specifically, P-type impurities such as boron (B) are implanted. The first P-type region P1 is formed such that the concentration of impurities contained in the first P-type region P1 is higher than the concentration of impurities contained in the second layer 1b. In a plan view of the main surface 11, the first P-type region P1 is formed so as to be surrounded by the first insulating region 3a.

[0034] Next, a step (S6) of forming the second N-type region N2 is performed. FIG. 9 is a schematic sectional view showing the next step of the step shown in FIG. 8 in the manufacturing method of the semiconductor element 1 of the first embodiment. In this step (S6), as shown in FIG. 9, the second N-type region N2 is formed on the main surface 11. Specifically, N-type impurities such as phosphorus (P) are implanted. The second N-type region N2 is formed such that a part of the P-type region P remains between the first P-type region P1 and the first N-type region N1 in the z direction. A part of the P-type region P remaining between the first P-type region P1 and the first N-type region N1 is the second P-type region P2. On the outer periphery of the second P-type region P2, the first N-type region N1 and the second N-type region N2 are connected.

[0035] Next, a step (S7) of forming the metal wiring 2 is performed. In this step (S7), the metal wiring 2 is formed on the main surface 11. The first electrode 2a is connected to the first P-type region P1 on the main surface 11. The second electrode 2b is connected to the second N-type region N2 on the main surface 11. The metal wiring 2 is formed, for example, by sputtering. The material constituting the metal wiring 2 may be any material having conductivity.

[0036] In this way, the semiconductor element 1 according to the first embodiment shown in FIG. 1 is manufactured.

[0037] (Function and Effect) The semiconductor element 1 according to the present disclosure has a main surface 11. The semiconductor element 1 includes a first N-type region N1, a first P-type region P1, and a second P-type region P2. The first N-type region N1 is formed inside the semiconductor element 1. The first P-type region P1 is formed on the main surface 11. The concentration of impurities contained in the second P-type region P2 is smaller than the concentration of impurities contained in the first P-type region P1. In a plan view of the main surface 11, the first P-type region P1 is formed so as to overlap the first N-type region N1. The second P-type region P2 is formed between the first N-type region N1 and the first P-type region P1. In a plan view, the area of the first P-type region P1 is smaller than the area of the second P-type region P2.

[0038] In this way, the connection interface between the depletion layer and the first P-type region P1 can be reduced. As a result, one electrode of the depletion layer becomes smaller. By making one electrode of the depletion layer smaller, the parasitic capacitance in the semiconductor element 1 can be greatly reduced while suppressing a decrease in the light sensitivity in the semiconductor element 1.

[0039] The semiconductor element 1 includes an insulating region 3 and a second N-type region N2. The insulating region 3 is formed on the main surface 11. The second N-type region N2 is formed on the main surface 11. On the main surface 11, the second N-type region N2 is formed so as to be separated from the first P-type region P1 with the insulating region 3 interposed therebetween.

[0040] In this way, on the main surface 11, the first P-type region P1 and the second N-type region N2 are insulated from each other.

[0041] (Embodiment 2) FIG. 10 is a schematic plan view of the semiconductor element 1 according to Embodiment 2. FIG. 10 corresponds to FIG. 1. FIG. 11 is a schematic cross-sectional view of the semiconductor element 1 taken along line XI-XI in FIG. 10. FIG. 11 corresponds to FIG. 2. The semiconductor element 1 shown in FIGS. 10 and 11 basically has the same configuration as the semiconductor element 1 shown in FIGS. 1 and 2 and can obtain the same effects, but is different in that there are a plurality of first P-type regions P1 formed on the main surface 11. In this way, the light sensitivity in the semiconductor element 1 increases.

[0042] On the main surface 11, the first P-type regions P1 are arranged apart from each other, so that the sensitivity to light increases. Therefore, as shown in FIG. 10, on the main surface 11, the plurality of first P-type regions P1 may be arranged in a matrix.

[0043] In the semiconductor device 1 according to the second embodiment, since there are a plurality of first P-type regions P1, the area of the electrode of the depletion layer (the total area of the connection interfaces between the depletion layer and the plurality of first P-type regions P1) is larger than the area of the electrode of the depletion layer in the semiconductor device 1 according to the first embodiment. That is, the parasitic capacitance in the semiconductor device 1 according to the second embodiment may increase compared to the parasitic capacitance in the semiconductor device 1 according to the first embodiment. However, the reduction rate of the parasitic capacitance in the second embodiment is, for example, 87%, and the reduction rate of the light sensitivity is, for example, 43%. Thus, the reduction rate of the parasitic capacitance is large with respect to the reduction rate of the light sensitivity. That is, the parasitic capacitance in the semiconductor device 1 can be greatly reduced while suppressing the reduction of the light sensitivity in the semiconductor device 1.

[0044] Note that the "reduction rate of the parasitic capacitance" here is the ratio of the parasitic capacitance in the second embodiment to the parasitic capacitance in the conventional semiconductor device. As described above, in the conventional semiconductor device, the first P-type region P1 is formed over substantially the entire main surface 11. That is, in the conventional semiconductor device, the area of the first P-type region P1 in a plan view of the main surface 11 is the same as the area of the second P-type region P2. The "reduction rate of the light sensitivity" here is the ratio of the light sensitivity in the second embodiment to the light sensitivity in the conventional semiconductor device.

[0045] (Function and Effect) The semiconductor device 1 according to the present disclosure has a main surface 11. The semiconductor device 1 includes a first N-type region N1, a plurality of first P-type regions P1, and a second P-type region P2. The first N-type region N1 is formed inside the semiconductor device 1. The first P-type regions P1 are formed on the main surface 11. The concentration of impurities contained in the second P-type region P2 is smaller than the concentration of impurities contained in the first P-type regions P1. In a plan view of the main surface 11, the first P-type regions P1 are formed so as to overlap the first N-type region N1. The second P-type region P2 is formed between the first N-type region N1 and the first P-type regions P1. In a plan view, the total area of the plurality of first P-type regions P1 may be smaller than the area of the second P-type region P2.

[0046] In this way, since the plurality of first P-type regions P1 are arranged at intervals from each other, the connection interface between the depletion layer and the first P-type regions P1 can be made smaller than the case where a single first P-type region P1 having the same area as the second P-type region P2 in a plan view is formed. As a result, one electrode of the depletion layer becomes smaller. By making one electrode of the depletion layer smaller, the parasitic capacitance in the semiconductor device 1 can be greatly reduced while further suppressing the reduction in the light sensitivity in the semiconductor device 1.

[0047] Regarding the semiconductor device 1, on the main surface 11, the plurality of first P-type regions P1 are arranged in a matrix.

[0048] In this way, the sensitivity of the semiconductor device 1 to light increases.

[0049] (Embodiment 3) FIG. 12 is a schematic plan view of the semiconductor element 1 according to Embodiment 3. FIG. 12 corresponds to FIG. 10. FIG. 13 is a schematic cross-sectional view of the semiconductor element 1 taken along line XIII-XIII in FIG. 12. FIG. 13 corresponds to FIG. 11. The semiconductor element 1 shown in FIGS. 12 and 13 basically has the same configuration as the semiconductor element 1 shown in FIGS. 10 and 11 and can obtain the same effects, but is different in that the insulating region 3 is not formed on the main surface 11. Specifically, as shown in FIG. 13, on the main surface 11, the second N-type region N2 is formed separately from the first P-type region P1 via the fourth P-type region P4.

[0050] The fourth P-type region P4 is a part of the second P-type region P2. The fourth P-type region P4 is formed on the main surface 11. That is, on the main surface 11, the second N-type region N2 is formed separately from the first P-type region P1 via the fourth P-type region P4 as the second P-type region.

[0051] In this way, the region where the second P-type region P2 is formed in the semiconductor element 1 according to Embodiment 3 is larger than the region where the second P-type region P2 is formed in the semiconductor element 1 according to Embodiment 2. That is, since the region where the depletion layer is formed increases, the light sensitivity is improved.

[0052] The distance w between the first P-type region P1 and the second N-type region N2 on the main surface 11 is 0.5 μm or more. In this way, the leakage generated between the first P-type region P1 and the second N-type region N2 can be suppressed. That is, the first P-type region P1 and the second N-type region N2 are insulated by the fourth P-type region P4.

[0053] (Operational Effects) The semiconductor element 1 includes a second N-type region N2. On the main surface 11, the second N-type region N2 is formed separately from the first P-type region P1 via the second P-type region P2.

[0054] By doing so, the area where the second P-type region P2 is formed in the semiconductor element 1 increases. As a result, the area where the depletion layer is formed increases, so the light sensitivity improves.

[0055] In the semiconductor element 1, the distance w between the first P-type region P1 and the second N-type region N2 on the main surface 11 is 0.5 μm or more.

[0056] By doing so, the leakage generated between the first P-type region P1 and the second N-type region N2 can be suppressed. That is, the first P-type region P1 and the second N-type region N2 are insulated by the fourth P-type region P4.

[0057] (Embodiment 4) FIG. 14 is a schematic plan view of the semiconductor element 1 of Embodiment 4. FIG. 14 corresponds to FIG. 10. FIG. 15 is a schematic cross-sectional view of the semiconductor element 1 taken along line segment XV-XV of FIG. 14. FIG. 15 corresponds to FIG. 11. The semiconductor element 1 shown in FIGS. 14 and 15 basically has the same configuration as the semiconductor element 1 shown in FIGS. 10 and 11 and can obtain the same effects, but is different in that the first insulating region 3a and the second N-type region N2 are not formed between adjacent first P-type regions P1. Specifically, as shown in FIG. 15, a part of the second P-type region P2 is formed on the main surface 11. A part of the second P-type region P2 is formed so as to fill the space between adjacent first P-type regions P1. That is, the second P-type region P2 is formed so as to surround the first P-type region P1.

[0058] By doing so, compared with the semiconductor element 1 shown in FIGS. 10 and 11, the area where the second P-type region P2 is formed in the semiconductor element 1 increases. As a result, the area where the depletion layer is formed increases, so the light sensitivity improves.

[0059] (Function and effect) In the semiconductor element 1, a part of the second P-type region P2 is formed on the main surface 11. On the main surface 11, a part of the second P-type region P2 formed on the main surface 11 is formed between adjacent first P-type regions P1.

[0060] In this way, the area where the second P-type region P2 in the semiconductor element 1 is formed increases. As a result, since the area where the depletion layer is formed increases, the light sensitivity is improved.

[0061] (Embodiment 5) FIG. 16 is a schematic cross-sectional view of the optical sensor 100 according to Embodiment 5. As shown in FIG. 16, the optical sensor 100 according to Embodiment 5 mainly includes a semiconductor element 1, an insulating layer 4, a plurality of color filter portions 5, a light-shielding portion 6, and a sealing resin 7.

[0062] The semiconductor element 1 is the semiconductor element 1 according to any one of Embodiments 1 to 4. The semiconductor element 1 is, for example, a photodiode and has a light-receiving portion PD. The light-receiving portion PD is formed on the main surface 11. The number of light-receiving portions PD formed on the main surface 11 may be one, or a plurality may be formed according to the light to be detected. The main surface 11 is an incident surface of the light detected by the optical sensor 100.

[0063] The insulating layer 4 is formed on the main surface 11. The material constituting the insulating layer 4 is, for example, silicon dioxide (SiO2).

[0064] The color filter portion 5 is connected to the insulating layer 4. As shown in FIG. 16, the color filter portion 5 is located on the opposite side of the region where the semiconductor element 1 is disposed when viewed from the insulating layer 4.

[0065] The color filter portion 5 transmits light in a wavelength region corresponding to a specific color among the light incident on the optical sensor 100. The wavelength regions of the light transmitted by the plurality of color filter portions 5 correspond to different colors. The material constituting the color filter portion 5 is, for example, an epoxy resin.

[0066] The light-shielding portion 6 is formed on the insulating layer 4 so as to cover the plurality of color filter portions 5. The light-shielding portion 6 shields light in the wavelength regions of infrared rays and ultraviolet rays. That is, the light-shielding portion 6 transmits light in the visible light region among the light incident on the optical sensor 100.

[0067] The encapsulating resin 7 encapsulates the semiconductor element 1, the insulating layer 4, the color filter portion 5, and the light-shielding portion 6. The encapsulating resin 7 is, for example, transparent.

[0068] (Function and effect) The optical sensor 100 according to the present disclosure includes a semiconductor element 1.

[0069] In this way, an optical sensor 100 including a semiconductor element 1 with a greatly reduced parasitic capacitance can be obtained.

[0070] In the optical sensor 100, the semiconductor element 1 is a photodiode.

[0071] In this way, an optical sensor 100 including a semiconductor element 1 with a greatly reduced parasitic capacitance can be obtained.

[0072] Hereinafter, various aspects of the present disclosure will be collectively described as appendices. (Appendix 1) A semiconductor element having a main surface, a first N-type region formed inside the semiconductor element, a first P-type region formed on the main surface, and a second P-type region including an impurity concentration smaller than the impurity concentration included in the first P-type region, wherein in a plan view of the main surface, the first P-type region is formed so as to overlap the first N-type region, the second P-type region is formed between the first N-type region and the first P-type region, and in the plan view, an area of the first P-type region is smaller than an area of the second P-type region, the semiconductor element. (Appendix 2) A semiconductor element having a main surface, a first N-type region formed inside the semiconductor element; a plurality of first P-type regions formed on the main surface; a second P-type region including an impurity concentration smaller than the impurity concentration included in the first P-type region, and in a plan view of the main surface, the first P-type region is formed to overlap the first N-type region, a semiconductor element, wherein the second P-type region is formed between the first N-type region and the first P-type region. (Appendix 3) a part of the second P-type region is formed on the main surface, and in the main surface, a part of the second P-type region formed on the main surface is formed between adjacent first P-type regions, the semiconductor element according to Appendix 2. (Appendix 4) further including a second N-type region formed on the main surface, and in the main surface, the second N-type region is formed to be separated from the first P-type region with the second P-type region therebetween, the semiconductor element according to Appendix 3. (Appendix 5) in the main surface, a distance between the first P-type region and the second N-type region is 0.5 μm or more, the semiconductor element according to Appendix 4. (Appendix 6) an insulating region formed on the main surface, and further including a second N-type region formed on the main surface, and in the main surface, the second N-type region is formed to be separated from the first P-type region with the insulating region therebetween, the semiconductor element according to any one of Appendices 1 to 5. (Appendix 7) in the main surface, the plurality of first P-type regions are arranged in a matrix, the semiconductor element according to any one of Appendices 2 to 5. (Appendix 8) an optical sensor including the semiconductor element according to any one of Appendices 1 to 7. (Appendix 9) The semiconductor element is a photodiode, and the optical sensor described in Supplementary Note 8.

[0073] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The basic scope of the present disclosure is indicated by the claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the claims.

Explanation of Reference Numerals

[0074] 1 Semiconductor element, 1a First layer, 1b Second layer, 1s Surface, 2 Metal wiring, 2a First electrode, 2b Second electrode, 3 Insulating region, 3a First insulating region, 3b Second insulating region, 4 Insulating layer, 5 Color filter section, 6 Light-shielding section, 7 Encapsulating resin, 11 Main surface, 100 Optical sensor, N N-type region, N1 First N-type region, P2 Second P-type region, N2 Second N-type region, P P-type region, P1 First P-type region, P2 Second P-type region, P3 Third P-type region, P4 Fourth P-type region, PD Light-receiving section, w Distance.

Claims

1. A semiconductor device having a main surface, comprising: a first N-type region formed inside the semiconductor device; a first P-type region formed on the main surface; a second P-type region having an impurity concentration smaller than the impurity concentration included in the first P-type region; in a plan view of the main surface, the first P-type region is formed so as to overlap the first N-type region; the second P-type region is formed between the first N-type region and the first P-type region; in the plan view, an area of the first P-type region is smaller than an area of the second P-type region. A semiconductor device.

2. A semiconductor device having a main surface, comprising: a first N-type region formed inside the semiconductor device; a plurality of first P-type regions formed on the main surface; a second P-type region having an impurity concentration smaller than the impurity concentration included in the first P-type region; in a plan view of the main surface, the first P-type region is formed so as to overlap the first N-type region; the second P-type region is formed between the first N-type region and the first P-type region. A semiconductor device.

3. A part of the second P-type region is formed on the main surface; on the main surface, a part of the second P-type region formed on the main surface is formed between adjacent first P-type regions. The semiconductor device according to claim 2.

4. Further comprising a second N-type region formed on the main surface; on the main surface, the second N-type region is formed to be separated from the first P-type region via the second P-type region. The semiconductor device according to claim 3.

5. A distance between the first P-type region and the second N-type region on the main surface is 0.5 μm or more. The semiconductor device according to claim 4.

6. Further comprising an insulating region formed on the main surface and a second N-type region formed on the main surface; on the main surface, the second N-type region is formed to be separated from the first P-type region via the insulating region. The semiconductor device according to claim 1 or claim 2.

7. On the main surface, the plurality of first P-type regions are arranged in a matrix. The semiconductor device according to any one of claims 2 to 5.

8. An optical sensor comprising the semiconductor device according to claim 1 or claim 2.

9. The semiconductor device is a photodiode. The optical sensor according to claim 8. ​

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