Semiconductor device and method for fabricating semiconductor device

Abstract

To provide a highly reliable semiconductor device.SOLUTION: There is provided a semiconductor device which includes: a semiconductor layer having an N type drift region, a P type body region on the N type drift region, and an N type source region on the P type body region; an insulating layer on the semiconductor layer; a first opening provided in the insulating layer; a second opening provided in the semiconductor layer and extending from the N type source region to the P type body region so as to overlap the first opening in plan view; an insulating film arranged on a sidewall of the second opening; a first metal layer provided on the insulating layer, on the semiconductor layer of the first opening, on the insulating film, and on the semiconductor layer of the second opening; and a second metal layer provided on the first metal layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Techniques for miniaturizing semiconductor devices have been developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when fabricating the electrodes, there has been a problem that the barrier metal breaks and the material forming the semiconductor layer reacts with the electrodes.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, the semiconductor device has a structure in which sidewalls of the source region and the body region are covered with an insulating film to prevent reaction with the electrodes.

Effects of the Invention

[0007] According to the above-described embodiment, a highly reliable semiconductor device can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0009] Embodiment Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Also, not all of the configurations described in the embodiments are essential as means for solving the problems. For clarity of explanation, the following description and drawings have been appropriately omitted and simplified. In each drawing, the same elements are denoted by the same reference numerals, and redundant explanations are omitted as necessary.

[0010] (Description of a semiconductor device according to Embodiment 1) FIG. 1 is a diagram showing a method of manufacturing an electrode of a related semiconductor device. FIG. 2 is a diagram showing a method of manufacturing an electrode of a semiconductor device of the present disclosure. FIG. 3 is a schematic diagram of a semiconductor device of the present disclosure. A semiconductor device according to the embodiment will be described with reference to FIGS. 1 to 3.

[0011] As shown in FIG. 1(a), a semiconductor device of the related art includes a semiconductor layer including an N-type drift region 108, a P-type body region 107 on the N-type drift region 108, and an N-type source region 106 on the P-type body region 107. The semiconductor device is provided on a semiconductor substrate such as a silicon substrate, for example, and the semiconductor layer uses the composition of the semiconductor substrate. A trench is formed in the semiconductor layer, and a shield electrode 102 and a gate electrode 101 are embedded together with an embedded insulating film 103. An insulating layer 104 is formed on the semiconductor layer. An SW (Side Wall) 105 for SAC (Self Align Contact) is provided on the side wall of the insulating layer 104. In this specification, the insulating layer 104 may include an SW for SAC.

[0012] A drain electrode is formed under the N-type drift region 108, and current flows through the semiconductor layer vertically. The semiconductor layer is formed of, for example, silicon (Si). The semiconductor device is a so-called power MOS (Metal Oxide Semiconductor) or MIS (Metal Insulator Semiconductor). A power MOS is a semiconductor device that functions as a switch or control element in which a channel is formed between the source and the drain and a relatively large current flows when a voltage is applied to the gate.

[0013] The N-type drift region 108 is formed in N-type for electrons to flow. The P-type body region 107 forms a channel and conducts electrons when the semiconductor device is turned on and a positive voltage is applied to the gate electrode 101. The P-type body region 107 has P-type impurities such as a small amount of boron (B) introduced therein. The N-type source region 106 injects electrons when the semiconductor device is turned on. The N-type source region 106 has N-type impurities introduced therein. The N-type source region 106 has more N-type impurities than the N-type drift region 108.

[0014] For example, in the semiconductor device according to the above embodiment, the conductivity type (P-type or N-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. may be reversed. Therefore, when one of the N-type and P-type conductivity types is defined as the first conductivity type and the other is defined as the second conductivity type, the first conductivity type can be P-type and the second conductivity type can be N-type, or conversely, the first conductivity type can be N-type and the second conductivity type can be P-type.

[0015] The buried insulating film 103 is formed to insulate the shield electrode 102 and the gate electrode 101 from the semiconductor layer. The buried insulating film 103 may function as a field plate insulating film 121 and a gate insulating film 122. The buried insulating film 103 on the side surface of the shield electrode 102 functions as the field plate insulating film 121, and the buried insulating film 103 on the side surface of the gate electrode 101 functions as the gate insulating film 122.

[0016] The gate electrode 101 is formed of, for example, polysilicon. By applying a voltage to the gate electrode 101, the semiconductor device controls the flow of current between the source and the drain. The shield electrode 102 is an electrode to which a ground potential or the same voltage as the gate electrode may be applied. The shield electrode 102 is formed of polysilicon. The shield electrode 102 assists in the control of the semiconductor device.

[0017] SAC109 is a technique for self-aligned impurity introduction and electrode formation. With SAC109, elements can be miniaturized beyond the limits of photolithography. Here, it is used to form a second opening 116 in the N-type source region 106. A source electrode is formed in the second opening 116. Therefore, the second opening 116 penetrates the N-type source region 106 and is formed up to about half of the P-type body region 107.

[0018] As shown in FIG. 1(b), the SAC-use SW105 is recessed by wet etching to form a first opening 115 in the insulating layer 104. In this process, the silicon on the source region 106 is exposed.

[0019] As shown in FIG. 1(c), a P-type impurity such as boron is introduced into the opening at a high concentration, and a first metal layer made of titanium (Ti) 110 and a barrier metal made of titanium nitride (TiN) 111 are formed on the first metal layer to make an ohmic connection.

[0020] As shown in FIG. 1(d), heat treatment is performed in this state, and the first metal layer reacts with the semiconductor layer to form a silicide. Particularly, when the first metal layer is titanium, titanium silicide is formed.

[0021] As the device is miniaturized, agglomeration 112 of titanium silicide occurs. The agglomeration of titanium silicide occurs at the side surface of the semiconductor layer, the bottom of the N-type source region 106, and the bottom of the P-type body region 107 depending on the formation conditions of titanium silicide. Since the titanium film thickness is different at the side wall portion and the bottoms of the N-type source region 106 and the P-type body region 107, the degree of titanium silicide agglomeration is different and stress is generated. Therefore, the barrier metal of titanium nitride 111 on the side wall of the semiconductor layer is disconnected.

[0022] Then, as shown in FIG. 1(e), when the tungsten (W) plug 113, which is the second metal layer, is embedded in the opening using tungsten fluoride, fluorine penetrates from the side wall of the semiconductor layer not covered by the barrier metal and reacts with the semiconductor layer to form a wormhole 114.

[0023] The semiconductor device of the present disclosure is a technique for preventing this wormhole 114. Since it is the same as FIG. 1 until the SAC 109 is formed, the description is omitted. As shown in FIG. 2(a), after forming the second opening 116 for embedding the source electrode in the insulating layer 104 and the semiconductor layer, the SAC SW 105 is retracted. By retracting the SAC SW 105, a first opening 115 that overlaps the second opening 116 in plan view is formed in the insulating layer 104 and the side wall. Then, an insulating film 117 is disposed in the first opening 115 and the second opening 116.

[0024] Next, as shown in FIG. 2(b), by anisotropic etching, the insulating film on the upper surface of the semiconductor layer is removed while leaving the insulating film 117 on the side surface of the semiconductor layer, thereby forming the insulating film 117 on the side wall of the semiconductor layer.

[0025] The insulating film 117 can be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stack thereof. The insulating film 117 may be the same silicon oxide film as that used for the SW for SAC. By using a silicon nitride film for the insulating film 117, film thinning is possible because there is no film reduction in subsequent processes. By forming the insulating film 117 into a multilayer structure of a silicon oxide film and a silicon nitride film, film reduction due to subsequent processes and stress caused by the silicon nitride film can be alleviated.

[0026] Thereafter, as shown in FIG. 2(c), a P-type impurity such as boron is implanted at a high concentration into the second opening 116, and titanium as the first metal layer and titanium nitride as the barrier metal are provided. The titanium as the first metal layer is reacted with silicon (Si) as the semiconductor layer to form titanium silicide 118 on the upper surfaces of the source region and the P-type body region.

[0027] As shown in FIG. 2(d), since the side wall of the semiconductor layer is in contact with the insulating film 117 and titanium and not in contact with silicon and titanium, titanium silicide is not formed and aggregation 112 does not occur either. The titanium as the first metal layer reacts with silicon only on the upper surface of the semiconductor layer in contact with the semiconductor layer.

[0028] As shown in FIG. 2(e), when tungsten as the second metal layer is embedded, no stress is generated due to the difference in aggregation, so the barrier metal does not break and no via holes are formed. In this way, a highly reliable semiconductor device can be obtained.

[0029] As shown in FIG. 3, silicide 119 on the upper surface of the N-type source region and silicide 118 on the upper surface of the P-type body region are formed. The side surfaces of the N-type source region 106 and the P-type body region 107 are in contact with the insulating film 117 and the first metal layer 110, and since the first metal layer 110 is not in contact with the semiconductor layer, no silicide is formed and neither aggregation 112 nor stress due to the difference in aggregation occurs.

[0030] Also, titanium was used for the first metal layer, but cobalt (Co) may be used instead. The same titanium nitride is used as the barrier metal. By using cobalt, fine patterning can be achieved, and an increase in resistance due to aggregation can be suppressed. When using cobalt, the first metal layer is formed before introducing P-type impurities into the second opening. After forming cobalt silicide, it is preferable to introduce P-type impurities to suppress the generation of spikes in the cobalt silicide.

[0031] (Description of the semiconductor device according to Embodiment 2) FIG. 4 is a schematic diagram of another semiconductor device of the present disclosure. The semiconductor device according to Embodiment 2 will be described with reference to FIG. 4.

[0032] The semiconductor device according to Embodiment 2 differs from the semiconductor device according to Embodiment 1 in that SW105 for SAC is not formed. That is, in the semiconductor device according to Embodiment 2, an opening is formed in the insulating layer 104 using ordinary photolithography.

[0033] As shown in FIG. 4, an insulating film 117 is formed on the sidewalls of the insulating layer 104 and the sidewalls of the semiconductor layer. Therefore, in the semiconductor device according to Embodiment 2, since disconnection of the barrier metal does not occur, wormholes do not occur. Also, the insulating film is removed from the upper surfaces of the insulating layer 104 and the semiconductor layer. Therefore, silicides 119 on the upper surface of the N-type source region and silicide 118 on the upper surface of the P-type body region are formed between the first metal layer and the semiconductor layer. In this way, a highly reliable semiconductor device can be obtained.

[0034] (Description of the manufacturing method of the semiconductor device according to Embodiment 1) FIG. 5 is a diagram showing the manufacturing method of the semiconductor device of the present disclosure. The manufacturing method of the semiconductor device according to Embodiment 1 will be described with reference to FIG. 5.

[0035] As shown in the upper diagram of FIG. 5, a semiconductor layer is formed which includes an N-type drift region 108, a P-type body region 107 on the N-type drift region 108, and an N-type source region 106 on the P-type body region 107. Next, a gate electrode 101, a shield electrode 102, and a buried insulating film 103 are formed in the semiconductor layer. The buried insulating film 103 has a field plate insulating film 121 and a gate insulating film 122. An insulating layer 104 is formed on the semiconductor layer and on the gate electrode 101. Next, a sidewall 105 is formed on the side surface of the insulating layer 104. A second opening 116 is formed in the semiconductor layer reaching from the N-type source region 106 to the P-type body region 107.

[0036] As shown in the lower diagram of FIG. 5, the sidewall 105 is retracted, and a first opening 115 overlapping the second opening 116 in a cross-sectional view is formed in the insulating layer 104. Next, an insulating film 117 is formed on the insulating layer 104, on the sidewall 105, and on the semiconductor layer. Next, the insulating film 117 is removed from above the semiconductor layer leaving the sidewalls of the semiconductor layer. The removal of the insulating film 117 uses, for example, anisotropic etching.

[0037] Next, P-type impurities are implanted into the semiconductor layer, and the P-type impurities are activated by heat treatment. Next, a first metal layer 110 is formed on the insulating layer 104, on the sidewall 105, and on the semiconductor layer. The first metal layer 110 also covers the insulating film 117. The first metal layer 110 is a material containing, for example, titanium, and the material containing titanium is a laminate of titanium and titanium nitride. By forming and heating a metal layer containing titanium, titanium silicide 118 of the semiconductor layer and titanium is formed.

[0038] A second metal layer 113 is formed on the first metal layer 110. The second metal layer 113 is a material containing tungsten. After forming the second metal layer 113, a wiring layer 120 formed from aluminum Al - copper Cu is formed, and the semiconductor device is completed.

[0039] A third metal layer may be provided between the first metal layer 110 and the second metal layer 113. For example, when cobalt is used for the first metal layer 110, a material containing titanium is used for the third metal layer, and a material containing tungsten is used for the second metal layer 113. At this time, after forming cobalt, heating is performed to form silicide. The material containing titanium is a laminate of titanium and titanium nitride, and serves as a barrier metal for tungsten.

[0040] In this way, a highly reliable semiconductor device can be obtained.

[0041] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0042] 101 Gate electrode, 102 Shield electrode, 103 Embedded insulating film, 104 Insulating layer, 105 SW for SAC, 106 N-type source region, 107 P-type body region, 108 N-type drift region, 109 SAC, 110 Ti film, First metal layer, 111 TiN film, 112 Aggregation, 113 Tungsten plug, Second metal layer, 114 via hole, 115 First opening, 116 Second opening, 117 Insulating film, 118 Silicide on the upper surface of the P-type body region, 119 Silicide on the upper surface of the N-type source region, 120 Al-Cu wiring, 121 Field plate insulating film, 122 Gate insulating film

Claims

1. A semiconductor layer including an N-type drift region, a P-type body region on the N-type drift region, and an N-type source region on the P-type body region; An insulating layer on the semiconductor layer; A first opening provided in the insulating layer; A second opening provided overlapping the first opening in plan view in the semiconductor layer reaching from the N-type source region to the P-type body region; An insulating film disposed on a sidewall of the second opening; A first metal layer provided on the insulating layer, on the semiconductor layer of the first opening, on the insulating film, and on the semiconductor layer of the second opening; A semiconductor device including a second metal layer provided on the first metal layer.

2. The insulating layer includes sidewalls, The second opening is self-alignedly formed by the sidewalls, The semiconductor device according to claim 1, wherein the first opening is formed by retracting the sidewalls.

3. The first metal layer contains titanium, The second metal layer contains tungsten, The semiconductor device according to claim 1, wherein the titanium forms a silicide in a region in contact with the semiconductor layer.

4. A third metal layer is provided between the first metal layer and the second metal layer, The first metal layer contains cobalt, The second metal layer contains tungsten, The third metal layer contains titanium, The semiconductor device according to claim 1, wherein the cobalt forms a silicide in a region in contact with the semiconductor layer.

5. A trench is provided in the semiconductor layer, An embedded insulating film, a shield electrode, and a gate electrode are provided in the trench, the semiconductor device according to claim 1.

6. Form a semiconductor layer in which an N-type drift region, a P-type body region on the N-type drift region, and an N-type source region on the P-type body region are formed, Form a field plate insulating film, a gate insulating film, a shield electrode, and a gate electrode in the semiconductor layer, Form an insulating layer on the gate electrode and on the semiconductor layer, Form sidewalls on a side surface of the insulating layer, Form a second opening in the semiconductor layer reaching from the N-type source region to the P-type body region, Retract the sidewalls to form a first opening overlapping the second opening in plan view in the insulating layer, Form an insulating film on the insulating layer, on the sidewalls, and on the semiconductor layer, Remove the insulating film on the semiconductor layer, leaving the insulating film on the side surface of the semiconductor layer, Inject P-type impurities into the semiconductor layer, Activate the P-type impurities, Form a first metal layer on the insulating layer and on the semiconductor layer, A method of manufacturing a semiconductor device, comprising forming a second metal layer on the first metal layer.

7. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the first metal layer, heating is performed to form silicide.

8. The first metal layer contains titanium, The method of manufacturing a semiconductor device according to claim 7, wherein the second metal layer contains tungsten.

9. A third metal layer is provided between the first metal layer and the second metal layer, The first metal layer contains cobalt, The second metal layer contains tungsten, The method of manufacturing a semiconductor device according to claim 7, wherein the third metal layer contains titanium.

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