Semiconductor device

Abstract

To provide a semiconductor device capable of increasing a contact area between a land and an insulating film toward the center of the chip and improving the resistance to peeling of the insulating film.SOLUTION: A semiconductor device includes a semiconductor chip CHP1 mounted on a wiring board SUB1 such that a main surface 501 faces a surface 802 of an insulating film SR of the wiring board SUB1, and a plurality of bumps 809 electrically connecting a plurality of lands 801 and a plurality of electrode pads 503, respectively, and a center 603 of the land is eccentric in a direction 605 toward the center of the semiconductor chip from a center 601 of an opening in the insulating film exposing a portion of the land in a cross-sectional view.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] There is a technique for mounting a semiconductor chip on a wiring board by a flip chip connection method (or a face down mounting method) (see, for example, Patent Document 1). In a semiconductor device employing the flip chip connection method, the semiconductor chip and the wiring board are electrically connected to each other via a plurality of bumps made of, for example, a solder material. Such a semiconductor device is also called an FCBGA (Flip Chip Ball Grid Array).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for miniaturization of semiconductor devices. Therefore, the interval between two adjacent bumps (i.e., the lands to which the bumps are joined) tends to be reduced. On the other hand, when a semiconductor device employing the flip chip connection method is mounted on a motherboard, cracks may occur in the insulating film of the wiring board constituting the semiconductor device due to heat treatment during mounting. Here, the "cracks" include interfacial peeling between the lands and the insulating film. When cracks occur in the insulating film, the solder material constituting the bumps melted by heat treatment flows into the portion where the cracks have occurred, and as a result, it has been found that there is a risk of causing a short circuit failure between two adjacent lands (or between a certain land and another wiring provided in the vicinity of this land).

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] In a semiconductor device according to one embodiment, the center of the land is eccentric in a direction from the center of the opening of the insulating film that exposes a part of the land to the center of the semiconductor chip in a plan view.

Advantages of the Invention

[0007] According to the above-described embodiment, there is provided a semiconductor device capable of increasing the contact area between the land in the direction of the center of the semiconductor chip and the insulating film and improving the resistance to peeling of the insulating film.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Best Mode for Carrying Out the Invention

[0009] (Embodiment) Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Also, not all of the configurations described in the embodiments are essential as means for solving the problems. For the sake of clarity of explanation, the following description and drawings have been appropriately omitted and simplified. In each drawing, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Explanation of Connection between Wiring Substrate and Semiconductor Chip According to Embodiment 1) FIG. 1 is a top view of the semiconductor device of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a diagram showing an outline of the wiring substrate of the present disclosure and the mounted semiconductor chip. FIG. 4 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 5 is a surface view of the semiconductor chip showing the crack generation situation of the insulating film of the wiring substrate of the present disclosure. FIG. 6 is a plan view showing the centers of the bumps and lands according to Structure 1 of the present disclosure. FIG. 7 is a plan view showing the centers of the bumps and lands according to Structure 2 and related structures of the present disclosure. FIG. 8 is a cross-sectional view showing the centers of the bumps and lands according to Structure 2 and related structures of the present disclosure. The wiring substrate and the semiconductor chip according to Embodiment 1 will be described with reference to FIGS. 1 to 8.

[0011] The semiconductor device PKG1 of the present embodiment has a wiring substrate SUB1 and a semiconductor chip CHP1 (see FIG. 3) mounted on the wiring substrate SUB1. The semiconductor device PKG1 also has a heat sink TIM disposed on the semiconductor chip CHP1 and a cover member LID that covers the entire semiconductor chip CHP1, the entire heat sink TIM, and a part of the wiring substrate SUB1. Although not shown, the technology described below can also be applied to a semiconductor device that does not have the heat sink TIM or the cover member LID.

[0012] As shown in FIG. 4, the wiring board SUB1 has an upper surface (surface, main surface, chip mounting surface) 2t on which the semiconductor chip CHP1 is mounted, and a lower surface (surface, main surface, mounting surface) 2b opposite to the upper surface 2t. The wiring board SUB1 also has a plurality of side surfaces 2s (see FIGS. 1 to 3) continuous with the outer edges of the upper surface 2t and the lower surface 2b, respectively. In the case of this embodiment, the upper surface 2t (see FIG. 1) and the lower surface 2b (see FIG. 2) of the wiring board SUB1 are each quadrilateral. The upper surface 2t is a chip mounting surface facing the surface 3t of the semiconductor chip CHP1.

[0013] The wiring board SUB1 has a plurality of wiring layers (six layers in the example shown in FIG. 4), namely 803, 821, 905, WL4, WL5, and WL6, that electrically connect the terminals (lands 801) on the upper surface 2t side, which is the chip mounting surface, and the terminals (lands 2LD) on the lower surface 2b side, which is the mounting surface. Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern such as wiring, which is a path for supplying electrical signals and power. An insulating layer 2e is disposed between each wiring layer. Each wiring layer is electrically connected to each other through via wirings 2v, which are interlayer conductive paths passing through the insulating layer 2e, or through-hole wirings 813. In this embodiment, a wiring board having six wiring layers is exemplified as an example of the wiring board SUB1, but the number of wiring layers provided in the wiring board SUB1 is not limited to six layers. For example, a wiring board having five or fewer or seven or more wiring layers can be used as a modified example.

[0014] Also, among the plurality of wiring layers, the wiring layer 803 disposed on the uppermost surface 2t side is covered with the organic insulating film SR. The organic insulating film SR is provided with openings, and a plurality of lands 801 provided on the wiring layer 803 are exposed from the organic insulating film SR at the openings. Also, among the plurality of wiring layers, the wiring layer WL6 disposed at the position closest to the lower surface 2b side of the wiring substrate SUB1 is provided with a plurality of lands 2LD. The wiring layer WL6 is covered with the organic insulating film SR2. Each of the organic insulating film SR and the organic insulating film SR2 is a solder resist film. Each of the plurality of lands 801 provided on the wiring layer 803 and the plurality of lands 2LD provided on the wiring layer WL6 is electrically connected via conductor patterns (wiring 2d and large-area conductor patterns), via wiring 2v, and through-hole wiring 813 formed in each wiring layer included in the wiring substrate SUB1.

[0015] Each of the wiring 2d, the land 801, the via wiring 2v, the via land, the through-hole wiring 813, the land 2LD, and the conductor pattern 2CP is made of, for example, copper or a metal material mainly composed of copper.

[0016] Also, the wiring substrate SUB1 is formed by laminating a plurality of wiring layers on the upper surface 2Ct and the lower surface 2Cb of an insulating layer (core material, core insulating layer) 2CR made of, for example, a prepreg impregnated with resin in glass fibers, by a build-up method. Also, the wiring layer 905 on the upper surface 2Ct side of the insulating layer 811 and the wiring layer WL4 on the lower surface 2Cb side are electrically connected via a plurality of through-hole wirings 813 embedded in a plurality of through-holes (through-holes) provided so as to penetrate from one of the upper surface 2Ct and the lower surface 2Cb to the other.

[0017] In the example shown in FIG. 4, the wiring board SUB1 shows a wiring board in which a plurality of wiring layers are laminated on the upper surface 2Ct side and the lower surface 2Cb side of an insulating layer 811 that is a core material. However, as a modification of FIG. 4, a so-called coreless board formed by sequentially laminating a conductor pattern such as an insulating layer 2e and a wiring 2d without having an insulating layer 811 made of a hard material such as a prepreg material may be used. When a coreless board is used, through-hole wiring 813 is not formed, and each wiring layer is electrically connected via via wiring 2v.

[0018] Also, in the example shown in FIG. 4, solder balls (solder material, external terminals, electrodes, external electrodes) SB are connected to each of the plurality of lands 2LD. The solder ball SB is a conductive member that electrically connects a plurality of terminals (not shown) on the motherboard side and the plurality of lands 2LD when mounting the semiconductor device PKG1 on a motherboard (not shown). The solder ball SB is, for example, a Sn-Pb solder material containing lead (Pb), or a so-called lead-free solder that substantially does not contain Pb. Examples of lead-free solder include, for example, only tin (Sn), tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), and the like. Here, lead-free solder means that the lead (Pb) content is 0.1 wt% or less, and this content is defined as the standard of the RoHS (Restriction of Hazardous Substances) directive.

[0019] Also, as shown in FIG. 2, a plurality of solder balls SB are arranged in a matrix (array, matrix) form. Also, although not shown in FIG. 2, a plurality of lands 2LD (see FIG. 4) to which the plurality of solder balls SB are joined are also arranged in a matrix (matrix) form. In this way, a semiconductor device in which a plurality of external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface side of the wiring board SUB1 is called an area array type semiconductor device. The area array type semiconductor device can effectively utilize the mounting surface (lower surface 2b) side of the wiring board SUB1 as an external terminal arrangement space, so it is preferable in that even if the number of external terminals increases, an increase in the mounting area of the semiconductor device can be suppressed. That is, with the increase in functionality and integration, a semiconductor device with an increasing number of external terminals can be mounted in a space-saving manner.

[0020] Also, the semiconductor device PKG1 includes a semiconductor chip CHP1 mounted on the wiring board SUB1. As shown in FIG. 4, each of the semiconductor chips CHP1 includes a surface (main surface, upper surface) 3t on which a plurality of bumps 809 are arranged, and a back surface (main surface, lower surface) 3b opposite to the surface 3t. The semiconductor chip CHP1 also includes a plurality of side surfaces 3s that intersect the surface 3t and the back surface 3b. The semiconductor chip CHP1 has a rectangular outer shape that is smaller in planar area than the wiring board SUB1 in a plan view as shown in FIG. 3. In the example shown in FIG. 3, the semiconductor chip CHP1 is mounted at the center of the upper surface 2t of the wiring board SUB1, and each of the four side surfaces 3s of the semiconductor chip CHP1 extends along each of the four side surfaces 2s of the wiring board SUB1.

[0021] Also, a plurality of pad electrodes (pads, electrode pads, bonding pads) 503 are formed on the surface 3t side of the semiconductor chip CHP1. In the example shown in FIG. 4, the semiconductor chip CHP1 is mounted on the wiring board SUB1 with the surface 3t facing the upper surface 2t of the wiring board SUB1. Such a mounting method is called a face-down mounting method or a flip-chip connection method.

[0022] Although illustration is omitted, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CHP1 (specifically, the semiconductor element formation region provided on the element formation surface of the semiconductor substrate which is the base material of the semiconductor chip CHP1). The plurality of pad electrodes 503 are electrically connected to the plurality of semiconductor elements respectively via wirings (illustration omitted) formed in a wiring layer disposed inside the semiconductor chip CHP1 (specifically, between the surface 3t and the semiconductor element formation region not shown).

[0023] The semiconductor chip CHP1 (specifically, the base material of the semiconductor chip CHP1) is made of, for example, silicon (Si). Also, an insulating film covering the base material and wirings of the semiconductor chip CHP1 is formed on the surface 3t, and a part of each of the plurality of pad electrodes 503 is exposed from the passivation film at the opening formed in this passivation film. Also, the plurality of pad electrodes 503 are each made of metal, and in the present embodiment, they are made of, for example, aluminum (Al).

[0024] Also, as shown in FIG. 4, bumps 809 are connected to the plurality of pad electrodes 503 respectively, and the plurality of pad electrodes 503 of the semiconductor chip CHP1 and the plurality of lands 801 of the wiring substrate SUB1 are electrically connected to each other via the plurality of bumps 809. As the soldering material, similar to the above-described solder balls SB, a lead-containing soldering material or lead-free solder can be used. Also, the present embodiment uses a so-called solder bump in which a columnar electrode made of nickel (Ni) or a micro solder ball is formed on the pad electrode 503 via an under-metal film.

[0025] Also, as shown in FIG. 4, an underfill resin (insulating resin) UF is disposed between the semiconductor chip CHP1 and the wiring substrate SUB1. The underfill resin UF is disposed so as to fill the space between the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1. Each of the plurality of bumps 809 is sealed by the underfill resin UF. Further, the underfill resin UF is made of an insulating (non-conductive) material (e.g., resin material) and is disposed so as to seal the electrical connection portion (joint portion of the plurality of bumps 809) between the semiconductor chip CHP1 and the wiring substrate SUB1. Thus, by covering the joint portion between the plurality of bumps 809 and the plurality of lands 801 with the underfill resin UF, the stress generated in the electrical connection portion between the semiconductor chip CHP1 and the wiring substrate SUB1 can be relaxed. Also, the stress generated at the joint portion between the plurality of pad electrodes 503 of the semiconductor chip CHP1 and the plurality of bumps 809 can be relaxed. Furthermore, the main surface on which the semiconductor element (circuit element) of the semiconductor chip CHP1 is formed can be protected.

[0026] A cover member (lid, heat spreader, heat dissipation member) LID is disposed on the back surface 3b of the semiconductor chip CHP1. The cover member LID is, for example, a metal plate having a higher thermal conductivity than the wiring substrate SUB1 and has a function of discharging the heat generated by the semiconductor chip CHP1 to the outside. Also, the cover member LID is thermally connected to the semiconductor chip CHP1 via a heat dissipation plate TIM. The heat dissipation plate TIM is in contact with each of the semiconductor chip CHP1 and the cover member LID.

[0027] The cover member LID is adhered to the surface of the insulating film SR of the wiring substrate SUB1. BND1 is an adhesion region between the cover member LID and the wiring substrate SUB1. The cover member LID includes a heat dissipation plate. Also, the heat dissipation plate is formed of a material containing copper.

[0028] As shown in FIG. 3, the center of the semiconductor chip CHP1 does not necessarily need to be coaxial with the center of the wiring substrate SUB1. However, considering the placement space, it is preferably coaxial. When mounting the semiconductor chip CHP1 on the wiring substrate SUB1, there may be some displacement depending on the mounting method and the device used. Therefore, in this embodiment, although it is described as "coaxial", it is not limited to the case where the positions of the respective centers completely coincide, and even in the case where they partially overlap (i.e., "substantially coaxial"), it is described as "coaxial".

[0029] As shown in FIG. 5, the semiconductor chip CHP1 has a main surface 501 and a plurality of electrode pads 503 disposed on the main surface 501. The semiconductor chip CHP1 is mounted on the wiring substrate SUB1 such that the main surface faces the surface 802 (illustrated in FIG. 8) of the insulating film of the wiring substrate.

[0030] As shown in FIG. 5, the main surface 501 of the semiconductor chip CHP1 has a first side 511 extending in a first direction 509 in a plan view. Further, the main surface 501 of the semiconductor chip CHP1 has a second side 515 extending in a second direction 513 intersecting the first direction 509. Further, the main surface 501 of the semiconductor chip CHP1 has a third side 517 extending in the first direction 509 and facing the first side 511. Further, the main surface 501 of the semiconductor chip CHP1 has a fourth side 519 extending in the second direction 513 and facing the second side 515. That is, the main surface 501 of the semiconductor chip CHP1 may be a parallelogram, a rectangle, or a square, but is preferably a rectangle.

[0031] As shown in FIG. 8, the semiconductor chip CHP1 and the wiring board SUB1 are connected by a plurality of bumps 809. The plurality of electrode pads 503 of the semiconductor chip CHP1 are electrically connected to the plurality of lands 801 of the wiring board SUB1 via the plurality of bumps 809. The electrode pad 503 is a terminal of the semiconductor chip CHP1. The land 801 is a terminal provided on the first wiring layer 803 which is the uppermost wiring layer of the wiring board SUB1. The insulating film SR covers the peripheral portions of the plurality of lands 801 so as to expose a part of each of the plurality of lands 801. The insulating film SR is an insulating film for protecting the land 801, which is so-called solder resist.

[0032] As shown in FIGS. 7 and 8, in the related structure of the bump and the land which is the connection part of the semiconductor chip CHP1 and the wiring board SUB1, the center 601 of the opening and the center 603 of the land were coincident. Therefore, when heat treatment was performed to mount the wiring board SUB1 on which the semiconductor chip CHP1 was mounted on the mother board, as shown in FIG. 5, cracks 839 occurred toward the center of the semiconductor chip CHP1 at the contact part 837 of the insulating film covering the land 801.

[0033] As shown in FIG. 5 (and FIG. 4), in plan view, the main surface 501 of the semiconductor chip CHP1 is divided into a central region 523 including the center 521 of the semiconductor chip and an outer peripheral region 525 arranged around the central region 523. The plurality of electrode pads 503 are arranged along the first side 511 and in a plurality of rows in plan view. That is, the electrode pads 503 are arranged in a matrix or a shape close thereto.

[0034] The aforementioned crack is likely to occur in the region of the insulating film SR that overlaps with the outer peripheral region 525 of the semiconductor chip CHP1. For example, the crack occurs at the electrode pad 527. This is presumably because the semiconductor chip CHP1, the wiring substrate SUB1, and the underfill resin UF filled therebetween expand due to heat treatment when the semiconductor device PKG1 is mounted on the motherboard. At this time, for example, the linear expansion coefficient of the semiconductor chip CHP1 made of silicon (Si), the linear expansion coefficient of the wiring substrate SUB1 having an insulating layer (including the core layer) made of a glass epoxy-based resin material, and the linear expansion coefficient of the underfill resin UF filled therebetween are different from each other. Therefore, when the wiring substrate SUB1 expands, the land 801 electrically connected to the electrode pad 505 located in the outer peripheral region 525 of the semiconductor chip CHP1 is pulled in the direction toward the peripheral edge of the wiring substrate SUB1. As a result, it is considered that a crack occurs in the insulating film SR covering the peripheral edge of the land 801 so as to expose a part of the land 801, on the center side of the wiring substrate SUB1 (i.e., the center side of the semiconductor chip CHP1) from the center of the land 801.

[0035] Particularly, it occurs in the region outside the region surrounded by one-fourth of the first side 511 from the center 521 of the semiconductor chip CHP1 and one-fourth of the second side 515 from the center 521 of the semiconductor chip CHP1. In other words, no crack occurs in the region surrounded by 1 / 2a of the first side 511 and 1 / 2b of the second side 515 of the semiconductor chip CHP1 including the center 521 (i.e., the central region 523), but a crack occurs in the region outside thereof (i.e., the outer peripheral region 525).

[0036] As shown in FIG. 8, in the connection method of the present disclosure, the center 603 of the land is displaced from the center of the bump. That is, the center 603 of the land is displaced from the center 601 of the opening. The center 601 of the opening is displaced in the direction toward the center of the chip. Particularly in the region where cracks occur, as shown in FIG. 4, it is preferable that the land located in the region of the wiring board SUB1 that overlaps with the outer peripheral region 525 of the semiconductor chip CHP1 has such a shape. That is, the center 603 of the land is eccentric in the direction 605 from the center 601 of the opening of the insulating film SR that exposes a part of the land 801 in a plan view toward the center of the semiconductor chip CHP1.

[0037] Also, as shown in FIG. 7, the shape of the land 801 may be an oval shape. For example, the shape of the land 801 may be an elliptical shape or an oblong shape. The center 603 of this land is eccentric in the direction 605 toward the center of the semiconductor chip CHP1 so that the major axis of the oval shape is aligned in the direction toward the center of the chip.

[0038] As shown in FIG. 8, in a cross-sectional view, the wiring board SUB1 has a first wiring layer 803 on which the land 801 is formed, an insulating layer BU1 below the first wiring layer 803, and a second wiring layer 821 below the insulating layer BU1. The wiring board SUB1 has an insulating film SR made of, for example, a solder resist on the first wiring layer 803. The wiring board SUB1 also has a plurality of via wirings 817 provided in the insulating layer BU1 and a plurality of wirings provided in the second wiring layer 821 and each connected to a plurality of lands 801 via the plurality of via wirings 817.

[0039] The plurality of electrode pads 503 includes a first electrode pad 507 disposed in the central region 523 and a second electrode pad 505 disposed in the outer peripheral region 525. The plurality of lands 801 includes a first land 807 electrically connected to the first electrode pad 507 via a first bump 810 among the plurality of bumps 809 and a second land 805 electrically connected to the second electrode pad 505 via a second bump 812 among the plurality of bumps 809.

[0040] The plurality of wirings include a first-layer first wiring 831 electrically connected to a first land 807 via a first via wiring 827 among the plurality of via wirings 817, and a first-layer second wiring 823 electrically connected to a second land 805 via a second via wiring 819 among the plurality of via wirings 817.

[0041] Here, the second electrode pad 505, the second bump 812, the second land 805, the second via wiring 819, and the first-layer second wiring 823 overlap each other in a cross-sectional view.

[0042] By doing so, the adhesion area between the land in the central direction of the semiconductor chip and the insulating film can be increased, and the resistance to insulating film peeling can be improved.

[0043] (Description of the connection between the wiring board and the semiconductor chip according to Embodiment 2) In addition to the Pad on Via structure in FIG. 9(A) shown in Embodiment 1, there is a Pad on Stacked Via structure in FIG. 9(B). The Pad on Via structure is a structure in which a land 801 overlaps a via wiring 817. The Pad on Stacked Via structure is a structure in which a first-layer via wiring 817 is stacked on a second-layer via wiring 901, and further a land 801 is stacked on the first-layer via wiring 817. In Embodiment 2, this Pad on Stacked Via structure will be described.

[0044] As shown in FIG. 9(B), the wiring board SUB1 has a plurality of wiring layers. For example, four wiring layers are formed on one side with a core layer as the center. In that case, the insulating layers on one side are three layers of BU1, BU2, and BU3.

[0045] As shown in FIG. 9(B), the wiring board SUB1 has a first wiring layer 803, a first insulating layer BU1 under the first wiring layer 803, and a second wiring layer 821 under the first insulating layer BU1. Further, the wiring board SUB1 has a second insulating layer BU2 under the second wiring layer 821 and a third wiring layer 905 under the second insulating layer BU2. Further, the wiring board SUB1 has an insulating film SR on the first wiring layer 803 and a plurality of lands 801 which are the first wirings provided on the first wiring layer 803. The wiring board SUB1 has a plurality of first-layer via wirings 817 provided in the first insulating layer BU1, and a plurality of second wirings provided in the second wiring layer 821 and each connected to a plurality of lands 801 via the plurality of first-layer via wirings 817. Further, the wiring board SUB1 has a plurality of second-layer via wirings 901 provided in the second insulating layer BU2, and a plurality of third wirings provided in the third wiring layer 905 and each connected to a plurality of second wirings via the plurality of second-layer via wirings 901.

[0046] And the plurality of second wirings include a second-layer first wiring electrically connected to the first land via the first via wiring among the plurality of first-layer via wirings 817, and a second-layer second wiring 823 electrically connected to the second land 805 via the second via wiring 819 among the plurality of first-layer via wirings 817.

[0047] The plurality of third wirings include a third-layer first wiring electrically connected to the second-layer first wiring via the first via wiring among the plurality of second-layer via wirings 901, and a third-layer second wiring 907 electrically connected to the second-layer second wiring 823 via the second via wiring 903 among the plurality of second-layer via wirings.

[0048] The second electrode pad 505, the second bump 812, the second land 805, the second via wiring 819 among the plurality of first-layer via wirings, the second-layer second wiring 823, the second via wiring 903 among the plurality of second-layer via wirings, and the third-layer second wiring 907 overlap each other in a cross-sectional view.

[0049] The center 603 of the second land is eccentric in the direction 605 from the center 601 of the opening of the insulating film SR that exposes a part of the second land, toward the center of the semiconductor chip, in a cross-sectional view.

[0050] As described above, in the structure shown in FIG. 9(B) (Pad on Stacked Via structure), the land 801 which is the first wiring (particularly, the portion of the first wiring to which the bump 812 is joined on its surface) overlaps not only the first-layer via wiring 817 but also the second-layer via wiring 901. Therefore, in the case of the structure shown in FIG. 9(B), the above-described crack is more likely to occur than in the structure shown in FIG. 9(A) (Pad on Via structure). However, the structure of the present disclosure is effective even in the structure shown in FIG. 9(B).

[0051] (Explanation of connection between wiring board and semiconductor chip according to Embodiment 3) In addition to the structure of FIG. 9(A) shown in Embodiment 1 and the structure of FIG. 9(B) shown in Embodiment 2, there is the structure of FIG. 9(C). In this structure, as shown in FIG. 9(C), the land 801, which is the first wiring located in the first wiring layer 803, which is the uppermost wiring layer, is electrically connected to the fourth wiring located in the fourth wiring layer 913 located on the upper surface of the core layer 811 via the first-layer via wiring 817, the second-layer via wiring 901, and the third-layer via wiring 909. And this land 801, the first-layer via wiring 817, the second-layer via wiring 901, the third-layer via wiring 909, and the fourth wiring layer overlap each other as shown in FIG. 9(c). Further, as shown in FIG. 9(C), the wiring substrate SUB1 has a third insulating layer BU3 under the third wiring layer 905, a fourth wiring layer 913 under the third insulating layer BU3, and a core layer 811 under the fourth wiring layer 913. The wiring substrate SUB1 has a plurality of third-layer via wirings 909 provided in the third insulating layer BU3, and a plurality of fourth wirings provided in the fourth wiring layer 913 and each connected to a plurality of third wiring layers 905 via the plurality of third-layer via wirings 909. Also, because the wiring substrate SUB1 is structurally symmetric, it has a fifth wiring layer under the core layer 811, a fourth insulating layer under the fifth wiring layer, a sixth wiring layer under the fourth insulating layer, a fifth insulating layer under the sixth wiring layer, a seventh wiring layer under the fifth insulating layer, a sixth insulating layer under the seventh wiring layer, and an eighth wiring layer under the sixth insulating layer. The structure shown in FIG. 4 was a six-layer wiring structure, but this embodiment shows an eight-layer wiring structure.

[0052] The plurality of fourth wirings include a fourth-layer first wiring electrically connected to a third-layer first wiring via a first via wiring among the plurality of third-layer via wirings 909, and a fourth-layer second wiring 915 electrically connected to a third-layer second wiring 907 via a second via wiring 911 among the plurality of third-layer via wirings.

[0053] Then, the second electrode pad 505, the second bump 812, the second land 805, the second via wiring 819 among the plurality of first-layer via wirings, the second-layer second wiring 823, the second via wiring 903 among the plurality of second-layer via wirings, the third-layer second wiring 907, and the second via wiring 911 among the plurality of third-layer via wirings, and the fourth-layer second wiring 915 overlap each other in a cross-sectional view.

[0054] The center 603 of the second land is eccentric in the direction 605 from the center 601 of the opening of the insulating film SR that exposes a part of the second land toward the center of the semiconductor chip in a cross-sectional view.

[0055] As described above, in the structure shown in FIG. 9(C), the land 801, which is the first wiring (particularly, the portion of the first wiring to which the bump 812 is joined on its surface), overlaps not only the first-layer via wiring 817 and the second-layer via wiring 901 but also the third-layer via wiring 909. Furthermore, it is electrically connected to the fourth wiring formed on the upper surface of the core layer 811 via these via wirings 817, 901, 909. Therefore, in the case of the structure shown in FIG. 9(C), the above-mentioned crack is more likely to occur than in the structures shown in FIGS. 9(A) and 9(B). Rather, in the structure shown in FIG. 9(C), since the land 801 is electrically connected to the fourth wiring formed on the upper surface of the core layer 811, which has a greater thickness than other insulating layers, it is most susceptible to the influence of the expansion (or contraction) of the wiring substrate SUB1 due to heat treatment as compared with the structures shown in FIGS. 9(A) and 9(B). That is, the above-mentioned crack is more prominent in the structure shown in FIG. 9(C) than in the structures shown in FIGS. 9(A) and 9(B). On the other hand, the structure of the present disclosure is also effective in the structure shown in FIG. 9(C).

[0056] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0057] PKG1 semiconductor device, CHP1 semiconductor chip, SUB1 wiring board, UF underfill resin, BND1 bonding region, BU1 first insulating layer, BU2 second insulating layer, BU3 third insulating layer, SR insulating film, 501 main surface, 503 electrode pad, 505 electrode pad located in the outer peripheral region, 507 electrode pad located in the central region, 509 first direction, 511 first side, 513 second direction, 515 second side, 517 third side, 519 fourth side, 521 center of the semiconductor chip, 523 central region, 525 outer peripheral region, 601 center of the opening, 603 center of the land, 605 direction toward the center of the semiconductor chip, 801 land, 802 surface of the insulating film, 803 first wiring layer, 805 second land, 807 first land, 809 bump, 810 first bump, 812 second bump, 817 via wiring, 819 second via wiring, 821 second wiring layer, 823 second wiring of the second layer, 827 first via wiring, 831 first wiring of the second layer, 837 contact portion of the insulating film, 839 crack, 901 second layer via wiring, 903 second via wiring among the second layer via wirings, 905 third wiring layer, 907 third second wiring layer, 909 third layer via wiring, 911 second via wiring among the plurality of third layer via wirings, 913 fourth wiring layer, 915 fourth second wiring

Claims

1. A wiring board having a first wiring layer, an insulating layer under the first wiring layer, a second wiring layer under the insulating layer, an insulating film on the first wiring layer, a plurality of lands provided on the first wiring layer, a plurality of via wirings provided on the insulating layer, and a plurality of wirings provided on the second wiring layer and each connected to the plurality of lands via the plurality of via wirings; A semiconductor chip mounted on the wiring board such that a main surface thereof has a main surface and a plurality of electrode pads disposed on the main surface, and the main surface faces the surface of the insulating film of the wiring board; A plurality of bumps that connect the plurality of lands and the plurality of electrode pads to each other and electrically; Comprising; The insulating film covers the peripheral portions of the plurality of lands so as to expose a part of each of the plurality of lands; The main surface of the semiconductor chip, in plan view, Has a first side extending in a first direction; A second side extending in a second direction intersecting the first direction; A third side extending in the first direction and facing the first side; A fourth side extending in the second direction and facing the second side; And has; The main surface of the semiconductor chip, in plan view, Has a central region including the center of the semiconductor chip; An outer peripheral region disposed around the central region; And has; The plurality of electrode pads are arranged along the first side and in a plurality of rows in plan view; The plurality of electrode pads further include; A first electrode pad disposed in the central region; A second electrode pad disposed in the outer peripheral region; And has; The plurality of lands include; A first land electrically connected to the first electrode pad via a first bump among the plurality of bumps; A second land electrically connected to the second electrode pad via a second bump among the plurality of bumps; And has; The plurality of wirings include; A first wiring electrically connected to the first land via a first via wiring among the plurality of via wirings; A second wiring electrically connected to the second land via a second via wiring among the plurality of via wirings; And has; The second electrode pad, the second bump, the second land, the second via wiring, and the second wiring overlap each other in a cross-sectional view. A semiconductor device in which the center of the second land is eccentric in a direction from the center of the opening of the insulating film that exposes a part of the second land toward the center of the semiconductor chip in a plan view.

2. A wiring board having a first wiring layer, a first insulating layer under the first wiring layer, a second wiring layer under the first insulating layer, a second insulating layer under the second wiring layer, a third wiring layer under the second insulating layer, an insulating film on the first wiring layer, a plurality of lands which are first wirings provided on the first wiring layer, a plurality of first-layer via wirings provided on the first insulating layer, a plurality of second wirings provided on the second wiring layer and each connected to the plurality of lands via the plurality of first via wirings, a plurality of second-layer via wirings provided on the second insulating layer, and a plurality of third wirings provided on the third wiring layer and each connected to the plurality of second wirings via the plurality of second via wirings; A semiconductor chip mounted on the wiring board such that a main surface thereof faces the surface of the insulating film of the wiring board, the semiconductor chip having the main surface and a plurality of electrode pads disposed on the main surface; A plurality of bumps that connect the plurality of lands and the plurality of electrode pads to each other and electrically; Comprising: In a plan view, the main surface of the semiconductor chip: Has a first side extending in a first direction; A second side extending in a second direction intersecting the first direction; A third side extending in the first direction and facing the first side; A fourth side extending in the second direction and facing the second side; And has: In a plan view, the main surface of the semiconductor chip: Has a central region including the center of the semiconductor chip; An outer peripheral region disposed around the central region; And has: In a plan view, the plurality of electrode pads are arranged along the first side and in a plurality of rows; The plurality of electrode pads further: Have a first electrode pad disposed in the central region; A second electrode pad disposed in the outer peripheral region; And have: The plurality of lands: A first land electrically connected to the first electrode pad via a first bump among the plurality of bumps; A second land electrically connected to the second electrode pad via a second bump among the plurality of bumps; And have: The plurality of second wirings: A second-layer first wiring electrically connected to the first land via a first via wiring among the plurality of first-layer via wirings; A second-layer second wiring electrically connected to the second land via a second via wiring among the plurality of first-layer via wirings; having; The plurality of third wirings; A third-layer first wiring electrically connected to the second-layer first wiring via a first via wiring among the plurality of second-layer via wirings; A third-layer second wiring electrically connected to the second-layer second wiring via a second via wiring among the plurality of second-layer via wirings; having; The second electrode pad, the second bump, the second land, the second via wiring among the plurality of first-layer via wirings, the second-layer second wiring, the second via wiring among the plurality of second-layer via wirings, and the third-layer second wiring overlap each other in a cross-sectional view; A semiconductor device in which the center of the second land is eccentric in a direction from the center of the opening of the insulating film that exposes a part of the second land to the center of the semiconductor chip in a plan view.

3. The semiconductor device according to claim 2, further comprising an underfill resin between the semiconductor chip and the wiring substrate.

4. The wiring substrate includes a third insulating layer under the third wiring layer, a fourth wiring layer under the third insulating layer, a core layer under the fourth wiring layer, a fifth wiring layer under the core layer, a fourth insulating layer under the fifth wiring layer, a sixth wiring layer under the fourth insulating layer, a fifth insulating layer under the sixth wiring layer, a seventh wiring layer under the fifth insulating layer, a sixth insulating layer under the seventh wiring layer, an eighth wiring layer under the sixth insulating layer, a plurality of third wirings provided in the third wiring layer and each connected to the plurality of second wirings via the plurality of second-layer via wirings, a plurality of third-layer via wirings provided in the third insulating layer, and a plurality of fourth wirings provided in the fourth wiring layer and each connected to the plurality of third wirings via the plurality of third-layer via wirings. The plurality of fourth wirings; A fourth-layer first wiring electrically connected to the third-layer first wiring via a first via wiring among the plurality of third-layer via wirings; A fourth-layer second wiring electrically connected to the third-layer second wiring via a second via wiring among the plurality of third-layer via wirings; having; The semiconductor device according to claim 2, wherein the second electrode pad, the second bump, the second land, the second via wiring among the plurality of first-layer via wirings, the second-layer second wiring, the second via wiring among the plurality of second-layer via wirings, the third-layer second wiring, the second via wiring among the plurality of third-layer via wirings, and the fourth-layer second wiring overlap each other in a plan view.

5. The semiconductor device according to claim 2, wherein the shape of the second land is oval in a plan view.

6. The semiconductor device according to claim 2, further comprising a cover member including a heat sink adhered to the surface of the insulating film of the wiring substrate so as to cover the semiconductor chip.

7. When the first side is a and the second side is b, the area (D) of the central region is D = (1 / 2 × a) × (1 / 2 × b) The semiconductor device according to claim 2, which is as described above.

8. The semiconductor device according to claim 2, wherein the center of the semiconductor chip is coaxial with the center of the wiring substrate.

9. A wiring substrate having a first wiring layer, a first insulating layer under the first wiring layer, a second wiring layer under the first insulating layer, a second insulating layer under the second wiring layer, a third wiring layer under the second insulating layer, a third insulating layer under the third wiring layer, a fourth wiring layer under the third insulating layer, a core layer under the fourth wiring layer, an insulating film on the first wiring layer, a plurality of lands which are first wirings provided on the first wiring layer, a plurality of first-layer via wirings provided on the first insulating layer, a plurality of second wirings provided on the second wiring layer and respectively connected to the plurality of lands via the plurality of first-layer via wirings, a plurality of second-layer via wirings provided on the second insulating layer, a plurality of third wirings provided on the third wiring layer and respectively connected to the plurality of second wirings via the plurality of second-layer via wirings, a plurality of third-layer via wirings provided on the third insulating layer, and a plurality of fourth wirings provided on the fourth wiring layer and respectively connected to the plurality of third wirings via the plurality of third-layer via wirings; A semiconductor chip having a main surface and a plurality of electrode pads disposed on the main surface, and mounted on the wiring substrate such that the main surface faces the surface of the insulating film of the wiring substrate; A plurality of bumps for connecting the plurality of lands and the plurality of electrode pads to each other and electrically; Comprising The main surface of the semiconductor chip is in a plan view a first side extending in a first direction, a second side extending in a second direction intersecting the first direction, a third side extending in the first direction and facing the first side, a fourth side extending in the second direction and facing the second side, and having the main surface of the semiconductor chip, in a plan view, a central region including the center of the semiconductor chip, an outer peripheral region disposed around the central region, and having the plurality of electrode pads are disposed along the first side and across a plurality of rows in a plan view, the plurality of electrode pads further include a first electrode pad disposed in the central region, a second electrode pad disposed in the outer peripheral region, and having the plurality of lands a first land electrically connected to the first electrode pad via a first bump among the plurality of bumps, a second land electrically connected to the second electrode pad via a second bump among the plurality of bumps, and having the plurality of second wirings a second-layer first wiring electrically connected to the first land via a first via wiring among the plurality of first-layer via wirings, a second-layer second wiring electrically connected to the second land via a second via wiring among the plurality of first-layer via wirings, and having the plurality of third wirings a third-layer first wiring electrically connected to the second-layer first wiring via a first via wiring among the plurality of second-layer via wirings, a third-layer second wiring electrically connected to the second-layer second wiring via a second via wiring among the plurality of second-layer via wirings, the plurality of fourth wirings a fourth-layer first wiring electrically connected to the third-layer first wiring via a first via wiring among the plurality of third-layer via wirings, a fourth-layer second wiring electrically connected to the third-layer second wiring via a second via wiring among the plurality of third-layer via wirings, and having the second electrode pad, the second bump, the second land, the second via wiring among the plurality of first-layer via wirings, the second-layer second wiring, the second via wiring among the plurality of second-layer via wirings, the third-layer second wiring, the second via wiring among the plurality of third-layer via wirings, and the fourth-layer second wiring overlap each other in a cross-sectional view, a semiconductor device in which the center of the second land is eccentric in a direction from the center of the opening of the insulating film exposing a part of the second land to the center of the semiconductor chip in a plan view.

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