Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor chip 10 having a source electrode pad SE and mounted on a die pad via a die bond material, a wire 12S electrically connected to the source electrode pad SE of the semiconductor chip 10, and an encapsulating body for sealing the semiconductor chip 10 and the wire 12S. The wire 12S and source electrode pad SE are made of different types of metals from each other. A wire bonding layer WBLS made of sintered metal is interposed between the source electrode pad SE and the wire 12S. The wire 12S is electrically connected to the source electrode pad SE via the wire bonding layer WBLS.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] There is a semiconductor device in which a semiconductor chip is mounted on a die pad, and a source electrode of the semiconductor chip and a lead are electrically connected via a metal plate made of a conductive resin and copper. For example, in the case of the semiconductor device described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2002-151554), a source electrode of a semiconductor chip and a source lead are electrically connected via a conductive paste and a copper plate. Further, a gate electrode of the semiconductor chip and a gate lead are electrically connected via a bonding wire.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the case of a semiconductor device in which an electrode pad of a semiconductor chip and a lead are electrically connected via a wire, it is necessary to improve the connection reliability of a portion connecting the wire and the electrode pad. For example, when the electrode pad and the wire are made of different types of metals, the bonding strength may decrease as compared with the case where the electrode pad and the wire are made of the same type of metal.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment includes a die pad, leads spaced apart from the die pad, a first electrode pad, a semiconductor chip mounted on the die pad via a die bonding material, wires electrically connected to the leads and the first electrode pad of the semiconductor chip, and a sealing body that seals the semiconductor chip, the die bonding material, and the wires. The first electrode pad and the wire are made of different types of metals. A wire bonding layer made of a sintered metal is interposed between the first electrode pad and the wire. The wire is electrically connected to the first electrode pad via the wire bonding layer.

[0007] A method of manufacturing a semiconductor device according to another embodiment includes: (a) a step of preparing a die pad; (b) a step of disposing a first paste material on the die pad; (c) a step of mounting a semiconductor chip having a first electrode pad on the first paste material; (d) a step of disposing a second paste material containing a plurality of metal particles on the first electrode pad of the semiconductor chip; (e) a step of sintering the plurality of metal particles contained in the second paste material by heating the second paste material to form a wire bonding layer; and (f) a step of bonding a wire made of a metal different from the first electrode pad to the wire bonding layer.

Advantages of the Invention

[0008] According to the above embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

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Figure 10

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Figure 15

Embodiments for Carrying Out the Invention

[0010] (Explanation of the description format, basic terms, and usage in this application) In this application, the description of the embodiments is divided into multiple sections or the like for convenience as necessary. However, unless otherwise explicitly stated, these are not mutually independent. Regardless of the order of description, each part of a single example, one part is a detailed description of another part, or a partial or complete modification of another part. In principle, repeated descriptions of similar parts are omitted. Also, each component in the embodiments is not essential unless otherwise explicitly stated, limited theoretically to a certain number, or clearly not the case from the context.

[0011] Similarly, in the description of the embodiments and the like, regarding materials, compositions, etc., even if it is stated as "X consisting of A", etc., unless otherwise explicitly stated or clearly not the case from the context, it does not exclude those containing elements other than A. For example, in terms of components, it means "X containing A as the main component". For example, even when referring to "silicon member", etc., it is not limited to pure silicon, but also includes members containing SiGe (silicon-germanium) alloy, other multi-element alloys with silicon as the main component, and other additives. Also, when referring to gold plating, Cu layer, nickel plating, etc., unless otherwise explicitly stated, it includes not only pure ones but also members with gold, Cu, nickel, etc. as the main components.

[0012] Furthermore, when referring to a specific numerical value or quantity, unless otherwise explicitly stated, limited theoretically to that number, or clearly not the case from the context, a numerical value greater than that specific numerical value or less than that specific numerical value may also be applicable.

[0013] Also, in each figure of the embodiments, the same or similar parts are indicated by the same or similar symbols or reference numbers, and the description is not repeated in principle.

[0014] In the accompanying drawings, conversely, in cases where it becomes complicated or the distinction from voids is clear, hatching or the like may be omitted even for cross-sections. In connection with this, in cases where it is clear from the description or the like, even for holes that are planar and closed, the background contour lines may be omitted. Furthermore, even if it is not a cross-section, hatching or a dot pattern may be added to clarify that it is not a void or to clarify the boundary of a region.

[0015] In the embodiments described below, as an example of a semiconductor device, a semiconductor device called a power device or a power semiconductor device incorporated in a power control circuit such as a power supply circuit will be taken up and described. The semiconductor device described below is incorporated in a power conversion circuit and functions as a switching element.

[0016] <Semiconductor Device> First, the package structure of the semiconductor device PKG1 shown in FIG. 1 will be described. FIG. 1 is a top view of the semiconductor device of the present embodiment. Further, FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. Further, FIG. 3 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 1 removed. Further, FIG. 4 is a cross-sectional view taken along line A-A of FIG. 3.

[0017] In FIGS. 1 to 4, any one of the X direction (see FIGS. 1 to 3), the Y direction, and the Z direction (see FIG. 4) is described. The Y direction is a side intersecting the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is the normal direction to the X-Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means a plan view as viewed from the X-Y plane.

[0018] The semiconductor device PKG1 of this embodiment includes a semiconductor chip 10 (see FIGS. 3 and 4), a die pad (metal plate, chip mounting portion, heat sink) 20 on which the semiconductor chip 10 is mounted (see FIGS. 2 to 4), a plurality of leads (terminals) 30 as external terminals, and a plurality of wires 12 (see FIG. 3).

[0019] As shown in FIG. 3, the die pad 20 has an upper surface (surface) 20t. The semiconductor chip 10 is mounted on the upper surface 20t of the die pad 20 via a die bonding material 11 (see FIG. 4). The plurality of leads 30 are arranged along a side (chip side) 10s1 that extends along the X direction among the plurality of sides 10s provided on the semiconductor chip 10. A plurality of electrode pads (gate electrode pad GE and source electrode pad SE shown in FIG. 3) arranged on the upper surface (chip surface, surface) 10t of the semiconductor chip 10 and the plurality of leads 30 are electrically connected to each other via a plurality of wires. As shown in FIG. 4, the semiconductor chip 10 and the plurality of wires 12 are encapsulated by an encapsulant 40. Further, the semiconductor chip 10, the upper surface 20t of the die pad 20, and the inner lead portion (encapsulated portion) 30M of the plurality of leads 30 (see FIG. 4) are encapsulated by the encapsulant 40. The encapsulant (resin encapsulant, resin body, mold resin) 40 is arranged to contact the die pad 20 and the inner lead portion 30M of the lead 30.

[0020] As shown in FIG. 4, the semiconductor chip 10 has an upper surface (main surface, front surface, surface) 10t and a lower surface (main surface, back surface, surface) 10b opposite to the upper surface 10t. As shown in FIG. 3, the semiconductor chip 10 has four sides (chip sides) 10s in a plan view. The four sides 10s are composed of a side 10s1 extending in the X direction, a side 10s2 opposite to the side 10s1, a side 10s3 intersecting the side 10s1 and the side 10s2 and extending in the Y direction, and a side 10s4 opposite to the side 10s3. The side 10s1 is arranged at the position closest to each of the plurality of leads 30 among the four sides 10s of the semiconductor chip 10 and is a side extending in the X direction. In the example shown in FIG. 3, the semiconductor chip 10 forms a rectangle in a plan view, and the long sides 10s1 and 10s2 are arranged to extend along the X direction.

[0021] On the upper surface 10t of the semiconductor chip 10, a gate electrode pad GE and a source electrode pad SE are arranged. A plurality of openings are arranged in an insulating film (passivation film) having the upper surface 10t of the semiconductor chip 10. Each of the gate electrode pad GE and the source electrode pad SE is exposed from the insulating film at the opening. The area of the source electrode pad SE is larger than the area of the gate electrode pad GE. The gate electrode pad GE is an electrode pad connected to the gate electrode G of the transistor Q1 shown in FIG. 5 described later. The source electrode pad SE is an electrode pad connected to the source S of the transistor Q1 shown in FIG. 5 described later.

[0022] Each of the gate electrode pad GE and the source electrode pad SE is made of, for example, a metal mainly composed of aluminum. The metal mainly composed of aluminum includes not only pure aluminum but also aluminum alloys in which additive elements such as silicon and copper are added to aluminum. When it is called a metal mainly composed of aluminum, aluminum occupies at least 90% by weight or more, preferably 95% by weight or more, of the metal. Note that the elements added to aluminum are not limited to copper and silicon, and there are various modifications.

[0023] As shown in FIG. 4, a drain electrode pad (drain electrode) DE is disposed on the lower surface 10b of the semiconductor chip 10. The drain electrode pad DE is an electrode pad connected to the drain D of the transistor Q1 shown in FIG. 5 to be described later. In the example shown in FIG. 4, the entire lower surface 10b of the semiconductor chip 10 serves as the drain electrode pad DE.

[0024] The drain electrode pad DE is made of a metal film. Although details will be described later, in the metal film constituting the drain electrode pad DE, the metal film disposed at the interface with the die bonding material 11 is preferably made of a metal that easily bonds to the die bonding material 11. For example, in the case of this embodiment, the die bonding material 11 is made of sintered copper. Therefore, in the drain electrode pad DE, it is preferable that a metal film made of any of gold, silver, copper, and nickel is formed on the portion in contact with the die bonding material 11. On the other hand, when the die bonding material 11 is solder or a conductive resin (a resin body in which a plurality of conductive particles are mixed in a resin including a thermosetting resin), it is preferable that a metal film made of gold or silver is formed on the portion in contact with the die bonding material 11.

[0025] In this embodiment, a MOSFET having a vertical channel structure is exemplified as an example of the transistor Q1. Therefore, the drain electrode pad DE is disposed on the lower surface 10b of the semiconductor chip 10, which is the surface opposite to the surface of the semiconductor chip 10 on which the gate electrode pad GE and the source electrode pad SE are disposed. The drain electrode pad DE of the semiconductor chip 10 is electrically connected to the die pad 20 via the die bonding material 11.

[0026] Although illustration is omitted, as a modification of this embodiment, when a MOSFET having a horizontal channel structure is used, a gate electrode pad GE, a source electrode pad SE, and a drain electrode pad DE are disposed on the upper surface 10t of the semiconductor chip 10.

[0027] As shown in FIGS. 3 and 4, the semiconductor device PKG1 has a die pad (metal plate, chip mounting portion, heat sink) 20 on which a semiconductor chip 10 is mounted. Each of the die pad 20 and the plurality of leads 30 (see FIG. 3) has a base material 31 made of, for example, copper (Cu) or an alloy material having copper (Cu) as a main component. As shown in FIG. 4, the die pad 20 has an upper surface (surface, main surface, chip mounting surface) 20t on which the semiconductor chip 10 is mounted via a die bonding material 11, and a lower surface (surface, main surface, back surface, main surface) 20b opposite to the upper surface 20t.

[0028] In the case of the present embodiment, the die bonding material 11 is made of a conductive material that electrically connects the drain electrode pad DE (see FIG. 4) and the die pad 20. The die bonding material 11 is made of a sintered metal such as sintered copper or sintered silver. In the case of the present embodiment, as shown in FIG. 3, a wire bonding layer WBL made of a sintered metal is disposed on the source electrode pad SE. By using a sintered metal as the die bonding material 11, in the manufacturing process of the semiconductor device, each of the die bonding material 11 and the wire bonding layer WBL can be sintered by a single sintering process.

[0029] As a modification of the die bonding material 11, a resin material containing conductive particles or solder can be exemplified. A resin material containing conductive particles is called a conductive resin or a conductive paste. Further, a material using silver particles as the conductive particles is called a silver paste.

[0030] As another modification, when an element structure (for example, a transistor having a lateral channel structure) in which no electrode is disposed on the lower surface 10b of the semiconductor chip 10 is applied, it is not essential for the die bonding material 11 to have conductivity. In this case, for example, an insulating resin adhesive can be used.

[0031] However, as will be described later, when a sintering process is performed, a heat treatment at a high temperature is performed. Therefore, from the viewpoint of preventing damage to the die bonding material 11 during the sintering process, it is preferable that the die bonding material 11 is a sintered metal.

[0032] As shown in FIG. 2, the die pad 20 has four sides 20s in plan view. Specifically, the die pad 20 has a side 20s1 extending in the X direction, a side 20s2 disposed on the opposite side of the side 20s1, a side 20s3 extending in the Y direction and intersecting the side 20s1, and a side 20s4 disposed on the opposite side of the side 20s3 and intersecting the side 20s1.

[0033] The die pad 20 has a main body portion (part) 20P1 including a region on which the semiconductor chip 10 (see FIG. 3) is mounted, a header portion (part) 20P2 having a side 20s2 disposed on the opposite side of the side 20s1 in plan view, and a connecting portion (part) 20P3 connecting the main body portion 20P1 and the header portion 20P2. Each of the sides 20s1, 20s3, and 20s4 is a side of the main body portion 20P1 of the die pad 20. The side 20s2 is a side of the header portion 20P2 of the die pad 20.

[0034] The main body portion 20P1 is a region including a region for mounting the semiconductor chip 10 (see FIG. 3) and a region for contacting a jig for fixing the die pad 20 in the process of bonding the wire 12 to the semiconductor chip (wire bonding process described later). The main body portion 20P1 forms a quadrilateral in plan view. In the example shown in FIG. 2, the main body portion 20P1 forms a rectangle, and the side 20s1 is the long side. The semiconductor chip 10 is disposed such that the side 10s1 and the side 20s1 of the die pad 20 extend along each other in plan view.

[0035] The header portion 20P2 is formed integrally with the main body portion 20P1 and the connecting portion 20P3, but the semiconductor chip 10 is not mounted on the header portion 20P2. The side 20s2 of the header portion 20P2 and its periphery are exposed from the sealing body 40. Since the header portion 20P2 exposed from the sealing body 40 and the main body portion 20P1 are formed integrally, the heat dissipation characteristics of the semiconductor device PKG1 can be improved. The connecting portion 20P3 is a portion for connecting the header portion 20P2 and the main body portion 20P1.

[0036] As shown in FIGS. 2 and 4, the lower surface 20b of the die pad 20 is exposed from the sealing body 40. Since the lower surface 20b of the die pad 20 is exposed from the sealing body 40, the heat dissipation characteristics of the die pad 20 can be improved. Further, when the die pad 20 is joined to a terminal of a mounting substrate (not shown), the die pad 20 itself can be used as a drain terminal (collector terminal in the case of an IGBT).

[0037] From the viewpoint of increasing the heat capacity of the die pad 20 or increasing the cross-sectional area of the conductive path through which current flows, it is preferable that the thickness of the die pad 20 (that is, the length in the Z direction) is large. In the example shown in FIG. 4, the thickness of the die pad 20 is larger than the thickness of the semiconductor chip 10. Further, the thickness of the die pad 20 (the distance from the upper surface 20t to the lower surface 20b) is larger than the thickness of the lead 30 (the distance from the upper surface 30t to the lower surface 30b). For example, in the example shown in FIG. 4, the thickness of the die pad 20 is about 500 μm to 2000 μm.

[0038] Further, the portion of the die pad 20 that is exposed from the sealing body 40 (outer portion, exposed portion) is covered with the metal film 22. Similarly, in each of the plurality of leads 30, the portion that is exposed from the sealing body 40 (outer lead portion 30X) is covered with the metal film 32. The metal film 22 and the metal film 32 are metal films for improving the wettability of the solder material used as a connection material when the semiconductor device PKG1 is mounted on a mounting substrate.

[0039] As shown in FIGS. 3 and 4, the semiconductor device PKG1 has a plurality of leads 30 electrically connected to the semiconductor chip 10. As shown in FIG. 3, each of the plurality of leads 30 faces the side 20s1 of the die pad 20 in a plan view. However, as shown in FIG. 4, the lower surface 30b of the lead 30 is at a position higher than the upper surface 20t of the die pad 20 in the Z direction. For this reason, in the cross-sectional view shown in FIG. 4, the lead 30 does not face the side 20s1 of the die pad 20. "The plurality of leads 30 and the side 20s1 of the die pad 20 face each other in a plan view" means that in the plan view as shown in FIG. 3, the plurality of leads 30 and the side 20s1 of the die pad 20 appear to face each other. Therefore, as shown in FIG. 4, there may be a case where the end face of the lead 30 and the end face of the die pad 20 do not face each other. Although illustration is omitted, as a modification of the present embodiment, even when the end face of the lead 30 and the end face of the die pad 20 face each other, it is included in the above-described state where "the plurality of leads 30 and the side 20s1 of the die pad 20 face each other in a plan view".

[0040] The plurality of leads 30 include a source lead (source lead, source terminal) 30S, a drain lead (drain lead, drain terminal) 30D, and a gate lead (gate lead, gate terminal) 30G. In the example shown in FIG. 3, the plurality of leads 30 are arranged along the X direction. In the example shown in FIG. 3, in the X direction, the leads 30G, 30D, and 30S are arranged in this order. However, the arrangement order is not limited to the mode shown in FIG. 3, and for example, they may be arranged in the order of lead 30G, lead 30S, and lead 30D.

[0041] As shown in FIG. 4, each of the plurality of leads 30 includes an inner lead portion 30M sealed in the sealing body 40 and an outer lead portion (outer portion, exposed portion) 30X exposed from the sealing body 40. In the case of the present embodiment, the outer lead portion 30X is bent, and the tip portion of the outer lead portion 30X is arranged at a position lower than the inner lead portion 30M. The shape of the outer lead portion 30X shown in FIG. 4 is called a gullwing shape.

[0042] As shown in FIG. 3, the die pad 20 is integrally formed with a lead 30D which is a drain terminal. The lead 30D is an external connection terminal electrically connected to a drain D shown in FIG. 5 described later. The lead 30D is electrically connected to a drain electrode pad DE (see FIG. 4) of the semiconductor chip 10 via the die pad 20 and the die bonding material 11. Further, since the lead 30D is connected (linked) to the die pad 20, in the manufacturing process of the semiconductor device described later, it has a function as a suspension lead for supporting the die pad 20.

[0043] Also, as shown in FIG. 3, the gate electrode pad GE of the semiconductor chip 10 and the lead 30G are electrically connected via a wire (conductive member, metal wire) 12 (specifically, a gate wire 12G). Similarly, the source electrode pad SE of the semiconductor chip 10 and the lead 30S are electrically connected via a wire 12 (specifically, a plurality of source wires 12S).

[0044] The wire 12 is a conductive member that connects the electrode pad on the upper surface 10t side of the semiconductor chip 10 and the lead 30. Examples of materials that can be used as the wire 12 include metals mainly composed of metals such as copper (Cu), gold (Au), silver (Ag), or aluminum (Al). In the case of this embodiment, each of the plurality of wires 12 is a copper wire made of copper. As described above, each of the gate electrode pad GE and the source electrode pad SE is made of, for example, a metal mainly composed of aluminum. Therefore, the wire 12 and the source electrode pad SE (or the gate electrode pad GE) are made of different types of metals.

[0045] When attempting to directly bond the wire 12 and the source electrode pad SE, which are different from each other, there is room for improvement in terms of the electrical connection reliability (for example, bonding strength or electrical characteristics) of the bonding interface as compared to the case of bonding the same type of metals.

[0046] Therefore, in the case of this embodiment, as shown in FIG. 4, a wire bonding layer WBLS to which the wire 12S is bonded is interposed between the source electrode pad SE and the wire 12S. Further, a wire bonding layer WBLG is interposed between the gate electrode pad GE and the wire 12G shown in FIG. 3. The wire bonding layer WBLS and the wire bonding layer WBLG are made of the same material and are manufactured by the same manufacturing method. Hereinafter, the wire bonding layer WBLS disposed on the source electrode pad SE will be typically taken up for explanation, but in some cases, it may be described as a wire bonding layer WBL as a general term for the wire bonding layer WBLS and the wire bonding layer WBLG.

[0047] The wire bonding layer WBL shown in FIG. 4 is made of a sintered metal. In the case of this embodiment, the wire bonding layer WBL is made of sintered copper in which a plurality of copper particles are sintered. As a modification of the wire bonding layer WBL, sintered silver in which a plurality of silver particles are sintered may be used. Details of the wire bonding layer WBL made of a sintered metal will be described later.

[0048] As shown in FIG. 3, one end of the source wire 12S is bonded to a wire bonding layer WBLS disposed on the source electrode pad SE of the semiconductor chip 10. On the other hand, the other end of the wire 12S opposite to the above-mentioned one end is bonded to a metal film 33 (see FIG. 4) covering the wire bonding region 30W of the lead 30S. One end of the gate wire 12G is bonded to a wire bonding layer WBLG disposed on the gate electrode pad GE of the semiconductor chip 10. On the other hand, the other end of the wire 12G opposite to the above-mentioned one end is bonded to a metal film (not shown) covering the wire bonding region 30W of the lead 30G. The metal film 33 is, for example, a film made of nickel (Ni) or silver (Ag). By bonding the wire 12 to the metal film 33 covering the wire bonding region 30W, the bonding strength between the wire 12 and the lead 30 can be improved. The metal film covering the wire bonding region 30W of the lead 30G is made of the same material as the metal film 33 shown in FIG. 4.

[0049] Also, in a power semiconductor device, a larger current flows through the wiring path connected to the source electrode pad SE than through the wiring path connected to the gate electrode pad GE. Therefore, in the example shown in FIG. 3, a plurality of wires 12S are connected to the source electrode pad SE. Also, in the example shown in FIG. 3, the thickness of each of the plurality of wires 12S is thicker than the thickness of the wire 12G. Further, when the wire 12S is made of copper, the electrical conductivity of the wire 12S can be increased as compared with the case where the wire 12S is made of gold or aluminum. Also, copper has the merit of being able to reduce the raw material cost as compared with silver and gold.

[0050] Note that the shape and number of the wires 12 are not limited to the embodiment shown in FIG. 3, and there are various modifications. For example, when the thicknesses of the wire 12S and the wire 12G are different as shown in FIG. 3, it is necessary to use different wire bonds even if the raw materials of the wire 12S and the wire 12G are the same. Therefore, the wire 12S may be made of, for example, copper, and the wire 12 may be made of different materials such as gold or aluminum for the wire 12G. In this case, the wire bonding layer WBLG disposed on the gate electrode pad GE may not be disposed. Alternatively, in FIG. 3, the thickness of the wire 12S is thicker than the thickness of the wire 12G, but as a modification, wires 12 having the same thickness may be used. In this case, each of the wire 12S and the wire 12G can be bonded by the same wire bond.

[0051] The semiconductor chip 10, the die bond material 11 (see FIG. 4), the inner lead portions 30M of the respective plurality of leads 30, the wire bonding layer WBL, and the plurality of wires 12 are sealed by a sealing body 40. The sealing body 40 is a resin body that seals the semiconductor chip 10 and the wires 12. The sealing body 40 has an upper surface 40t (see FIGS. 1 and 4) and a lower surface (mounting surface) 40b (see FIGS. 2 and 4) located on the opposite side of the upper surface 40t. Also, as shown in FIGS. 1 and 2, each of the upper surface 40t (see FIG. 1) and the lower surface 40b (see FIG. 2) of the sealing body 40 has a plurality of sides 40s at the peripheral portion.

[0052] The sealing body 40 is mainly composed of a thermosetting resin such as an epoxy resin. Further, in the present embodiment, in order to improve the characteristics of the sealing body 40 (for example, the expansion characteristics due to heat influence), for example, filler particles such as silica (silicon dioxide; SiO2) particles are mixed in the resin material.

[0053] <Circuit configuration example> Next, a configuration example of the circuit included in the semiconductor device PKG1 shown in FIG. 3 and an example of the element structure of the transistor will be described. FIG. 5 is an explanatory diagram schematically showing an example of the circuit included in the semiconductor device shown in FIG. 1. Further, FIG. 6 is a cross-sectional view of a main part showing an example of the element structure of the field effect transistor shown in FIG. 5.

[0054] Semiconductor devices for power control called power semiconductor devices include those having semiconductor elements such as diodes, thyristors, or transistors. Transistors are used in various fields, but as in the present embodiment, for example, a transistor incorporated in a power control circuit through which a large current of 1 A (ampere) or more flows and operates as a switching element is called a power transistor. The semiconductor device PKG1 of the present embodiment has a semiconductor chip 10 provided with a transistor Q1 that is a power transistor, as shown in FIG. 5. In the examples shown in FIGS. 5 and 6, the transistor Q1 included in the semiconductor chip 10 is a field effect transistor, specifically, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In a power semiconductor device, a transistor is used as a switching element, for example. A MOSFET used in a power semiconductor device is called a power MOSFET.

[0055] The MOSFET described above is described as a general term representing a field-effect transistor having a gate electrode made of a conductive material disposed on a gate insulating film. Therefore, even when described as a MOSFET, it does not exclude a gate insulating film other than an oxide film. Also, even when described as a MOSFET, it does not exclude a gate electrode material other than a metal, such as polysilicon.

[0056] The transistor Q1 shown in FIG. 5 is formed, for example, by an n-channel type field-effect transistor as shown in FIG. 6. FIG. 6 is a cross-sectional view of a main part showing an example of the element structure of the field-effect transistor shown in FIG. 5.

[0057] In the example shown in FIG. 6, an n-type epitaxial layer EP is formed on the main surface WHt of a semiconductor substrate WH made of, for example, n-type single-crystalline silicon. The semiconductor substrate WH and the epitaxial layer EP constitute the drain region of the MOSFET (the region corresponding to the drain D shown in FIG. 5). This drain region is electrically connected to a drain electrode pad DE formed on the lower surface 10b (see FIG. 4) side of the semiconductor chip 10.

[0058] A channel formation region CH, which is a p+-type semiconductor region, is formed on the epitaxial layer EP, and a source region (the region corresponding to the source S shown in FIG. 5) SR, which is an n+-type semiconductor region, is formed on the channel formation region CH. The source region SR is electrically connected to a source electrode pad SE formed on the upper surface 10t (see FIG. 4) side of the semiconductor chip 10 via a lead-out wiring. Also, a trench (opening, groove) TRQ is formed in the semiconductor region laminated on the semiconductor substrate WH, penetrating the channel formation region CH from the upper surface of the source region SR and reaching the inside of the epitaxial layer EP.

[0059] Also, a gate insulating film GI is disposed on the inner wall of the trench TRQ. Further, a gate electrode G laminated so as to fill the trench TRQ is disposed on the gate insulating film GI. The gate electrode G is electrically connected to the gate electrode pad GE of the semiconductor chip 10 via a lead wiring.

[0060] Also, in the transistor Q1, since the drain region and the source region SR are disposed in the thickness direction with the channel formation region CH interposed therebetween, a channel is formed in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field effect transistor in which a channel is formed along the main surface WHt, the occupied area of the element in a plan view can be reduced. For this reason, the planar size of the semiconductor chip 10 can be reduced.

[0061] Also, in the case of the above-described vertical channel structure, in a plan view, since the channel width per unit area can be increased, the on-resistance can be reduced. Note that FIG. 6 is a diagram showing the element structure of the field effect transistor. In the semiconductor chip 10 shown in FIG. 5, for example, a plurality (a large number) of transistors Q1 having an element structure as shown in FIG. 6 are connected in parallel. Thereby, for example, a power MOSFET through which a large current exceeding 1 ampere flows can be configured.

[0062] As described above, when a MOSFET is configured by connecting a plurality of transistors Q1 having a vertical channel structure in parallel, the electrical characteristics (mainly breakdown voltage characteristics, on-resistance characteristics, and capacitance characteristics) of the MOSFET change according to the planar size of the semiconductor chip 10. For example, if the planar area of the semiconductor chip 10 is increased, the number of cells of the transistors Q1 connected in parallel (that is, the number of elements) increases, so the on-resistance decreases and the capacitance increases.

[0063] In FIGS. 5 and 6, as an example of the power transistor included in the power semiconductor device, a MOSFET is illustrated, but various modifications can be applied. For example, instead of the MOSFET, an insulated gate bipolar transistor (IGBT) may be provided.

[0064] Also, in the example shown in FIG. 6, the transistor having a vertical channel structure was illustratively described, but it can also be replaced with a transistor having a horizontal channel structure. In this case, the drain electrode pad DE is disposed on the upper surface 10t (see FIG. 3) of the semiconductor chip 10. Therefore, the drain lead 30D shown in FIG. 3 and the drain electrode pad DE (see FIG. 6) connected to the drain of the transistor having a horizontal channel structure are electrically connected via a wire (drain wire) not shown. Further, among the drain leads 30D, the region (wire bonding region) to which the drain wire is connected is covered with the metal film 33 as in FIG. 4, and the drain wire is connected to the drain lead 30D via the metal film 33.

[0065] <Details of the wire bonding layer> Next, the details of the wire bonding layer WBL shown in FIGS. 3 and 4 will be described. FIG. 7 is an enlarged cross-sectional view showing an enlarged portion of each of the semiconductor chip, the wire bonding layer, and the wire shown in FIG. 4. Although not shown in FIG. 7, between the source electrode pad SE and the semiconductor substrate 13, a wiring layer electrically connected to the transistor Q1 (see FIG. 5) formed on the semiconductor substrate 13 and the source electrode pad SE is formed.

[0066] The semiconductor chip 10 has a semiconductor substrate 13, a source electrode pad SE disposed on the semiconductor substrate 13, and an insulating film 14 covering the source electrode pad SE.

[0067] In the example shown in FIG. 7, the insulating film 14 is a laminated film of an insulating film 14A and an insulating film 14B. The insulating film 14A is an inorganic insulating film made of, for example, silicon oxide or silicon nitride. On the other hand, the insulating film 14B is an organic insulating film made of a resin such as polyimide.

[0068] The insulating film 14 is formed so as to cover the source electrode pad SE, but an opening is formed in part thereof. A part of the source electrode pad SE is exposed from the insulating film 14 at the opening.

[0069] As described with reference to FIG. 4, when attempting to directly bond the wire 12S and the source electrode pad SE made of different metals to each other, there is room for improvement in terms of the electrical connection reliability at the bonding interface as compared with the case of bonding the same kind of metals. For example, when the wire 12 is made of copper and the source electrode pad SE is made of aluminum as in the present embodiment, since copper is harder than aluminum, the source electrode pad SE may be damaged by the external force applied when bonding the wire 12. If the source electrode pad SE is damaged by an external force, there is a concern that the electrical characteristics of the damaged portion of the source electrode pad SE will deteriorate (for example, the resistance value will increase). Further, if the source electrode pad SE is damaged by an external force, there is a concern that the bonding strength between the wire 12 and the source electrode pad SE will decrease.

[0070] Therefore, the inventor of the present application has studied a method of disposing a layer for bonding the wire 12, that is, a wire bonding layer WBL, on the source electrode pad SE as a method for preventing the source electrode pad SE from being damaged when bonding the wire 12.

[0071] Although illustration is omitted, first, a plating metal film formed, for example, by a plating method is formed on the source electrode pad SE, and a method of bonding the wire 12 to this plating metal film was studied. In the case of this study example, since the wire 12 is not directly bonded to the source electrode pad SE, it was found that damage to the source electrode pad SE can be suppressed when the thickness of the plating metal film is sufficiently thick.

[0072] However, when forming a metal film by a plating method, the thicker the metal film is to be made, the more difficult it becomes to form the film.

[0073] In the case of this embodiment, as the wire bonding layer WBL, a metal member made of sintered metal is used. As shown in FIG. 7, the wire bonding layer WBL made of sintered metal is a sintered body in which a plurality of metal particles 51 are sintered together. Each of the plurality of metal particles 51 is a fine particle having a particle size on the order of sub-micrometers. Also, a large number of metal particles 51 can be handled as a powder. Note that metal particles having a particle size on the order of nanometers may be used. Thereby, a plurality of metal particles can be sintered together at a lower temperature and with a lower load. However, when using metal particles having a particle size on the order of nanometers, the member cost (that is, the manufacturing cost of the semiconductor device) may be higher compared to metal particles having a particle size of sub-micrometers. Also, metal particles having a particle size on the order of micrometers may be used. Thereby, the cost can be reduced. However, when using metal particles having a particle size on the order of micrometers, the reactivity (sinterability) may decrease compared to metal particles having a particle size of sub-micrometers.

[0074] When forming the sintered body, a binder material is mixed with the powder of the metal particles 51 to make a paste material. After this paste material is formed into a predetermined shape and then heated, a plurality of metal particles 51 can be sintered together. The binder material evaporates during the heat treatment. The remaining sintered body becomes a porous body having voids 52 between the plurality of metal particles 51 sintered together.

[0075] As described above, since the sintered metal forms a paste-like raw material, the thickness of the wire bonding layer WBL can be increased compared to the method of forming a metal film by a plating method. For example, in the case of this embodiment, the thickness of the wire bonding layer WBL is about 60 μm. Since the thickness of the source electrode pad SE is about 5 μm, the thickness of the wire bonding layer WBL is more than 10 times the thickness of the source electrode pad SE.

[0076] Since the wire bonding layer WBL made of sintered metal can easily have its thickness increased, it is difficult for the external force when bonding the wire 12 to be transmitted to the source electrode pad SE. Further, as described above, the wire bonding layer WBL made of sintered metal is a porous body. For this reason, the external force when bonding the wire 12 is relaxed by the voids 52 of the wire bonding layer WBL and is difficult to be transmitted to the source electrode pad SE. In the case of the present embodiment, a wire bonding WBL made of sintered metal is provided, and the wire 12 is bonded to the wire bonding layer WBL. Thereby, it is possible to prevent or suppress damage to the source electrode pad SE when bonding the wire 12. By suppressing damage to the source electrode pad SE, the electrical connection reliability of the path for electrically connecting the wire 12 and the source electrode pad SE can be improved.

[0077] Each of the plurality of metal particles 51 is, for example, a copper particle. That is, the wire bonding layer WBL is made of sintered copper. As described above, when bonding a wire 12 made of copper, it is particularly preferable that the wire bonding layer WBL is made of sintered copper.

[0078] However, as a modification, each of the plurality of metal particles 51 may be, for example, a silver particle. In other words, the wire bonding layer WBL may be made of sintered silver. Even when the wire bonding layer WBL is sintered silver, the wire 12 and the wire bonding layer WBL can be bonded. However, copper is a metal having a hardness (Vickers hardness) more than twice that of silver. Therefore, sintered copper is preferable as the material of the wire bonding layer WBL to which the wire 12 made of copper is bonded.

[0079] Incidentally, in the case of the present embodiment, as shown in FIG. 7, a metal film 60 is interposed between the wire bonding layer WBL and the source electrode pad SE. Among the metal film 60, a metal film 62 made of any one of gold, silver, copper, and nickel is formed at a portion in contact with the wire bonding layer WBL.

[0080] In the case of the example shown in FIG. 7, the metal film 60 is a laminated film of a metal film 61 formed on the source electrode pad SE and a metal film 62 formed on the metal film 61. The metal film 61 is a nickel film made of nickel, for example. The metal film 62 is a gold film made of gold, for example. From the following viewpoints, it is preferable that the metal film 60 is interposed between the wire bonding layer WBL and the source electrode pad SE.

[0081] That is, considering the characteristics of the electrical connection path between the source electrode pad SE and the wire 12S, it is preferable to reduce the impedance in the electrical connection path between the wire bonding layer WBL made of sintered metal and the source electrode pad SE. In the case of the present embodiment, the wire bonding layer WBL is sintered on the source electrode pad SE to form a sintered body. At this time, the lower surface WBLb of the wire bonding layer WBL is sintered to the underlying layer (the metal film 62 in the example shown in FIG. 7) facing the lower surface WBLb.

[0082] When the wire bonding layer WBL is made of sintered copper, the underlying layer is preferably a metal on which copper is easily sintered. This is because the resistance value of the bonding interface between the sintered copper and the underlying layer can be reduced by sintering the sintered copper over the entire underlying layer. For this reason, it is preferable that a metal film 62 made of any of gold, silver, copper, and nickel is formed on the bonding interface with the wire bonding layer WBL.

[0083] As a modification of the present embodiment, the wire bonding layer WBL may be directly sintered on the source electrode pad SE. However, from the viewpoint of improving the connection reliability of the path for electrically connecting the wire bonding layer WBL and the source electrode pad SE, it is preferable that a metal film 62 made of any of gold, silver, copper, and nickel is in close contact with the lower surface WBLb of the wire bonding layer WBL.

[0084] The metal film 61 shown in FIG. 7 can be omitted. In the case of the example shown in FIG. 7, since the metal film 61 made of nickel is provided as the underlying layer of the metal film 62, it functions as an antioxidant film for preventing the portion of the source electrode pad SE exposed from the insulating film 14 from oxidizing.

[0085] <Details of Die Bonding Material> Next, the peripheral structure of the die bonding material shown in FIG. 4 will be described with reference to FIG. 8. FIG. 8 is an enlarged cross-sectional view showing an enlarged portion of each of the semiconductor chip, die bonding material, and die pad shown in FIG. 4.

[0086] As shown in FIG. 8, in the case of this embodiment, the die bonding material 11 is made of a sintered metal. As shown in FIG. 8, the die bonding material 11 is a sintered body in which a plurality of metal particles 53 are sintered together. Each of the plurality of metal particles 53 is a fine particle having a particle size on the order of sub-micrometers. Also, a large number of metal particles 53 can be handled as a powder. Note that metal particles having a particle size on the order of nanometers may be used. Thereby, a plurality of metal particles can be sintered together at a lower temperature and with a lower load. However, when using metal particles having a particle size on the order of nanometers, there is a possibility that the member cost (i.e., the manufacturing cost of the semiconductor device) will be higher compared to metal particles having a particle size of sub-micrometers. Also, metal particles having a particle size on the order of micrometers may be used. Thereby, the cost can be reduced. However, when using metal particles having a particle size on the order of micrometers, there is a possibility that the reactivity (sinterability) will decrease compared to metal particles having a particle size of sub-micrometers. Also, the sintered die bonding material 11 is a porous body having voids 54 between a plurality of sintered metal particles 53. When the die bonding material 11 shown in FIG. 8 is made of a sintered metal, in the process of sintering the wire bonding layer WBL (see FIG. 7), the wire bonding layer WBL and the die bonding material 11 can be sintered together.

[0087] In the case of this embodiment, the die bonding material 11 is made of the same sintered copper as the wire bonding layer WBL shown in FIG. 7. In other words, each of the plurality of metal particles 53 shown in FIG. 8 is a copper particle.

[0088] As a modification of this embodiment, the wire bonding layer WBL and the die bonding material 11 may be made of different materials. For example, one of the wire bonding layer WBL and the die bonding material 11 may be sintered copper and the other may be sintered silver. However, when the sintering process is performed in a batch, the sintering process temperature is processed at the same temperature. Therefore, from the viewpoint of making the sintered states of the wire bonding layer WBL and the die bonding material 11 uniform, it is preferable that the wire bonding layer WBL and the die bonding material 11 are made of the same material as each other.

[0089] Also, as another modification of this embodiment, the die bonding material 11 may be made of, for example, solder or a conductive resin. In the case of this modification, since the die bonding material 11 is cured first and then the wire bonding layer WBL is sintered, the sintering temperature of the wire bonding layer WBL needs to be such that the already cured die bonding material 11 is not remelted or damaged by heat.

[0090] Therefore, in terms of being able to reduce the constraints on the sintering temperature, it is preferable that each of the wire bonding layer WBL and the die bonding material 11 is a sintered metal, and it is particularly preferable that they are made of the same material as each other.

[0091] As shown in FIG. 8, in the drain electrode pad DE, a metal film 65 made of any one of gold, silver, copper, and nickel is formed at the portion in contact with the die bonding material 11. In the example shown in FIG. 8, the drain electrode pad DE is a laminated film of a metal film 63, a metal film 64, and a metal film 65 in order from the semiconductor substrate 13 side.

[0092] The metal film 63 is a titanium film made of titanium that has good adhesion to the semiconductor substrate 13 made of silicon. The metal film 64 is a nickel film made of, for example, nickel. Also, the metal film 65 is a silver film made of, for example, silver.

[0093] When the die bonding material 11 is made of sintered silver, the metal film 65 is preferably made of any one of gold, silver, and copper. On the other hand, when the die bonding material 11 is made of sintered silver, the metal film 65 is preferably made of any one of gold, silver, copper, and nickel.

[0094] By disposing the metal film 65 made of any of the above metals at the portion where the die bonding material 11 made of sintered metal is in contact with the drain electrode pad DE, the die bonding material 11 and the drain electrode pad DE can be easily sintered.

[0095] By the way, when the die bonding material 11 is made of solder or a conductive resin as described above, the metal film 65 is preferably made of gold or silver. When solder is joined to the metal film 65 made of gold or silver, a joint interface with a good connection state can be obtained.

[0096] Also, when the die bonding material 11 is made of a conductive resin, the electrical connection reliability can be improved by bringing a plurality of metal particles (for example, silver particles) contained in the conductive particles into close contact with the metal film 65 made of gold or silver. When the die bonding material 11 is a conductive resin, the adhesion strength between the drain electrode pad DE and the die bonding material 11 is determined by the adhesion strength between the resin contained in the conductive resin and the drain electrode pad DE.

[0097] In the example shown in FIG. 8, the die bonding material 11 is directly joined onto the upper surface 20t of the die pad 20 made of copper or a copper alloy. However, as a modification of FIG. 8, a metal film (not shown) made of, for example, silver may be disposed on the upper surface 20t of the die pad 20, and the die bonding material 11 may be joined to this silver-made metal film. In particular, when the die bonding material 11 is made of sintered silver, solder, or a conductive resin, it is preferable to interpose a metal film made of gold or silver between the die bonding material 11 and the die pad 20.

[0098] Each of the wire bonding layer WBL and the die bonding material 11 is made of, for example, a sintered metal as described above, but their thicknesses are different from each other. That is, the thickness TWBL of the wire bonding layer WBL shown in FIG. 7 is thicker than the thickness T11 of the die bonding material 11.

[0099] As described above, the wire bonding layer WBL is provided to prevent or suppress damage to the source electrode pad SE when bonding the wire 12 shown in FIG. 7. On the other hand, for the die bonding material 11 shown in FIG. 8, as long as the functions of fixing the semiconductor chip 10 on the die pad 20 and electrically connecting the semiconductor chip 10 and the die pad 20 are satisfied, its thickness T11 can be thin. For this reason, it is preferable that the thickness TWBL of the wire bonding layer WBL is thicker than the thickness T11 of the die bonding material 11.

[0100] For example, the thickness TWBL of the wire bonding layer WBL is about 60 μm. Also, the thickness T11 of the die bonding material 11 shown in FIG. 8 (in other words, the separation distance between the lower surface 10b of the semiconductor chip 10 and the upper surface 20t of the die pad 20) is, for example, about 30 μm.

[0101] As a modification of the present embodiment as described above, in the case where the die bonding material shown in FIG. 4 is solder or a conductive resin. Even in these modified examples, it is not necessary to increase the thickness of the die bonding material 11, and it is preferable that the thickness TWBL of the wire bonding layer WBL is thicker than the thickness T11 of the die bonding material 11.

[0102] <Method for manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device shown in FIGS. 1 to 4 will be described. FIG. 9 is a flowchart showing an example of the manufacturing process of the semiconductor device shown in FIGS. 1 to 4. In the example shown in FIG. 9, the method for manufacturing the semiconductor device of the present embodiment includes a lead frame preparation step, a semiconductor chip mounting step, a wire bonding step, a sealing step, a solder film forming step, and a singulation step.

[0103] <Lead frame preparation step> First, in the lead frame preparation step shown in FIG. 9, a lead frame LF shown in FIG. 10 is prepared. FIG. 10 is an enlarged plan view showing a part of the lead frame prepared in the lead frame preparation step shown in FIG. 9.

[0104] As shown in FIG. 10, the lead frame LF prepared in this step includes a plurality of device forming portions LFd connected to a frame portion (frame part) LFf. FIG. 10 shows eight device forming portions LFd. The plurality of device forming portions LFd each correspond to one semiconductor device PKG1 shown in FIG. 1. The lead frame LF is a so-called multi-piece substrate in which a plurality of device forming portions LFd are arranged in a matrix. In this way, by using the lead frame LF having a plurality of device forming portions LFd, a plurality of semiconductor devices PKG1 (see FIG. 1) can be manufactured collectively, so that the manufacturing efficiency can be improved. Note that FIG. 10 shows an example in which two columns of a plurality of device forming portions LFd arranged along the X direction are arranged side by side, but there are various modifications to the number of arrangements of the device forming portions LFd. For example, it may be one column or three or more columns.

[0105] The lead frame LF is made of a metal material mainly composed of, for example, copper (Cu). Each of the plurality of device forming portions LFd is connected to the frame portion LFf. The frame portion LFf is a support portion that supports each member formed in the device forming portion LFd until the singulation step shown in FIG. 9.

[0106] In addition, a die pad 20 and a plurality of leads 30 shown in FIG. 3 are formed in the device forming portion LFd. The die pad 20 is connected to the frame portion LFf via one of the plurality of leads 30 and is supported by the frame portion LFf. Also, the plurality of leads 30 are each connected to the frame portion LFf and are supported by the frame portion LFf.

[0107] Focusing on one of the plurality of device forming portions LFd, this step can be expressed as a step of preparing a die pad having an upper surface 20t, that is, a die pad preparation step.

[0108] Also, each of the plurality of leads 30 is connected to each other via a tie bar Lft1. Also, in the example shown in FIG. 10, each of the plurality of die pads 20 is connected to each other via a tie bar Lft2. As shown in FIG. 10, the tie bar Lft2 is disposed on the opposite side of the plurality of leads 30 via the die pad 20 in the device forming portion LFd, and includes a side 20s2 opposite to the side 20s1 facing the plurality of leads 30.

[0109] A groove T21 shown in FIGS. 7 and 9 is formed in the die pad 20. The groove T21 is formed by press working using a mold in the lead frame preparation process.

[0110] Among the plurality of leads 30, the leads 30 corresponding to the source lead 30S and the gate lead 30G shown in FIG. 3 have a wire bonding region 30W. In the lead frame preparation process, a metal film 33 is formed on the wire bonding region 30W so as to cover the upper surface 30t. The metal film 33 is made of silver and can be formed, for example, by a plating method.

[0111] Note that, as described above, a metal film made of, for example, silver may be formed on the upper surface 20t of the die pad 20. In this case, for example, when forming the metal film 33, the metal film on the die pad 20 can be formed simultaneously.

[0112] <Die Bonding Process> Next, in the die bonding process shown in FIG. 9, as shown in FIG. 3, the semiconductor chip 10 is mounted on the die pad 20. As shown in FIG. 9, the die bonding process includes a die bond paste application process and a semiconductor chip mounting process. FIG. 11 is an enlarged cross-sectional view showing a state where a die bonding paste is applied on the die pad in the die bond paste application process of FIG. 9. FIG. 12 is an enlarged cross-sectional view showing a state where a semiconductor chip is mounted on the die bonding paste shown in FIG. 11.

[0113] In the die bonding paste application process, for example, as shown in FIG. 11, a paste material for die bonding (die bonding paste material) 11P is applied onto the upper surface 20t of a die pad 20. The paste material 11P for die bonding includes a binder 53B and a plurality of metal particles 53 mixed in the binder 53B.

[0114] In the case of this embodiment, the plurality of metal particles 53 are, for example, copper particles. As a modification, the plurality of metal particles 53 may be silver particles. The binder 53B is an organic solvent that holds each of the plurality of metal particles 53 by its adhesiveness. The paste material 11P has a paste-like property as a whole and can be formed on the die pad 20 as shown in FIG. 11.

[0115] Although not shown in FIG. 9, after the die bonding paste application process and before the semiconductor chip mounting process, a drying process for drying the applied paste material 11P shown in FIG. 11 may be performed. In the drying process, for example, a heat treatment at about 120 degrees Celsius for about 10 minutes is performed with the lead frame LF disposed in a heating furnace (not shown). When this drying process is performed, a part of the binder 53B shown in FIG. 11 evaporates, and the density of the plurality of metal particles 53 increases, so that in the sintering process shown in FIG. 9, the plurality of metal particles 53 (see FIG. 11) are more easily sintered to each other.

[0116] In the semiconductor chip mounting process, as shown in FIG. 12, a semiconductor chip 10 having a source electrode pad SE is mounted on the die bonding paste material 11P. In this process, the lower surface 10b of the semiconductor chip 10 is pressed toward the paste material 11P. At this time, the lower surface 10b of the semiconductor chip 10 is adhered to the paste material 11P by the adhesive force of the binder 53B contained in the paste material 11P.

[0117] When the die bonding material 11 shown in FIG. 4 is made of a sintered metal as in this embodiment, in this process, the sintering process is not performed, and the paste material 11P is sintered in the sintering process shown in FIG. 9.

[0118] On the other hand, as a modification of the present embodiment, when the die bonding material 11 shown in FIG. 4 is made of solder or conductive resin, the die bonding process includes a die bonding material curing process as shown by the dotted line in FIG. 9. In the die bonding material process, the paste (solder paste or conductive resin paste), which is the raw material of the die bonding material, is cured.

[0119] When curing the solder paste, in the die bonding material curing process, after heating to a temperature equal to or higher than the melting point of the solder paste contained in the solder paste, it is cooled (referred to as a reflow process). On the other hand, when curing the conductive resin paste, in the die bonding material curing process, it is heated to a temperature equal to or higher than the curing temperature of the thermosetting resin contained in the conductive resin paste and maintained at a high temperature to cure the thermosetting resin (referred to as a cure bake process).

[0120] In the case of these modifications, when the die bonding process is completed, the semiconductor chip 10 is fixed on the die pad 20 via the die bonding material 11.

[0121] <Wire bonding layer forming process> Next, the wire bonding layer forming process shown in FIG. 9 includes a sintered metal paste coating process and a sintering process. FIG. 13 is an enlarged cross-sectional view showing a state in which a paste for sintered metal is applied on the die pad in the sintered metal paste coating process of FIG. 9. FIG. 14 is an explanatory diagram schematically showing a state in which the lead frame is heated in a vacuum furnace in the sintering process shown in FIG. 9.

[0122] In the sintered metal paste coating process, for example, as shown in FIG. 13, a paste material (paste material for sintered metal) WBLP, which is the raw material for the wire bonding layer, is applied on the source electrode pad SE of the semiconductor chip 10. The paste material 11P for the wire bonding layer has a binder 51B and a plurality of metal particles 51 mixed in the binder 51B.

[0123] In the case of this embodiment, the plurality of metal particles 51 are, for example, copper particles. As a modification, the plurality of metal particles 51 may be silver particles. The binder 51B is an organic solvent that holds each of the plurality of metal particles 51 by its adhesiveness. The paste material WBLP has a paste-like property as a whole and can be thickly formed on the source electrode pad SE as shown in FIG. 13.

[0124] In the case of this embodiment, the thickness of the paste material WBLP applied on the source electrode pad SE is, for example, 60 μm or more. Thus, in the case of the method of applying the paste material WBLP, the thickness TWBL of the wire bonding layer WBL shown in FIG. 7 can be increased as compared with, for example, the method of forming a metal film by plating.

[0125] Various methods can be used for the method of applying the paste material WBLP. For example, as a method of applying the paste material WBLP, a method can be exemplified in which the paste material WBLP is directly discharged onto the source electrode pad SE using a dispenser (not shown) and then formed. Alternatively, a method can be exemplified in which the paste material WBLP is directly applied onto the source electrode pad SE while being formed into a plate shape using a printing and coating apparatus (not shown). Alternatively, a method can be exemplified in which the paste material WBLP pre-formed into a plate shape as shown in FIG. 13 is placed on the source electrode pad SE.

[0126] Although not shown in FIG. 9, a drying process for drying the applied paste material WBLP (see FIG. 13) may be performed after the paste application process for sintering and before the sintering process. In the drying process, for example, heat treatment is performed at about 120 degrees Celsius for about 10 minutes with the lead frame LF placed in a heating furnace (not shown). When this drying process is performed, a part of the binder 51B shown in FIG. 13 evaporates and the density of the plurality of metal particles 51 increases, so that in the sintering process shown in FIG. 9, the plurality of metal particles 51 (see FIG. 13) are more easily sintered to each other.

[0127] Next, in the sintering process shown in FIG. 9, as shown in FIG. 14, for example, with the lead frame LF placed in the vacuum furnace 70, the lead frame LF is heated in a reduced-pressure atmosphere. In the example shown in FIG. 14, the vacuum furnace 70 has a sealed space connected to a vacuum pump 71, and a reduced-pressure state can be created by discharging the gas in the sealed space to the outside by the vacuum pump 71. Further, a heater 72 is arranged in the vacuum furnace 70 to heat the temperature in the sealed space. Note that there are various modifications to the method of heating the lead frame LF arranged in the vacuum furnace 70. For example, in some cases, heaters may be built into the stage 73 and the pressing jig 74 shown in FIG. 14 respectively.

[0128] The reason for performing this process in a reduced-pressure atmosphere is to inhibit the growth of the oxide film formed on the surface of the sintered metal by the sintering process. In particular, in the case of sintered copper, since an oxide film is more likely to be formed compared to sintered silver, it is preferable to perform the sintering process in a reduced-pressure atmosphere.

[0129] Note that, as a modification to this embodiment, there is a method of performing the sintering process in an inert gas atmosphere such as nitrogen gas, for example. Alternatively, as another modification, there is a method of performing the sintering process in a reducing atmosphere using, for example, formic acid. From the viewpoint of preventing the growth of the oxide film formed on the sintered metal, the modifications performed in an inert gas atmosphere or a reducing atmosphere are also effective.

[0130] However, when performing the sintering process in a reduced-pressure atmosphere, the effect of promoting the evaporation of the binder 51B shown in FIG. 13 can be obtained. In this regard, it is particularly preferable to perform the sintering process in a reduced-pressure atmosphere.

[0131] In the sintering process, as schematically shown by the white arrows in FIG. 14, the lead frame LF is sandwiched between the stage 73 and the pressing jig 74 and heated while applying a pressing force. The heating temperature and time have various modifications depending on the type of metal used. For example, when forming sintered copper, it is heated at 260 degrees Celsius for 5 minutes while applying a pressing force of 10 MPa.

[0132] In this process, from the viewpoint of facilitating the control of the sintered state of the die bond material 11 and the wire bonding layer WBL, as already described, it is particularly preferable that the die bond material 11 and the wire bonding layer WBL are sintered metals made of the same metal as each other.

[0133] The plurality of metal particles 53 shown in FIG. 11 are sintered by this process and bond to each other. At this time, as shown in FIG. 8, a part of the plurality of metal particles 53 is sintered to the die pad 20, and the other part is sintered to the drain electrode pad DE.

[0134] Similarly, the plurality of metal particles 51 shown in FIG. 13 are sintered by this process and bond to each other. At this time, as shown in FIG. 7, a part of the plurality of metal particles 51 is sintered to the source electrode pad SE (specifically, the metal film 62 formed on the source electrode pad SE).

[0135] In FIG. 13, the state of applying the paste material WBLP on the source electrode pad SE is shown as an example. However, when forming the wire bonding layer WBLG on the gate electrode pad GE shown in FIG. 3, in this process, the paste material WBLP (see FIG. 13), which is the raw material of the wire bonding layer WBLG, is applied on the gate electrode pad GE.

[0136] <Cleaning Process> Next, before the wire bonding process shown in FIG. 9, there may be a case where it includes a process of cleaning the wire bonding layer obtained in the wire bonding layer forming process shown in FIG. 9 as a cleaning treatment process. In the cleaning process, the wire bonding layer is cleaned using a cleaning material to remove the oxide film formed on the surface of the wire bonding layer, thereby exposing the non-oxidized metal on the surface. Note that the cleaning material used in this embodiment has a component closer to neutral than acidic. Therefore, damage to the wire bonding layer can be reduced. On the other hand, if it is desired to surely remove the oxide film, an acidic cleaning material may be used.

[0137] The pickling process includes, for example, a process of removing the oxide film with an acidic solution such as sulfuric acid, a process of flushing the acidic solution with water, and a process of drying to remove the remaining moisture.

[0138] In addition, when the oxide film can be removed by the pickling treatment step, the sintering treatment step shown in FIG. 9 can be carried out in an air atmosphere. Further, by performing the sintering treatment step in a reduced-pressure atmosphere, an inert gas atmosphere, or a reducing atmosphere, when the thickness of the oxide film formed on the surface of the wire bonding layer is substantially negligible between the sintering treatment step and the wire bonding step, the pickling treatment can be omitted.

[0139] However, as described above, since the sintered metal is a porous body, there may be a case where the cleaning liquid does not penetrate the entire surface of the metal. In addition, there may be a long time lag between the wire connection layer manufacturing step and the wire bonding step. In that case, there is a risk of growth of the oxide film on the surface of the sintered metal. Therefore, from the viewpoint of joining the wire 12 and the wire bonding layer WBL shown in FIG. 7 in a good connection state, it is particularly preferable to perform the sintering treatment step in a reduced-pressure atmosphere, an inert gas atmosphere, or a reducing atmosphere, and to perform the pickling treatment step before the wire bonding step.

[0140] <Wire Bonding Step> Next, in the wire bonding step shown in FIG. 9, as shown in FIG. 3, each of a plurality of electrode pads (gate electrode pad GE and source electrode pad SE) of the semiconductor chip 10 and a plurality of leads 30 is electrically connected via a wire (metal wire) 12. FIG. 15 is an enlarged cross-sectional view schematically showing a state in which a load and ultrasonic waves are applied to the wire via a bonding tool in the wire bonding step shown in FIG. 9.

[0141] In this step, the gate electrode pad GE of the semiconductor chip 10 and the lead 30G are electrically connected via the wire 12G (and the wire bonding layer WBLG). Further, in this step, the source electrode pad SE of the semiconductor chip 10 and the lead 30S are electrically connected via the wire 12S and the wire bonding layer WBLS.

[0142] Various modifications are applicable to the method of connecting the wire 12. For example, a wedge bonding method using a bonding tool called a wedge tool can be exemplified.

[0143] In the case of this embodiment, a metal film 33 (see FIG. 4) made of silver is formed in the wire bonding region 30W. One end of the wire 12 is joined to the gate electrode pad GE or the source electrode pad SE, and the other end of the wire 12 is joined to the metal film 33 formed in the wire bonding region 30W.

[0144] In the case of this embodiment, in the wire bonding process, as shown in FIG. 15, a wire 12 made of a metal different from the source electrode pad SE is joined to the wire bonding layer WBL. As an example as described above, the source electrode pad SE is made of a metal mainly composed of aluminum, and the wire 12S is made of copper.

[0145] In the wire bonding process, in order to surely join the wire 12 and the wire bonding layer WBL, as schematically shown in FIG. 15, the wire 12 and the wire bonding layer WBL are joined in a state where ultrasonic waves USW and a load F1 are applied to the wire 12. Further, in the wire bonding process, in order to surely join the wire 12 and the wire bonding layer WBL, the wire 12 is joined to the wire bonding layer WBL in a heated state.

[0146] At this time, when the wire 12 is directly joined to the source electrode pad SE shown in FIG. 15, or when joined to the metal film 60 shown in FIG. 15, the source electrode pad SE may be damaged due to the force transmitted to the source electrode pad SE through the hard wire 12.

[0147] On the other hand, in the case of this embodiment, as already described, the wire bonding layer WBL, which is a sintered metal, forms a paste-like raw material, so the thickness of the wire bonding layer WBL can be made thicker compared to the method of forming a metal film by plating. Therefore, it is difficult for the external force when joining the wire 12 to be transmitted to the source electrode pad SE.

[0148] In addition, the wire bonding layer WBL made of sintered metal is a porous body. Therefore, the external force when bonding the wire 12 is relaxed by the voids 52 of the wire bonding layer WBL and is difficult to be transmitted to the source electrode pad SE. In the case of this embodiment, the wire bonding layer WBL made of sintered metal is provided, and the wire 12 is bonded to the wire bonding layer WBL. Thereby, it is possible to prevent or suppress damage to the source electrode pad SE when bonding the wire 12. By suppressing damage to the source electrode pad SE, the electrical connection reliability of the path for electrically connecting the wire 12 and the source electrode pad SE can be improved.

[0149] In this section, as a representative example, the process of electrically connecting the source electrode pad SE and the wire 12S has been taken up and described. However, the process of electrically connecting the gate electrode pad GE and the wire 12G shown in FIG. 3 is the same.

[0150] In addition, in the case of this embodiment, after the wire bonding process, no cleaning process is particularly performed. However, as a modification, the above-described pickling process may be performed after the wire bonding process. Since the wire bonding process is performed in a heated state as described above, an oxide film may be formed on the wire bonding layer WBL during the wire bonding process and the oxide film may grow. When the pickling process is performed after the wire bonding process, this oxide film can be removed, so that an increase in the resistance value of the wire bonding layer WBL can be suppressed.

[0151] <Sealing process> Next, in the sealing process shown in FIG. 9, the semiconductor chip 10 shown in FIG. 3, a part of the die pad 20, a part of each of the plurality of leads 30 (inner lead portion 30M shown in FIG. 4), the wire bonding layer WBL, and the plurality of wires 12 are sealed with an insulating resin to form the sealing body 40 shown in FIG. 4.

[0152] In this process, for example, a molding die including an upper die (first die), not shown, and a lower die (second die) is used to form a sealing body 40 by a so-called transfer molding method. The lead frame LF is arranged such that the die pad 20 of the device forming portion LFd and the inner lead portions 30M (see FIG. 4) of the plurality of leads 30 shown in FIG. 10 are located within the cavity of the molding die. Then, the lead frame LF is sandwiched between the upper die and the lower die. In this state, when the softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity of the molding die, the insulating resin is molded following the shape of the cavity.

[0153] At this time, a part of the upper surface 20t of the die pad 20 that is continuous with the side 20s2 and the lower surface 20b of the die pad 20 are in close contact with the molding die. For this reason, as shown in FIG. 4, after this process, a part of the upper surface 20t and the lower surface 20b of the die pad 20 are exposed from the sealing body 40.

[0154] After the sealing body 40 is molded, it is heated until a part of the thermosetting resin contained in the sealing body 40 is cured (referred to as pre-curing). When it becomes possible to take out the lead frame LF from the molding die due to this pre-curing, the lead frame LF is taken out from the molding die. Then, it is transported to a heating furnace for further heat treatment (cure bake). Thereby, the remaining portion of the thermosetting resin is cured to obtain the sealing body 40.

[0155] Also, the sealing body 40 is mainly composed of an insulating resin. For example, by mixing filler particles such as silica (silicon dioxide; SiO2) particles into the thermosetting resin, the function of the sealing body 40 (for example, resistance to warping deformation) can be improved.

[0156] <Solder film forming process> Although not shown in Fig. 9, when forming the metal film 32 shown in Fig. 4, as a solder film forming step, the lead frame LF is immersed in a plating solution (not shown), and a metal film (the metal film 32 shown in Fig. 4) is formed on the surface of the metal portion (outer portion) exposed from the sealing body 40. Note that the metal film 22 formed on the lower surface 20b etc. of the die pad 20 shown in Fig. 4 is formed in advance in the lead frame preparation step. As a method of forming the metal film 22, for example, a plating method can be exemplified.

[0157] In this step, for example, by the solder dip method, a metal film 32 (see Fig. 4) made of solder is formed on the portion (outer lead portion 30X in Fig. 4) of each of the plurality of leads 30 exposed from the resin. Although not shown, in the solder dip method, the lead frame LF shown in Fig. 10 is disposed in a solder bath filled with molten solder. At this time, among the lead frame LF, the portions of the plurality of leads 30 are selectively immersed in the molten solder, and most of the sealing body 40 is not immersed in the molten solder. Thereby, a metal film 32 (see Fig. 4) made of solder can be formed on each of the plurality of leads 30.

[0158] <Singulation process> Next, the singulation process shown in Fig. 9 includes a lead cut process of cutting the tip portions of each of the plurality of leads 30 shown in Fig. 10, and a tie bar cut process of cutting the tie bar LFT1 shown in Fig. 10. Further, in the case of this embodiment, the singulation process includes a lead forming process of performing bending processing on the outer lead portion 30X of the lead 30 as shown in Fig. 4. For example, in this embodiment, the singulation process is performed in the order of the lead cut process, the lead forming process, and the tie bar cut process.

[0159] In the lead cut process, each of the plurality of leads 30 is separated by separating the plurality of leads 30 and the frame portion LFf. In this step, the tip portions of each of the plurality of leads 30 are cut by pressing (cutting process) using a punch and a die (not shown). The newly formed tip surface cut in this step is not covered with the metal film 32.

[0160] In the lead forming process, the outer lead portion 30X of the lead 30 is formed by pressing using a punch and a die (not shown). In the example shown in FIG. 4, the outer lead portion 30X is formed in a gullwing shape.

[0161] In the tie bar cutting process, the tie bar LFT1 shown in FIG. 10 is cut. Also, in the tie bar cutting process, the tie bar LFT2 is cut, and a plurality of die pads 20 connected via the tie bar LFT2 are each divided. After this process, the plurality of leads 30 are connected via the frame portion LFf. Also, the plurality of die pads 20 are connected via the drain lead 30D (see FIG. 3) that functions as a suspension lead and the frame portion LFf.

[0162] As the cutting method for the tie bar LFT1 and the tie bar LFT2, press working (cutting) using a punch and a die (not shown) can be used. Since this process is performed after the solder film forming process, the newly formed side surfaces cut in this process are not covered with the metal film 32. By this process, the device forming portion LFd shown in FIG. 10 is separated into individual pieces, and the semiconductor device shown in FIG. 1 is obtained.

[0163] Through the above-described respective processes, the semiconductor device PKG1 shown in FIGS. 1 to 4 is obtained. Thereafter, after performing any tests or inspections such as electrical tests and appearance inspections as necessary, those determined to be good products are conveyed to the next process such as the packaging process of the semiconductor device.

[0164] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0165] 10 Semiconductor chip 10b Lower surface (main surface, back surface, surface) 10s, 10s1, 10s2, 10s3, 10s4 Sides (chip sides)​ 10t upper surface (main surface, surface, face) 11 Die bonding material 11P, WBLP paste material (paste material for die bonding, paste material for sintered metal) 12, 12G, 12S wire (conductive member, metal wire) 13 Semiconductor substrate 14, 14A, 14B Insulating film 20 Die pad (metal plate, chip mounting part, heat sink) 20b lower surface (surface, main surface, back surface, main surface) 20P1 body part (portion) 20P2 header part (portion) 20P3 connecting part (portion) 20s, 20s1, 20s2, 20s3, 20s4 side 20t upper surface (surface, main surface, chip mounting surface) 22, 32, 33 Metal film 30, 30D, 30G, 30S lead (terminal) 30b lower surface 30M inner lead part (sealed part) 30t upper surface 30W wire bonding area 30X outer lead part (outer part, exposed part) 31 Base material 40 Sealing body (resin sealing body, resin body, molding resin) 40b lower surface (mounting surface) 40s side 40t upper surface 51, 53 Metal particles 51B, 53B Binder 52, 54 Void 60, 61, 62, 63, 64, 65 Metal film 70 Vacuum furnace 71 Vacuum pump 72 Heater 73 Stage 74 Pressing jig CH Channel formation area D Drain DE Drain electrode pad (drain electrode) EP Epitaxial layer F1 Load G Gate electrode GE Gate electrode pad GI Gate insulating film LF Lead frame LFd Device formation part LFf Frame part LFt1,LFt2 Tie bar Ni Nickel PKG1 Semiconductor device Q1 Transistor S Source SE Source electrode pad SR Source region (region corresponding to source S shown in Fig. 5) T11,TWBL Thickness T21 Groove TRQ Trench (opening, groove) USW Ultrasonic wave WBL,WBLG,WBLS Wire bonding layer WBLb Bottom surface WH Semiconductor substrate WHt Main surface

Claims

1. A die pad, a lead spaced apart from the die pad, a semiconductor chip provided with a first electrode pad and mounted on the die pad via a die bonding material, a wire electrically connected to each of the lead and the first electrode pad of the semiconductor chip, a sealing body for sealing the semiconductor chip, the die bonding material, and the wire, comprising: the first electrode pad and the wire are made of different types of metals from each other, a wire bonding layer made of a sintered metal is interposed between the first electrode pad and the wire, the wire is electrically connected to the first electrode pad via the wire bonding layer, a semiconductor device.

2. In claim 1, the wire is made of copper, the first electrode pad is made of a metal mainly composed of aluminum, a semiconductor device.

3. In claim 2, the wire bonding layer is made of sintered copper, a semiconductor device.

4. In claim 3, a first metal film is further interposed between the wire bonding layer and the first electrode pad, a metal film made of any one of gold, silver, copper, and nickel is formed in a portion of the first metal film that contacts the wire bonding layer, a semiconductor device.

5. In claim 1, the die bonding material is made of a sintered metal, a semiconductor device.

6. In claim 5, the wire is made of copper, the first electrode pad is made of a metal mainly composed of aluminum, each of the wire bonding layer and the die bonding material is made of sintered copper, a semiconductor device.

7. In claim 5, the semiconductor chip includes: a first surface facing the die pad, a second surface located on the opposite side of the first surface, a second electrode pad formed on the second surface, comprising: a first metal film is interposed between the wire bonding layer and the first electrode pad, a metal film made of any one of gold, silver, copper, and nickel is formed in a portion of the first metal film that contacts the wire bonding layer, a metal film made of any one of gold, silver, copper, and nickel is formed in a portion of the second electrode pad that contacts the die bonding material, a semiconductor device.

8. In claim 5, the thickness of the wire bonding layer is thicker than the thickness of the die bonding material, a semiconductor device.

9. In claim 1, The semiconductor chip has a power transistor composed of a power MOSFET or an IGBT, The first electrode pad is electrically connected to the source of the power MOSFET or the emitter of the IGBT, a semiconductor device.

10. (a) A step of preparing a lead frame provided with a die pad; (b) A step of applying a first paste material onto the die pad; (c) A step of mounting a semiconductor chip having a first electrode pad on the first paste material; (d) A step of disposing a second paste material containing a plurality of metal particles on the first electrode pad of the semiconductor chip; (e) A step of sintering the plurality of metal particles contained in the second paste material by heating the second paste material to form a wire bonding layer; (f) A step of bonding a wire made of a metal different from the first electrode pad to the wire bonding layer; A method of manufacturing a semiconductor device, including the above steps.

11. In Claim 10, The first paste material is made of the same material as the second paste material, In the step (e), by heating the first paste material, a plurality of metal particles contained in the first paste material are sintered to form a die bonding material for fixing the semiconductor chip on the die pad. A method of manufacturing a semiconductor device.

12. In Claim 11, Each of the plurality of metal particles is composed of copper particles, After the step (e) and before the step (f), the method of manufacturing a semiconductor device includes a step of pickling and cleaning the wire bonding layer.

13. In Claim 10, In the step (f), the wire and the wire bonding layer are joined in a state where ultrasonic waves and a load are applied to the wire. A method of manufacturing a semiconductor device.

14. In Claim 10, The wire is made of copper, The first electrode pad is made of a metal mainly composed of aluminum. A method of manufacturing a semiconductor device.

15. In Claim 13, Each of the plurality of metal particles is made of copper. A method of manufacturing a semiconductor device.

16. In Claim 10, The step (e) is carried out in a reduced-pressure treatment atmosphere, an inert gas atmosphere, or a reducing atmosphere. A method of manufacturing a semiconductor device.

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