Semiconductor device

Abstract

To provide a trimming circuit having high reliability; and provide a rewritable trimming circuit; and provide a driving method of a trimming circuit having high reliability; and provide a driving method of a rewritable trimming circuit.SOLUTION: A trimming circuit composed by using a storage node connected to a source electrode or a drain electrode of a transistor having extremely small off leakage current and a transistor with a gate electrode being connected to the storage node. And in a driving method, by using the transistor having extremely small off leakage current, a trimming state of an element or a circuit, which is connected in parallel with a source electrode and a drain electrode of a transistor with a gate electrode being connected to the storage node is controlled.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a trimming circuit and a method for driving a trimming circuit. [Background technology]

[0002] Integrated circuits that require highly accurate voltage and current values ​​(such as AD converters and DA converters) In the manufacturing process of the semiconductor device, the variation in characteristics that cannot be suppressed by adjusting the manufacturing conditions is compensated for. There is a need for a method to do this.

[0003] In addition, in the manufacturing process of integrated circuits (such as large-capacity memory devices) that require high yields, What is needed is a method for switching connections to built-in redundant circuitry.

[0004] A circuit called a trimming circuit is used for such purposes. The trimming circuit is connected in parallel to the device or circuit in a usable state or in an unusable state. This is a circuit that selects whether the output is in a normal state (trimming state) or in a normal state (trimming state). For example, a fuse or a Zener zap diode is used.

[0005] In addition, a transistor using an oxide semiconductor for a channel formation region is known (see Patent Document 2). 1) The oxide semiconductor layer can be manufactured relatively easily by using a sputtering method or the like. A transistor using an oxide semiconductor for a channel formation region has the advantage of being easy to manufacture. can. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP2007-123861A

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, fuses, Zener zapper diodes, etc. may cause problems in reliability. For example, in the laser cutting method of cutting a fuse using a laser, residues may remain at the cutting location, and the circuit may not be correctly interrupted.

[0008] In addition, conventional trimming circuits using irreversible elements such as fuses and Zener zapper diodes cannot return to the original state once cut, so there are problems such as being unable to re-trim and rewrite.

[0009] One aspect of the present invention has been made under such a technical background. One aspect of the present invention aims to provide a highly reliable trimming circuit. Or, one of the problems is to provide a rewritable trimming circuit. Or, one of the problems is to provide a driving method for a highly reliable trimming circuit. Or, one of the problems is to provide a driving method for a rewritable trimming circuit.

Means for Solving the Problems

[0010] To achieve the above object, one aspect of the present invention focuses on a configuration that maintains the set state of the switch for a long period without physically cutting the circuit. And, a storage node connected to the source electrode or drain electrode of a transistor with an extremely small off-leakage current, and a configuration including a transistor having a gate electrode connected to the storage node was conceived. Also, the off-leakage Using a transistor with an extremely small current, the inventors conceived a method for controlling the trimming state of an element or circuit connected in parallel to the source electrode and drain electrode of a transistor whose gate electrode is connected to the memory node, and thus solved the above problems. That is, one aspect of the present invention has a capacitor element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The first transistor and the second transistor are provided with a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, and the trimming circuit is such that source electrodes and drain electrodes of the third transistor are connected in parallel to a resistance element.

[0011] The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... That is, one aspect of the present invention has a capacitor element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The first transistor and the second transistor are provided with a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, and the trimming circuit is such that source electrodes and drain electrodes of the third transistor are connected in parallel to a resistance element. That is, one aspect of the present invention has a capacitor element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The first transistor and the second transistor are provided with a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, and the trimming circuit is such that source electrodes and drain electrodes of the third transistor are connected in parallel to a resistance element. That is, one aspect of the present invention has a capacitor element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The first transistor and the second transistor are provided with a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, and the trimming circuit is such that source electrodes and drain electrodes of the third transistor are connected in parallel to a resistance element. That is, one aspect of the present invention has a capacitor element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, one of a source electrode or a drain electrode is electrically connected to the memory node, and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The first transistor and the second transistor are provided with a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, and the trimming circuit is such that source electrodes and drain electrodes of the third transistor are connected in parallel to a resistance element.

[0012] The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The trimming circuit according to one aspect of the present invention described above includes the first transistor and the second transistor each having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region, one of the source electrodes or drain electrodes of each transistor, the gate electrode of the third transistor, and a memory node to which one electrode of the capacitor element is connected. A transistor having a semiconductor material having a bandgap of 2.5 eV or more in a channel formation region has a small off-leakage current, and a memory node having such a configuration has excellent charge holding ability, and the gate electrode connected to the memory node... The operating state of the third transistor connected to the auto electrode can be stably maintained. As a result, the operating state of the third transistor can be maintained for a long period without changing the structure of the components (for example, without causing damage to the elements or wiring). As a result, a highly reliable trimming circuit can be provided.

[0013] In addition, the trimming circuit according to one aspect of the present invention can change the operating state of the third transistor without causing an irreversible structural change in its components. As a result, the operating state of the third transistor can be changed any number of times. As a result, a rewritable trimming circuit can be provided.

[0014] One aspect of the present invention also includes a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a first transistor in which a gate electrode is electrically connected to a write terminal, and one of a source electrode or a drain electrode is electrically connected to the memory node and the other is electrically connected to a power supply potential line, a second transistor in which a gate electrode is electrically connected to an erase terminal, and one of a source electrode or a drain electrode is electrically connected to the memory node and the other is electrically connected to the ground potential line, and a third transistor in which a gate electrode is electrically connected to the memory node. The off-leakage currents of the first transistor and the second transistor are 1×10 A or less per 1 μm channel width, and the source electrode and the drain electrode of the third transistor are connected in parallel to a resistance element. The trimming circuit according to one aspect of the present invention includes a first transistor and a second transistor having extremely small off-leakage currents. Specifically, an oxide semiconductor is used in the channel formation region. -17

[0015] ​​​​​​​​​​​​ A transistor including a layer, wherein the magnitude of its off-leakage current is 1×10 -17 A or less per 1 μm channel width. One of the source electrode or drain electrode of each transistor is connected to one electrode of a storage node, to which one of the gate electrode of the third transistor and one electrode of a capacitive element are connected. The storage node having such a configuration has excellent charge holding ability, and can stably hold the operating state of the third transistor whose gate electrode is connected to the storage node. As a result, the operating state of the third transistor can be maintained for a long time without changing the structure of the components (for example, without causing damage to elements or wirings). Accordingly, a highly reliable trimming circuit can be provided.

[0016] Also, the trimming circuit according to one aspect of the present invention can change the operating state of the third transistor without causing an irreversible structural change in its components. As a result, the operating state of the third transistor can be changed any number of times. Accordingly, a rewritable trimming circuit can be provided.

[0017] Also, one aspect of the present invention is the above-described trimming circuit in which the first transistor and the second transistor both include an oxide semiconductor layer in a channel formation region.

[0018] The trimming circuit according to one aspect of the present invention includes a first transistor and a second transistor having an extremely small off-leakage current. Specifically, it is a transistor including an oxide semiconductor layer in a channel formation region, and one of the source electrode or drain electrode of each transistor is connected to one electrode of a storage node, to which one of the gate electrode of the third transistor and one electrode of a capacitive element are connected. ​It includes a gate. A transistor using an oxide semiconductor layer has an extremely small off-leakage current. In addition, the oxide semiconductor layer can be easily formed by a sputtering method or the like. Thereby, a highly reliable trimming circuit can be provided easily. Also, it can be laminated on other semiconductor devices (for example, semiconductor devices using single crystalline silicon) to form a trimming circuit. As a result, a semiconductor device with high added value can be provided.

[0019] Also, in one aspect of the present invention, a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, a gate electrode is electrically connected to a write terminal, and one of a source electrode or a drain electrode is electrically connected to the memory node and the other is electrically connected to a power supply potential line, a first transistor, a capacitive element in which a gate electrode is electrically connected to an erase terminal, and one of a source electrode or a drain electrode is electrically connected to the memory node and the other is electrically connected to the ground potential line, a second transistor, and a third transistor in which a gate electrode is electrically connected to the memory node. Also, it has a third transistor in which a gate electrode is electrically connected to the memory node. Moreover, it has a third transistor whose gate electrode is electrically connected to the memory node. In addition, the off-leakage currents of the first transistor and the second transistor are 1×10 A or less per 1 μm of channel width, and the source electrode and drain -17 electrodes of the third transistor are connected in parallel to a resistance element, which is a driving method of a trimming circuit of the resistance element. And it is a first step of inputting a signal that turns on the first transistor to the write terminal and a signal that turns off the second transistor to the erase terminal to set the potential of the memory node to a potential at which the third transistor turns on, and a second step of inputting a signal that turns off the first transistor and the second transistor to each of the write terminal and the erase terminal. That is, a signal that turns on the first transistor is input to the write terminal, a signal that turns off the second transistor is input to the erase terminal, and a first step of setting the potential of the memory node to a potential at which the third transistor turns on, and a second step of inputting a signal that turns off the first transistor and the second transistor to each of the write terminal and the erase terminal. And it is a first step of inputting a signal that turns on the first transistor to the write terminal and a signal that turns off the second transistor to the erase terminal to set the potential of the memory node to a potential at which the third transistor turns on, and a second step of inputting a signal that turns off the first transistor and the second transistor to each of the write terminal and the erase terminal. It is a first step of inputting a signal that turns on the first transistor to the write terminal and a signal that turns off the second transistor to the erase terminal to set the potential of the memory node to a potential at which the third transistor turns on, and a second step of inputting a signal that turns off the first transistor and the second transistor to each of the write terminal and the erase terminal. A method of driving a trimming circuit for trimming a resistor element, comprising the steps of: It is law.

[0020] The method for driving the trimming circuit according to the embodiment of the present invention further comprises: A step of applying a potential to the memory node so that the memory node is in an on-state; turning off the first and second transistors having poles connected to each other; This allows the trimming circuit to be configured without changing the structure of any of the elements constituting the trimming circuit. This allows the third transistor to be reversibly changed in operating state without any problem. It is possible to provide a method for driving a timing circuit.

[0021] In one aspect of the present invention, one electrode is connected to a memory node, the other electrode is connected to a ground potential line, The gate electrode is electrically connected to the write terminal, and the source electrode or drain electrode is connected to the write terminal. A drain electrode is electrically connected to a storage node and the other to a power supply potential line. The transistor with the gate electrode connected to the erase terminal and the source or drain electrode connected to the a second transistor electrically connected to the storage node and the other to a ground potential line; and a third transistor having a gate electrode electrically connected to the storage node. The off-leak current of the first transistor and the second transistor is 1×10 -17 A or less, and the source electrode and the drain electrode of the third transistor This is a method for driving a trimming circuit for a resistor element, in which a resistor is connected in parallel with the trimming circuit. This is done by applying a signal to the write terminal to turn off the first transistor and applying a signal to the erase terminal to turn off the second transistor. A signal is input to turn on the transistor, and the potential of the storage node is changed by the third transistor. A first step of setting a potential to an off state, and for each of a write terminal and an erase terminal a second step of inputting a signal that turns off a first transistor and a second transistor This is a driving method for a trimming circuit that enables the use of a resistive element, including

[0022] The driving method for the trimming circuit according to one aspect of the present invention includes a step of setting the potential of a memory node to a potential at which a third transistor is in an off state, and a step of turning off a first transistor and a second transistor having a source electrode or a drain electrode connected to the memory node This has. As a result, the structure of any element constituting the trimming circuit does not change, and the operating state of the third transistor can be reversibly changed. Consequently, a highly reliable driving method for a trimming circuit can be provided. without changing, and reversibly changing the operating state of the third transistor. As a result, a highly reliable trimming circuit driving method can be provided. Furthermore, in one aspect of the present invention, following the above-described second step, a signal that turns on the first transistor is input to the write terminal, and a signal that turns off the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an on state, or a signal that turns off the first transistor is input to the write terminal, and a signal that turns on the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an off state, and the potential of the memory node is set to a potential different from that in the second step. A third step, and for each of the write terminal and the erase terminal, a fourth step of inputting a signal that turns off the first transistor and the second transistor, which is a driving method for a trimming circuit that changes the trimming state of a resistive element.

[0023] a signal that turns on the first transistor is input to the write terminal, and a signal that turns off the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an on state, or a signal that turns off the first transistor is input to the write terminal, and a signal that turns on the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an off state, and the potential of the memory node is set to a potential different from that in the second step. A third step, and for each of the write terminal and the erase terminal, a fourth step of inputting a signal that turns off the first transistor and the second transistor, which is a driving method for a trimming circuit that changes the trimming state of a resistive element. a signal that turns off the first transistor is input to the write terminal, and a signal that turns on the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an off state, and the potential of the memory node is set to a potential different from that in the second step. A third step, and for each of the write terminal and the erase terminal, a fourth step of inputting a signal that turns off the first transistor and the second transistor, which is a driving method for a trimming circuit that changes the trimming state of a resistive element. a signal that turns off the first transistor is input to the write terminal, and a signal that turns on the second transistor is input to the erase terminal, so that the potential of the memory node becomes the potential at which the third transistor is in an off state, and the potential of the memory node is set to a potential different from that in the second step. A third step, and for each of the write terminal and the erase terminal, a fourth step of inputting a signal that turns off the first transistor and the second transistor, which is a driving method for a trimming circuit that changes the trimming state of a resistive element. state, and the potential of the memory node is set to a potential different from that in the second step. A third step, and for each of the write terminal and the erase terminal, a fourth step of inputting a signal that turns off the first transistor and the second transistor, which is a driving method for a trimming circuit that changes the trimming state of a resistive element. This is a driving method for a trimming circuit that changes the trimming state of a resistive element, including a third step, and a fourth step of inputting a signal that turns off the first transistor and the second transistor to each of the write terminal and the erase terminal.

[0024] ​​ The method for driving the trimming circuit according to one embodiment of the present invention includes changing the potential of the memory node from that before the driving. a step of setting a potential at a potential corresponding to the storage node; The step of turning off the first transistor and the second transistor is also included. The third trimming circuit can be reversibly formed without changing the structure of any of the elements constituting the trimming circuit. The operating state of the transistor can be changed, resulting in the driving of a rewritable trimming circuit. We can provide a method. Effect of the Invention

[0025] According to one embodiment of the present invention, a highly reliable trimming circuit can be provided. A trimming circuit capable of performing trimming can be provided. Alternatively, a method for driving a highly reliable trimming circuit can be provided. Alternatively, a method for driving a rewritable trimming circuit can be provided. [Brief description of the drawings]

[0026]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. without departing from the spirit and scope of the present invention. Those skilled in the art can easily understand this. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. Among them, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof will be omitted. The repeated description thereof will be omitted.

[0028] (Embodiment 1) In this embodiment, a memory node connected to a source electrode or a drain electrode of a transistor with an extremely small off-leak current, and a transistor having a gate electrode connected to the memory node will be described with reference to FIG. 1 in the configuration of a trimming circuit including the same. The configuration of a trimming circuit according to an aspect of the present invention is shown in FIG. 1. The trimming circuit 100 illustrated in FIG. 1

[0029] has a capacitor element 140, a first transistor 110, a second transistor 120 , and a third transistor 130. Note that the first transistor 110 and the second transistor 120 have a semiconductor material with a bandgap of 2.5 eV or more in the channel formation region and are transistors with an extremely small off-leak current. By making the off-leak current extremely small , the charge written in the memory node 150 can be held for a long time. For example, an oxide semiconductor layer with a bandgap of 3.15 eV is provided in the channel formation region, and the off-leak current is extremely small. is extremely small, the charge written in the memory node 150 can be held for a long time. For example, an oxide semiconductor layer with a bandgap of 3.15 eV is provided in the channel formation region, and the off-leak current having a size of 1×10 per channel width of 1 μm -17 A transistor with the following can be used to achieve this.

[0030] The transistors that can be used for the first transistor 110 and the second transistor 120 are preferably transistors having a semiconductor material with a bandgap larger than 1.12 eV of a silicon semiconductor in its channel formation region. For example, transistors having a semiconductor material with a bandgap of 2.5 eV or more, preferably 3.0 eV or more, in the channel formation region Specifically, transistors having an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a carbide semiconductor, a diamond thin film showing semiconductor characteristics, etc. in the channel formation region can be used to achieve this. Transistors having a semiconductor material with a bandgap of 2.5 eV or more in the channel formation region can have a smaller off-leakage current than transistors having a silicon semiconductor with a bandgap of 1.12 eV in their channel formation region.

[0031] In addition, in order to reduce the off-leakage currents of the first transistor and the second transistor, transistors with various configurations can be used. For example, a multi-gate transistor including a semiconductor layer having two or more channel formation regions connected in series can be used. Also, a transistor having a gap (also called an offset) provided between the source electrode or the drain electrode and the channel formation region can be used.

[0032] One electrode of the capacitor element 140 is electrically connected to the storage node 150, and the other electrode is electrically connected to the ground potential line respectively.

[0033] ​The memory node 150 includes a semiconductor material having a bandgap of 2.5 eV or more in the channel formation region and is connected to a first transistor 110 with a reduced off-leakage current, a second transistor 120, and a capacitive element 140. Providing the capacitive element 140 can suppress the occurrence of a phenomenon in which the potential of the memory node 150 becomes unstable due to a surge current or the like, which is preferable because of high reliability

[0034] For the first transistor 110, the gate electrode is electrically connected to the write terminal 115, one of the source electrode or the drain electrode is electrically connected to the memory node 150, and the other is electrically connected to the power supply potential line Note that a power supply potential Vdd higher than the ground potential is supplied to the power supply potential line

[0035] For the second transistor 120, the gate electrode is electrically connected to the erase terminal 125, one of the source electrode or the drain electrode is electrically connected to the memory node 150, and the other is electrically connected to the ground potential line

[0036] For the third transistor 130, the gate electrode is electrically connected to the memory node 150, and the source electrode and the drain electrode are connected in parallel to the resistance element 105

[0037] One electrode of the capacitive element 140 is connected to the memory node 150. The memory node 150 is electrically disconnected from the power supply potential line by the first transistor 110 with an extremely small off-leakage current and is electrically disconnected from the ground potential line by the second transistor 120 with an extremely small off-leakage current The memory node 150 configured in this way can stably hold the written charge for a long time

[0038] ​​​​​​​​​A third transistor 1 is connected to a memory node 150 that can stably hold the written charge for a long time. With a configuration in which 30 gate electrodes are connected, the operating state of the third transistor 130 (specifically, either the on state or the off state) can be maintained for a long time through the gate electrode. It can be done.

[0039] Also, according to this configuration, the operating state of the third transistor 130 can be maintained for a long time without irreversible structural changes in any components, so it is particularly reliable. Also, the potential of the memory node 150 can be rewritten without irreversible structural changes, and the operating state of the third transistor 130 can be changed any number of times. It can be changed any number of times.

[0040] According to one aspect of the present invention, a highly reliable trimming circuit can be provided. Or, a rewritable trimming circuit can be provided. It can provide a rewritable trimming circuit.

[0041] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. 。

[0042] (Embodiment 2) In this embodiment, a driving method of a trimming circuit including a memory node connected to a source electrode or a drain electrode of a transistor with an extremely small off-leakage current and a transistor having a gate electrode connected to the memory node will be described with reference to FIG. 2. Specifically, a driving method of the trimming circuit 100 exemplified in Embodiment 1 will be described. With reference to FIGS. 2(A) and 2(C), a method of setting elements and circuits connected in parallel to the trimming circuit to an unusable state (trimming state) will be described first. The driving method of the trimming circuit 100 exemplified in Embodiment 1 will be described.

[0043] <Example of driving method 1.> First, a method of setting elements and circuits connected in parallel to the trimming circuit to an unusable state (trimming state) will be described with reference to FIGS. 2(A) and 2(C). It will be described using FIGS. 2(A) and 2(C).

[0044] A signal that turns the first transistor 110 on is input to the write terminal 115, and a signal that turns the second transistor 120 off is input to the erase terminal 12 5. As a result, the memory node 150 is connected to the power potential line via the first transistor 110, and charges are accumulated in the memory node 150 connected to the capacitive element 14 0. Also, the third transistor having its gate electrode connected to the memory node 150 is turned on, and a current flows through the third transistor via its source electrode and drain electrode. Note that the above is the first step of driving method example 1 (see Fig. 2(A)). (See Fig. 2(A)). (See Fig. 2(A)).

[0045] Next, a signal that turns the first transistor 110 off is input to the write terminal 115, and a signal that turns the second transistor 120 off is input to the erase terminal 125. As a result, the memory node 150 is electrically disconnected from both the power potential line and the ground potential line, and the charges written in the memory node 150 are retained. Note that the above is the second step of driving method example 1 (see Fig. 2(C)).

[0046] The driving method of the trimming circuit 100 according to one aspect of the present invention described above includes a first step of setting the potential of the memory node 150 to a potential at which the third transistor 130 is turned on, and a second step of turning off the first transistor 110 and the second transistor 120 having their source electrodes or drain electrodes connected to the memory node 15 0. As a result, without changing the structure of any of the elements constituting the trimming circuit 100, more current can be made to flow through the third transistor 13 0. As a result, a driving method for a highly reliable trimming circuit can be provided. (See Fig. 2(C)).

[0047] <Driving method example 2.> Next, we will discuss how to make the elements and circuits connected in parallel to the trimming circuit available. This will be explained with reference to FIG. 2(B) and FIG. 2(C).

[0048] A signal that turns off the first transistor 110 is applied to the write terminal 115 and an erase terminal 12 A signal that turns on the second transistor 120 is input to the storage node 150 is connected to the ground potential line via the second transistor 120, and the storage node 150 is The third transistor, whose gate electrode is connected to the storage node 150, is connected to the ground potential. The transistor is turned off, and the resistor element 1 connected in parallel to its source and drain electrodes A current flows through the transistor 05. The above steps are considered as the first step of the driving method example 2. (See Figure 2(B)).

[0049] Next, a signal that turns off the first transistor 110 is applied to the write terminal 115. A signal that turns off the second transistor 120 is input to the terminal 125. As a result, The memory node 150 is electrically isolated from either the power supply potential line or the ground potential line, and The charge written to the node 150 is held. This step is called step (see Figure 2(C)).

[0050] The driving method of the trimming circuit 100 according to the embodiment of the present invention is to drive the potential of the storage node 150 in a A first step of setting the storage node 15 to a potential at which the transistor 130 of the third transistor is turned off; A first transistor 110 having a source electrode or a drain electrode connected to It has a second step of turning off the transistor 120. As a result, without changing the structure of any element constituting the trimming circuit 100, more current can flow through the resistor element 105 connected in parallel to the source electrode and the drain electrode of the third transistor 13 0. As a result, a highly reliable driving method for the trimming circuit 100 can be provided.

[0051] <Driving Method Example 3.> Next, a method for changing the setting of the trimming circuit 100 in which the trimming state is set using the method described in Driving Method Example 1 or Driving Method Example 2 will be described.

[0052] A signal that turns on the first transistor 110 is input to the write terminal 115, and a signal that turns off the second transistor 120 is input to the erase terminal 12 5, and the potential of the memory node 150 is set to the potential at which the third transistor 130 is turned on (see Fig. 2(A)), or a signal that turns off the first transistor 110 is input to the write terminal 115, and a signal that turns on the second transistor 120 is input to the erase terminal 125. After setting the potential of the memory node 150 to the potential at which the third transistor 130 is turned off (see Fig. 2(B)), the potential of the memory node 150 in which the trimming state is set using the method described in Driving Method Example 1 or Driving Method Example 2 is rewritten. Note that since the steps up to here are carried out after the first step and the second step of any one of the driving methods described in Driving Method Example 1 or Driving Method Example 2, it is the third step of Driving Method Example 3. 150 is rewritten. Note that since the steps up to here are carried out after the first step and the second step of any one of the driving methods described in Driving Method Example 1 or Driving Method Example 2, it is the third step of Driving Method Example 3.

[0053] Next, a signal that turns off the first transistor 110 is input to the write terminal 115, and the erase A signal that turns the second transistor 120 off is input to the terminal 125. As a result, the memory node 150 is electrically disconnected from both the power supply potential line and the ground potential line, and the charge written to the memory node 150 is retained. Note that up to this point is the fourth step of Driving Method Example 3 (see Fig. 2(C)).

[0054] The driving method of the trimming circuit 100 according to one aspect of the present invention includes a third step of setting the potential of the memory node 150 to a potential different from that before driving the trimming circuit 100 using Driving Method Example 3, and a fourth step of turning off the first transistor 110 and the second transistor 120 to which the source electrode or the drain electrode is connected to the memory node 150. As a result, the operating state of the third transistor 130 can be changed without changing the structure of any element constituting the trimming circuit. Consequently, a driving method for the rewritable trimming circuit 100 can be provided.

[0055] <Modification Example> In Driving Method Example 3, a method of changing the operating state of the third transistor 130 has been described. However, a driving method in which the operating state of the third transistor 130 is not changed and a signal is input again to the write terminal 115 and the erase terminal 125 to write data can also be regarded as one aspect of the present invention.

[0056] A trimming circuit according to one aspect of the present invention includes a first transistor 110 and a second transistor 120 having an extremely small off-leakage current, and can retain the charge written to the memory node 150 for a long period of time. Here, while the memory node 150 holds the charge ​​​​​​​​​​By inputting signals to the write terminal 115 and the erase terminal 125 so as to maintain The reliability can be further improved.

[0057] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0058] (Embodiment 3) In this embodiment, the configuration of the trimming circuit according to one aspect of the present invention will be described with reference to FIG. 3. Specifically, the configuration of a trimming circuit including a transistor using a semiconductor other than an oxide semiconductor and a transistor having an oxide semiconductor layer in a channel formation region will be described.

[0059] The configuration of the trimming circuit according to one aspect of the present invention is shown in FIG. 3. FIG. 3(A) is a top view of the trimming circuit 300, FIG. 3(B) is a cross-sectional view taken along the cut line C1-C2 shown in FIG. 3(A), and FIG. 3(C) is a cross-sectional view taken along the cut line D1-D2 shown in FIG. 3(A).

[0060] The trimming circuit 300 illustrated in FIG. 3 includes a first transistor 310, a second transistor 320, and a capacitor element 340 provided via an insulating layer 304 on a substrate 301 on which a third transistor 330 and a resistor element 305 are formed.

[0061] <Configuration of the third transistor and the resistor element> In this embodiment, a case where a semiconductor material other than an oxide semiconductor is applied to the channel formation region of the third transistor 330 will be described. Specifically, a configuration in which a silicon single crystal substrate is used for the substrate 301 and the third transistor 330 is formed on the surface thereof will be described (see FIG. 3(B)).

[0062] In addition, as semiconductor materials other than oxide semiconductors, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used. Further, organic semiconductor materials or the like may be used.

[0063] Also, any semiconductor material may contain an amorphous state or a crystalline state, but using a single crystal semiconductor substrate is preferable because a transistor that can operate at high speed can be fabricated.

[0064] In addition, an SOI substrate or the like can be applied. Generally, the "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor film is provided on an insulating surface. However, in this specification and the like, it also includes a substrate having a configuration in which a semiconductor film made of a material other than silicon is provided on an insulating surface. That is, the semiconductor film included in the "SOI substrate" is not limited to a silicon semiconductor film. Further, the SOI substrate includes those having a configuration in which a semiconductor film is provided via an insulating layer on an insulating substrate such as a glass substrate. substrate" is not limited to a silicon semiconductor film. Further, the SOI substrate includes those having a configuration in which a semiconductor film is provided via an insulating layer on an insulating substrate such as a glass substrate. That is, the SOI substrate includes those having a configuration in which a semiconductor film is provided via an insulating layer on an insulating substrate such as a glass substrate.

[0065] The element isolation insulating layer 302 is provided so as to surround the third transistor 330. The gate electrode 331 of the third transistor 330 is electrically connected to the wiring 332 through an opening provided in the insulating layer 303.

[0066] A bent portion provided in the wiring 335 made of the same conductive layer as the wiring 332 functions as a resistance element 305. And the resistance element 305 is connected in parallel to the source electrode and the drain electrode of the third transistor 330 (see Fig. 3(A)).

[0067] <Configuration of the capacitor element, the first transistor, and the second transistor> The capacitor element 340 is provided with an insulating layer sandwiched between the wiring 341 and the wiring 352, and is formed on the insulating layer 304. Note that the wiring 352 is connected to the wiring 332 through an opening formed in the insulating layer 304 (see Fig. 3(B)).

[0068] The first transistor 310 includes a gate insulating layer 312 between an oxide semiconductor layer 313 formed on the insulating layer 304 and a wiring 311 that functions as a gate electrode. Note that the wiring 311 has an insulating layer provided on its sidewall and is insulated from the wiring 351 and the wiring 352 that function as a source electrode or a drain electrode (see Fig. 3(C)).

[0069] The second transistor 320 includes a gate insulating layer 322 between an oxide semiconductor layer 323 formed on the insulating layer 304 and a wiring 321 that functions as a gate electrode. Note that the wiring 321 has an insulating layer provided on its sidewall and is insulated from the wiring 352 and the wiring 353 that function as a source electrode or a drain electrode (see Fig. 3(C)).

[0070] The trimming circuit exemplified in this embodiment includes a first transistor 310 with an extremely small off-leakage current and a second transistor 320. Specifically, it is a transistor having an oxide semiconductor layer in the channel formation region, and the magnitude of its off-leakage current is 1×10 A or less per 1 μm of channel width. By making the off-leakage current extremely small (for example, 1×10 A or less per 1 μm of channel width), the electric charge written in the memory node can be held for a long period. -17 -17

[0071] In addition, the trimming circuit exemplified in this embodiment includes a transistor including an oxide semiconductor layer. The transistor including the oxide semiconductor layer is provided on a substrate on which a transistor using a semiconductor other than the oxide semiconductor is formed. By adopting such a configuration, for example, a transistor that operates at high speed and a transistor using an oxide semiconductor with reduced off-leakage current can be combined and used. As a result, a trimming circuit that makes use of the advantages of a semiconductor other than the oxide semiconductor and the oxide semiconductor with reduced off-leakage current, and a semiconductor device including the trimming circuit can be provided.

[0072] In addition, the trimming circuit exemplified in this embodiment has a stacked configuration. Specifically, a transistor including an oxide semiconductor layer and a resistor element are provided so as to overlap each other. As a result, the area occupied by the trimming circuit can be reduced. Further, by applying the trimming circuit, the semiconductor device can be miniaturized.

[0073] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0074] (Embodiment 4) In this embodiment, the configuration of a transistor that can be used for the trimming circuit according to one aspect of the present invention will be described. Specifically, the configuration of a transistor including a semiconductor material having a band gap of 2.5 eV or more in a channel formation region will be described. Note that the method for manufacturing the transistor exemplified in this embodiment will be described in Embodiment 5.

[0075] The configuration of the transistor exemplified in this embodiment will be described with reference to FIG. 4(D). FIG. 4(D ) shows a cross-section of the transistor.

[0076] The transistor 710 exemplified in this embodiment includes an underlying insulating layer 704 on a substrate 701 , an oxide semiconductor layer 713, a gate insulating layer 712, a gate electrode 711, a source electrode or electrodes 751 and 752 that function as drain electrodes, and an insulating layer 705 that protects the transistor .

[0077] <Configuration of the underlying insulating layer> The underlying insulating layer 704 has an insulating surface and serves as the underlying layer for the oxide semiconductor layer 7 13 where the channel is formed.

[0078] The underlying insulating layer 704 may be a single-layer structure of a layer containing one or more materials selected from, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, etc., or a laminated structure of two or more layers.

[0079] <Oxide semiconductor layer> The oxide semiconductor layer 713 where the channel is formed overlaps with the gate electrode 711 via the gate insulating layer 712 , and is electrically connected to the electrodes 751 and 752 provided with the gate electrode 711 interposed therebetween. Note that the electrodes 751 and 752 function as source electrodes or drain electrodes .

[0080] The thickness of the oxide semiconductor layer 713 where the channel is formed is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less.

[0081] Note that the oxide semiconductor layer 713 does not have to be processed into an island shape.

[0082] The oxide semiconductor layer 713 is in a state such as single crystal, polycrystal (also referred to as polycrystal), or amorphous. takes the state of.

[0083] Preferably, the oxide semiconductor layer is a CAAC-OS (C Axis Aligned Cr ystalline Oxide Semiconductor) layer.

[0084] As an example of the oxide semiconductor layer having crystallinity, an oxide semiconductor layer having c-axis aligned crystals (CAAC: c-axis aligned crystals) can be mentioned. Note that the details of the oxide semiconductor layer having c axis aligned crystals will be described in Embodiment 7.

[0085] The oxide semiconductor layer 713 preferably has a configuration in which oxygen is contained in excess with respect to its stoichiometric ratio. Acid By making oxygen excessive, generation of carriers due to oxygen deficiency in the metal oxide layer can be suppressed. This can be done.

[0086] The oxide semiconductor layer 713 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn.

[0087] In addition, in order to reduce variations in the electrical characteristics of the transistor using the oxide semiconductor layer, it is preferable to have gallium (Ga) in addition to them. Also, it is preferable to have tin (Sn) as a stabilizer. Also, as a stabilizer it is preferable to have hafnium (Hf). Also, as a stabilizer it is preferable to have aluminum (Al). has it.

[0088] Also, as other stabilizers, any one or more of lanthanoids such as lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu) may be included.

[0089] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides , In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, quaternary metal oxides such as In-Sn-Ga-Zn-based oxides, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used. can exist.

[0090] Here, for example, the In-Ga-Zn-O-based material means an oxide containing indium (In), gallium (G a), and zinc (Zn), and the composition ratio is not limited. Also, metal elements other than In, Ga, and Zn may be included. For example, SiO2 may be included as well.

[0091] Also, as the oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer) The material represented by may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, In2SnO5 (ZnO) (n > 0, and n is an integer) may be used. n (n > 0, and n is an integer) may be used.

[0092] However, it is not limited to these, and a material with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic bond distance, density etc. appropriate. etc. appropriate.

[0093] <Gate insulating layer> The gate insulating layer 712 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, gallium oxide, aluminum oxide, aluminum oxynitride, tantalum oxide, etc. The gate insulating layer 712 can also use a high dielectric constant (high-k) material. As the high dielectric constant material, hafnium oxide, yttrium oxide, lanthanum oxide, hafnium silicate can be used.

[0094] The gate insulating layer 712 can also use a high dielectric constant (high-k) material. As the high dielectric constant material, hafnium oxide, yttrium oxide, lanthanum oxide, hafnium silicate can be used. As the high dielectric constant material, hafnium oxide, yttrium oxide, lanthanum oxide, hafnium silicate (HfSi x O y (x>0, y>0)), hafnium aluminate (HfAl x O y (x >0, y>0)), hafnium silicate doped with nitrogen (HfSi x O y N z (x> 0, y>0, z>0)), hafnium aluminate doped with nitrogen (HfAl x O y N z (x>0, y>0, z>0)) and the like can be cited as examples.

[0095] The gate insulating layer 712 may have a single-layer structure or a stacked structure. For example, it may be a stacked structure of a layer containing a high -k material and a layer containing a material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and the like.

[0096] If the thickness of the gate insulating layer 712 is reduced or the above-mentioned high-k material is used, the transistor can be miniaturized without degrading the operating characteristics. For example, when using silicon oxide, it can be set to be 1 nm or more and 100 nm or less, preferably 10 n

[0097] m or more and 50 nm or less. On the other hand, when using a high-k material, the transistor can be miniaturized without making the thickness so thin that gate leakage occurs due to the tunneling effect or the like.

[0098] In addition, an insulating material containing a Group 13 element and oxygen can be applied to the gate insulating layer 712. In addition, the insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements.

[0099] ​​means.

[0100] For example, gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. can be cited as an example of an insulating material containing Group 13 elements and oxygen. Here, aluminum gallium oxide refers to the one with a higher content (atomic %) of aluminum than that of gallium, and gallium aluminum oxide refers to the one with a content (atomic %) of gallium equal to or higher than the content (atomic %) of aluminum. (atomic %) of gallium equal to or higher than the content (atomic %) of aluminum.

[0101] Many oxide semiconductor materials contain Group 13 elements, and the insulating materials containing Group 13 elements are compatible with oxide semiconductor materials. Therefore, by using an insulating material containing Group 13 elements and oxygen for the insulating layer in contact with the oxide semiconductor layer, the state of the interface with the oxide semiconductor layer can be kept good. (atomic %) of gallium equal to or higher than the content (atomic %) of aluminum.

[0102] For example, when forming a gate insulating layer in contact with an oxide semiconductor layer containing gallium, by using a material containing gallium oxide for the gate insulating layer, the interface characteristics between the oxide semiconductor layer and the gate insulating layer can be kept good. (atomic %) of gallium equal to or higher than the content (atomic %) of aluminum.

[0103] Also, by providing an oxide semiconductor layer in contact with an insulating layer containing gallium oxide, the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating layer can be reduced.

[0104] For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Note that since aluminum oxide has the property of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor layer.

[0105] Thus, when an element belonging to the same group as the component element of the oxide semiconductor is used for the insulating layer, a similar effect can be obtained.

[0106] <Gate electrode> The gate electrode 711 overlaps with the oxide semiconductor layer 713 via the gate insulating layer 712 and functions as the gate electrode of the transistor 710.

[0107] The gate electrode 711 may have a single-layer structure of a layer containing a conductive material or a laminated structure of two or more layers. It may be.

[0108] The conductive material may be any material that can withstand the heat treatment process. For example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used, or an alloy containing one selected from these can be used. It can be used.

[0109] In addition, a semiconductor layer typified by a polycrystalline silicon layer doped with impurity elements such as phosphorus, a silicide layer such as nickel silicide may be used.

[0110] <Insulating layer on gate electrode and sidewall> The insulating layer 714a on the gate electrode overlaps with the gate electrode 711 and has insulating properties.

[0111] The sidewall 714b is in contact with the side surface of the laminate of the gate insulating layer 712, the gate electrode 711, and the insulating layer 714a on the gate electrode and has an insulating layer.

[0112] <Source electrode and drain electrode> Either the electrode 751 or the electrode 752 is electrically connected to the oxide semiconductor layer 713 and functions as the source electrode and the drain electrode of the transistor.

[0113] The electrode functioning as the source electrode or the drain electrode has a single-layer structure containing a conductive material. Alternatively, it may have a laminated structure of two or more layers.

[0114] The conductive material may be any material that can withstand the heat treatment process, such as aluminum, chromium, copper, etc. a metal selected from the group consisting of titanium, tantalum, molybdenum and tungsten, or In addition, an alloy containing one selected from the group consisting of manganese, magnesium, diamine, and tin can be used. A metal selected from the group consisting of zinc, beryllium, neodymium and scandium, or An alloy containing one selected from these may also be used.

[0115] The conductive material may be a metal nitride. Specifically, titanium nitride, molybdenum nitride, etc. Examples include butene and tungsten nitride.

[0116] The conductive material may be a conductive metal oxide. tin oxide, indium tin oxide (also known as ITO), indium zinc oxide, Zinc oxide, zinc oxide doped with gallium or aluminum, or these metal oxides For example, a material containing silicon oxide can be used.

[0117] In addition, graphene or the like can be used as the conductive material.

[0118] For example, a single layer structure made of titanium or titanium nitride, or a single layer structure of aluminum containing silicon , a two-layer structure with a titanium layer laminated on an aluminum layer, and a titanium layer laminated on a titanium nitride layer Examples include a two-layer structure with a titanium layer, an aluminum layer, and a three-layer structure with a titanium layer, an aluminum layer, and a titanium layer. Can be obtained.

[0119] Note that the channel length (L) of the transistor is determined by the distance between the end of the source electrode in contact with the oxide semiconductor layer and the end of the drain electrode in contact with the oxide semiconductor layer.

[0120] <Insulating layer for protecting the transistor> The insulating layer 705 for protecting the transistor prevents the intrusion of impurities such as moisture from the outside and is a layer for protecting the transistor.

[0121] The thickness of the insulating layer 705 shall be at least 1 nm or more.

[0122] The insulating layer 705 may have a single-layer structure of a layer containing an insulator having a barrier property or a laminated structure of two or more layers.

[0123] In particular, a configuration containing aluminum oxide is preferable, and a laminated structure of an aluminum oxide layer and a layer containing another inorganic insulating material may be used. This is because aluminum oxide hardly permeates moisture, oxygen, and other impurities.

[0124] Further, the insulating layer 705 may be a laminate of an oxide insulating layer having an oxygen-excess region and an aluminum oxide layer, and may be configured such that an oxide insulating layer having an oxygen-excess region is provided on the oxide semiconductor layer side.

[0125] The oxide insulating layer having an oxygen-excess region can be formed of, for example, a silicon oxide film, a silicon oxynitride film, or the like.

[0126] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0127] (Embodiment 5) In this embodiment, the semiconductor material having a band gap of 2.5 eV or more described in Embodiment 4​​​​​​​​​ A method for manufacturing a transistor 710 having a material in a channel formation region will be described with reference to FIG. 4. Explain.

[0128] <Formation of an insulating layer as a base> First, an insulating layer 704 serving as a base for an oxide semiconductor layer in which a channel is to be formed is formed. The insulating layer 704 serving as a base is formed on the substrate 701 by a plasma CVD method, a sputtering method, or the like. Form.

[0129] The substrate 701 may have heat resistance sufficient to withstand the processing in the steps after the step of forming the insulating layer serving as a base, and there is no limitation on its size. Have heat resistance, and there is no limit to its size.

[0130] Other semiconductor elements may be provided on the substrate 701 in advance.

[0131] As the substrate 701, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Of glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can also be applied. Of compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied.

[0132] As the substrate 701, a flexible substrate may be used. A transistor may be directly manufactured on the flexible substrate, or a transistor may be manufactured on another manufacturing substrate and then peeled and transferred to the flexible substrate. When peeling and transferring from the manufacturing substrate to the flexible substrate, it is advisable to provide a peeling layer between the manufacturing substrate and the transistor including the oxide semiconductor layer. A transistor may be directly fabricated on the flexible substrate, or a transistor may be fabricated on another fabrication substrate and then peeled and transferred to the flexible substrate. Separated and transferred, it may also be possible. When peeling and transferring from the manufacturing substrate to the flexible substrate, a peeling layer is provided between the manufacturing substrate and the transistor including the oxide semiconductor layer. And a transistor including an oxide semiconductor layer.

[0133] <Formation of an oxide semiconductor layer> Next, an oxide semiconductor layer 713 in which a channel is to be formed is formed on the insulating layer 704 serving as a base. It is.

[0134] The oxide semiconductor layer can be formed by sputtering, molecular beam epitaxy, atomic layer deposition, or pulsed laser deposition.

[0135] For example, when using an In-Ga-Zn-O-based material as the oxide semiconductor, it can be fabricated using a target. Various materials and composition ratios of the target can be used. For example, an oxide target containing In2O3, Ga2O3, and ZnO in a ratio of 1:1:1 [mole ratio] (=In2O3:Ga2O3:ZnO) can be used. Also, for example, an oxide target containing In2O3, Ga2O3, and ZnO in a ratio of 1:1:2 [mole ratio] (= In2O3:Ga2O3:ZnO) can also be used. .

[0136] Also, when using an In-Zn-O-based material as the oxide semiconductor, the atomic ratio of the metal elements in the target used is In:Zn = 50:1 to 1:2 (converted to mole ratio is In2O 3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to mole ratio is In2O3:ZnO = 10:1 to 1:2), more preferably In:Zn = 15:1 to 1.5:1 (converted to mole ratio is In2O3:ZnO = 15:2 to 3:4) . For example, for the target used to form the In-Zn-O-based oxide semiconductor, when the atomic ratio is In:Zn:O = X:Y:Z, then Z > 1.5X + Y.

[0137] Also, for example, when using an In-Sn-Zn-O-based material as the oxide semiconductor, it can be fabricated using a target. The composition ratio of the target can use various ones. It is possible. For example, an oxide target containing In, Sn, and Zn in an atomic ratio of 1:2:2 (= In:Sn:Zn) can be used. Also, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 2:1:3 (= In:Sn:Zn) can be used. Also, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 1:1:1 (= In:Sn :Zn) can be used. Also, for example, an oxide target containing In, S n, and Zn in an atomic ratio of 20:45:35 (= In:Sn:Zn) can be used. The relative density of the target is 90% or more and 100% or less, preferably 95% or more and 99.9

[0138] % or less. By using a target with a high relative density, the formed oxide semiconductor layer can be made into a dense film.

[0139] Also, the oxide semiconductor layer can reduce the carrier density and be substantially of type I. The details of the method will be described in Embodiment 6.

[0140] Next, a resist mask is formed by a photolithography process, and using the resist mask, the oxide semiconductor layer is selectively etched to form it into an island shape (see Fig. 4(A)).

[0141] When etching while retracting the resist mask, the oxide semiconductor layer can be made into a tapered shape. Making the island-shaped oxide semiconductor layer into a tapered shape can prevent disconnection of the layers formed after this step and improve the coverage.

[0142] <Formation of Gate Insulating Layer, Gate Electrode, and Insulating Layer on Gate Electrode> Next, a laminate of the gate insulating layer 712, the gate electrode 711, and the insulating layer 714a on the gate electrode is formed on the oxide semiconductor layer 713.

[0143] The insulating layer serving as the gate insulating layer and the insulating layer serving as the insulating layer on the gate electrode are formed by a method such as plasma CVD or sputtering.

[0144] The conductive layer serving as the gate electrode is formed by a method such as sputtering.

[0145] Next, a resist mask is formed by a photolithography process, and using the resist mask, the insulating layer serving as the gate insulating layer, the conductive layer serving as the gate electrode, and the insulating layer serving as the insulating layer on the gate electrode are etched to form a laminate of the gate insulating layer 712, the gate electrode 711, and the insulating layer 714a on the gate electrode.

[0146] <Formation of sidewalls> Next, sidewalls 714b are formed in contact with the side surfaces of the laminate of the gate insulating layer 712, the gate electrode 711, and the insulating layer 714a on the gate electrode.

[0147] The insulating layer serving as the sidewalls is formed by a method such as plasma CVD or sputtering.

[0148] Next, anisotropic etching is performed to form sidewalls while leaving the insulating layer in contact with the side surfaces of the laminate (see FIG. 4(B)).

[0149] <Formation of electrodes functioning as source electrodes or drain electrodes> Next, electrodes 751 and 752 that function as source electrodes or drain electrodes are formed.

[0150] The layer containing the conductive material serving as the source electrode or drain electrode is formed by a method such as sputtering. to form a film.

[0151] Next, a resist mask is formed by a photolithography process, and using this resist mask a layer containing a conductive material is selectively etched to form electrodes 751 and 752 (see Fig. 4(C)). Wiring etc. (not shown) made of a layer containing the same conductive material is also formed in the same process .

[0152] In addition, when forming a transistor with a channel length (L) of 10 nm or more and 1000 nm (1 μm) or less, particularly less than 25 nm it is preferable to form a mask using extreme ultraviolet rays with a wavelength of several nm to several tens of nm. This is because when using extreme ultraviolet rays the resolution is high and the depth of focus is also large.

[0153] It is also preferable to form an electrode that functions as a source electrode or a drain electrode in a tapered shape. When an electrode that functions as a source electrode or a drain electrode is in a tapered shape, it is possible to prevent breakage of a layer (for example, a gate insulating layer) formed after this process and improve the coating property. The taper angle is preferably, for example, 30° or more and 60° or less.

[0154] In addition, when the layer containing the conductive material has a single-layer structure such as a titanium layer or a titanium nitride layer, it is easy to process it into source electrodes and drain electrodes having a tapered shape.

[0155] <Formation of an insulating layer for protecting the transistor> Next, an insulating layer 705 for protecting the transistor is formed.

[0156] The insulating layer for protecting the transistor is formed by film deposition using a plasma CVD method, a sputtering method, or the like. .

[0157] By the above process, a transistor 710 using an oxide semiconductor material in the region where the channel is formed can be fabricated.

[0158] Note that the resist mask used in this embodiment is not limited to being formed by a photolithography process. In addition to the photolithography method, it can be formed by appropriately using an inkjet method, a printing method, etc. When a resist mask is formed without using a photomask, the manufacturing cost of the semiconductor device can be reduced.

[0159] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0160] (Embodiment 6) In this embodiment, a method for forming an oxide semiconductor layer applicable to a transistor having an extremely small off-leakage current (for example, 1 × 10 A or less per 1 μm channel width) that can be used in a trimming circuit according to one aspect of the present invention will be described. Specifically, a method for fabricating an oxide semiconductor layer with a reduced carrier density and substantially a type-I oxide semiconductor layer will be described with reference to FIG. 5. -17

[0161] <Configuration of the underlying insulating layer and method for manufacturing the same> At least the region of the insulating layer 504 underlying the oxide semiconductor layer where the channel is formed preferably includes an insulating layer from which oxygen desorbs by heat treatment. This is because when the insulating layer 504 has an oxygen-excess region, the phenomenon of oxygen moving from the oxide semiconductor layer to the insulating layer 504 can be prevented, and by performing a heat treatment described later, oxygen can be supplied from the insulating layer 504 to the oxide semiconductor layer. ​

[0162] When the underlying insulating layer has a laminated structure, it is more preferable to provide an oxide insulating layer having an oxygen-excess region on the side of the oxide semiconductor layer. On the side of the oxide semiconductor layer

[0163] For example, it is preferable that the underlying insulating layer has a laminated structure of a silicon oxide layer having an oxygen-excess region and an aluminum oxide layer from the side of the oxide semiconductor layer. On the side of the oxide semiconductor layer

[0164] In this specification and the like, "oxygen is desorbed by heat treatment" means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount (or release amount) of oxygen converted into oxygen atoms is 1.0 × 10 cm or more, preferably 3.0 × 10 18 cm -3 or more. Also, "oxygen is not desorbed by heat treatment" means that in TDS analysis, the desorption amount (or release amount) of oxygen converted into oxygen atoms is less than 1.0 × 10 cm 20 cm -3 or less. As a method for producing an insulating layer from which oxygen is desorbed by heat treatment, a method of forming a film in an oxygen atmosphere or a method of injecting oxygen (including at least any one of oxygen radicals, oxygen atoms, or oxygen ions) after film formation can be mentioned. cm 18 cm -3 or less.

[0165] As a method for injecting oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used. After film formation Including any one of oxygen radicals, oxygen atoms, or oxygen ions

[0166] <Method 1 for forming an oxide semiconductor layer with reduced impurity concentration: Film formation method> Method, plasma immersion ion implantation method, plasma treatment, etc. can be used.

[0167] <Method 1 for forming an oxide semiconductor layer with reduced impurity concentration: Film formation method> Form an oxide semiconductor layer 413a on an underlying insulating layer 504 (see Fig. 5(A)). Since the oxide semiconductor layer 413a will be the oxide semiconductor layer where a channel is to be formed later, impurities containing hydrogen atoms are formed so as to exclude them as much as possible. This is because impurities containing hydrogen atoms are likely to form donor levels in the oxide semiconductor layer.

[0168] As a method for producing an oxide semiconductor layer with reduced impurities containing hydrogen atoms, it is preferable to form a film using a sputtering method. In particular, it is preferable to use an insulating layer not exposed to the atmosphere as a base and continuously form an oxide semiconductor layer on the insulating layer.

[0169] For example, after removing impurities containing hydrogen adhering to the substrate surface by heat treatment or plasma treatment, form an underlying insulating layer without exposing it to the atmosphere, and then continuously form an oxide semiconductor layer without exposing it to the atmosphere. By doing so, impurities containing hydrogen adhering to the surface of the underlying insulating layer can be reduced, and the phenomenon of atmospheric components adhering to the interface between the substrate and the underlying insulating layer and the interface between the underlying insulating layer and the oxide semiconductor layer can be suppressed.

[0170] Before forming the oxide semiconductor layer using the sputtering method, it is preferable to perform reverse sputtering in which argon gas is introduced into the processing chamber to generate plasma to remove powdery substances (also called particles or dust) adhering to the surface of the underlying insulating layer.

[0171] Reverse sputtering is a method of modifying the surface by forming plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side. ​​​​​​​​​​​Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0172] Also, a method of forming the oxide semiconductor layer using a processing chamber with a low leak rate is preferable. Specifically, by setting the leak rate of the processing chamber of the sputtering apparatus to 1×10 -10 Pa·m 3 / second or less, it is possible to reduce the incorporation of impurities such as alkali metals and hydrides into the oxide semiconductor layer during film formation.

[0173] Also, a method of forming the oxide semiconductor layer in a processing chamber of a sputtering apparatus evacuated using an adsorption type vacuum pump (for example, a cryopump) is preferable. It is possible to reduce the backflow of impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides from the exhaust system.

[0174] Also, a method of forming the oxide semiconductor layer by supplying a high-purity atmosphere gas into the processing chamber of the sputtering apparatus is preferable. Specifically, a high-purity rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen from which impurities such as water, a compound containing a hydroxyl group, or a hydride have been removed is appropriately used.

[0175] For example, the purity of argon is 9N (99.9999999%) or higher (H2O is 0.1p pb, H2 is 0.5 ppb), and the dew point is -121°C. Also, the purity of oxygen is 8N (99.999999%) or higher (H2O is 1 ppb, H2 is 1 ppb), and the dew point is - 112°C.

[0176] Also, when using a mixed gas of a rare gas and oxygen, it is preferable to increase the flow rate ratio of oxygen. ​

[0177] <An example of the film formation conditions for the oxide semiconductor layer.> As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa , and the conditions under an atmosphere of a DC (direct current) power supply of 0.5 kW and oxygen (oxygen flow rate ratio 100%) are applicable . Note that when using a pulsed DC power supply, it is preferable because dust generated during film formation can be reduced and the film thickness distribution becomes uniform .

[0178] <Method for forming an oxide semiconductor layer with reduced impurity concentration 2: First heat treatment> Form an oxide semiconductor layer 413b in which impurities containing hydrogen atoms are excluded as much as possible (see Fig. 5(B)) .

[0179] As a method for producing an oxide semiconductor layer in which impurities containing hydrogen atoms are reduced, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor layer (also referred to as dehydration or dehydrogenation) , a method of performing a first heat treatment on the oxide semiconductor layer is preferable .

[0180] When performing the first heat treatment, it is preferable to use an insulating layer in contact with the oxide semiconductor layer, which is an insulating layer from which oxygen desorbs by the heat treatment . This is because when the first heat treatment is performed, oxygen is also released from the oxide semiconductor layer together with impurities containing hydrogen atoms . A part of the oxygen vacancies generated in the oxide semiconductor layer from which oxygen is released becomes donors, and carriers may be generated in the oxide semiconductor layer, which may affect the characteristics of the transistor .

[0181] The temperature of the first heat treatment is, for example, 150°C or higher and lower than the substrate distortion point temperature, preferably 250°C or higher and 450°C or lower, and more preferably 300°C or higher and 450°C or lower

[0182] ​The time of the first heat treatment shall be from 3 minutes to 24 hours. Heat treatment exceeding 24 hours is not preferable as it will lead to a decrease in productivity.

[0183] The first heat treatment is carried out in an oxidizing atmosphere or an inert atmosphere. Here, the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or nitrogen oxide. Also, the inert atmosphere refers to an atmosphere in which the aforementioned oxidizing gas is less than 10 ppm and the rest is filled with nitrogen or a rare gas.

[0184] For example, under a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an atmosphere of ultra-dry air (with a moisture content of 20 ppm (dew point conversion of -55 °C) or less, preferably 1 ppm or less, more preferably 10 ppb or less as measured using a dew point meter of the CRDS (Cavity Ring Down Laser Spectroscopy) method).

[0185] Also, it is preferable that nitrogen or a rare gas such as helium, neon, or argon does not contain water, hydrogen, etc. Or, the purity of the nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.999 99%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0186] The heating device used for the first heat treatment is not particularly limited. The heating device may be equipped with a device for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element.

[0187] For example, an electric furnace or an LRTA (Lamp Rapid Thermal Anneali ​​​​​​​​​ng) apparatus, GRTA (Gas Rapid Thermal Annealing) apparatus, etc. It is possible to use an RTA (Rapid Thermal Annealing) apparatus such as an LRTA apparatus. The LRTA apparatus is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is a device that performs heat treatment using a high-temperature gas.

[0188] By performing the above-described first heat treatment, hydrogen (a compound containing water and hydroxyl groups) can be released from the oxide semiconductor layer. Also, impurities are reduced by the first heat treatment, and an i-type (intrinsic) or substantially i-type oxide semiconductor layer

[0189] can be formed. By desorbing hydrogen, which is an unstable carrier source, from the oxide semiconductor layer by the first heat treatment, it is possible to suppress the phenomenon in which the threshold voltage of the

[0190] transistor fluctuates in the negative direction. Furthermore, the reliability of the transistor can be improved. <Modification Example> After the first heat treatment, oxygen (including at least any one of oxygen

[0191] radicals, oxygen atoms, or oxygen ions) may be implanted into the oxide semiconductor layer. As a method for implanting oxygen, an ion implantation method, an ion doping method, a plasma immersion

[0192] <Configuration and Fabrication Method of Gate Insulating Layer> At least an oxide of the gate insulating layer 512 covering the oxide semiconductor layer 513 in which a The region in contact with the oxide semiconductor layer preferably has a structure including an insulating layer from which oxygen is desorbed by heat treatment. This is because when the gate insulating layer 512 has an oxygen-excess region, the phenomenon of oxygen moving from the oxide semiconductor layer 513 to the gate insulating layer 512 can be prevented, and by performing a second heat treatment to be described later, oxygen can be supplied from the gate insulating layer 512 to the oxide semiconductor layer 513. This is the reason.

[0193] When the insulating layer covering the oxide semiconductor layer in which the channel is formed has a laminated structure, a configuration in which an oxide insulating layer having an oxygen-excess region is provided on the oxide semiconductor layer side is more preferable.

[0194] For example, the insulating layer covering the oxide semiconductor layer in which the channel is formed preferably has a laminated structure of a silicon oxide layer having an oxygen-excess region and an aluminum oxide layer from the oxide semiconductor layer side.

[0195] The aluminum oxide layer has an effect of not permeating impurities such as hydrogen and moisture, and both oxygen, in other words, a high blocking effect. By performing a second heat treatment after forming the aluminum oxide layer, the release of oxygen from the oxide semiconductor layer can be prevented.

[0196] <Formation of Gate Insulating Layer, Gate Electrode, and Insulating Layer on Gate Electrode> Next, a laminate of the gate insulating layer 512, the gate electrode 511, and the insulating layer 514a on the gate electrode is formed on the oxide semiconductor layer 513.

[0197] The insulating layer serving as the gate insulating layer and the insulating layer serving as the insulating layer on the gate electrode are formed by a film formation method such as plasma CVD method or sputtering method.

[0198] ​​​​​​The conductive layer serving as the gate electrode is formed by a sputtering method or the like.

[0199] Next, a resist mask is formed by a photolithography process, and using the resist mask, the insulating layer serving as the gate insulating layer, the conductive layer serving as the gate electrode, and the insulating layer on the gate electrode are etched to form a laminate of the gate insulating layer 512, the gate electrode 511, and the insulating layer 514a on the gate electrode.

[0200] <Formation of sidewalls> Next, the insulating layer 514b is formed in contact with the sidewalls of the laminate of the gate insulating layer 512, the gate electrode 511, and the insulating layer 514a on the gate electrode.

[0201] The insulating layer serving as the sidewall is formed by a plasma CVD method, a sputtering method, or the like.

[0202] Next, anisotropic etching is performed to form sidewalls while leaving the insulating layer in contact with the side surfaces of the laminate.

[0203] <Method for manufacturing an oxide semiconductor layer supplied with oxygen 1: Second heat treatment> The oxide semiconductor layer 513 in which a channel is formed is preferably an oxide semiconductor layer supplied with oxygen. In particular, an oxide semiconductor layer in which oxygen deficiency is compensated is preferable. This is because a part of the oxygen deficiency becomes a donor and carriers are generated in the oxide semiconductor layer, which may affect the characteristics of the transistor.

[0204] As a method for manufacturing an oxide semiconductor layer supplied with oxygen, a method of performing a second heat treatment in a state where an insulating layer from which oxygen is desorbed by heat treatment and the oxide semiconductor layer in which a channel is formed are in contact can be mentioned. Specifically, using an insulating layer from which oxygen is desorbed by heat treatment as a base, ​​​​​ An insulating layer covering a region where an edge layer and / or a channel is formed is formed, and a second heat treatment is performed to supply oxygen to the oxide semiconductor layer (see FIG. 5(C)).

[0205] Note that the second heat treatment may be performed after any process as long as an insulating layer including an insulating layer from which oxygen desorbs by heat treatment is formed in contact with a region where a channel of the oxide semiconductor layer is formed. Even if it is after any process, an effect can be obtained.

[0206] In particular, a laminated structure of a silicon oxide layer having an oxygen-excess region and an aluminum oxide layer having a high blocking effect (blocking effect) is formed from the oxide semiconductor layer side, and a method of performing the second heat treatment in a state where the aluminum oxide layer is formed is preferable.

[0207] The second heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, etc.). However, it is preferable that the atmosphere of nitrogen, oxygen, ultra-dry air, or rare gas does not contain water, hydrogen, etc. Further, the purity of nitrogen, oxygen, or rare gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, preferably 7N (99.99 999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0208] 《Method for measuring the amount of desorbed oxygen converted to oxygen atoms.》 Hereinafter, a method for quantifying the amount of oxygen released by converting it to oxygen atoms by TDS analysis will be described.

[0209] The amount of gas desorbed during TDS analysis is proportional to the integral value of the spectrum. Therefore, the insulating The desorption amount of the gas can be calculated based on the integrated value of the spectrum of the layer and the ratio to the reference value of the standard sample. This can be done. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of a sample containing a predetermined atom.

[0210] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating layer, the desorption amount (N ) of oxygen molecules in the insulating layer can be obtained by Equation 1. Here, it is assumed that all of the spectrum detected at mass number 32 obtained by TDS analysis is derived from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as the possibility of its existence is low. Also, for oxygen molecules containing oxygen atoms with mass numbers 17 and 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely small. O2

[0211] N O2 = N H2 / S H2 × S O2 × α (Equation 1)

[0212] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integrated value of the spectrum when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is taken as N H2 / S H2 O2 S is the integrated value of the spectrum when the insulating layer is subjected to TDS analysis. α is a coefficient that affects the spectrum intensity in TDS analysis. For details of Equation 1, reference can be made to Japanese Patent Laid-Open No. 6-275697. Note that the numerical values of the desorption amount of oxygen described above ​​​​​​​Using the temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd., the values were measured using a silicon wafer containing 1×10 as a standard sample. 16 cm -3 of hydrogen atoms. There are.

[0213] In addition, in TDS analysis, a part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the desorption amount of oxygen molecules, the desorption amount of oxygen atoms can also be estimated. Furthermore, since the above α includes the ionization rate of oxygen molecules, by evaluating the desorption amount of oxygen molecules, the desorption amount of oxygen atoms can also be estimated. Since the above α includes the ionization rate of oxygen molecules, by evaluating the desorption amount of oxygen molecules, the desorption amount of oxygen atoms can also be estimated. can be estimated.

[0214] Note that NO2 is the desorption amount of oxygen molecules. In the insulating layer, the desorption amount of oxygen in terms of oxygen atoms is twice the desorption amount of oxygen molecules. The desorption amount of oxygen is twice the desorption amount of oxygen molecules.

[0215] As an example of a layer from which oxygen desorbs by heat treatment, there is silicon oxide (SiOx (x > 2)) with excess oxygen. Silicon oxide with excess oxygen (SiOx (x> 2)) means that it contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method. contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

[0216] <Formation of an electrode that functions as a source electrode or a drain electrode> Next, electrodes 551 and 552 that function as a source electrode or a drain electrode are formed. .

[0217] A layer containing a conductive material that becomes a source electrode or a drain electrode is formed by a sputtering method or the like. is formed.

[0218] Next, a resist mask is formed by a photolithography process, and using this resist mask, a layer containing a conductive material is selectively etched to form electrode 551 and electrode 552. Also, wiring or the like (not shown) made of the same layer containing a conductive material is formed in the same process.

[0219] In addition, when forming a transistor with a channel length (L) of 10 nm or more and 1000 nm (1 μm) or less, particularly less than 25 nm, it is preferable to form a mask using extreme ultraviolet light with a wavelength of several nm to several tens of nm. This is because when using extreme ultraviolet light, the resolution is high and the depth of focus is large.

[0220] In addition, it is preferable to form an electrode that functions as a source electrode or a drain electrode in a tapered shape. When an electrode that functions as a source electrode or a drain electrode is formed in a tapered shape, it is possible to prevent disconnection of a layer (for example, a gate insulating layer) formed after this step and improve the coverage. The taper angle is preferably, for example, 30° or more and 60° or less.

[0221] In addition, when the layer containing a conductive material has a single-layer structure such as a titanium layer or a titanium nitride layer, it is easy to process the source electrode and the drain electrode having a tapered shape.

[0222] <Formation of an insulating layer for protecting the transistor> Next, an insulating layer 505 for protecting the transistor is formed.

[0223] The insulating layer for protecting the transistor is formed by film deposition using a plasma CVD method, a sputtering method, or the like (see FIG. 5(D)).

[0224] As described above, since the generation of carriers in the oxide semiconductor layer in which the channel is formed can be suppressed,​​​​​​​ It is possible to suppress variations in the characteristics of the transistor.

[0225] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0226] (Embodiment 7) In this embodiment, an oxide semiconductor layer applicable to a trimming circuit according to one aspect of the present invention and having an extremely small off-leak current (for example, 1 × 10 A or less per 1 μm of channel width) will be described for the transistor. Specifically, an oxide semiconductor layer having a c-axis oriented crystal will be described. -17 A or less) for the transistor. A description will be given of an oxide semiconductor layer applicable to a transistor. Specifically, an oxide semiconductor layer having a c-axis oriented crystal will be described. A description will be given of an oxide semiconductor layer having a c-axis oriented crystal.

[0227] In this embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers on the c-axis or metal atoms and oxygen atoms are arranged in layers, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described. In this embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers on the c-axis or metal atoms and oxygen atoms are arranged in layers, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described. In this embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers on the c-axis or metal atoms and oxygen atoms are arranged in layers, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described. In this embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers on the c-axis or metal atoms and oxygen atoms are arranged in layers, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described. In this embodiment, an oxide containing a crystal (also referred to as CAAC: C Axis Aligned Crystal) that is c-axis oriented and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in which metal atoms are arranged in layers on the c-axis or metal atoms and oxygen atoms are arranged in layers, and the directions of the a-axis or b-axis are different (rotated around the c-axis as the center) in the ab-plane will be described.

[0228] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous material. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed-phase structure having a crystal part and an amorphous part in an amorphous phase. Note that the crystal part often has a size that can be accommodated within a cube having a side length of less than 100 nm. In an observation image obtained by a transmission electron microscope (TEM: Transmission Electro n Microscope), the boundary between the amorphous part and the crystal part contained in the CAAC-OS film is not clear. Also, no grain boundaries (grain Also referred to as an in-boundary. ) cannot be confirmed. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is suppressed.

[0229] The crystal portions included in the CAAC-OS film have their c-axes aligned in a direction parallel to the normal vector of the film formation surface of the CAAC-OS film or the normal vector of the surface, and have a trigonal shape or a hexagonal atomic arrangement when viewed from a direction perpendicular to the ab-plane, and when viewed from a direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and b-axis may be different between different crystal portions. In this specification, when simply described as perpendicular, the range of 8 5° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5 ° or more and 5° or less is also included.

[0230] Note that in the CAAC-OS film, the distribution of crystal portions does not have to be uniform. For example, in the process of forming the CAAC- OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal portions may be higher near the surface than near the film formation surface. Also, by adding impurities to the CAAC- OS film, the crystal portions may become amorphous in the impurity addition region.

[0231] Since the c-axes of the crystal portions included in the CAAC-OS film are aligned in a direction parallel to the normal vector of the film formation surface of the CAAC-OS film or the normal vector of the surface, depending on the shape of the CAAC-OS film (the cross-sectional shape of the film formation surface or the cross-sectional shape of the surface), they may face different directions from each other. Note that the direction of the c-axis of the crystal portions is the normal vector of the film formation surface when the CAAC-OS film is formed. Also, the direction of the c-axis of the crystal portions is the normal vector of the film formation surface when the CAAC-OS film is formed. It is in a direction parallel to the normal vector of the groove or surface. The crystal part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. It is formed by performing a crystallization treatment such as heat treatment after film formation.

[0232] A transistor using a CAAC-OS film can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability. A transistor using a CAAC-OS film can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0233] An oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab plane, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, it includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. An oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab plane, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, it includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. An oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab plane, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, it includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. An oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab plane, it has an atomic arrangement of a triangle, a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, it includes a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers.

[0234] CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CAAC contains crystallized parts (crystal parts), but in some cases, the boundaries between one crystal part and another cannot be clearly distinguished. CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CAAC contains crystallized parts (crystal parts), but in some cases, the boundaries between one crystal part and another cannot be clearly distinguished. CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CAAC contains crystallized parts (crystal parts), but in some cases, the boundaries between one crystal part and another cannot be clearly distinguished.

[0235] When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystal parts constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab planes of the individual crystal parts constituting CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystal parts constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab planes of the individual crystal parts constituting CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystal parts constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab planes of the individual crystal parts constituting CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystal parts constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab planes of the individual crystal parts constituting CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystal parts constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.). Or, the normal vectors of the ab planes of the individual crystal parts constituting CAAC may be oriented in a certain direction (for example, a direction perpendicular to the substrate surface on which CAAC is formed, the surface of CAAC, etc.).

[0236] Depending on its composition, etc., CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition, etc., it can be transparent or opaque to visible light. Depending on its composition, etc., CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition, etc., it can be transparent or opaque to visible light. Depending on its composition, etc., CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition, etc., it can be transparent or opaque to visible light.

[0237] As an example of such a CAAC, when observed from a direction perpendicular to the film surface or the surface of the supporting substrate, which is formed in a film shape, an atomic arrangement of a triangle or a hexagon is recognized, and when the film cross-section is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) can also be cited as a crystal. is recognized. A crystal in which a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized will be described in detail with reference to FIGS. 6 to 8 as an example of the crystal structure included in CAAC. Note that, unless otherwise specified, in FIGS. 6 to 8, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab-plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab-plane. In FIG. 6, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms.

[0238] A detailed description will be given of an example of the crystal structure included in CAAC with reference to FIGS. 6 to 8. Note that, unless otherwise specified, in FIGS. 6 to 8, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab-plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab-plane. Also, in FIG. 6, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms. the ab-plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab-plane. Also, in FIG. 6, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms. When simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab-plane. Also, in FIG. 6, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms. In FIG. 6, the O atoms surrounded by circles indicate 4-coordinate O atoms, and the O atoms surrounded by double circles indicate 3-coordinate O atoms.

[0239] FIG. 6(A) shows a structure having one 6-coordinate In atom and six 4-coordinate oxygen atoms (hereinafter referred to as 4-coordinate O atoms) adjacent to the In atom. Here, the structure showing only the adjacent oxygen atoms with respect to one metal atom is called a small group. The structure of FIG. 6(A) has an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(A). The small group shown in FIG. 6(A) has a charge of 0. Here, the structure showing only the adjacent oxygen atoms with respect to one metal atom is called a small group. The structure of FIG. 6(A) has an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(A). The small group shown in FIG. 6(A) has a charge of 0. The structure of FIG. 6(A) has an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(A). The small group shown in FIG. 6(A) has a charge of 0. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(A). The small group shown in FIG. 6(A) has a charge of 0. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(A). The small group shown in FIG. 6(A) has a charge of 0.

[0240] FIG. 6(B) shows a structure having one 5-coordinate Ga atom, three 3-coordinate oxygen atoms (hereinafter referred to as 3-coordinate O atoms) adjacent to the Ga atom, and two 4-coordinate O atoms adjacent to the Ga atom. All of the 3-coordinate O atoms are present in the ab-plane. There are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(B). Hereinafter referred to as 3-coordinate O atoms), and two 4-coordinate O atoms adjacent to the Ga atom. All of the 3-coordinate O atoms are present in the ab-plane. There are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(B). All of the 3-coordinate O atoms are present in the ab-plane. There are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 6(B). ​​There is one 4 - coordinated O atom each. Also, since the In atom also has a 5 - coordination, it can have the structure shown in Fig. 6( B). The small group shown in Fig. 6(B) has a charge of 0.

[0241] Fig. 6(C) shows a structure having one 4 - coordinated Zn atom, four 4 - coordinated O atoms adjacent to the Zn atom, and. There is one 4 - coordinated O atom in the upper half of Fig. 6(C) and three 4 - coordinated O atoms in the lower half. Or, there may be three 4 - coordinated O atoms in the upper half of Fig. 6(C) and one 4 - coordinated O atom in the lower half. The small group shown in Fig. 6(C) has a charge of 0.

[0242] Fig. 6(D) shows a structure having one 6 - coordinated Sn atom, six 4 - coordinated O atoms adjacent to the Sn atom, and. There are three 4 - coordinated O atoms in the upper half of Fig. 6(D) and three 4 - coordinated O atoms in the lower half. The small group shown in Fig. 6(D) has a charge of + 1.

[0243] Fig. 6(E) shows a small group containing two Zn atoms. There is one 4 - coordinated O atom in the upper half of Fig. 6(E) and one 4 - coordinated O atom in the lower half. The small gr oup shown in Fig. 6(E) has a charge of - 1.

[0244] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also called a unit cell).

[0245] Here, the rule for the combination of these small groups will be explained. The three O atoms in the upper half of the 6 - coordinated In atom shown in Fig. 6(A) each have three adjacent In atoms downward, and the three O atoms in the lower half each have three adjacent In atoms upward. Fig. 6(B) One of the O atoms in the upper half of the 5-coordinate Ga atom shown in [Fig. 6(A)] has one adjacent Ga atom downward, and one of the O atoms in the lower half has one adjacent Ga atom upward. One of the O atoms in the upper half of the 4-coordinate Zn atom shown in Fig. 6(C) has one adjacent Zn atom downward, and three of the O atoms in the lower half each have three adjacent Zn atoms upward. Thus, the number of 4-coordinate O atoms above the metal atom is equal to the number of adjacent metal atoms below that O atom, and similarly, the number of 4-coordinate O atoms below the metal atom is equal to the number of adjacent metal atoms above that O atom. Since the O atom is 4-coordinate, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, when the sum of the number of 4-coordinate O atoms above one metal atom and the number of 4-coordinate O atoms below another metal atom is 4, two small groups containing metal atoms can bond to each other. For example, when a 6-coordinate metal atom (In or Sn) bonds through the 4-coordinate O atoms in the lower half, since there are three 4-coordinate O atoms, it will bond to either a 5-coordinate metal atom (Ga or In) or a 4-coordinate metal atom (Zn). Metal atoms having these coordination numbers bond through 4-coordinate O atoms in the c-axis direction. In addition, multiple small groups bond to form a medium group so that the total charge of the layer structure becomes 0.

[0246] Fig. 7(A) shows a model diagram of a medium group constituting the layer structure of the In-Sn-Zn-O system. Fig. 7(B) shows a large group composed of three medium groups. Note that Fig. 7(C) shows the atomic arrangement when the layer structure of Fig. 7(B) is observed from the c-axis direction.

[0247]

[0248] In Fig. 7(A), for simplicity, the 3-coordinated O atoms are omitted, and the 4-coordinated O atoms are shown by the number For example, there are 3 four-coordinated O atoms each in the upper and lower halves of the Sn atom, which are shown as 3 in the solid frame. Similarly, in Fig. 7(A), there is 1 four-coordinated O atom each in the upper and lower halves of the In atom, which is shown as 1 in the solid frame. In the upper half and lower half of the In atom, and is shown as 1 in the solid frame. Similarly, in Fig. 7(A), there is 1 four-coordinated O atom in the lower half, and there are 3 four-coordinated O atoms in the upper half for the Zn atom, and there is 1 four-coordinated O atom in the upper half and 3 four-coordinated O atoms in the lower half for the Zn atom. are shown. in the lower half.

[0249] In Fig. 7(A), the middle group that constitutes the layer structure of the In-Sn-Zn-O system, from top to bottom in order, there are Sn atoms with 3 four-coordinated O atoms each in the upper and lower halves, which are bonded to In atoms with 1 four-coordinated O atom each in the upper and lower halves. The In atom is bonded to a Zn atom with 3 four-coordinated O atoms in the upper half. The 1 four-coordinated O atom in the lower half of the Zn atom is bonded to In atoms with 3 four-coordinated O atoms each in the upper and lower halves through it. The In atom is bonded to a small group consisting of 2 Zn atoms with 1 four-coordinated O atom each in the upper half. Through the 1 four-coordinated O atom in the lower half of this small group, it is bonded to Sn atoms with 3 four-coordinated O atoms each in the upper and lower halves. A plurality of these middle groups are combined to form a large group. through the 1 four-coordinated O atom in the lower half of this small group, and is bonded to Sn atoms with 3 four-coordinated O atoms each in the upper and lower halves. This is the structure. A plurality of these middle groups are combined to form a large group. to form a large group.

[0250] Here, for the 3-coordinated O atom and the 4-coordinated O atom, the charge per bond can be considered to be -0.667 and -0.5 respectively. For example, In (6-coordinated or 5-coordinated) atoms ​The charges of the Zn (4 - coordinated) atoms and Sn (5 - or 6 - coordinated) atoms are +3 and + 2, +4 respectively. Therefore, the small group containing Sn atoms has a charge of +1. Thus, to form a layer structure containing Sn atoms, a charge of -1 to cancel out the charge +1 is required. As a structure with a charge of -1, as shown in Fig. 6(E), a small group containing 2 Zn atoms can be cited. For example, if there is 1 small group containing Sn atoms and 1 small group containing 2 Zn atoms, the charges are canceled out, so that the total charge of the layer structure can be made 0.

[0251] Specifically, by using the large group shown in Fig. 7(B), a crystal of In - Sn - Zn - O system (In2SnZn3O8) can be obtained. Note that the obtained layer structure of the In - Sn - Zn - O system can be represented by a composition formula of In2SnZn2O7(ZnO) (m is 0 or a natural number.). m (m is 0 or a natural number.).

[0252] In addition, there are also oxides of quaternary metals such as In - Sn - Ga - Zn - O system oxides and , oxides of ternary metals such as In - Ga - Zn - O system oxides (also denoted as IGZO), In - Al - Zn - O system oxides, Sn - Ga - Zn - O system oxides, Al - Ga - Zn - O system oxides, Sn - Al - Zn - O system oxides, and In - Hf - Zn - O system oxides, In - La - Zn - O system oxides, In - Ce - Zn - O system oxides, In - Pr - Zn - O system oxides , In - Nd - Zn - O system oxides, In - Sm - Zn - O system oxides, In - Eu - Zn - O system oxides, In - Gd - Zn - O system oxides, In - Tb - Zn - O system oxides, In - Dy - Zn - O system oxides, In - Ho - Zn - O system oxides, In - Er - Zn - O system oxides​​ substances, In-Tm-Zn-O based oxides, In-Yb-Zn-O based oxides, In-Lu-Zn -O based oxides, and binary metal oxides such as In-Zn-O based oxides, Sn-Zn-O based oxides, Al-Zn-O based oxides, Zn-Mg-O based oxides, Sn-Mg-O based oxides, In-Mg-O based oxides, In-Ga-O based oxides, etc. are the same when used.

[0253] For example, FIG. 8(A) shows a model diagram of the middle group constituting the layer structure of the In-Ga-Zn-O system. is shown.

[0254] In FIG. 8(A), in the middle group constituting the layer structure of the In-Ga-Zn-O system, from the top in order, three 4-coordinate O atoms are in the upper half and lower half respectively, and the In atoms are such that the 4-coordinate O atoms are bonded to one Zn atom in the upper half, and through the three 4-coordinate O atoms in the lower half of the Zn atom, the 4-coordinate O atoms are bonded to the Ga atoms with one 4-coordinate O atom in the upper half and lower half respectively, and through the one 4-coordinate O atom in the lower half of the Ga atom, the 4-coordinate O atoms are bonded to the In atoms with three 4-coordinate O atoms in the upper half and lower half respectively. This middle group is bonded in multiple numbers to form a large group. is formed.

[0255] FIG. 8(B) shows a large group composed of three middle groups. Note that FIG. 8(C) shows the atomic arrangement when observing the layer structure of FIG. 8(B) from the c-axis direction.

[0256] Here, since the charges of In (6-coordinate or 5-coordinate) atoms, Zn (4-coordinate) atoms, and Ga (5-coordinate) atoms are +3, +2, and +3 respectively, a small group containing any of the In atoms, Zn atoms, and Ga atoms has a charge of 0. Therefore, the combination of these small groups is such that Therefore, the total charge of the middle group is always 0.

[0257] In addition, the middle group that constitutes the layer structure of the In-Ga-Zn-O system is not limited to the middle group shown in Fig. 8(A), and a large group in which different arrangements of In atoms, Ga atoms, and Zn atoms are combined is also possible.

[0258] Specifically, by using the large group shown in Fig. 8(B), a crystal of the In-Ga-Zn-O system can be obtained. Note that the obtained layer structure of the In-Ga-Zn-O system can be represented by a composition formula of InGaO 3(ZnO) (n is a natural number). n (n is a natural number.)

[0259] In the case of n = 1 (InGaZnO4), for example, the crystal structure shown in Fig. 9(A) can be adopted. In the crystal structure shown in Fig. 9(A), as described in Fig. 6(B), since Ga atoms and In atoms are penta-coordinated, a structure in which Ga atoms are replaced by In atoms is also possible.

[0260] In addition, in the case of n = 2 (InGaZn2O5), for example, the crystal structure shown in Fig. 9(B) can be adopted. In the crystal structure shown in Fig. 9(B), as described in Fig. 6(B), since Ga atoms and In atoms are penta-coordinated, a structure in which Ga atoms are replaced by In atoms is also possible.

[0261] By adopting a configuration in which a transistor used in one aspect of the present invention has an oxide semiconductor layer containing CAAC in a channel formation region, high reliability can be expected, which is preferable.

[0262] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

Description of Reference Numerals

[0263] 100 Trimming Circuit 105 Resistor Element 110 Transistor 115 Terminal 120 Transistor 125 Erase Terminal 130 Transistor 140 Capacitor Element 150 Memory Node 300 Trimming Circuit 301 Substrate 302 Element Isolation Insulating Layer 303 Insulating Layer 304 Insulating Layer 305 Resistor Element 310 Transistor 311 Wiring 312 Gate Insulating Layer 313 Oxide Semiconductor Layer 320 Transistor 321 Wiring 322 Gate Insulating Layer 323 Oxide Semiconductor Layer 330 Transistor 331 Gate Electrode 332 Wiring 335 Wiring 340 Capacitor Element 341 Wiring 351 Wiring 352 Wiring 353 Wiring 413a Oxide Semiconductor Layer 413b Oxide Semiconductor Layer 504 Insulating Layer 505 Insulating Layer 511 Gate Electrode 512 Gate Insulating Layer 513 Oxide Semiconductor Layer 514a Insulating Layer 514b Insulating Layer 551 Electrode 552 Electrode 701 Substrate 704 Insulating Layer 705 Insulating layer 710 Transistor 711 Gate electrode 712 Gate insulating layer 713 Oxide semiconductor layer 714a Insulating layer 714b Sidewall 751 Electrode 752 Electrode

Claims

1. A first conductive film; a first insulating layer having a region disposed above the first conductive film; a first oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a first transistor; a second oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a second transistor; a second conductive film having a region disposed above the first oxide semiconductor layer; a third conductive film having a region disposed above the first oxide semiconductor layer and a region disposed above the second oxide semiconductor layer; a fourth conductive film having a region disposed above the second oxide semiconductor layer; a fifth conductive film having a region located above the first oxide semiconductor layer and functioning as a gate of the first transistor; a sixth conductive film having a region located above the second oxide semiconductor layer and functioning as a gate of the second transistor; the second conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fourth conductive film functions as the other of the source and the drain of the second transistor, a first power supply potential is supplied to the second conductive film; a second power supply potential is supplied to the fourth conductive film; the third conductive film overlaps with the first conductive film; the second conductive film, the third conductive film, and the fourth conductive film are spaced apart from one another; an operating state of the element is controlled according to the potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; Semiconductor device.

2. A first conductive film; a first insulating layer having a region disposed above the first conductive film; a first oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a first transistor; a second oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a second transistor; a second conductive film having a region disposed above the first oxide semiconductor layer; a third conductive film having a region disposed above the first oxide semiconductor layer and a region disposed above the second oxide semiconductor layer; a fourth conductive film having a region disposed above the second oxide semiconductor layer; a fifth conductive film having a region located above the first oxide semiconductor layer and functioning as a gate of the first transistor; a sixth conductive film having a region located above the second oxide semiconductor layer and functioning as a gate of the second transistor; the second conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fourth conductive film functions as the other of the source and the drain of the second transistor, a first power supply potential is supplied to the second conductive film; a second power supply potential is supplied to the fourth conductive film; a first signal is input to the fifth conductive film; A second signal is input to the sixth conductive film, the third conductive film overlaps with the first conductive film; the second conductive film, the third conductive film, and the fourth conductive film are spaced apart from one another; an operating state of the element is controlled according to the potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; Semiconductor device.

3. A first conductive film; a first insulating layer having a region disposed above the first conductive film; a first oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a first transistor; a second oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a second transistor; a second conductive film having a region in contact with an upper surface of the first oxide semiconductor layer; a third conductive film having a region in contact with an upper surface of the first oxide semiconductor layer and a region in contact with an upper surface of the second oxide semiconductor layer; a fourth conductive film having a region in contact with an upper surface of the second oxide semiconductor layer; a fifth conductive film having a region located above the first oxide semiconductor layer and functioning as a gate of the first transistor; a sixth conductive film having a region located above the second oxide semiconductor layer and functioning as a gate of the second transistor; the second conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fourth conductive film functions as the other of the source and the drain of the second transistor, a first power supply potential is supplied to the second conductive film; a second power supply potential is supplied to the fourth conductive film; the third conductive film overlaps with the first conductive film; the second conductive film, the third conductive film, and the fourth conductive film are spaced apart from one another; an operating state of the element is controlled according to the potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; Semiconductor device.

4. A first conductive film; a first insulating layer having a region disposed above the first conductive film; a first oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a first transistor; a second oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of a second transistor; a second conductive film having a region in contact with an upper surface of the first oxide semiconductor layer; a third conductive film having a region in contact with an upper surface of the first oxide semiconductor layer and a region in contact with an upper surface of the second oxide semiconductor layer; a fourth conductive film having a region in contact with an upper surface of the second oxide semiconductor layer; a fifth conductive film having a region located above the first oxide semiconductor layer and functioning as a gate of the first transistor; a sixth conductive film having a region located above the second oxide semiconductor layer and functioning as a gate of the second transistor; the second conductive film functions as one of a source and a drain of the first transistor, the third conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fourth conductive film functions as the other of the source and the drain of the second transistor, a first power supply potential is supplied to the second conductive film; a second power supply potential is supplied to the fourth conductive film; a first signal is input to the fifth conductive film; A second signal is input to the sixth conductive film, the third conductive film overlaps with the first conductive film; the second conductive film, the third conductive film, and the fourth conductive film are spaced apart from one another; an operating state of the element is controlled according to the potential of the third conductive film; a period during which the first transistor is off and the second transistor is off; Semiconductor device.

5. In any one of claims 1 to 4, the third conductive film functions as an electrode of a capacitor element; Semiconductor device.

6. In any one of claims 1 to 5, The element is disposed in a layer different from the first transistor and the second transistor. Semiconductor device.

7. In any one of claims 1 to 6, the second conductive film is separated from the fifth conductive film, the fourth conductive film is separated from the sixth conductive film; Semiconductor device.

Images