Semiconductor device

Abstract

To provide a semiconductor device in which the reliability of a Ni-plated layer can be improved in a structure in which the Ni-plated layer is formed on an electrode exposed from an opening of an organic insulating layer.SOLUTION: A semiconductor device includes a chip having a side surface, an electrode formed on the chip, an inorganic insulating layer covering the electrode, an organic insulating layer covering the inorganic insulating layer, having a second opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between a first opening and the second opening, and a metal layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening. The organic insulating layer has a second outer wall existing inside a first outer wall of the inorganic insulating layer. The second outer wall is formed along the side surface with a space on the inside from the side surface.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 (FIG. 4) discloses a semiconductor device including a semiconductor substrate, an aluminum film (electrode), a polyimide film (organic insulating layer), and a Ni plating film (Ni plating layer). The aluminum film is formed on the semiconductor substrate. The polyimide film is formed on the aluminum film and has an opening exposing the aluminum film. The Ni plating film is formed on the aluminum film exposed from the opening of the polyimide film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The organic insulating layer has a property of low adhesion to Ni. Therefore, when a metal layer is formed on the electrode exposed from the opening of the organic insulating layer, the metal layer forms a gap extending toward the electrode between the organic insulating layer. As a result, the connection of the metal layer to the electrode becomes insufficient, and the reliability of the metal layer decreases.

[0005] One embodiment of the present invention provides a semiconductor device capable of improving the reliability of a metal layer in a structure in which the metal layer is formed on an electrode exposed from an opening of an organic insulating layer.

Means for Solving the Problems

[0006] One embodiment of the present invention provides a semiconductor device including a chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening spaced from the first opening and surrounding the first opening, the organic insulating layer exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening.

[0007] According to this semiconductor device, the Ni plating layer covers the inner peripheral edge of the inorganic insulating layer, which has a higher adhesion to Ni than the organic insulating layer. Thereby, the gap formation region can be moved away from the electrode, and at the same time, the formation of a gap extending toward the electrode can be suppressed. Compared with a structure in which the inner peripheral edge of the inorganic insulating layer is not exposed, the gap formation region between the inorganic insulating layer and the organic insulating layer can be reduced. Therefore, the reliability of the Ni plating layer can be improved.

[0008] One embodiment of the present invention provides a semiconductor device including a chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening spaced from the first opening and surrounding the first opening, the organic insulating layer exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a metal layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening.

[0009] According to this semiconductor device, the metal layer covers the inner peripheral edge of the inorganic insulating layer, which has a higher adhesion to the metal layer than the organic insulating layer. Thereby, the gap formation region can be moved away from the electrode, and at the same time, the formation of a gap extending toward the electrode can be suppressed. Compared with a structure in which the inner peripheral edge of the inorganic insulating layer is not exposed, the gap formation region between the inorganic insulating layer and the organic insulating layer can be reduced. Therefore, the reliability of the metal layer can be improved.

[0010] The above-mentioned, or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-section along line II-II shown in FIG. 1 together with an outer surface plating layer 42 according to a first exemplary form. FIG. 3 is an enlarged view of region III shown in FIG. 2.

[0013] Referring to FIGS. 1 to 3, in this embodiment, the semiconductor device 1 is composed of a SiC semiconductor device including a SiC chip 2 (chip). The SiC chip 2 includes a SiC single crystal composed of a hexagonal crystal. The SiC single crystal composed of a hexagonal crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, the SiC chip 2 is made of a 4H-SiC single crystal, but does not exclude other polytypes.

[0014] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") when viewed from their normal direction Z.

[0015] The thickness of the SiC chip 2 may be 40 μm or more and 300 μm or less. The thickness of the SiC chip 2 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less. The thickness of the SiC chip 2 is preferably 60 μm or more and 150 μm or less.

[0016] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 faces the carbon plane ((000-1) plane) of the SiC single crystal. The second main surface 4 may be composed of a rough surface having either or both of grinding marks and annealing marks. The annealing mark is a laser irradiation mark. The second main surface 4 may be an ohmic surface having an annealing mark.

[0017] The first major surface 3 and the second major surface 4 may have an off-angle that is inclined at a predetermined off-angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle is preferably inclined at an angle of 0° or more and 10° or less in the off-direction. The off-angle may be 0° or more and 6° or less. The off-angle may be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less.

[0018] The off-angle is preferably more than 0° and 4.5° or less. The off-angle may be 3° or more and 4.5° or less. In this case, the off-angle is preferably 3° or more and 3.5° or less, or 3.5° or more and 4° or less. The off-angle may be 1.5° or more and 3° or less. In this case, the off-angle is preferably 1.5° or more and 2° or less, or 2° or more and 2.5° or less.

[0019] The side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend along the first direction X and face each other in a second direction Y that intersects the first direction X. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face each other in the first direction X. Specifically, the second direction Y is perpendicular to the first direction X.

[0020] The first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. The first side surface 5A and the second side surface 5B may form an inclined surface that is inclined in the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z when the normal direction Z is used as a reference. When the normal direction Z is set to 0°, the first side surface 5A and the second side surface 5B may be inclined at an angle corresponding to the off-angle with respect to the normal direction Z. The angle corresponding to the off-angle may be equal to the off-angle or may be an angle that is more than 0° and less than the off-angle.

[0021] The third side surface 5C and the fourth side surface 5D are formed by an m-plane of a SiC single crystal. The third side surface 5C and the fourth side surface 5D extend planarly along the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0022] The side surfaces 5A to 5D may be cleaved or ground surfaces. The length of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less. The length of the side surfaces 5A to 5D is preferably 0.5 mm or more and 2.5 mm or less.

[0023] In this embodiment, the SiC chip 2 is + The SiC chip 2 has a layered structure including an n-type SiC substrate 6 and an n-type SiC epitaxial layer 7. The second main surface 4 and parts of the side surfaces 5A-5D of the SiC chip 2 are formed by the SiC substrate 6. The first main surface 3 and parts of the side surfaces 5A-5D of the SiC chip 2 are formed by the SiC epitaxial layer 7.

[0024] The n-type impurity concentration of the SiC epitaxial layer 7 is less than the n-type impurity concentration of the SiC substrate 6. The n-type impurity concentration of the SiC substrate 6 is 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0025] The thickness of the SiC substrate 6 may be 40 μm or more and 250 μm or less. The thickness of the SiC substrate 6 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, or 200 μm or more and 250 μm or less. The thickness of the SiC substrate 6 is preferably 40 μm or more and 150 μm or less. By thinning the SiC substrate 6, the resistance value of the SiC substrate 6 can be reduced.

[0026] The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 is preferably 5 μm or more and 15 μm or less.

[0027] The SiC chip 2 includes an active region 8 and an outer region 9. The active region 8 is a region including an SBD (Schottky Barrier Diode) as an example of a functional device (diode). The active region 8 is formed at the central portion of the SiC chip 2 at a distance inward from the side surfaces 5A to 5D in a plan view. The active region 8 is formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0028] The outer region 9 is a region outside the active region 8. The outer region 9 is formed in the region between the side surfaces 5A to 5D and the active region 8. The outer region 9 is formed in an annular shape (specifically, endless) surrounding the active region 8 in a plan view.

[0029] The semiconductor device 1 includes an n-type diode region 10 formed in the surface layer portion of the first main surface 3 in the active region 8. The diode region 10 is formed at the central portion of the first main surface 3. The planar shape of the diode region 10 is arbitrary. The diode region 10 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0030] In this form, the diode region 10 is formed by utilizing a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 may exceed the n-type impurity concentration of the SiC epitaxial layer 7. In this case, the diode region 10 is formed by introducing n-type impurities into the surface layer portion of the SiC epitaxial layer 7.

[0031] In the outer region 9, a guard region 11 containing p-type impurities is formed in the surface layer portion of the first main surface 3. The p-type impurities in the guard region 11 may or may not be activated. The guard region 11 is formed in a strip shape extending along the diode region 10 in plan view. Specifically, the guard region 11 is formed in an annular shape (specifically, an endless shape) surrounding the diode region 10 in plan view.

[0032] Thereby, the guard region 11 is formed as a guard ring region. The guard region 11 defines the active region 8 (diode region 10). The planar shape of the active region 8 (diode region 10) is adjusted by the planar shape of the guard region 11. The guard region 11 may be formed in a polygonal annular shape or an annular shape in plan view.

[0033] The semiconductor device 1 includes a main surface insulating layer 12 formed on the first main surface 3. The main surface insulating layer 12 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The main surface insulating layer 12 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the main surface insulating layer 12 has a single-layer structure composed of a silicon oxide layer.

[0034] The main surface insulating layer 12 has a contact opening 13 that exposes the diode region 10. The contact opening 13 also exposes the inner peripheral edge of the guard region 11. The planar shape of the contact opening 13 is arbitrary. The contact opening 13 may be partitioned into a square shape having four sides parallel to the side surfaces 5A to 5D in plan view.

[0035] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this form, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. The periphery of the main surface insulating layer 12 may be formed at an interval inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes the portion located in the outer region 9 on the first main surface 3.

[0036] The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness of the main surface insulating layer 12 is 0.5 μm or more and 5 μm or less.

[0037] The semiconductor device 1 includes a first main surface electrode 21 (electrode) formed on the first main surface 3. The first main surface electrode 21 is connected to the diode region 10 and the guard region 11 in the contact opening 13. The first main surface electrode 21 is drawn out from the contact opening 13 onto the main surface insulating layer 12. The periphery of the first main surface electrode 21 is formed on the main surface insulating layer 12 at an interval inward from the side surfaces 5A to 5D. Thereby, the first main surface electrode 21 exposes the peripheral portion of the main surface insulating layer 12.

[0038] The thickness T1 of the first main surface electrode 21 may be 10 μm or more and 100 μm or less. The thickness T1 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. It is preferable that the thickness T1 is 20 μm or more and 60 μm or less.

[0039] Specifically, the first main surface electrode 21 has a laminated structure including a barrier electrode 22 and a main electrode 23 laminated in this order from the side of the first main surface 3. The barrier electrode 22 is formed in a film shape along the first main surface 3 and the main surface insulating layer 12. The barrier electrode 22 forms a Schottky junction with the diode region 10. Thereby, an SBD having the first main surface electrode 21 as an anode and the diode region 10 as a cathode is formed. That is, the first main surface electrode 21 is the anode electrode of the SBD.

[0040] The barrier electrode 22 may contain at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0041] The main electrode 23 is formed in a film shape on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 is made of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer (an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0042] The main electrode 23 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order. The main electrode 23 may have a single-layer structure made of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. It is preferable that the main electrode 23 has a single-layer structure made of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0043] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. Preferably, the thickness of the main electrode 23 is 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first main surface electrode 21 is approximated to the thickness of the main electrode 23.

[0044] The semiconductor device 1 includes an insulating layer 24 that covers the first main surface electrode 21 on the first main surface 3. In FIG. 1, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the main surface insulating layer 12. The periphery of the insulating layer 24 is formed at an interval inward from the side surfaces 5A to 5D. Thereby, the insulating layer 24 exposes the peripheral portion of the main surface insulating layer 12.

[0045] The periphery of the insulating layer 24 demarcates a dicing street 25 between the side surfaces 5A to 5D. According to the dicing street 25, when cutting out the semiconductor device 1 from the wafer, it is not necessary to physically cut the insulating layer 24. Thereby, the semiconductor device 1 can be smoothly cut out from the wafer, and at the same time, peeling and deterioration of the insulating layer 24 can be suppressed. As a result, the insulating layer 24 can appropriately protect the objects to be protected such as the SiC chip 2 and the first main surface electrode 21.

[0046] The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in a direction orthogonal to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0047] The insulating layer 24 has a pad opening 26 that exposes the first main surface electrode 21. The pad opening 26 exposes the first main surface electrode 21 within a region surrounded by the contact opening 13 in a plan view. The pad opening 26 may surround the contact opening 13 in a region outside the contact opening 13 in a plan view. The planar shape of the pad opening 26 is arbitrary. The pad opening 26 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0048] Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31 laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film shape along the main surface insulating layer 12 and the first main surface electrode 21. The inorganic insulating layer 30 includes a first inner wall 32 and a first outer wall 33. The first inner wall 32 of the inorganic insulating layer 30 defines a first opening 34 that exposes a part of the first main surface electrode 21. The first opening 34 forms a part of the pad opening 26.

[0049] The first opening 34 is defined within a region surrounded by the contact opening 13 in a plan view. The first opening 34 may surround the contact opening 13 from the outside of the contact opening 13 in a plan view. The planar shape of the first opening 34 is arbitrary. The first opening 34 may be defined in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0050] The first outer wall 33 of the inorganic insulating layer 30 is formed at a distance inward from the side surfaces 5A to 5D, exposing the peripheral portion of the main surface insulating layer 12. The inorganic insulating layer 30 partitions a part of the dicing street 25 between the side surfaces 5A to 5D. The first outer wall 33 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0051] The angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. It is preferable that the angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is 45° or more and less than 90°. The angle of the first inner wall 32 (the first outer wall 33) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21.

[0052] The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. The inorganic insulating layer 30 preferably contains an insulating material different from the main surface insulating layer 12. In this form, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer.

[0053] It is preferable that the thickness T2 of the inorganic insulating layer 30 is less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness T2 is 1 μm or more and 5 μm or less. It is particularly preferable that the thickness T2 is 1 μm or more and 2 μm or less.

[0054] The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second inner wall 35 and a second outer wall 36. The second inner wall 35 of the organic insulating layer 31 defines a second opening 37 that exposes a part of the first main surface electrode 21. In this form, the second inner wall 35 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side.

[0055] Referring to FIG. 3, the second opening 37 communicates with the first opening 34 of the inorganic insulating layer 30 and forms a pad opening 26 therebetween. The second opening 37 is partitioned within a region surrounded by the contact opening 13 in a plan view. The second opening 37 may surround the contact opening 13 from the outside of the contact opening 13 in a plan view. The planar shape of the second opening 37 is arbitrary. The second opening 37 may be partitioned into a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0056] The second opening 37 surrounds the first opening 34 at an interval from the first opening 34 and exposes a part of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a part of the main surface of the inorganic insulating layer 30 as an inner peripheral edge 38 in a region between the first opening 34 and the second opening 37.

[0057] The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 may be more than 0 μm and 10 μm or less. The width W may be more than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The width W is preferably 1 μm or more and 5 μm or less. The width W is arbitrary, but it is preferably not more than the thickness T2 of the inorganic insulating layer 30 (W≦T2). The width W is particularly preferably 1 μm or more and 2 μm or less.

[0058] In this form, the second outer wall 36 of the organic insulating layer 31 is formed in a curved shape recessed toward the inorganic insulating layer 30 side. The second outer wall 36 is formed on the inorganic insulating layer 30 at an interval inward from the side surfaces 5A to 5D and partitions a part of the dicing street 25 therebetween. Thereby, the organic insulating layer 31 exposes the peripheral portion of the main surface insulating layer 12. The second outer wall 36 may be formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0059] The second outer wall 36 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 33 of the inorganic insulating layer 30. In this case, the dicing street 25 is partitioned by the second outer wall 36 of the organic insulating layer 31.

[0060] The angle formed between the second inner wall 35 (second outer wall 36) of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. It is preferable that the angle formed between the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is 45° or more and less than 90°. The angle of the second inner wall 35 (second outer wall 36) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30.

[0061] The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 31 contains polyimide.

[0062] The organic insulating layer 31 preferably has a thickness T3 (T2 < T3) that exceeds the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and 10 or less. The ratio T3 / T2 may be more than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The ratio T3 / T2 is preferably 2 or more and 6 or less.

[0063] The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness T3 is preferably 5 μm or more and 30 μm or less.

[0064] The semiconductor device 1 includes a rough surface region 39 formed on an exposed surface exposed from a pad opening 26 (a first opening 34 of the inorganic insulating layer 30) at the first main surface electrode 21. The rough surface region 39 includes a depression formed in a region directly below the first inner wall 32 of the inorganic insulating layer 30. As a result, the first inner wall 32 of the inorganic insulating layer 30 includes a portion that overhangs the rough surface region 39.

[0065] The semiconductor device 1 includes a pad electrode 40 formed in the pad opening 26. The pad electrode 40 includes a Ni plating layer (metal layer) 41 formed on the first main surface electrode 21 within the pad opening 26. The Ni plating layer 41 covers the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the first main surface electrode 21 side. In this form, the Ni plating layer 41 covers the organic insulating layer 31 within the second opening 37.

[0066] Referring to FIG. 3, the Ni plating layer 41 has a first portion 41A that covers the first main surface electrode 21 and a second portion 41B that covers the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the rough surface region 39 within the first opening 34 and covers the first main surface electrode 21. The first portion 41A covers the entire area of the first inner wall 32 of the inorganic insulating layer 30 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0067] The second portion 41B of the Ni plating layer 41 is drawn out from the first portion 41A toward the organic insulating layer 31 side within the second opening 37. The second portion 41B is formed in an arc shape extending from the opening end of the first opening 34 toward the organic insulating layer 31.

[0068] The second portion 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. Thereby, the second portion 41B faces the first main surface electrode 21 with the inner peripheral edge 38 of the inorganic insulating layer 30 interposed therebetween. The second portion 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0069] In this form, the second portion 41B further covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. The second portion 41B covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B covers the organic insulating layer 31 such that the exposed area of the second inner wall 35 (organic insulating layer 31) exceeds the hidden area of the second inner wall 35 (organic insulating layer 31). Thus, the Ni plating layer 41 is formed such that the first portion 41A and the second portion 41B engage from different two directions with the opening end of the first opening 34.

[0070] The Ni plating layer 41 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 exceeds the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T2 + W < T4). This is the condition for the Ni plating layer 41 to contact the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with reference to the main surface of the first main surface electrode 21.

[0071] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5.

[0072] The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less.

[0073] The pad electrode 40 is made of a metal material different from the Ni plating layer 41 and includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41 in the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) less than the thickness T4 of the Ni plating layer 41. The outer plating layer 42 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0074] The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the second inner wall 35 of the organic insulating layer 31.

[0075] In this form, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0076] The Pd plating layer 43 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0077] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0078] The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm or more and 1 μm or less. The thickness of the Au plating layer 44 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0079] The outer surface plating layer 42 can take various forms shown in FIGS. 4A to 4D.

[0080] FIG. 4A is a corresponding view of FIG. 3 and is an enlarged view showing the outer surface plating layer 42 according to the second exemplary form. Hereinafter, the differences from the outer surface plating layer 42 according to the first exemplary form will be described.

[0081] Referring to FIG. 4A, in this form, the outer surface plating layer 42 has a single-layer structure composed of the Au plating layer 44. The Au plating layer 44 is formed in a film shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0082] FIG. 4B is a corresponding view of FIG. 3 and is an enlarged view showing the outer surface plating layer 42 according to the third exemplary form. Hereinafter, the differences from the outer surface plating layer 42 according to the first exemplary form will be described.

[0083] Referring to FIG. 4B, in this form, the outer surface plating layer 42 has a single-layer structure composed of a Pd plating layer 43. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0084] FIG. 4C is a corresponding view of FIG. 3 and is an enlarged view showing the outer surface plating layer 42 according to the fourth exemplary form. Hereinafter, differences from the outer surface plating layer 42 according to the first exemplary form will be described.

[0085] Referring to FIG. 4C, in this form, the outer surface plating layer 42 has a single-layer structure composed of an Ag plating layer 45. The Ag plating layer 45 is formed in a film shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0086] The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 1 μm or less. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0087] FIG. 4D is a corresponding view of FIG. 3 and is an enlarged view showing the outer surface plating layer 42 according to the fifth exemplary form. Hereinafter, differences from the outer surface plating layer 42 according to the first exemplary form will be described.

[0088] Referring to FIG. 4D, the outer surface plating layer 42 has a laminated structure including a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45 laminated in this order from the Ni plating layer 41 side.

[0089] The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0090] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0091] The Ag plating layer 45 is formed in a film shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 covers the Au plating layer 44 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0092] Referring to FIG. 2 again, the semiconductor device 1 includes a second main surface electrode (back surface electrode) 46 formed on the second main surface 4. The second main surface electrode 46 covers the entire area of the second main surface 4. The second main surface electrode 46 forms an ohmic contact with the second main surface 4. The second main surface electrode 46 is formed as the cathode electrode of the SBD.

[0093] The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may have a laminated structure in which at least two of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer are laminated in an arbitrary order. The second main surface electrode 46 may have a single-layer structure composed of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this form, the second main surface electrode 46 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer laminated in this order from the second main surface 4 side.

[0094] FIGS. 5A to 5O are cross-sectional views for explaining an example of a method of manufacturing the semiconductor device 1 shown in FIG. 1.

[0095] Referring to FIG. 5A, first, a SiC epitaxial wafer 50 serving as a base of the SiC chip 2 is prepared. The SiC epitaxial wafer 50 has a stacked structure including a SiC wafer 51 and a SiC epitaxial layer 52. The SiC wafer 51 serves as a base of the SiC substrate 6. The SiC epitaxial layer 52 serves as a base of the SiC epitaxial layer 7. The SiC epitaxial layer 52 is formed by epitaxially growing SiC from the main surface of the SiC wafer 51.

[0096] The SiC epitaxial wafer 50 has a first wafer main surface 53 on one side and a second wafer main surface 54 on the other side. The first wafer main surface 53 and the second wafer main surface 54 respectively correspond to the first main surface 3 and the second main surface 4 of the SiC chip 2.

[0097] In the SiC epitaxial wafer 50, a plurality of device regions 55 respectively corresponding to the semiconductor device 1 and dicing planned lines 56 partitioning the plurality of device regions 55 are set. In FIG. 5A, one device region 55 is shown, and illustration of other regions is omitted (the same applies to FIGS. 5B to 5O below). The plurality of device regions 55 are set in a matrix along the first direction X and the second direction Y. The dicing planned lines 56 are set in a grid extending along the first direction X and the second direction Y.

[0098] Next, referring to FIG. 5B, main parts of functional devices are formed in each device region 55. In this form, n-type impurities and / or p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 53 to form an n-type diode region 10 and a p-type guard region 11. The n-type impurities and / or p-type impurities are introduced into the surface layer portion of the first wafer main surface 53 by an ion implantation method through an ion implantation mask (not shown).

[0099] Next, referring to FIG. 5C, the main surface insulating layer 12 is formed on the first wafer main surface 53. The main surface insulating layer 12 may be formed by a CVD (Chemical Vapor Deposition) method and / or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0100] Next, referring to FIG. 5D, a resist mask 57 having a predetermined pattern is formed on the main surface insulating layer 12. The resist mask 57 exposes the region where the contact opening 13 is to be formed in the main surface insulating layer 12 and covers the other regions. Next, the unnecessary portions of the main surface insulating layer 12 are removed by an etching method through the resist mask 57. The etching method may be a wet etching method and / or a dry etching method. Thereby, the contact opening 13 is formed in the main surface insulating layer 12.

[0101] Next, referring to FIG. 5E, a base electrode layer 58 serving as the base of the first main surface electrode 21 is formed on the main surface insulating layer 12. The base electrode layer 58 has a stacked structure including a barrier electrode 22 and a main electrode 23 stacked in this order from the main surface insulating layer 12 side. The barrier electrode 22 and the main electrode 23 may be formed by a sputtering method and / or a vapor deposition method, respectively.

[0102] Next, referring to FIG. 5F, a resist mask 59 having a predetermined pattern is formed on the base electrode layer 58. The resist mask 59 exposes the region where the first main surface electrode 21 is to be formed in the base electrode layer 58 and covers the other regions. Next, the unnecessary portions of the base electrode layer 58 are removed by an etching method through the resist mask 59. The etching method may be a wet etching method and / or a dry etching method. Thereby, the first main surface electrode 21 is formed on the main surface insulating layer 12.

[0103] Next, referring to FIG. 5G, an inorganic insulating layer 30 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21. In this form, the inorganic insulating layer 30 has a single-layer structure made of a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC epitaxial wafer 50 side. The inorganic insulating layer 30 may be formed by a CVD method.

[0104] Next, referring to FIG. 5H, a resist mask 60 having a predetermined pattern is formed on the inorganic insulating layer 30. The resist mask 60 exposes regions in the inorganic insulating layer 30 where the first opening 34 and the dicing street 25 are to be formed, and covers the other regions.

[0105] Next, unnecessary portions of the inorganic insulating layer 30 are removed by an etching method through the resist mask 60. The etching method may be a wet etching method and / or a dry etching method. Thereby, a first opening 34 for exposing the first main surface electrode 21 and a dicing street 25 extending in a grid pattern along the planned cutting line 56 are formed in the inorganic insulating layer 30.

[0106] Next, referring to FIG. 5I, an organic insulating layer 31 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21 and the inorganic insulating layer 30. The organic insulating layer 31 is formed by applying polyimide, which is an example of a photosensitive resin, to the first wafer main surface 53 side.

[0107] Next, referring to FIG. 5J, after the organic insulating layer 31 is exposed with a pattern corresponding to the second opening 37 and the dicing street 25, it is developed. Thereby, a second opening 37 for exposing the first main surface electrode 21 and a dicing street 25 extending in a grid pattern along the planned cutting line 56 are formed in the organic insulating layer 31.

[0108] The second opening 37 of the organic insulating layer 31 is formed so as to surround the first opening 34 with a space from the first opening 34 of the inorganic insulating layer 30. Thereby, an organic insulating layer 31 is formed that exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37.

[0109] Next, referring to FIG. 5K, a rough surface region 39 is formed in a portion of the first main surface electrode 21 that is exposed from the first opening 34 and the second opening 37. The rough surface region 39 is formed by a chelate treatment method (zinc substitution treatment method) for the exposed portion of the first main surface electrode 21.

[0110] Next, referring to FIG. 5L, a Ni plating layer 41 is formed on a portion of the first main surface electrode 21 that is exposed from the first opening 34 and the second opening 37. The Ni plating layer 41 is formed by depositing Ni from the first main surface electrode 21 by an electrolytic plating method or an electroless plating method (in this form, the electroless plating method). Thereby, a Ni plating layer 41 is formed that covers the first main surface electrode 21 in the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 in the second opening 37. Since the specific structure of the Ni plating layer 41 is as described above, the description thereof is omitted.

[0111] Next, referring to FIG. 5M, an outer surface plating layer 42 is formed on the outer surface of the Ni plating layer 41 in the second opening 37. The outer surface plating layer 42 includes at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. The outer surface plating layer 42 is formed by depositing an arbitrary material among Pd, Au, and Ag from the first main surface electrode 21 by an electrolytic plating method or an electroless plating method (in this form, the electroless plating method).

[0112] Next, referring to FIG. 5N, the SiC epitaxial wafer 50 is thinned by grinding the second wafer main surface 54 until it reaches the desired thickness. The second wafer main surface 54 may be ground by a CMP (Chemical Mechanical Polishing) method. After the grinding process of the second wafer main surface 54, an annealing process may be performed on the second wafer main surface 54. The annealing process may be performed by a laser irradiation method. As a result, the second wafer main surface 54 (second main surface 4) becomes an ohmic surface.

[0113] Next, referring to FIG. 5O, the second main surface electrode 46 is formed on the second wafer main surface 54. The second main surface electrode 46 may be formed by a sputtering method, a vapor deposition method, and / or a plating method. Thereafter, the SiC epitaxial wafer 50 is cut or cleaved along the dicing street 25, and a plurality of semiconductor devices 1 are cut out. Through the steps including the above, the semiconductor device 1 is manufactured.

[0114] As described above, the semiconductor device 1 includes the SiC chip 2, the first main surface electrode 21, the inorganic insulating layer 30, the organic insulating layer 31, and the Ni plating layer 41. The first main surface electrode 21 is formed on the SiC chip 2. The inorganic insulating layer 30 covers the first main surface electrode 21 and has a first opening 34 that exposes the first main surface electrode 21. The organic insulating layer 31 covers the inorganic insulating layer 30 and has a second opening 37 that surrounds the first opening 34 with a space therebetween, and exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The Ni plating layer 41 is connected to the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37.

[0115] The inorganic insulating layer 30 has a property of high adhesion to Ni, while the organic insulating layer 31 has a property of low adhesion to Ni compared to the inorganic insulating layer 30. Therefore, for example, when the inorganic insulating layer 30 does not exist or when the organic insulating layer 31 is formed flush with the inorganic insulating layer 30, the Ni plating layer 41 forms a gap extending toward the first main surface electrode 21 between the organic insulating layer 31. As a result, the connection of the Ni plating layer 41 to the first main surface electrode 21 becomes insufficient, and the reliability of the Ni plating layer 41 decreases.

[0116] Therefore, in the semiconductor device 1, an organic insulating layer 31 that exposes the inner peripheral edge 38 of the inorganic insulating layer 30 having a property of high adhesion to Ni is formed, and a structure is adopted in which the Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30. In this case, the Ni plating layer 41 forms a first connection portion extending in the thickness direction of the inorganic insulating layer 30 and a second connection portion extending in the width direction of the inorganic insulating layer 30 between the inorganic insulating layer 30.

[0117] Thereby, the gap formation region can be moved away from the first main surface electrode 21, and at the same time, the formation of a gap extending toward the first main surface electrode 21 can be appropriately suppressed. Further, compared with the case where the inner peripheral edge 38 of the inorganic insulating layer 30 does not exist, the gap formation region between the organic insulating layer 31 can be reduced. Therefore, the reliability of the Ni plating layer 41 can be improved.

[0118] In the semiconductor device 1, the second portion 41B of the Ni plating layer 41 covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B of the Ni plating layer 41 covers the organic insulating layer 31 such that the hidden area of the second inner wall 35 (organic insulating layer 31) is less than the exposed area of the second inner wall 35 (organic insulating layer 31). According to such a Ni plating layer 41, the gap formation region can be appropriately reduced.

[0119] The semiconductor device 1 further includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41. According to such a structure, since the formation of a gap is suppressed between the organic insulating layer 31 and the Ni plating layer 41, the entry of the plating solution into the gap can be suppressed. Thereby, abnormal film formation of the outer plating layer 42 starting from the gap can be suppressed. As a result, it is possible to suppress the connection failure of the Ni plating layer 41 due to the abnormal film formation of the outer plating layer 42, and at the same time, it is possible to suppress the peeling (connection failure) of the outer plating layer 42.

[0120] Specifically, the outer plating layer 42 can include at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. Therefore, it is possible to suppress the connection failure of the Ni plating layer 41 due to the abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, it is possible to suppress the peeling (connection failure) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45.

[0121] FIG. 6 is a corresponding diagram of FIG. 2, and is a cross-sectional view showing the semiconductor device 61 according to the second embodiment of the present invention together with the outer plating layer 42 according to the first exemplary form. FIG. 7 is an enlarged view of the region VII shown in FIG. 6. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0122] Referring to FIGS. 6 and 7, the organic insulating layer 31 exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 is arbitrary, but it is preferably greater than the thickness T2 of the inorganic insulating layer 30 (T2 < W).

[0123] The ratio W / T2 of the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 10. The ratio W / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 4, greater than or equal to 4 and less than or equal to 6, greater than or equal to 6 and less than or equal to 8, or greater than or equal to 8 and less than or equal to 10. Preferably, the ratio W / T2 is greater than or equal to 2 and less than or equal to 5. The width W may be greater than 0 μm and less than or equal to 10 μm. The width W may be greater than 0 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm.

[0124] The Ni plating layer 41 is formed on the first main surface electrode 21 within the pad opening 26. The Ni plating layer 41 covers the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the first main surface electrode 21. The Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second opening 37.

[0125] Specifically, the Ni plating layer 41 has a first portion 41A that covers the first main surface electrode 21 and a second portion 41B that covers the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the rough surface region 39 within the first opening 34 and covers the first main surface electrode 21. The first portion 41A covers the entire area of the first inner wall 32 of the inorganic insulating layer 30 within the first opening 34 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion that extends in the thickness direction of the inorganic insulating layer 30.

[0126] The second portion 41B of the Ni plating layer 41 is drawn from the first portion 41A toward the organic insulating layer 31 side within the second opening 37. The second portion 41B is formed in an arc shape that extends from the opening end of the first opening 34 toward the second inner wall 35 of the organic insulating layer 31.

[0127] The second part 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. In this form, the second part 41B partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 side of the inorganic insulating layer 30 within the second opening 37 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0128] Thereby, the Ni plating layer 41 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. The second part 41B faces the first main surface electrode 21 across the inner peripheral edge 38 of the inorganic insulating layer 30. The second part 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection part extending in the width direction of the inorganic insulating layer 30.

[0129] The Ni plating layer 41 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 is less than the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + W). This is the condition for the Ni plating layer 41 to expose the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with reference to the main surface of the first main surface electrode 21.

[0130] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm.

[0131] The outer plating layer 42 covers the outer surface of the Ni plating layer 41 within the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the Ni plating layer 41. In this form, the outer plating layer 42 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37.

[0132] The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0133] Specifically, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0134] The Pd plating layer 43 has a thickness that is less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0135] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a space from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0136] The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm or more and 1 μm or less. The thickness of the Au plating layer 44 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0137] In this embodiment, an example in which the outer surface plating layer 42 that exposes the entire area of the second inner wall 35 of the organic insulating layer 31 is formed has been described. However, an outer surface plating layer 42 that covers a part of the second inner wall 35 of the organic insulating layer 31 may be employed. In this case, at least one of the Pd plating layer 43 and the Au plating layer 44 may cover a part of the second inner wall 35 of the organic insulating layer 31. The outer surface plating layer 42 can take various forms shown in FIGS. 8A to 8D.

[0138] FIG. 8A is a corresponding view of FIG. 7 and is an enlarged view showing the outer surface plating layer 42 according to the second exemplary embodiment. Hereinafter, differences from the outer surface plating layer 42 according to the first exemplary embodiment will be described.

[0139] Referring to FIG. 8A, in this form, the outer surface plating layer 42 has a single-layer structure composed of an Au plating layer 44. The Au plating layer 44 is formed in a film shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0140] The Au plating layer 44 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 to the inorganic insulating layer 30 side. Thereby, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Au plating layer 44 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0141] FIG. 8B is a corresponding view of FIG. 7 and is an enlarged view showing the outer surface plating layer 42 according to the third exemplary form. Hereinafter, the differences from the outer surface plating layer 42 according to the first exemplary form will be described.

[0142] Referring to FIG. 8B, in this form, the outer surface plating layer 42 has a single-layer structure composed of a Pd plating layer 43. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0143] The Pd plating layer 43 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 to the inorganic insulating layer 30 side. Thereby, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Pd plating layer 43 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0144] FIG. 8C is a corresponding view of FIG. 7 and is an enlarged view showing the outer plating layer 42 according to the fourth exemplary form. Hereinafter, differences from the outer plating layer 42 according to the first exemplary form will be described.

[0145] Referring to FIG. 8C, in this form, the outer plating layer 42 has a single-layer structure composed of an Ag plating layer 45. The Ag plating layer 45 is formed in a film shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0146] The Ag plating layer 45 covers the Ni plating layer 41 at a distance from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. Thereby, the Ag plating layer 45 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37. The Ag plating layer 45 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0147] The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 1 μm or less. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0148] FIG. 8D is a corresponding view of FIG. 7 and is an enlarged view showing the outer plating layer 42 according to the fifth exemplary form. Hereinafter, differences from the outer plating layer 42 according to the first exemplary form will be described.

[0149] Referring to FIG. 8D, the outer plating layer 42 has a laminated structure including a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45 laminated in this order from the Ni plating layer 41 side.

[0150] The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a space from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Pd plating layer 43 covers the Ni plating layer 41 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. Thereby, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0151] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a space from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Au plating layer 44 covers the Pd plating layer 43 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. Thereby, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0152] The Ag plating layer 45 is formed in a film shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a space from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 in the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Ag plating layer 45 covers the Au plating layer 44 with a space from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. Thereby, the Ag plating layer 45 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of the second inner wall 35 of the organic insulating layer 31 in the second opening 37. At least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 may cover a part of the second inner wall 35 of the organic insulating layer 31.

[0153] As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 1. In particular, the Ni plating layer 41 related to the semiconductor device 61 covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a space from the organic insulating layer 31 within the second opening 37. Thereby, it is possible to prevent an undesired gap from being formed between the organic insulating layer 31 and the Ni plating layer 41. Therefore, the reliability of the Ni plating layer 41 can be surely improved.

[0154] Furthermore, the semiconductor device 61 includes an outer surface plating layer 42 that covers the outer surface of the Ni plating layer 41. According to such a structure, since no gap is formed between the organic insulating layer 31 and the Ni plating layer 41, the outer surface plating layer 42 can be appropriately formed along the outer surface of the Ni plating layer 41. Therefore, it is possible to appropriately suppress the connection failure of the Ni plating layer 41 caused by abnormal film formation of the outer surface plating layer 42, and at the same time, it is possible to appropriately suppress the peeling (connection failure) of the outer surface plating layer 42.

[0155] Specifically, the outer surface plating layer 42 can include at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. Therefore, it is possible to suppress the connection failure of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, it is possible to suppress the peeling (connection failure) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45.

[0156] FIG. 9 is a plan view showing a semiconductor device 101 according to the third embodiment. FIG. 10 is an enlarged view of a region X shown in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 10. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 9. FIG. 13 is an enlarged view of a region XIII shown in FIG. 12. FIG. 14 is an enlarged view of a region XIV shown in FIG. 12. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 1, the same reference numerals will be given and the description will be omitted.

[0157] Referring to FIGS. 9 to 14, the semiconductor device 101 is a SiC semiconductor device in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor), as an example of a functional device, is formed in the active region 8 instead of an SBD.

[0158] The semiconductor device 101 includes a SiC chip 2, a main surface insulating layer 12, a first main surface electrode 21, an insulating layer 24, a pad electrode 40, and a second main surface electrode (back surface electrode) 46. In FIG. 9, the insulating layer 24 is shown by hatching. The first main surface 3 and the second main surface 4 of the SiC chip 2 are formed in a rectangular shape (a rectangular shape in this form) in plan view.

[0159] The first side surface 5A and the second side surface 5B extend along the first direction X and face each other in the second direction Y intersecting the first direction X. The first side surface 5A and the second side surface 5B form the short sides of the SiC chip 2. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face each other in the first direction X. The third side surface 5C and the fourth side surface 5D form the long sides of the SiC chip 2.

[0160] The length of the first side surface 5A (the second side surface 5B) may be 0.1 mm or more and 8 mm or less. The length of the first side surface 5A (the second side surface 5B) is preferably 0.1 mm or more and 2.5 mm or less. The length of the third side surface 5C (the fourth side surface 5D) may be 0.2 mm or more and 16 mm or less. The length of the third side surface 5C (the fourth side surface 5D) is preferably 0.5 mm or more and 5 mm or less.

[0161] Similar to the case of the first embodiment, the SiC chip 2 has a stacked structure including a SiC substrate 6 and a SiC epitaxial layer 7. The SiC substrate 6 is formed as the drain region of the MISFET. The SiC epitaxial layer 7 is formed as the drift region of the MISFET.

[0162] In this form, the SiC epitaxial layer 7 has different n-type impurity concentrations along the normal direction Z. Specifically, the SiC epitaxial layer 7 includes a high-concentration region 102 with a high n-type impurity concentration and a low-concentration region 103 with an n-type impurity concentration lower than that of the high-concentration region 102.

[0163] The high-concentration region 102 is formed in the region on the side of the first main surface 3. The low-concentration region 103 is formed in the region on the side of the second main surface 4 with respect to the high-concentration region 102. The thickness of the high-concentration region 102 is less than the thickness of the low-concentration region 103. The thickness of the high-concentration region 102 is less than half of the total thickness of the SiC epitaxial layer 7.

[0164] The n-type impurity concentration of the high-concentration region 102 may be 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. The n-type impurity concentration of the low-concentration region 103 may be 1.0×10 15 cm -3 or more and 1.0×10 16 cm -3 or less. Of course, the n-type impurity concentration of the SiC epitaxial layer 7 may have a concentration gradient that gradually decreases from the SiC substrate 6 toward the first main surface 3 within the range of 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0165] The active region 8 is formed at the center of the SiC chip 2 at a distance inward from the side surfaces 5A to 5D in a plan view. The active region 8 is formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view. On the other hand, the outer region 9 is formed in a rectangular annular shape surrounding the active region 8 in a plan view.

[0166] The semiconductor device 101 includes a plurality of trench gate structures 104 formed on the first main surface 3 in the active region 8. The plurality of trench gate structures 104 are each formed in a strip shape extending along the first direction X and are formed at intervals in the second direction Y. The plurality of trench gate structures 104 are formed in a stripe shape extending along the first direction X in a plan view.

[0167] In this form, the plurality of trench gate structures 104 extend in a strip shape from the peripheral edge on one side (the third side surface 5C side) to the peripheral edge on the other side (the fourth side surface 5D side) in the active region 8. The plurality of trench gate structures 104 cross the middle part between the peripheral edge on one side and the peripheral edge on the other side in the active region 8.

[0168] The length of each trench gate structure 104 may be 1 mm or more and 10 mm or less. The length of each trench gate structure 104 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. It is preferable that the length of each trench gate structure 104 is 2 mm or more and 6 mm or less. The total extension per unit area of one trench gate structure 104 is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[0169] Each trench gate structure 104 includes a gate trench 105, a gate insulating layer 106, and a gate electrode 107. In FIG. 10, the gate insulating layer 106 and the gate electrode 107 are shown by hatching.

[0170] The gate trench 105 is formed in the SiC epitaxial layer 7. The gate trench 105 includes side walls and a bottom wall. The side walls forming the long sides of the gate trench 105 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the gate trench 105 are formed by the m-plane of the SiC single crystal.

[0171] The side wall of the gate trench 105 may extend along the normal direction Z. The angle formed by the side wall of the gate trench 105 with respect to the first main surface 3 in the SiC chip 2 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The side wall of the gate trench 105 may be formed substantially perpendicular to the first main surface 3. The gate trench 105 may be formed in a tapered shape with a narrowing opening width from the first main surface 3 toward the bottom wall.

[0172] The bottom wall of the gate trench 105 is located in the high-concentration region 102. The bottom wall of the gate trench 105 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 has an off-angle inclined in the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 105 may be formed in a curved shape toward the second main surface 4.

[0173] The gate trench 105 has a first depth D1. The first depth D1 may be 0.5 μm or more and 3 μm or less. The first depth D1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0174] The width of the gate trench 105 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of the gate trench 105 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0175] The opening edge portion of the gate trench 105 includes an inclined portion that slopes downward from the first main surface 3 toward the inside of the gate trench 105. The opening edge portion of the gate trench 105 is a portion that connects the first main surface 3 and the side wall of the gate trench 105. The inclined portion of the gate trench 105 is formed in a curved shape that is recessed toward the SiC chip 2. The inclined portion of the gate trench 105 may be formed in a curved shape toward the gate trench 105. The inclined portion of the gate trench 105 alleviates the electric field concentration with respect to the opening edge portion of the gate trench 105.

[0176] The gate insulating layer 106 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 106 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in an arbitrary order. The gate insulating layer 106 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the gate insulating layer 106 has a single-layer structure composed of a silicon oxide layer.

[0177] The gate insulating layer 106 is formed in a film shape along the inner wall of the gate trench 105 and partitions a recessed space in the gate trench 105. The gate insulating layer 106 includes a first region 108, a second region 109, and a third region 110. The first region 108 is formed along the side wall of the gate trench 105. The second region 109 is formed along the bottom wall of the gate trench 105. The third region 110 partially covers the first main surface 3 through the opening edge portion of the gate trench 105.

[0178] The thickness of the first region 108 may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 109 may be 0.05 μm or more and 0.5 μm or less. The thickness of the second region 109 may exceed the thickness of the first region 108. The thickness of the third region 110 may be 0.05 μm or more and 0.5 μm or less. The thickness of the third region 110 may exceed the thickness of the first region 108.

[0179] The gate insulating layer 106 includes a bulging portion 111 that bulges toward the inside of the gate trench 105 at the opening edge portion. The bulging portion 111 is formed at the connection portion of the first region 108 and the third region 110 of the gate insulating layer 106. The bulging portion 111 is formed in a curved shape that curves inward toward the gate trench 105. The bulging portion 111 narrows the opening of the gate trench 105 at the opening edge portion. A gate insulating layer 106 without the bulging portion 111 may be formed. A gate insulating layer 106 having a uniform thickness may be formed.

[0180] The gate electrode 107 is embedded in the gate trench 105 with the gate insulating layer 106 interposed therebetween. Specifically, the gate electrode 107 is embedded in a recessed space partitioned by the gate insulating layer 106 within the gate trench 105. The gate electrode 107 has an electrode surface that is exposed from the opening of the gate trench 105. The electrode surface of the gate electrode 107 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 105. The electrode surface of the gate electrode 107 is narrowed by the bulging portion 111 of the gate insulating layer 106.

[0181] The gate electrode 107 is made of a conductive material other than a metal material. Preferably, the gate electrode 107 is made of conductive polysilicon. In this form, the gate electrode 107 includes p-type polysilicon doped with p-type impurities.

[0182] The p-type impurity concentration of the gate electrode 107 is 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less may be sufficient. The p-type impurities of the gate electrode 107 may include at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 107 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form). The thickness of the gate electrode 107 may be 0.5 μm or more and 3 μm or less.

[0183] The semiconductor device 101 includes a first low-resistance layer 112 that covers the gate electrode 107. The first low-resistance layer 112 covers the gate electrode 107 within the gate trench 105. The first low-resistance layer 112 forms part of the trench gate structure 104.

[0184] The first low-resistance layer 112 includes a conductive material having a sheet resistance less than that of the gate electrode 107. The sheet resistance of the first low-resistance layer 112 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The thickness of the first low-resistance layer 112 may be 0.01 μm or more and 3 μm or less. The thickness of the first low-resistance layer 112 is preferably less than the thickness of the gate electrode 107.

[0185] Specifically, the first low-resistance layer 112 includes a polysilicide layer. The polysilicide layer is formed by siliciding the surface layer portion of the gate electrode 107 with a metal material. That is, the electrode surface of the gate electrode 107 is formed by the first low-resistance layer 112. Specifically, the polysilicide layer consists of a p-type polysilicide layer containing p-type impurities added to the gate electrode 107. The polysilicide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0186] The sheet resistance within the gate trench 105 in which the gate electrode 107 and the first low-resistance layer 112 are embedded is less than the sheet resistance of the gate electrode 107 alone. The sheet resistance within the gate trench 105 is preferably less than or equal to the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance within the gate trench 105 is approximated to the sheet resistance of the first low-resistance layer 112. The sheet resistance within the gate trench 105 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The sheet resistance within the gate trench 105 is preferably less than 10 Ω / sq.

[0187] The first low-resistance layer 112 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. In particular, among these types, NiSi, CoSi2, and TiSi2 are suitable as the polysilicide layer for forming the first low-resistance layer 112 because the resistivity value and temperature dependence are relatively small. Most preferably, the first low-resistance layer 112 is made of CoSi2 which has the property of less diffusion into other regions.

[0188] The first low-resistance layer 112 includes a contact portion in contact with the gate insulating layer 106. Specifically, the contact portion of the first low-resistance layer 112 is in contact with the third region 110 (bulge portion 111) of the gate insulating layer 106. Thereby, the current path between the first low-resistance layer 112 and the SiC epitaxial layer 7 can be suppressed. In particular, the design of connecting the contact portion of the first low-resistance layer 112 to a relatively thick corner portion in the gate insulating layer 106 is effective in reducing the risk of current path.

[0189] By embedding p-type polysilicon having a work function different from that of n-type polysilicon into the gate trench 105, the gate threshold voltage Vth can be increased by about 1V. However, p-type polysilicon has a sheet resistance that is several tens of times (about 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is adopted as the material of the gate electrode 107, the energy loss increases as the parasitic resistance (hereinafter simply referred to as "gate resistance") in the gate trench 105 increases.

[0190] Therefore, in the semiconductor device 101, the first low-resistance layer 112 (p-type polyside) is formed on the gate electrode 107 (p-type polysilicon). According to the first low-resistance layer 112, the sheet resistance in the gate trench 105 can be reduced while allowing an increase in the gate threshold voltage Vth.

[0191] For example, according to the structure having the first low-resistance layer 112, the sheet resistance can be reduced to 1 / 100 or less compared to the structure without the first low-resistance layer 112. According to the structure having the first low-resistance layer 112, the sheet resistance can be reduced to 1 / 5 or less compared to the gate electrode 107 containing n-type polysilicon.

[0192] As a result, the gate resistance can be reduced, and current can be efficiently diffused along the trench gate structure 104. That is, the first low-resistance layer 112 is formed as a current diffusion layer that diffuses current within the gate trench 105. In particular, in the case of the gate trench 105 having a length on the order of millimeters (a length of 1 mm or more), it takes time for current transmission, but according to the first low-resistance layer 112, the switching delay can be appropriately suppressed.

[0193] According to the structure having the first low-resistance layer 112, it is not necessary to increase the p-type impurity concentration in the SiC epitaxial layer 7 in order to increase the gate threshold voltage Vth. Therefore, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in channel resistance.

[0194] The semiconductor device 101 includes a plurality of trench source structures 121 respectively formed in regions between adjacent trench gate structures 104. The plurality of trench source structures 121 are formed at intervals in the second direction Y in a manner sandwiching one trench gate structure 104.

[0195] The plurality of trench source structures 121 are each formed in a strip shape extending along the first direction X. The plurality of trench source structures 121 are formed in a stripe shape extending along the first direction X in a plan view.

[0196] The pitch PS between the central portions of the trench source structures 121 adjacent to the second direction Y may be 1 μm or more and 5 μm or less. The pitch PS may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. The pitch PS is preferably 1.5 μm or more and 3 μm or less.

[0197] Each trench source structure 121 includes a source trench 122, a source insulating layer 123, and a source electrode 124. In FIG. 10, the source electrode 124 is indicated by hatching.

[0198] The source trench 122 is formed in the SiC epitaxial layer 7. The source trench 122 includes sidewalls and a bottom wall. The sidewalls forming the long sides of the source trench 122 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of the source trench 122 are formed by the m-plane of the SiC single crystal.

[0199] The bottom wall of the source trench 122 is located in the high-concentration region 102. The bottom wall of the source trench 122 is located in the region on the second main surface 4 side with respect to the bottom wall of the gate trench 105. The bottom wall of the source trench 122 is located in the region between the bottom wall of the gate trench 105 and the low-concentration region 103 with respect to the normal direction Z.

[0200] The bottom wall of the source trench 122 faces the c-plane of the SiC single crystal. The bottom wall of the source trench 122 has an off-angle inclined in the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the source trench 122 may be formed parallel to the first main surface 3. The bottom wall of the source trench 122 may be formed in a curved shape toward the second main surface 4.

[0201] The source trench 122 has a second depth D2 that exceeds the first depth D1 of the gate trench 105. The ratio DS / DG of the second depth D2 to the first depth D1 may be 1.5 or more under the condition that the source trench 122 is located within the high-concentration region 102. The ratio DS / DG is preferably 2 or more.

[0202] The second depth D2 may be 0.5 μm or more and 10 μm or less. The second depth D2 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. A source trench 122 having a second depth D2 substantially equal to the first depth D1 may be formed.

[0203] The source trench 122 includes a first trench portion 125 and a second trench portion 126. The first trench portion 125 is formed on the opening side of the source trench 122. The first trench portion 125 has a first width W1 with respect to the second direction Y. The first trench portion 125 may be formed in a tapered shape in which the first width W1 narrows from the first main surface 3 toward the bottom wall side.

[0204] The first trench portion 125 is preferably formed in a region on the first main surface 3 side with respect to the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 is preferably less than the first depth D1 of the gate trench 105. A first trench portion 125 may be formed across the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 may exceed the first depth D1 of the gate trench 105.

[0205] The depth of the first trench portion 125 may be 0.1 μm or more and 2 μm or less. The depth of the first trench portion 125 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0206] The first width W1 of the first trench portion 125 may be greater than or equal to the width of the gate trench 105, or may be less than the width of the gate trench 105. The first width W1 is preferably greater than the width of the gate trench 105. The first width W1 may be 0.1 μm or more and 2 μm or less. The first width W1 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0207] The second trench portion 126 is formed on the bottom wall side of the source trench 122. The second trench portion 126 is formed in a region between the first trench portion 125 and the bottom of the SiC epitaxial layer 7 with respect to the normal direction Z, and crosses the bottom wall of the gate trench 105. With respect to the normal direction Z, the depth of the second trench portion 126 with reference to the first trench portion 125 preferably exceeds the first depth D1 of the gate trench 105.

[0208] The second trench portion 126 has a second width W2 that is less than the first width W1 in the second direction Y. The second width W2 may be greater than or equal to the width of the gate trench 105, or may be less than the width of the gate trench 105, under the condition of being less than the first width W1.

[0209] The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and less than 2 μm. Of course, a second trench portion 126 having a second width W2 that is approximately equal to the first width W1 may be formed.

[0210] The overall opening width of the source trench 122 is preferably formed to be approximately the same as the opening width of the gate trench 105. That the opening width of the source trench 122 is approximately the same as the opening width of the gate trench 105 means that the opening width of the source trench 122 is within the range of ±20% of the opening width of the gate trench 105.

[0211] The side wall of the second trench portion 126 may extend along the normal direction Z. The angle formed by the side wall of the second trench portion 126 with respect to the first main surface 3 in the SiC chip 2 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The side wall of the second trench portion 126 may be formed substantially perpendicular to the first main surface 3. The second trench portion 126 may be formed in a tapered shape in which the second width W2 narrows toward the bottom wall side from the first trench portion 125.

[0212] The source insulating layer 123 contains at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. The source insulating layer 123 may have a laminated structure in which a silicon oxide layer and a silicon nitride layer are laminated in an arbitrary order. The source insulating layer 123 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. In this form, the source insulating layer 123 has a single-layer structure composed of a silicon oxide layer.

[0213] The source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122 and partitions a recess space in the source trench 122. Specifically, the source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122 so as to expose the first trench portion 125 and cover the second trench portion 126.

[0214] Thereby, the source insulating layer 123 partitions a recess space in the second trench portion 126. The source insulating layer 123 has a side wall window portion 127 that exposes the first trench portion 125.

[0215] The source insulating layer 123 includes a first region 128 and a second region 129. The first region 128 is formed along the side wall of the source trench 122. The second region 129 is formed along the bottom wall of the source trench 122. The thickness of the first region 128 is less than the thickness of the second region 129. The thickness of the first region 128 may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 129 may be 0.05 μm or more and 0.5 μm or less.

[0216] The thickness of the first region 128 may be approximately equal to the thickness of the first region 128 of the gate insulating layer 106. The thickness of the second region 129 may be approximately equal to the thickness of the second region 129 of the gate insulating layer 106. A source insulating layer 123 having a uniform thickness may be formed.

[0217] The source electrode 124 is embedded in the source trench 122 with the source insulating layer 123 interposed therebetween. Specifically, the source electrode 124 is embedded in the first trench portion 125 and the second trench portion 126 with the source insulating layer 123 interposed therebetween.

[0218] The source electrode 124 is embedded in a recessed space partitioned by the second trench portion 126 on the bottom wall side of the source trench 122. The source electrode 124 has a side wall contact portion 130 that contacts the side wall of the first trench portion 125 exposed from the side wall window portion 127 on the opening side of the source trench 122.

[0219] The source electrode 124 has an electrode surface exposed from the opening of the source trench 122. The electrode surface of the source electrode 124 is formed in a curved shape that is recessed toward the bottom wall of the source trench 122. The electrode surface of the source electrode 124 may be formed parallel to the first main surface 3.

[0220] In the normal direction Z, the thickness of the source electrode 124 may be 0.5 μm or more and 10 μm or less. The thickness of the source electrode 124 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0221] The source electrode 124 is made of a conductive material other than a metal material. The source electrode 124 is preferably made of conductive polysilicon. In this form, the source electrode 124 includes p-type polysilicon doped with p-type impurities.

[0222] The p-type impurity concentration of the source electrode 124 is 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less. The p-type impurity concentration of the source electrode 124 is preferably equal to the p-type impurity concentration of the gate electrode 107. The p-type impurities of the source electrode 124 may include at least one of boron, aluminum, indium, and gallium.

[0223] The semiconductor device 101 includes a second low-resistance layer 131 that covers the source electrode 124. The second low-resistance layer 131 covers the source electrode 124 in the source trench 122. The second low-resistance layer 131 forms a part of the trench source structure 121. The second low-resistance layer 131 has the same structure as the first low-resistance layer 112. For the description of the second low-resistance layer 131, the description of the first low-resistance layer 112 is applied mutatis mutandis.

[0224] The semiconductor device 101 includes a p-type body region 141 formed in the surface layer portion of the first main surface 3 in the active region 8. The body region 141 defines the active region 8. The p-type impurity concentration of the body region 141 is less than the p-type impurity concentrations of the gate electrode 107 and the source electrode 124. The peak value of the p-type impurity concentration of the body region 141 is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3It may be as follows.

[0225] The body region 141 covers the side walls of the gate trench 105 and the source trench 122 in the surface layer portion of the first main surface 3. The body region 141 is formed in a region on the side of the first main surface 3 with respect to the bottom wall of the gate trench 105. The body region 141 faces the gate electrode 107 with the gate insulating layer 106 interposed therebetween.

[0226] The body region 141 is formed in a region on the side of the first trench portion 125 with respect to the second trench portion 126. The body region 141 covers the first trench portion 125. The body region 141 is connected to the side wall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. Thereby, the body region 141 is source-grounded in the SiC chip 2. The body region 141 may cover a part of the second trench portion 126. In this case, the body region 141 may face the source electrode 124 with a part of the source insulating layer 123 interposed therebetween.

[0227] The semiconductor device 101 includes an n + -type source region 142 formed in the surface layer portion of the body region 141. The source region 142 is formed along the gate trench 105. The peak value of the n-type impurity concentration in the source region 142 exceeds the peak value of the n-type impurity concentration in the high-concentration region 102. The peak value of the n-type impurity concentration in the source region 142 is 1.0×10 18 cm -3 or more and may be 1.0×10 21 cm -3 or less.

[0228] The source region 142 covers the side walls of the gate trench 105 and the source trench 122 in the surface layer portion of the body region 141. The source region 142 faces the gate electrode 107 with the gate insulating layer 106 interposed therebetween. The source region 142 preferably faces the first low-resistance layer 112 with the gate insulating layer 106 interposed therebetween.

[0229] The source region 142 is further formed in a region on the side of the first trench portion 125 with respect to the second trench portion 126. The source region 142 covers the first trench portion 125. The source region 142 is connected to the sidewall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. Thereby, the source region 142 is source-grounded within the SiC chip 2.

[0230] In this form, the source region 142 has a concealed portion concealed by the third region 110 of the gate insulating layer 106 on the first main surface 3, and an exposed portion exposed from the third region 110. The entire area of the source region 142 may be covered by the third region 110.

[0231] The portion along the sidewall of the gate trench 105 in the source region 142 defines a channel of the MISFET with the high-concentration region 102 within the body region 141. The ON / OFF of the channel is controlled by the gate electrode 107.

[0232] The semiconductor device 101 includes a plurality of p-type contact regions 143 formed in the surface layer portion of the first main surface 3 in the active region 8. + The peak value of the p-type impurity concentration of each contact region 143 exceeds the peak value of the p-type impurity concentration of the body region 141. The peak value of the p-type impurity concentration of each contact region 143 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less.

[0233] The plurality of contact regions 143 are respectively formed in regions along the plurality of source trenches 122. Specifically, the plurality of contact regions 143 are formed in a one-to-multiple relationship with respect to each corresponding one source trench 122. The plurality of contact regions 143 are respectively formed at intervals along the corresponding source trench 122. The plurality of contact regions 143 are respectively formed at intervals from the gate trench 105.

[0234] Each contact region 143 covers the corresponding first trench portion 125. Each contact region 143 is interposed between the sidewall contact portion 130 of the source electrode 124 and the source region 142 in the corresponding first trench portion 125. Each contact region 143 is further interposed between the sidewall contact portion 130 of the source electrode 124 and the body region 141 in the corresponding first trench portion 125.

[0235] As a result, each contact region 143 is electrically connected to the source electrode 124, the body region 141, and the source region 142. Each contact region 143 is source-grounded within the SiC chip 2.

[0236] The portion of each contact region 143 that covers the first trench portion 125 is drawn toward the gate trench 105. The portion of each contact region 143 that covers the first trench portion 125 is formed in a region on the first main surface 3 side with respect to the bottom of the body region 141. The portion of each contact region 143 that covers the first trench portion 125 may extend to an intermediate region between the gate trench 105 and the source trench 122.

[0237] Each contact region 143 further covers the corresponding second trench portion 126. Each contact region 143 faces the source electrode 124 with the source insulating layer 123 interposed therebetween in the corresponding second trench portion 126.

[0238] Each contact region 143 further covers the bottom wall of the corresponding source trench 122. Each contact region 143 faces the source electrode 124 with the bottom wall of the corresponding source trench 122 interposed therebetween. The bottom of each contact region 143 may be formed parallel to the bottom wall of the corresponding source trench 122.

[0239] The semiconductor device 101 includes a plurality of p-type deep well regions 144 formed in the surface layer portion of the first main surface 3 in the active region 8. The peak value of the p-type impurity concentration in each deep well region 144 is less than the peak value of the p-type impurity concentration in the contact region 143.

[0240] The peak value of the p-type impurity concentration in each deep well region 144 may be equal to or greater than the peak value of the p-type impurity concentration in the body region 141, or may be less than the peak value of the p-type impurity concentration in the body region 141. The peak value of the p-type impurity concentration in each deep well region 144 is 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less.

[0241] The plurality of deep well regions 144 are formed in a one-to-one correspondence with the plurality of source trenches 122. Each deep well region 144 is formed in a strip shape extending along the corresponding source trench 122 in a plan view. Each deep well region 144 is formed in the high-concentration region 102. Each deep well region 144 is formed in a region on the second main surface 4 side with respect to the body region 141. Each deep well region 144 is continuous with the body region 141.

[0242] Each deep well region 144 includes a portion covering the corresponding second trench portion 126. Each deep well region 144 includes a portion covering the corresponding second trench portion 126 with the contact region 143 interposed therebetween. Each deep well region 144 further includes a portion covering the bottom wall of the corresponding source trench 122. Each deep well region 144 includes a portion covering the bottom wall of the corresponding source trench 122 with the contact region 143 interposed therebetween.

[0243] Each deep well region 144 has a bottom portion located on the side of the second main surface 4 with respect to the bottom wall of the gate trench 105. The bottom portion of each deep well region 144 may be formed parallel to the bottom wall of each source trench 122. The plurality of deep well regions 144 are preferably formed at a constant depth.

[0244] Each deep well region 144 forms a pn junction with the high-concentration region 102. From this pn junction, a depletion layer spreads toward the gate trench 105. The depletion layer may overlap the bottom wall of the gate trench 105.

[0245] In the semiconductor device 101 including only the pn junction diode, due to the structure without trenches, the problem of electric field concentration in the SiC chip 2 is less. Each deep well region 144 makes the trench gate type MISFET approach the structure of the pn junction diode. Thereby, in the trench gate type MISFET, the electric field in the SiC chip 2 can be relaxed.

[0246] According to the deep well region 144 having a bottom portion on the side of the second main surface 4 with respect to the bottom wall of the gate trench 105, the electric field concentration with respect to the gate trench 105 can be appropriately relaxed by the depletion layer. Narrowing the pitch PS between the plurality of source trenches 122 (deep well regions 144) is effective in relaxing the electric field concentration and improving the breakdown voltage.

[0247] The plurality of deep well regions 144 are preferably formed at a constant depth. Thereby, it is possible to suppress the breakdown voltage (for example, breakdown withstand) of the SiC chip 2 from being limited by each deep well region 144, and thus the breakdown voltage can be appropriately improved.

[0248] By using the source trench 122, the deep well region 144 can be appropriately formed in a relatively deep region of the SiC chip 2. Since the deep well region 144 can be formed along the source trench 122, variations in the depths of the plurality of deep well regions 144 can be appropriately suppressed.

[0249] In this form, a part of the high-concentration region 102 is interposed in the region between the plurality of deep well regions 144. Thereby, the JFET (Junction Field Effect Transistor) resistance can be reduced in the region between the plurality of deep well regions 144.

[0250] In this form, the bottom of each deep well region 144 is located in the high-concentration region 102. Thereby, a current path can be formed in the lateral direction parallel to the first main surface 3 in the region directly below each deep well region 144 in the high-concentration region 102. As a result, the current spreading resistance can be reduced. The low-concentration region 103 increases the breakdown voltage of the SiC chip 2 in such a structure.

[0251] The main surface insulating layer 12 covers the entire area of the first main surface 3. The main surface insulating layer 12 covers the source region 142 and the contact region 143 in the active region 8. Specifically, the main surface insulating layer 12 covers the entire area of the source region 142 and the entire area of the contact region 143 in a cross-sectional view along the second direction Y in the active region 8. The main surface insulating layer 12 covers the entire area of the source region 142 and the entire area of the contact region 143 in a plan view.

[0252] More specifically, the main surface insulating layer 12 covers the source electrode 124 across the first trench portion 125 in the active region 8. The main surface insulating layer 12 covers the sidewall contact portion 130 of the source electrode 124 on the first main surface 3.

[0253] The main surface insulating layer 12 has a plurality of contact openings 151 that expose a plurality of source electrodes 124 in the active region 8. The plurality of contact openings 151 are formed in a one-to-one correspondence with the plurality of source electrodes 124. Each contact opening 151 may be formed in a strip shape extending along the trench source structure 121. Each contact opening 151 is formed in a region surrounded by the side walls of the source trench 122 (first trench portion 125) in a plan view.

[0254] Each contact opening 151 exposes the source electrode 124 at a distance inward from the side wall of the source trench 122 (first trench portion 125). The contact opening 151 exposes only the source electrode 124. The opening edge portion of the contact opening 151 is formed in a curved shape toward the inside of the contact opening 151.

[0255] A recess 152 that is recessed toward the bottom wall of the source trench 122 is formed on the electrode surface of the source electrode 124. The recess 152 may be formed in a strip shape extending along the trench source structure 121. The recess 152 is formed in a region surrounded by the side walls of the source trench 122 (first trench portion 125) in a plan view.

[0256] The recess 152 is formed at a distance inward from the side wall of the source trench 122 (first trench portion 125). The recess 152 exposes the second low-resistance layer 131. The recess 152 may penetrate the second low-resistance layer 131. The contact opening 151 communicates with the recess 152 of the source electrode 124.

[0257] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this form, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. The periphery of the main surface insulating layer 12 may be formed at a distance inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 exposes a portion located in the outer region 9 on the first main surface 3.

[0258] The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness of the main surface insulating layer 12 is 0.5 μm or more and 5 μm or less.

[0259] The first main surface electrode 21 is formed on the main surface insulating layer 12. The thickness T1 of the first main surface electrode 21 may be 1 μm or more and 100 μm or less. The thickness T1 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. It is preferable that the thickness T1 is 20 μm or more and 60 μm or less.

[0260] The first main surface electrode 21 includes a gate main surface electrode 153, a gate wiring electrode 154, and a source main surface electrode 155. A gate voltage is applied to the gate main surface electrode 153 (gate wiring electrode 154). The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source main surface electrode 155. The source voltage may be a reference voltage (for example, GND voltage).

[0261] The gate main surface electrode 153 is formed in the active region 8. The gate main surface electrode 153 is formed in the region on the side of the first side surface 5A in plan view. Specifically, the gate main surface electrode 153 is formed at the center of the first side surface 5A in plan view. The gate main surface electrode 153 may be formed at a corner connecting any two of the side surfaces 5A to 5D in plan view. The gate main surface electrode 153 may be formed in a square shape in plan view.

[0262] The gate wiring electrode 154 is drawn out from the gate main surface electrode 153 and extends in a strip shape along the periphery of the active region 8. In this form, the gate wiring electrode 154 extends along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D, partitioning the inside of the active region 8 from three directions. The gate wiring electrode 154 is electrically connected to the gate electrode 107 through the main surface insulating layer 12. The electrical signal from the gate main surface electrode 153 is transmitted to the gate electrode 107 through the gate wiring electrode 154.

[0263] The source main surface electrode 155 is formed in the active region 8 at a distance from the gate main surface electrode 153 and the gate wiring electrode 154. The source main surface electrode 155 covers the region partitioned by the gate main surface electrode 153 and the gate wiring electrode 154 and is formed in a C shape in plan view.

[0264] The source main surface electrode 155 is electrically connected to the source electrode 124 through the contact opening 151. That is, in this form, the source main surface electrode 155 made of a metal material is electrically connected to the source electrode 124 made of conductive polysilicon.

[0265] The first main surface electrodes 21 (gate main surface electrode 153, gate wiring electrode 154, and source main surface electrode 155) each have a stacked structure including a barrier electrode 22 and a main electrode 23 stacked in this order from the SiC chip 2 side.

[0266] In this form, the barrier electrode 22 includes at least one of a Ti layer and a TiN layer. The barrier electrode 22 preferably has a stacked structure including a Ti layer and a TiN layer stacked in this order from the SiC chip 2 side. The barrier electrode 22 may have a single-layer structure composed of a Ti layer or a TiN layer.

[0267] The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0268] The main electrode 23 is formed in a film shape on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 has a resistance value less than that of the barrier electrode 22. The main electrode 23 is made of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0269] The main electrode 23 may have a laminated structure in which two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer are laminated in an arbitrary order. The main electrode 23 may have a single-layer structure composed of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. Preferably, the main electrode 23 has a single-layer structure composed of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0270] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. Preferably, the thickness of the main electrode 23 is 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first main surface electrode 21 is approximated to the thickness of the main electrode 23.

[0271] The insulating layer 24 covers the first main surface electrode 21 on the first main surface 3. In FIG. 9, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the main surface insulating layer 12. The periphery of the insulating layer 24 is formed at an interval inward from the side surfaces 5A to 5D. Thereby, the insulating layer 24 exposes the peripheral portion of the main surface insulating layer 12.

[0272] The periphery of the insulating layer 24 demarcates the dicing street 25 between the side surfaces 5A to 5D. According to the dicing street 25, when cutting out the semiconductor device 101 from the wafer, it is not necessary to physically cut the insulating layer 24. Thereby, the semiconductor device 101 can be smoothly cut out from the wafer, and at the same time, peeling and deterioration of the insulating layer 24 can be suppressed. As a result, the insulating layer 24 can appropriately protect the objects to be protected such as the SiC chip 2 and the first main surface electrode 21.

[0273] The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in a direction orthogonal to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less.

[0274] The insulating layer 24 has a pad opening 26 that exposes the first main surface electrode 21. In this form, the pad opening 26 includes a gate pad opening 161 that exposes the gate main surface electrode 153 and a source pad opening 162 that exposes the source main surface electrode 155. The gate pad opening 161 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in plan view. The source pad opening 162 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in plan view. The planar shape of the gate pad opening 161 and the planar shape of the source pad opening 162 are arbitrary.

[0275] The insulating layer 24 specifically has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31 laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film shape along the main surface insulating layer 12, the gate main surface electrode 153, and the source main surface electrode 155. The inorganic insulating layer 30 includes a first gate inner wall 163, a first source inner wall 164, and a first outer wall 165. Hereinafter, the first gate inner wall 163, the first source inner wall 164, and the first outer wall 165 may be collectively referred to as the first wall surface.

[0276] The first gate inner wall 163 defines a first gate opening 166 that exposes a part of the gate main surface electrode 153. The first gate opening 166 forms a part of the gate pad opening 161. The first gate opening 166 has a planar shape similar to the planar shape of the gate main surface electrode 153 and exposes the inner part of the gate main surface electrode 153. The planar shape of the first gate opening 166 is arbitrary. The first gate opening 166 may be defined as a polygon having four sides parallel to the side surfaces 5A to 5D in plan view.

[0277] The first source inner wall 164 defines a first source opening 167 that exposes a part of the source main surface electrode 155. The first source opening 167 forms a part of the source pad opening 162. The first source opening 167 has a planar shape similar to the planar shape of the source main surface electrode 155 and exposes the inner part of the source main surface electrode 155. The planar shape of the first source opening 167 is arbitrary. The first source opening 167 may be defined as a polygon having four sides parallel to the side surfaces 5A to 5D in plan view.

[0278] The first outer wall 165 of the inorganic insulating layer 30 is formed at an interval inward from the side surfaces 5A to 5D and defines a part of the dicing street 25 between the side surfaces 5A to 5D. Thereby, the inorganic insulating layer 30 exposes the peripheral portion of the main surface insulating layer 12. The first outer wall 165 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view.

[0279] The angle formed between the first wall surface of the inorganic insulating layer 30 and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. It is preferable that the angle formed between the first wall surface and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is 45° or more and less than 90°. The angle of the first wall surface is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the first wall surface and the main surface of the first main surface electrode 21.

[0280] The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. It is preferable that the inorganic insulating layer 30 contains an insulating material different from the main surface insulating layer 12. In this form, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer.

[0281] It is preferable that the thickness T2 of the inorganic insulating layer 30 is less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness T2 is 1 μm or more and 5 μm or less. It is particularly preferable that the thickness T2 is 1 μm or more and 2 μm or less.

[0282] The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second gate inner wall 168, a second source inner wall 169, and a second outer wall 170. Hereinafter, the second gate inner wall 168, the second source inner wall 169, and the second outer wall 170 may be collectively referred to as the second wall surface.

[0283] Referring to FIG. 13, in this form, the second gate inner wall 168 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side. The second gate inner wall 168 defines a second gate opening 171 that exposes a part of the gate main surface electrode 153. The second gate opening 171 has a planar shape similar to the planar shape of the gate main surface electrode 153 and exposes the inner part of the gate main surface electrode 153. The planar shape of the second gate opening 171 is arbitrary. The second gate opening 171 may be defined in a polygonal shape having four sides parallel to the sides 5A to 5D in plan view.

[0284] The second gate opening 171 communicates with the first gate opening 166 of the inorganic insulating layer 30 and forms a gate pad opening 161 between the second gate opening 171 and the first gate opening 166. The second gate opening 171 surrounds the first gate opening 166 with a space therebetween and exposes a part of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a part of the main surface of the inorganic insulating layer 30 as a gate inner periphery 172 in the region between the first gate opening 166 and the second gate opening 171.

[0285] The width WG of the gate inner periphery 172 may be more than 0 μm and 10 μm or less. The width WG may be more than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The width WG is preferably 1 μm or more and 5 μm or less. The width WG is arbitrary, but it is preferably not more than the thickness T2 of the inorganic insulating layer 30 (WG ≦ T2). The width WG is particularly preferably 1 μm or more and 2 μm or less.

[0286] Referring to FIG. 14, in this embodiment, the second source inner wall 169 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side. The second source inner wall 169 defines a second source opening 173 that exposes a part of the source main surface electrode 155. The second source opening 173 has a planar shape similar to the planar shape of the source main surface electrode 155 and exposes the inner portion of the source main surface electrode 155. The planar shape of the second source opening 173 is arbitrary. The second source opening 173 may be defined in a polygonal shape having four sides parallel to the sides 5A to 5D in plan view.

[0287] The second source opening 173 communicates with the first source opening 167 of the inorganic insulating layer 30 and forms a source pad opening 162 between the second source opening 173 and the first source opening 167. The second source opening 173 surrounds the first source opening 167 with a space therebetween and exposes a part of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a part of the main surface of the inorganic insulating layer 30 as a source inner periphery 174 in the region between the first source opening 167 and the second source opening 173.

[0288] The width WS of the source inner periphery 174 may be greater than 0 μm and 10 μm or less. The width WS may be greater than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The width WS is preferably 1 μm or more and 5 μm or less. The width WS is arbitrary, but it is preferably not more than the thickness T2 of the inorganic insulating layer 30 (WS ≦ T2). The width WS is particularly preferably 1 μm or more and 2 μm or less.

[0289] In this embodiment, the second outer wall 170 of the organic insulating layer 31 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side. The second outer wall 170 is formed on the inorganic insulating layer 30 at a distance inward from the side surfaces 5A to 5D, and partitions a part of the dicing street 25 between the side surfaces 5A to 5D. Thereby, the organic insulating layer 31 exposes the peripheral portion of the main surface insulating layer 12. The second outer wall 170 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view.

[0290] The second outer wall 170 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 165 of the inorganic insulating layer 30. In this case, the dicing street 25 is partitioned by the second outer wall 170 of the organic insulating layer 31.

[0291] The angle formed between the second wall surface of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. Preferably, the angle formed between the second wall surface and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is 45° or more and less than 90°. The angle of the second wall surface is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the second wall surface and the main surface of the inorganic insulating layer 30.

[0292] The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 31 contains polyimide.

[0293] Preferably, the organic insulating layer 31 has a thickness T3 (T2 < T3) that exceeds the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and 10 or less. The ratio T3 / T2 may be greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, 8 or more and 10 or less. Preferably, the ratio T3 / T2 is 2 or more and 6 or less.

[0294] The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The thickness T3 is preferably 5 μm or more and 30 μm or less.

[0295] In this form, the rough surface region 39 of the first main surface electrode 21 includes the gate rough surface region 175 and the source rough surface region 176. The gate rough surface region 175 is formed on the exposed surface exposed from the gate pad opening 161 (the first gate opening 166 of the inorganic insulating layer 30) in the gate main surface electrode 153. The gate rough surface region 175 includes a depression formed in the region directly below the first gate inner wall 163. Thereby, the first gate inner wall 163 includes a portion that overhangs the gate rough surface region 175.

[0296] The source rough surface region 176 is formed on the exposed surface exposed from the source pad opening 162 (the first source opening 167 of the inorganic insulating layer 30) in the source main surface electrode 155. The source rough surface region 176 includes a depression formed in the region directly below the first source inner wall 164. Thereby, the first source inner wall 164 includes a portion that overhangs the source rough surface region 176.

[0297] In this form, the pad electrode 40 includes the gate pad electrode 181 and the source pad electrode 182. The gate pad electrode 181 includes a first Ni plating layer (metal layer) 183 formed on the gate main surface electrode 153 within the gate pad opening 161. The first Ni plating layer 183 corresponds to the Ni plating layer 41 according to the first embodiment.

[0298] The first Ni plating layer 183 covers the gate main surface electrode 153 within the first gate opening 166 and covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. The first Ni plating layer 183 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the gate main surface electrode 153 side. The first Ni plating layer 183 covers the organic insulating layer 31 within the second gate opening 171.

[0299] Referring to FIG. 13, specifically, the first Ni plating layer 183 has a first portion 183A that covers the gate main surface electrode 153 and a second portion 183B that covers the gate inner peripheral edge 172 of the inorganic insulating layer 30.

[0300] The first portion 183A of the first Ni plating layer 183 fills the gate rough surface region 175 within the first gate opening 166 and covers the gate main surface electrode 153. The first portion 183A covers the entire area of the first gate inner wall 163 of the inorganic insulating layer 30 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0301] The second portion 183B of the first Ni plating layer 183 is drawn out from the first portion 183A toward the organic insulating layer 31 side within the second gate opening 171. The second portion 183B is formed in an arc shape toward the organic insulating layer 31 starting from the opening end of the first gate opening 166.

[0302] The second portion 183B covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. As a result, the second portion 183B faces the gate main surface electrode 153 with the gate inner peripheral edge 172 of the inorganic insulating layer 30 interposed therebetween. The second portion 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0303] In this form, the second part 183B further covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. The second part 183B covers the region on the inorganic insulating layer 30 side with respect to the middle part of the second gate inner wall 168 of the organic insulating layer 31. In other words, the second part 183B covers the organic insulating layer 31 such that the exposed area of the second gate inner wall 168 (organic insulating layer 31) exceeds the hidden area of the second gate inner wall 168 (organic insulating layer 31). Thus, the first Ni plating layer 183 is formed such that the first part 183A and the second part 183B engage from different two directions with the opening end of the first gate opening 166.

[0304] The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value (T2 + WG) obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T2 + WG < T4). This is the condition for the first Ni plating layer 183 to contact the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153.

[0305] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5.

[0306] The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less.

[0307] The gate pad electrode 181 is made of a metal material different from that of the first Ni plating layer 183, and includes a first outer surface plating layer 184 that covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 corresponds to the outer surface plating layer 42 according to the first embodiment.

[0308] The first outer surface plating layer 184 has a thickness T5 (T5 < T4) less than the thickness T4 of the first Ni plating layer 183. The first outer surface plating layer 184 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0309] The first outer surface plating layer 184 has a gate terminal surface 185A that is externally connected via a conductive bonding material (e.g., solder). The gate terminal surface 185A is located on the first Ni plating layer 183 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). Thereby, the first outer surface plating layer 184 exposes a part of the second gate inner wall 168 of the organic insulating layer 31.

[0310] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a first Au plating layer 186 laminated in this order from the first Ni plating layer 183 side. The first Pd plating layer 185 and the first Au plating layer 186 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment.

[0311] The first Pd plating layer 185 is formed in a film shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 with a space from the opening end of the second gate opening 171 toward the inorganic insulating layer 30 side. The first Pd plating layer 185 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0312] The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0313] The first Au plating layer 186 is formed in a film shape along the outer surface of the first Pd plating layer 185. The first Au plating layer 186 covers the first Pd plating layer 185 with a space from the opening end of the second gate opening 171 toward the inorganic insulating layer 30 side. The first Au plating layer 186 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0314] The first Au plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0315] In this form, an example in which the first outer surface plating layer 184 has a laminated structure including the first Pd plating layer 185 and the first Au plating layer 186 has been described. However, the first outer surface plating layer 184 having the same form as any one of the outer surface plating layers 42 according to the second to fourth exemplary forms shown in FIGS. 4A to 4D described above may be employed.

[0316] The source pad electrode 182 includes a second Ni plating layer (metal layer) 193 formed on the source main surface electrode 155 within the source pad opening 162. The second Ni plating layer 193 corresponds to the Ni plating layer 41 according to the first embodiment.

[0317] The second Ni plating layer 193 covers the source main surface electrode 155 within the first source opening 167 and covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. The second Ni plating layer 193 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the source main surface electrode 155 side. The second Ni plating layer 193 covers the organic insulating layer 31 within the second source opening 173.

[0318] Referring to FIG. 14, specifically, the second Ni plating layer 193 has a first portion 193A that covers the source main surface electrode 155 and a second portion 193B that covers the source inner peripheral edge 174 of the inorganic insulating layer 30.

[0319] The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 within the first source opening 167 to cover the source main surface electrode 155. The first portion 193A covers the entire area of the first source inner wall 164 of the inorganic insulating layer 30 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0320] The second portion 193B of the second Ni plating layer 193 is drawn out from the first portion 193A toward the organic insulating layer 31 side within the second source opening 173. The second portion 193B is formed in an arc shape toward the organic insulating layer 31 starting from the opening end of the first source opening 167.

[0321] The second portion 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. As a result, the second portion 193B faces the source main surface electrode 155 with the source inner peripheral edge 174 of the inorganic insulating layer 30 interposed therebetween. The second portion 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0322] In this form, the second part 193B further covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. The second part 193B covers the region on the inorganic insulating layer 30 side with respect to the middle part of the second source inner wall 169 of the organic insulating layer 31. In other words, the second part 193B covers the organic insulating layer 31 such that the exposed area of the second source inner wall 169 (organic insulating layer 31) exceeds the hidden area of the second source inner wall 169 (organic insulating layer 31). Thus, the second Ni plating layer 193 is formed such that the first part 193A and the second part 193B engage from different two directions with the opening end of the first source opening 167.

[0323] The second Ni plating layer 193 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value obtained by adding the width WS of the source inner peripheral edge 174 to the thickness T2 of the inorganic insulating layer 30 (T2 + WS < T4). This is the condition for the second Ni plating layer 193 to contact the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155.

[0324] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5.

[0325] The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less.

[0326] The source pad electrode 182 is made of a metal material different from the second Ni plating layer 193, and includes a second outer surface plating layer 194 that covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer surface plating layer 194 corresponds to the outer surface plating layer 42 according to the first embodiment.

[0327] The second outer surface plating layer 194 has a thickness T5 (T5 < T4) less than the thickness T4 of the second Ni plating layer 193. The second outer surface plating layer 194 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0328] The second outer surface plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (e.g., solder). The source terminal surface 194A is located on the second Ni plating layer 193 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer surface plating layer 194 exposes a part of the second source inner wall 169 of the organic insulating layer 31.

[0329] Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the second Ni plating layer 193 side. The second Pd plating layer 195 and the second Au plating layer 196 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment.

[0330] The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 with a space from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side. The second Pd plating layer 195 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0331] The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0332] The second Au plating layer 196 is formed in a film shape along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a space from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side. The second Au plating layer 196 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0333] The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0334] In this form, an example in which the second outer surface plating layer 194 has a laminated structure including the second Pd plating layer 195 and the second Au plating layer 196 has been described. However, a second outer surface plating layer 194 having the same form as any one of the outer surface plating layers 42 according to the second to fourth exemplary forms shown in FIGS. 4A to 4D described above may be employed.

[0335] The second main surface electrode 46 covers the entire area of the second main surface 4. The second main surface electrode 46 forms an ohmic contact with the second main surface 4. The second main surface electrode 46 is formed as a drain electrode.

[0336] The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may have a stacked structure in which at least two of the Ti layer, the Ni layer, the Pd layer, the Au layer, and the Ag layer are stacked in an arbitrary order. The second main surface electrode 46 may have a single-layer structure composed of the Ti layer, the Ni layer, the Pd layer, the Au layer, and the Ag layer. The second main surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this form, the second main surface electrode 46 has a stacked structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer stacked in this order from the second main surface 4 side.

[0337] As described above, the semiconductor device 101 including the MISFET instead of the SBD can also achieve the same effects as those described for the semiconductor device 1.

[0338] FIG. 15 is a corresponding diagram of FIG. 12 and is a cross-sectional view showing a semiconductor device 201 according to a fourth embodiment of the present invention. FIG. 16 is an enlarged view of a region XVI shown in FIG. 15. FIG. 17 is an enlarged view of a region XVII shown in FIG. 15. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101 (see FIGS. 9 to 14), the same reference numerals will be given and the description will be omitted.

[0339] Referring to FIGS. 15 to 17, the organic insulating layer 31 exposes the gate inner peripheral edge 172 of the inorganic insulating layer 30 in a region between the first gate opening 166 and the second gate opening 171. The width WG of the gate inner peripheral edge 172 preferably exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < WG).

[0340] The ratio WG / T2 of the width WG of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 10. The ratio WG / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 4, greater than or equal to 4 and less than or equal to 6, greater than or equal to 6 and less than or equal to 8, or greater than or equal to 8 and less than or equal to 10. The ratio WG / T2 is preferably greater than or equal to 2 and less than or equal to 5. The width WG may be greater than 0 μm and less than or equal to 10 μm. The width WG may be greater than 0 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm.

[0341] The first Ni plating layer 183 is formed on the gate main surface electrode 153 within the gate pad opening 161. The first Ni plating layer 183 covers the gate main surface electrode 153 within the first gate opening 166 and covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. The first Ni plating layer 183 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the gate main surface electrode 153 side. The first Ni plating layer 183 covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second gate opening 171.

[0342] Referring to FIG. 16, specifically, the first Ni plating layer 183 has a first portion 183A that covers the gate main surface electrode 153 and a second portion 183B that covers the gate inner peripheral edge 172 of the inorganic insulating layer 30.

[0343] The first portion 183A of the first Ni plating layer 183 fills the gate rough surface region 175 within the first gate opening 166 to cover the gate main surface electrode 153. The first portion 183A covers the entire area of the first gate inner wall 163 of the inorganic insulating layer 30 within the first gate opening 166 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0344] The second part 183B of the first Ni plating layer 183 is drawn out from the first part 183A toward the organic insulating layer 31 within the second gate opening 171. The second part 183B is formed in an arc shape that extends from the opening end of the first gate opening 166 toward the second gate inner wall 168 of the organic insulating layer 31.

[0345] The second part 183B covers the gate inner periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. In this form, the second part 183B partially covers the gate inner periphery 172 of the inorganic insulating layer 30 at an interval from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 such that a part of the inner periphery 38 of the inorganic insulating layer 30 is exposed.

[0346] As a result, the first Ni plating layer 183 exposes a part of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31. The second part 183B faces the gate main surface electrode 153 with the gate inner periphery 172 of the inorganic insulating layer 30 interposed therebetween. The second part 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion that extends in the width direction of the inorganic insulating layer 30.

[0347] The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the value (T2 + WG) obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WG). This is a condition for the first Ni plating layer 183 to expose the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153.

[0348] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm.

[0349] The first outer surface plating layer 184 covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 has a thickness T5 (T5 < T4) less than the thickness T4 of the first Ni plating layer 183. In this form, the first outer surface plating layer 184 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at a distance from the second gate inner wall 168 of the organic insulating layer 31 to the first gate inner wall 163 side of the inorganic insulating layer 30 within the second gate opening 171 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0350] The first outer surface plating layer 184 has a gate terminal surface 184A that is externally connected via a conductive bonding material (e.g., solder). The gate terminal surface 184A is located on the first Ni plating layer 183 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). Thereby, the first outer surface plating layer 184 exposes a part of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0351] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a Pd plating layer 186 laminated in this order from the first Ni plating layer 183 side. The first Pd plating layer 185 is formed in a film shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 at a distance from the opening end of the second gate opening 171 to the inorganic insulating layer 30 side.

[0352] The first Pd plating layer 185 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at an interval from the second gate inner wall 168 of the organic insulating layer 31 to the first gate inner wall 163 side of the inorganic insulating layer 30 in the second gate opening 171 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the first Pd plating layer 185 exposes a part of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire area of the second gate inner wall 168 of the organic insulating layer 31 in the second gate opening 171.

[0353] The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0354] The Pd plating layer 186 is formed in a film shape along the outer surface of the first Pd plating layer 185. The Pd plating layer 186 covers the first Pd plating layer 185 at an interval from the opening end of the second gate opening 171 to the inorganic insulating layer 30 side.

[0355] The Pd plating layer 186 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at an interval from the second gate inner wall 168 of the organic insulating layer 31 to the first gate inner wall 163 side of the inorganic insulating layer 30 in the second gate opening 171 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the Pd plating layer 186 exposes a part of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire area of the second gate inner wall 168 of the organic insulating layer 31 in the second gate opening 171.

[0356] The Pd plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0357] In this form, an example in which the first outer surface plating layer 184 has a laminated structure including the first Pd plating layer 185 and the Pd plating layer 186 has been described. However, a first outer surface plating layer 184 having the same form as any one of the outer surface plating layers 42 according to the second to fourth exemplary forms shown in FIGS. 8A to 8D described above may be adopted.

[0358] The organic insulating layer 31 exposes the source inner peripheral edge 174 of the inorganic insulating layer 30 in the region between the first source opening 167 and the second source opening 173. In this form, the width WS of the source inner peripheral edge 174 exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < WS).

[0359] The ratio WS / T2 of the width WS of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and 10 or less. The ratio WS / T2 may be more than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The ratio WS / T2 is preferably 2 or more and 5 or less. The width WS may be more than 0 μm and 10 μm or less. The width WS may be more than 0 μm and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0360] The second Ni plating layer 193 is formed on the source main surface electrode 155 within the source pad opening 162. The second Ni plating layer 193 covers the source main surface electrode 155 within the second source opening 173 and covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. The second Ni plating layer 193 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the source main surface electrode 155 side. The second Ni plating layer 193 covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second source opening 173.

[0361] Referring to FIG. 17, specifically, the second Ni plating layer 193 has a first portion 193A that covers the source main surface electrode 155 and a second portion 193B that covers the source inner peripheral edge 174 of the inorganic insulating layer 30.

[0362] The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 within the first source opening 167 and covers the source main surface electrode 155. The first portion 193A covers the entire area of the first source inner wall 164 of the inorganic insulating layer 30 within the first source opening 167 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of the inorganic insulating layer 30.

[0363] The second portion 193B of the second Ni plating layer 193 is drawn out from the first portion 193A toward the organic insulating layer 31 side within the second source opening 173. The second portion 193B is formed in an arc shape from the opening end of the first source opening 167 toward the second source inner wall 169 of the organic insulating layer 31.

[0364] The second part 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. In this form, the second part 193B partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at a distance from the second source inner wall 169 of the organic insulating layer 31 to the first source inner wall 164 side of the inorganic insulating layer 30 within the second source opening 173 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0365] Thereby, the second Ni plating layer 193 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31. The second part 193B faces the source main surface electrode 155 with the source inner peripheral edge 174 of the inorganic insulating layer 30 interposed therebetween. The second part 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection part extending in the width direction of the inorganic insulating layer 30.

[0366] The second Ni plating layer 193 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 is less than the value (T2 + WS) obtained by adding the width WS of the source inner peripheral edge 174 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WS). This is a condition for the second Ni plating layer 193 to expose the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155.

[0367] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be 0.1 μm or more and 10 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0368] The second outer plating layer 194 covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer plating layer 194 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the second Ni plating layer 193. In this form, the second outer plating layer 194 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0369] The second outer plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (e.g., solder). The source terminal surface 194A is located on the side of the second Ni plating layer 193 with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer plating layer 194 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0370] Specifically, the second outer plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the side of the second Ni plating layer 193. The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 at an interval from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side.

[0371] The second Pd plating layer 195 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the second Pd plating layer 195 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0372] The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0373] The second Au plating layer 196 is formed in a film shape along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a space from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side.

[0374] The second Au plating layer 196 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 with a space from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 side of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the second Au plating layer 196 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire area of the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0375] The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0376] In this embodiment, an example has been described in which the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196. However, a second outer surface plating layer 194 having the same form as any one of the outer surface plating layers 42 according to the second to fourth exemplary embodiments shown in FIGS. 8A to 8D described above may be employed.

[0377] As described above, the semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 101. According to the semiconductor device 201, the same effects as those described for the semiconductor device 61 can be achieved.

[0378] FIG. 18 is a plan view of a semiconductor package 301 incorporating a semiconductor device (reference numerals omitted) according to the first to fourth embodiments, as viewed from one side. FIG. 19 is a plan view of the semiconductor package 301 shown in FIG. 18, as viewed from the other side. FIG. 20 is a perspective view of the semiconductor package 301 shown in FIG. 18. FIG. 21 is an exploded perspective view of the semiconductor package 301 shown in FIG. 18. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 18. FIG. 23 is a circuit diagram of the semiconductor package 301 shown in FIG. 18.

[0379] Referring to FIGS. 18 to 23, in this embodiment, the semiconductor package 301 has a form called a power guard. The semiconductor package 301 includes a resin package body 302. The package body 302 is made of a molding resin including a filler (e.g., an insulating filler) and a matrix resin. The matrix resin is preferably made of an epoxy resin.

[0380] The package body 302 has a first main surface 303 (first surface) on one side, a second main surface 304 (second surface) on the other side, and side surfaces 305A to 305D connecting the first main surface 303 and the second main surface 304. The first main surface 303 and the second main surface 304 are formed in a rectangular shape (a rectangular shape in this embodiment) in a plan view as viewed from their normal direction Z.

[0381] The side faces 305A to 305D include a first side face 305A, a second side face 305B, a third side face 305C, and a fourth side face 305D. The first side face 305A and the second side face 305B extend along the first direction X and face each other in a second direction Y intersecting the first direction X. The first side face 305A and the second side face 305B form the long sides of the package body 302. The third side face 305C and the fourth side face 305D extend along the second direction Y and face each other in the first direction X. The third side face 305C and the fourth side face 305D form the short sides of the package body 302. Specifically, the second direction Y is orthogonal to the first direction X.

[0382] The semiconductor package 301 includes a first metal plate 310 disposed within the package body 302. The first metal plate 310 is disposed on the side of the first main surface 303 of the package body 302 and integrally includes a first heat dissipation portion 311 and a first terminal portion 312. The first heat dissipation portion 311 is disposed within the package body 302 so as to be exposed from the first main surface 303. The first heat dissipation portion 311 is formed in a rectangular shape extending along the first direction X in plan view. The first heat dissipation portion 311 has a planar area less than the planar area of the first main surface 303 and is exposed from the first main surface 303 with a space inward from the side faces 305A to 305D.

[0383] The first terminal portion 312 is exposed from the first side face 305A. Specifically, the first terminal portion 312 extends in a strip shape from the first heat dissipation portion 311 toward the first side face 305A, penetrates the first side face 305A, and is drawn out of the package body 302. When a central line LC crossing the second direction Y is set at the central portion of the first side face 305A (the second side face 305B), the first heat dissipation portion 311 is located on the side of the fourth side face 305D with respect to the central line LC.

[0384] The first terminal portion 312 has a first length L1 in the second direction Y. The width of the first terminal portion 312 in the first direction X is less than the width of the first heat dissipation portion 311 in the first direction X. The first terminal portion 312 is connected to the first heat dissipation portion 311 via a bent portion 313 that bends from the first main surface 303 side to the second main surface 304 side within the package body 302. As a result, the first terminal portion 312 is exposed from the first side surface 305A with a space from the first main surface 303 to the second main surface 304 side.

[0385] The semiconductor package 301 includes a second metal plate 320 disposed within the package body 302. The second metal plate 320 is disposed on the second main surface 304 side of the package body 302 at a distance from the first metal plate 310, and integrally includes a second heat dissipation portion 321 and a second terminal portion 322. The second heat dissipation portion 321 is disposed within the package body 302 so as to be exposed from the second main surface 304. The second heat dissipation portion 321 is formed in a rectangular shape extending along the first direction X in a plan view. The second heat dissipation portion 321 has a planar area less than the planar area of the second main surface 304, and is exposed from the second main surface 304 with a space inward from the side surfaces 305A to 305D.

[0386] The second terminal portion 322 is exposed from the first side surface 305A. Specifically, the second terminal portion 322 extends in a strip shape from the second heat dissipation portion 321 toward the first side surface 305A, penetrates the first side surface 305A, and is drawn out of the package body 302. The second terminal portion 322 is located on the third side surface 305C side with respect to the center line LC.

[0387] In this form, the second terminal portion 322 has a second length L2 different from the first length L1 of the first terminal portion 312 in the second direction Y. The first terminal portion 312 and the second terminal portion 322 are distinguishable from each other by their shapes (lengths). The second length L2 of the second terminal portion 322 may be greater than the first length L1, or may be less than the first length L1. Of course, a second terminal portion 322 having a second length L2 equal to the first length L1 may be formed.

[0388] The width of the second terminal portion 322 in the first direction X is less than the width of the second heat dissipation portion 321 in the first direction X. The second terminal portion 322 is connected to the second heat dissipation portion 321 via a bent portion 323 that is bent from the second main surface 304 side to the first main surface 303 side within the package body 302. As a result, the second terminal portion 322 is exposed from the second side surface 305B with a space from the second main surface 304 to the first main surface 303 side.

[0389] The second terminal portion 322 is drawn out from a thickness position different from that of the first terminal portion 312 with respect to the normal direction Z. In this form, the second terminal portion 322 is formed with a space from the first terminal portion 312 to the second main surface 304 side. The second terminal portion 322 does not face the first terminal portion 312 in the first direction X.

[0390] The semiconductor package 301 includes one or more (five in this form) control terminals 330 disposed within the package body 302. The plurality of control terminals 330 are exposed from the second side surface 305B opposite to the first side surface 305A where the first terminal portion 312 and the second terminal portion 322 are exposed. The plurality of control terminals 330 are located on the third side surface 305C side with respect to the central line LC. The plurality of control terminals 330 are linearly located in the same straight line as the second terminal portion 322 of the second metal plate 320 in a plan view. The arrangement of the plurality of control terminals 330 is arbitrary.

[0391] The plurality of control terminals 330 are each formed in a strip shape extending along the second direction Y. Specifically, the plurality of control terminals 330 each include an internal connection portion 331, an external connection portion 332, and a strip portion 333. The internal connection portion 331 is disposed within the package body 302. The external connection portion 332 is disposed outside the package body 302.

[0392] The strip portion 333 extends in a strip shape from the internal connection portion 331 through the second side surface 305B toward the external connection portion 332. The strip portion 333 may have a curved portion 334 that is recessed toward the second main surface 304 in a portion located outside the package body 302. Of course, a strip portion 333 without the curved portion 334 may be formed.

[0393] The plurality of control terminals 330 are drawn out from thickness positions different from those of the first heat radiating portion 311 and the second heat radiating portion 321 with respect to the normal direction Z. In this form, the plurality of control terminals 330 are arranged in the region between the first heat radiating portion 311 and the second heat radiating portion 321 with a space therebetween.

[0394] The semiconductor package 301 includes an SBD chip 341 and a MISFET chip 342 arranged in the package body 302. The SBD chip 341 is composed of any one of the semiconductor devices (reference numerals omitted) according to the first to second embodiments. The MISFET chip 342 is composed of any one of the semiconductor devices (reference numerals omitted) according to the third to fourth embodiments.

[0395] The SBD chip 341 is arranged in the space sandwiched by the first heat radiating portion 311 and the second heat radiating portion 321 within the package body 302. The SBD chip 341 is arranged on the fourth side surface 305D side of the package body 302 with respect to the center line LC. The SBD chip 341 is arranged on the second heat radiating portion 321 with the second main surface electrode 46 facing the second heat radiating portion 321.

[0396] The MISFET chip 342 is arranged in the space sandwiched by the first heat radiating portion 311 and the second heat radiating portion 321 within the package body 302 with a space from the SBD chip 341. The MISFET chip 342 is arranged on the third side surface 305C side of the package body 302 with respect to the center line LC. The MISFET chip 342 is arranged on the second heat radiating portion 321 with the second main surface electrode 46 facing the second heat radiating portion 321.

[0397] The semiconductor package 301 includes a first conductive bonding material 343 and a second conductive bonding material 344. The first conductive bonding material 343 and the second conductive bonding material 344 each include solder or a metal paste. The first conductive bonding material 343 is interposed between the second main surface electrode 46 of the SBD chip 341 and the second heat dissipation part 321, thermally, mechanically, and electrically connecting the SBD chip 341 and the second heat dissipation part 321. The second conductive bonding material 344 is interposed between the second main surface electrode 46 of the MISFET chip 342 and the second heat dissipation part 321, thermally, mechanically, and electrically connecting the MISFET chip 342 and the second heat dissipation part 321.

[0398] Thereby, the cathode of the SBD chip 341 is electrically connected to the drain of the MISFET chip 342. That is, the second metal plate 320 (the second heat dissipation part 321) functions as a cathode-drain terminal for the SBD chip 341 and the MISFET chip 342.

[0399] The semiconductor package 301 includes a first metal spacer 351 and a second metal spacer 352. The first metal spacer 351 and the second metal spacer (plate-like member) 352 each consist of a plate-like member containing copper in this form. The second metal spacer 352 has the same thickness as the first metal spacer 351.

[0400] The first metal spacer 351 is interposed between the SBD chip 341 and the first heat dissipation part 311, separating the SBD chip 341 from the first heat dissipation part 311. The second metal spacer 352 is interposed between the MISFET chip 342 and the first heat dissipation part 311, separating the MISFET chip 342 from the first heat dissipation part 311. In this form, the first metal spacer 351 and the second metal spacer 352 are separate bodies, but the first metal spacer 351 and the second metal spacer 352 may be integrally formed.

[0401] The semiconductor package 301 includes a third conductive bonding material 353 and a fourth conductive bonding material 354. The third conductive bonding material 353 and the fourth conductive bonding material 354 each include solder or a metal paste. Preferably, the third conductive bonding material 353 and the fourth conductive bonding material 354 are each made of solder.

[0402] The third conductive bonding material 353 is interposed between the pad electrode 40 of the SBD chip 341 and the first metal spacer 351, thermally, mechanically, and electrically connecting the SBD chip 341 and the first metal spacer 351. The fourth conductive bonding material 354 is interposed between the source pad electrode 182 of the MISFET chip 342 and the second metal spacer 352, thermally, mechanically, and electrically connecting the MISFET chip 342 and the second metal spacer 352.

[0403] The semiconductor package 301 includes a fifth conductive bonding material 355 and a sixth conductive bonding material 356. The fifth conductive bonding material 355 and the sixth conductive bonding material 356 each include solder or a metal paste. The fifth conductive bonding material 355 is interposed between the first heat dissipation part 311 and the first metal spacer 351, thermally, mechanically, and electrically connecting the first heat dissipation part 311 and the first metal spacer 351. The sixth conductive bonding material 356 is interposed between the first heat dissipation part 311 and the second metal spacer 352, thermally, mechanically, and electrically connecting the first heat dissipation part 311 and the second metal spacer 352.

[0404] Thereby, the anode of the SBD chip 341 is electrically connected to the source of the MISFET chip 342. That is, the first metal plate 310 (the first heat dissipation part 311) functions as an anode-source terminal for the SBD chip 341 and the MISFET chip 342.

[0405] The semiconductor package 301 includes one or more (five in this form) conductive wires 357. The conductive wires 357 are also referred to as bonding wires. The conductive wires 357 may be made of gold wires, copper wires, or aluminum wires. The plurality of conductive wires 357 are respectively connected to the gate pad electrode 181 of the MISFET chip 342 and the internal connection portion 331 of the plurality of control terminals 330.

[0406] Thereby, the gate of the MISFET chip 342 is electrically connected to the plurality of control terminals 330. That is, the plurality of control terminals 330 each function as a gate terminal of the MISFET chip 342. It is not necessary for the conductive wires 357 to connect all the control terminals 330 and the gate pad electrode 181. Any control terminal 330 may be electrically open.

[0407] As described above, according to the semiconductor package 301, the first conductive bonding material 343 is connected to the pad electrode 40 of the SBD chip 341. The pad electrode 40 of the SBD chip 341 includes the Ni plating layer 41 and the outer surface plating layer 42 as described in the first to second embodiments. Thereby, the first conductive bonding material 343 can be appropriately connected to the pad electrode 40 of the SBD chip 341. Therefore, the SBD chip 341 can be appropriately thermally, mechanically, and electrically connected to the first heat dissipation portion 311 and the second heat dissipation portion 321.

[0408] When the SBD chip 341 does not include the organic insulating layer 31, cracks, peeling, etc. may occur in the pad electrode 40 of the SBD chip 341 due to the filler contained in the package body 302. This type of problem is called filler attack and is one of the factors causing a decrease in the reliability of the pad electrode 40 and the like. Therefore, in the SBD chip 341, the organic insulating layer 31 is formed on the inorganic insulating layer 30. Thereby, since the organic insulating layer 31 serves as a cushion against the filler, the pad electrode 40 and the like can be appropriately protected from filler attack.

[0409] Furthermore, in the SBD chip 341, as described in the first and second embodiments, in the structure including the organic insulating layer 31, the Ni plating layer 41 is connected to the inner peripheral edge 38 of the inorganic insulating layer 30. Thereby, cracks, peeling, etc. of the Ni plating layer 41 (outer surface plating layer 42) due to filler attack can also be appropriately suppressed.

[0410] According to the semiconductor package 301, the second conductive bonding material 344 is connected to the source pad electrode 182 of the MISFET chip 342. The source pad electrode 182 of the MISFET chip 342 includes the second Ni plating layer 193 and the second outer surface plating layer 194 as described in the third and fourth embodiments. Thereby, the second conductive bonding material 344 can be appropriately connected to the source pad electrode 182 of the MISFET chip 342. Therefore, the MISFET chip 342 can be appropriately thermally, mechanically, and electrically connected to the first heat dissipation part 311 and the second heat dissipation part 321.

[0411] When the MISFET chip 342 does not include the organic insulating layer 31, cracks, peeling, etc. may occur in the source pad electrode 182, etc. of the MISFET chip 342 due to the filler contained in the package body 302. This type of problem is called filler attack and is one of the factors causing a decrease in the reliability of the source pad electrode 182, etc. Therefore, in the MISFET chip 342, the organic insulating layer 31 is formed on the inorganic insulating layer 30. Thereby, since the organic insulating layer 31 serves as a cushion against the filler, the source pad electrode 182, etc. can be appropriately protected from filler attack.

[0412] Furthermore, in the MISFET chip 342, as described in the third to fourth embodiments, in the structure including the organic insulating layer 31, the second Ni plating layer 193 is connected to the first source inner wall 164 of the inorganic insulating layer 30. Thereby, cracks, peeling, etc. of the second Ni plating layer 193 (the second outer surface plating layer 194) due to filler attack can be appropriately suppressed. In the MISFET chip 342, the same effect as that on the source pad electrode 182 side can be achieved also on the gate pad electrode 181 side.

[0413] In this embodiment, an example in which the semiconductor package 301 includes the SBD chip 341 and the MISFET chip 342 has been described. However, a semiconductor package 301 including only one of the SBD chip 341 and the MISFET chip 342 may be adopted. A semiconductor package 301 including a plurality of SBD chips 341 and / or a plurality of MISFET chips 342 may be adopted.

[0414] The embodiments of the present invention can be implemented in still other embodiments.

[0415] In the above-described third to fourth embodiments, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode 107 may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon. In this case, the first low-resistance layer 112 made of n-type poly side is formed. In the case of such a structure, the gate resistance can be further reduced.

[0416] In the above-described third to fourth embodiments, it may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon. In the above-described third to fourth embodiments, a structure in which neither or both of the first low-resistance layer 112 and the second low-resistance layer 131 are formed may be adopted.

[0417] In the above-described third to fourth embodiments, n + type drain region may be replaced with p +A collector region of a type may be adopted. According to this structure, instead of the MISFET, an IGBT (Insulated Gate Bipolar Transistor) can be provided. In this case, in the above-described third to fourth embodiments, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

[0418] In each of the above-described embodiments, an Si chip made of a single crystal of Si may be adopted instead of the SiC chip 2. That is, the semiconductor device (reference numerals omitted) according to each of the above-described embodiments may be an Si semiconductor device. In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0419] Examples of features extracted from this specification and the drawings are shown below. The following [A1] to [A19], [B1] to [B15], and [C1] to [C16] provide a semiconductor device capable of improving the reliability of a Ni plating layer in a structure in which a Ni plating layer is formed on an electrode exposed from an opening of an organic insulating layer.

[0420] [A1] A semiconductor device including a chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening surrounding the first opening with a space from the first opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening.

[0421] [A2] The semiconductor device according to A1, wherein the Ni plating layer covers the organic insulating layer in the second opening.

[0422] [A3] The semiconductor device according to A2, wherein the Ni plating layer is formed at a space from an opening end of the second opening toward the inorganic insulating layer side.

[0423] [A4] The Ni plating layer covers the organic insulating layer in the second opening such that the exposed area of the organic insulating layer exceeds the hidden area of the organic insulating layer, the semiconductor device according to A2 or A3.

[0424] [A5] The inner peripheral edge of the inorganic insulating layer has a width equal to or less than the thickness of the inorganic insulating layer, the semiconductor device according to any one of A2 to A4.

[0425] [A6] The semiconductor device according to any one of A2 to A5, further comprising an outer plating layer that covers the outer surface of the Ni plating layer in the second opening.

[0426] [A7] The outer plating layer covers the organic insulating layer in the second opening, the semiconductor device according to A6.

[0427] [A8] The outer plating layer covers the Ni plating layer with a space from the opening end of the second opening toward the inorganic insulating layer side, the semiconductor device according to A6 or A7.

[0428] [A9] The outer plating layer has a thickness less than the thickness of the Ni plating layer, the semiconductor device according to any one of A6 to A8.

[0429] [A10] The Ni plating layer covers the inner peripheral edge of the inorganic insulating layer with a space from the organic insulating layer in the second opening, the semiconductor device according to A1.

[0430] [A11] The Ni plating layer is formed with a space from the opening end of the second opening toward the inorganic insulating layer side, the semiconductor device according to A10.

[0431] [A12] The inner peripheral edge of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer, the semiconductor device according to A10 or A11.

[0432] The semiconductor device according to any one of A10 to A12, further comprising an outer plating layer that covers the outer surface of the Ni plating layer within the second opening.

[0433] [A14] The semiconductor device according to A13, wherein the outer plating layer covers the inner peripheral edge of the inorganic insulating layer.

[0434] [A15] The semiconductor device according to A13 or A14, wherein the outer plating layer covers the Ni plating layer with a space from the organic insulating layer.

[0435] [A16] The semiconductor device according to any one of A13 to A15, wherein the outer plating layer covers the Ni plating layer with a space from the opening end of the second opening toward the inorganic insulating layer side.

[0436] [A17] The semiconductor device according to any one of A13 to A16, wherein the outer plating layer has a thickness less than the thickness of the Ni plating layer.

[0437] [A18] The semiconductor device according to any one of A1 to A17, wherein the chip is made of a SiC chip.

[0438] [A19] A semiconductor package including: a resin package body having a first surface on one side, a second surface on the other side, and a side surface; a first heat dissipation portion exposed from the first surface, and a first terminal portion exposed from the side surface, and a first metal plate disposed within the package body; a second heat dissipation portion exposed from the second surface, and a second terminal portion exposed from the side surface, and a second metal plate disposed within the package body at a space from the first metal plate toward the second surface side; and the semiconductor device according to any one of A1 to A18 disposed in a space sandwiched by the first heat dissipation portion and the second heat dissipation portion within the package body.

[0439] [B1]A chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening for exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening spaced from the first opening and surrounding the first opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening. The semiconductor device, wherein the organic insulating layer has a second outer wall located inward of a first outer wall of the inorganic insulating layer.

[0440] [B2]The semiconductor device according to B1, wherein the Ni plating layer is formed at a distance from an opening end of the second opening toward the inorganic insulating layer side.

[0441] [B3]The semiconductor device according to B1 or B2, further comprising an outer surface plating layer covering an outer surface of the Ni plating layer in the second opening.

[0442] [B4]The semiconductor device according to B3, wherein the outer surface plating layer has a thickness less than a thickness of the Ni plating layer.

[0443] [B5]The semiconductor device according to any one of B1 to B4, wherein the inner peripheral edge of the inorganic insulating layer has a width exceeding a thickness of the inorganic insulating layer.

[0444] [B6]The semiconductor device according to any one of B1 to B5, wherein the second outer wall of the organic insulating layer is formed in a curved shape recessed toward the inorganic insulating layer side.

[0445] [B7]The semiconductor device according to any one of B1 to B6, wherein the chip is made of a SiC chip.

[0446] [B8]The semiconductor device according to any one of B1 to B7, further comprising a transistor formed on the chip.

[0447] [B9]The transistor is the semiconductor device according to B8, including a plurality of unit cells extending in a stripe shape.

[0448] [B10]The transistor is the semiconductor device according to B9, including a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

[0449] [B11]The chip has a rectangular shape in plan view, The semiconductor device according to B10, wherein the plurality of trench gate structures extend along the short side of the chip.

[0450] [B12]The chip has a rectangular shape in plan view, and is the semiconductor device according to any one of B1 to B10.

[0451] [B13]The chip has a second main surface opposite to the first main surface covered by the electrode, further includes a back surface electrode covering the second main surface, The semiconductor device according to any one of B1 to B12, wherein the back surface electrode includes a Ti layer.

[0452] [B14]The chip has a second main surface opposite to the first main surface covered by the electrode, further includes a back surface electrode covering the second main surface, The semiconductor device according to any one of B1 to B12, wherein the back surface electrode includes a Ni layer.

[0453] [B15]A resin package body, a plate-like member containing copper disposed in the package body, and the semiconductor device according to any one of B1 to B14 disposed in the package body, and includes: the electrode includes a source pad electrode, The semiconductor package, wherein the plate-like member is electrically connected to the source pad electrode.

[0454] [C1]A chip having a side surface, The electrode formed on the chip, An inorganic insulating layer that covers the electrode and exposes the electrode from the first opening, An organic insulating layer that covers the inorganic insulating layer and has a second opening having an open end formed at a distance from the open end of the first opening, and exposes the inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, A Ni plating layer that covers the electrode in the first opening and covers the inner peripheral edge of the inorganic insulating layer in the second opening, The organic insulating layer has a second outer wall located inward of a first outer wall of the inorganic insulating layer, The second outer wall is formed along a cutting line at a distance inward from the side surface, a semiconductor device.

[0455] [C2] The semiconductor device according to C1, wherein the first outer wall of the inorganic insulating layer is formed at a distance inward from the side surface.

[0456] [C3] The semiconductor device according to C1 or C2, wherein the Ni plating layer is formed at a distance from the open end of the second opening toward the inorganic insulating layer side.

[0457] [C4] The semiconductor device according to any one of C1 to C3, further including an outer surface plating layer that covers an outer surface of the Ni plating layer in the second opening.

[0458] [C5] The semiconductor device according to C4, wherein the outer surface plating layer has a thickness less than the thickness of the Ni plating layer.

[0459] [C6] The semiconductor device according to any one of C1 to C5, wherein the inner peripheral edge of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer.

[0460] [C7] The semiconductor device according to any one of C1 to C6, wherein the second outer wall of the organic insulating layer is formed in a curved shape recessed toward the inorganic insulating layer side.

[0461] [C8] The chip is the semiconductor device according to any one of C1 to C7, which is made of a SiC chip.

[0462] [C9] The semiconductor device according to any one of C1 to C8, further including a transistor formed on the chip.

[0463] [C10] The transistor in the semiconductor device according to C9 includes a plurality of unit cells extending in a stripe shape.

[0464] [C11] The transistor in the semiconductor device according to C10 includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

[0465] [C12] The chip has a rectangular shape in plan view, In the semiconductor device according to C11, the plurality of trench gate structures extend along the short side of the chip.

[0466] [C13] The chip has a rectangular shape in plan view, and is the semiconductor device according to any one of C1 to C11.

[0467] [C14] The chip has a second main surface opposite to the first main surface covered by the electrode, and further includes a back surface electrode covering the second main surface, The back surface electrode includes a Ti layer, and is the semiconductor device according to any one of C1 to C13.

[0468] [C15] The chip has a second main surface opposite to the first main surface covered by the electrode, and further includes a back surface electrode covering the second main surface, The back surface electrode includes a Ni layer, and is the semiconductor device according to any one of C1 to C13.

[0469] [C16] A resin package body, and a plate-like member containing copper disposed in the package body, including the semiconductor device according to any one of C1 to C15 disposed in the package body; the electrode includes a source pad electrode; a semiconductor package, wherein the plate-like member is electrically connected to the source pad electrode.

[0470] This application corresponds to Japanese Patent Application No. 2019-180861 filed with the Japan Patent Office on September 30, 2019, and the entire disclosure of this application is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims.

Description of Reference Numerals

[0471] 1 Semiconductor device 2 SiC chip (chip) 21 First main surface electrode (electrode) 30 Inorganic insulating layer 31 Organic insulating layer 34 First opening 37 Second opening 38 Inner peripheral edge of inorganic insulating layer 41 Ni plating layer (metal layer) 42 Outer surface plating layer 61 Semiconductor device 101 Semiconductor device 153 Gate main surface electrode (electrode) 155 Source main surface electrode (electrode) 166 First gate opening (first opening) 167 First source opening (first opening) 171 Second gate opening (second opening) 172 Gate inner peripheral edge of inorganic insulating layer 173 Second source opening (second opening) 174 Source inner peripheral edge of inorganic insulating layer 183 First Ni plating layer (metal layer) 184 First outer surface plating layer 193 Second Ni plating layer (metal layer) 194 Second outer plating layer 201 Semiconductor device 301 Semiconductor package 302 Package body 303 First main surface (first surface) 304 Second main surface (second surface) 305A Side surface 305B Side surface 305C Side surface 305D Side surface 310 First metal plate 311 First heat dissipation part 312 First terminal part 320 Second metal plate 321 Second heat dissipation part 322 Second terminal part 341 SBD chip (semiconductor device) 342 MISFET chip (semiconductor device) 351 First metal spacer 352 Second metal spacer T2 Thickness of inorganic insulating layer T4 Thickness of Ni plating layer T5 Thickness of outer plating layer W Width of inner peripheral edge of inorganic insulating layer WG Width of gate inner peripheral edge of inorganic insulating layer WS Width of source inner peripheral edge of inorganic insulating layer

Claims

1. a chip having a side surface; An electrode formed on the chip; an inorganic insulating layer covering the electrode and exposing the electrode through a first opening; an organic insulating layer covering the inorganic insulating layer, the organic insulating layer having a second opening with an opening end spaced apart from an opening end of the first opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening; a metal layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening; the organic insulating layer has a second outer wall located inwardly of the first outer wall of the inorganic insulating layer, The second outer wall is formed along the side surface at a distance inward from the side surface.

2. The semiconductor device according to claim 1 , wherein the first outer wall of the inorganic insulating layer is formed inwardly and spaced from the side surface.

3. The semiconductor device according to claim 1 , wherein the metal layer is formed on a side of the inorganic insulating layer from an end of the second opening at a distance therefrom.

4. 4. The semiconductor device according to claim 1, further comprising an outer surface plating layer that covers an outer surface of said metal layer within said second opening.

5. The semiconductor device according to claim 4 , wherein the outer surface plating layer has a thickness less than a thickness of the metal layer.

6. 6. The semiconductor device according to claim 1, wherein the metal layer includes a Ni plating layer.

7. 7. The semiconductor device according to claim 1, wherein the inner periphery of the inorganic insulating layer has a width greater than a thickness of the inorganic insulating layer.

8. 8. The semiconductor device according to claim 1, wherein the second outer wall of the organic insulating layer is formed in a curved shape recessed toward the inorganic insulating layer.

9. 9. The semiconductor device according to claim 1, wherein the chip is a SiC chip.

10. 10. The semiconductor device according to claim 1, further comprising a transistor formed on the chip.

11. The semiconductor device according to claim 10 , wherein the transistor includes a plurality of unit cells extending in a stripe shape.

12. The semiconductor device according to claim 11 , wherein the transistor includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

13. The chip has a rectangular shape in a plan view, The semiconductor device according to claim 12 , wherein the trench gate structures extend along a short side of the chip.

14. 13. The semiconductor device according to claim 1, wherein the chip has a rectangular shape in a plan view.

15. the chip has a second main surface opposite to the first main surface covered by the electrode; further comprising a back electrode covering the second major surface; The semiconductor device according to claim 1, wherein the back electrode includes a Ti layer.

16. the chip has a second main surface opposite to the first main surface covered by the electrode; further comprising a back electrode covering the second major surface; The semiconductor device according to claim 1, wherein the back electrode includes a Ni layer.

17. A resin package body; a plate-shaped member including copper that is disposed within the package body; and the semiconductor device according to any one of claims 1 to 16, which is disposed in the package body; the electrodes include a source pad electrode; the plate-like member is electrically connected to the source pad electrode.

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