Semiconductor device

Abstract

To provide a semiconductor device in which a parasitic inductance is reduced and a parasitic resistance is reduced.SOLUTION: A semiconductor device A1 includes: a semiconductor element 1; a semiconductor element 2; a control element 3; a leadframe 4 including a plurality of leads; a wire 5B bonded to a source electrode 12 of the semiconductor element 1; and a wire 5C bonded to a drain electrode 21 of the semiconductor element 2. The plurality of leads include a lead 4A on which the semiconductor element 1 is mounted, a lead 4B on which the semiconductor element 2 is mounted, and a lead 4C on which the control element 3 is mounted. The lead 4A and the lead 4B overlap with each other as viewed in an x direction, and the lead 4C overlaps with both the lead 4A and the lead 4B as viewed in a y direction. The lead 4A includes a die pad portion 411 to which the semiconductor element 1 is bonded, and a bonding portion 412 to which the wire 5B is bonded. The bonding portion 412 is located between the semiconductor element 1 and the semiconductor element 2 as viewed in a z direction, and the wire 5C is bonded thereto.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a plurality of semiconductor elements mounted thereon.

Background Art

[0002] Conventionally, a semiconductor device in which a plurality of semiconductor elements are molded with a single resin member has been known. Such a semiconductor device is called a system in package. Patent Document 1 discloses a semiconductor device in which two switching elements and a control IC are packaged together. The control IC is a semiconductor element that controls each switching element. Each switching element performs a switching operation in response to a signal from the control IC. Such a semiconductor device is mounted on a circuit board of, for example, an electronic device and used in a power supply circuit such as a DC / DC converter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, with the energy saving and high performance of electronic devices, semiconductor devices are required to reduce power consumption and improve the responsiveness of switching operations. In order to reduce power consumption and improve the responsiveness of switching operations, it is effective to reduce parasitic inductance and parasitic resistance.

[0005] The present disclosure has been conceived in view of the above circumstances, and an object thereof is to provide a semiconductor device in which a plurality of semiconductor elements are packaged together and in which parasitic inductance and parasitic resistance are reduced.

Means for Solving the Problems

[0006] The semiconductor device provided by the present disclosure has a first main surface and a first back surface spaced apart in the thickness direction, and a first semiconductor element in which a first drain electrode, a first source electrode, and a first gate electrode are disposed on the first main surface; a second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, and a second drain electrode, a second source electrode, and a second gate electrode are disposed on the second main surface; a control element electrically connected to the first gate electrode and the second gate electrode; and a lead frame including a plurality of leads spaced apart from each other, wherein the plurality of leads include a first lead facing the first back surface and on which the first semiconductor element is mounted, a second lead facing the second back surface and on which the second semiconductor element is mounted, and a third lead on which the control element is mounted, and the first lead and the second lead overlap each other when viewed in a first direction orthogonal to the thickness direction, and the third lead overlaps both the first lead and the second lead when viewed in a second direction orthogonal to both the thickness direction and the first direction.

Effects of the Invention

[0007] According to the semiconductor device of the present disclosure, in a semiconductor device in which a plurality of semiconductor elements and a control element are packaged together, parasitic inductance and parasitic resistance can be reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Note that the same or similar components are denoted by the same reference numerals, and the description thereof will be omitted.

[0010] In the present disclosure, "a certain object A overlaps a certain object B when viewed in a certain direction" means, unless otherwise specified, "when viewed in a certain direction, a certain object A overlaps all of a certain object B" and "when viewed in a certain direction, a certain object A overlaps a part of a certain object B". Also, terms such as "first", "second", "third", etc. in the present disclosure are merely used as labels and are not necessarily intended to assign an order to those objects.

[0011] <First Embodiment> A semiconductor device A1 according to the first embodiment will be described with reference to FIGS. 1 to 7. The semiconductor device A1 is used in a power converter such as an inverter or a converter, for example.

[0012] First, the module structure of the semiconductor device A1 according to the first embodiment will be described with reference to FIGS. 1 to 6. The semiconductor device A1 includes, in its module structure, two semiconductor elements 1 and 2, a control element 3, a lead frame 4, a plurality of connection members 5, and a sealing member 6. Further, in the semiconductor device A1, the lead frame 4 includes a plurality of leads 4A to 4J separated from each other. The plurality of connection members 5 include a plurality of wires 5A to 5N.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1, showing the case when viewed from the bottom side. FIG. 2 is a plan view showing the semiconductor device A1, with the sealing member 6 shown by an imaginary line (two-dot chain line). FIG. 3 is a bottom view showing the semiconductor device A1, with the sealing member 6 shown by an imaginary line (two-dot chain line). FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 2. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 2. FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 2. In FIGS. 4 to 6, the illustration of the plurality of connection members 5 is omitted.

[0014] For convenience of explanation, three mutually orthogonal directions are defined as the x direction, the y direction, and the z direction. The z direction is the thickness direction of the semiconductor device A1. The x direction is the left-right direction in the plan view (see FIG. 2) of the semiconductor device A1. The y direction is the up-down direction in the plan view (see FIG. 2) of the semiconductor device A1. Also, one of the x directions is the x1 direction and the other is the x2 direction. Similarly, one of the y directions is the y1 direction and the other is the y2 direction, and one of the z directions is the z1 direction and the other is the z2 direction. In the present disclosure, there may be cases where the z1 direction is downward and the z2 direction is upward. The x direction and the y direction correspond to the "first direction" and the "second direction" described in the claims.

[0015] The semiconductor device A1 is mounted on a circuit board such as an electronic device. The semiconductor device A1 has, for example, a surface-mount package structure, and in this embodiment, it has a package form called SON (Small Outline Non-lead), for example.

[0016] The two semiconductor elements 1 and 2 are both elements that exhibit the electrical functions of the semiconductor device A1. Each of the semiconductor elements 1 and 2 is a switching element, for example, an n-type MOSFET. Note that each of the semiconductor elements 1 and 2 is not limited to an n-type MOSFET and may be a p-type MOSFET. Also, each of the semiconductor elements 1 and 2 is not limited to a MOSFET and may be other transistors such as a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a HEMT (High Electron Mobility Transistor), a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor). It may also be so.

[0017] As shown in FIG. 2, each of the semiconductor elements 1 and 2 is, in a plan view (viewed in the z direction), for example, rectangular. The semiconductor element 1 is mounted on the lead 4A, and the semiconductor element 2 is mounted on the lead 4B. The two semiconductor elements 1 and 2 are arranged side by side in the x direction as shown in FIGS. 2 and 4. Each constituent material of each of the semiconductor elements 1 and 2 includes, for example, GaN (gallium nitride). Note that each constituent material of each of the semiconductor elements 1 and 2 is not limited to GaN and may include, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or Ga2O3 (gallium oxide). The semiconductor element 1 corresponds to the "first semiconductor element" described in the claims, and the semiconductor element 2 corresponds to the "second semiconductor element" described in the claims.

[0018] The semiconductor element 1 has a device front surface 1a and a device back surface 1b. The device front surface 1a and the device back surface 1b are spaced apart in the z direction. The device front surface 1a faces the z2 direction, and the device back surface 1b faces the z1 direction. The device back surface 1b faces the lead 4A. The device front surface 1a corresponds to the "first main surface" described in the claims, and the device back surface 1b corresponds to the "first back surface" described in the claims.

[0019] The semiconductor element 1 is a three-terminal element having three electrodes. In the present embodiment, the semiconductor element 1 includes a drain electrode 11, a source electrode 12, and a gate electrode 13. The drain electrode 11, the source electrode 12, and the gate electrode 13 are disposed on the main element surface 1a. The drain electrode 11 corresponds to the "first drain electrode" described in the claims, the source electrode 12 corresponds to the "first source electrode" described in the claims, and the gate electrode 13 corresponds to the "first gate electrode" described in the claims.

[0020] The drain electrode 11 includes a plurality of pad portions 111. Each pad portion 111 is strip-shaped extending in the x direction. Each pad portion 111 is electrically connected to the drain region inside the semiconductor element 1. The source electrode 12 includes a plurality of pad portions 121. Each pad portion 121 is strip-shaped extending in the x direction. Each pad portion 121 is electrically connected to the source region inside the semiconductor element 1. The plurality of pad portions 111 and the plurality of pad portions 121 are arranged side by side in the y direction and are alternately disposed. The gate electrode 13 includes two pad portions 131, 132. Each of the pad portions 131, 132 is electrically connected to the gate region (channel region) inside the semiconductor element 1. Each of the pad portions 131, 132 is disposed at the edge portion far from the semiconductor element 2 in the x direction. The two pad portions 131, 132 are separated from each other in the y direction. In the example shown in FIG. 2, the pad portion 131 is disposed at the corner on the x1 direction side and the y1 direction side in plan view. The pad portion 132 is disposed at the corner on the x1 direction side and the y2 direction side in plan view. The two pad portions 131, 132 are at the same potential. Note that the gate electrode 13 may not include the pad portion 132. Each of the pad portions 131, 132 corresponds to the "first pad portion" described in the claims.

[0021] A drive signal is input to the semiconductor element 1 from the control element 3, and according to the drive signal, the conduction state and the cutoff state are switched (a switching operation is performed). The drive signal is input to the gate electrode 13. The semiconductor element 1 corresponds to the "first semiconductor element" described in the claims.

[0022] The semiconductor element 2 has a device main surface 2a and a device back surface 2b. The device main surface 2a and the device back surface 2b are spaced apart in the z direction. The device main surface 2a faces the z2 direction, and the device back surface 2b faces the z1 direction. The device back surface 2b faces the lead 4B. The device main surface 2a corresponds to the "second main surface" described in the claims, and the device back surface 2b corresponds to the "second back surface" described in the claims.

[0023] The semiconductor element 2 is a three-terminal element having three electrodes. In the present embodiment, the semiconductor element 2 includes a drain electrode 21, a source electrode 22, and a gate electrode 23. The drain electrode 21, the source electrode 22, and the gate electrode 23 are disposed on the device main surface 2a. The drain electrode 21 corresponds to the "second drain electrode" described in the claims, the source electrode 22 corresponds to the "second source electrode" described in the claims, and the gate electrode 23 corresponds to the "second gate electrode" described in the claims.

[0024] The drain electrode 21 includes a plurality of pad portions 211. Each pad portion 211 is strip-shaped and extends in the x direction. Each pad portion 211 is electrically connected to the drain region inside the semiconductor element 2. The source electrode 22 includes a plurality of pad portions 221. Each pad portion 221 is strip-shaped and extends in the x direction. Each pad portion 221 is electrically connected to the source region inside the semiconductor element 2. The plurality of pad portions 211 and the plurality of pad portions 221 are arranged side by side in the y direction and are alternately arranged. The gate electrode 23 includes two pad portions 231 and 232. Each of the pad portions 231 and 232 is electrically connected to the gate region (channel region) inside the semiconductor element 2. Each of the pad portions 231 and 232 is arranged at the edge portion far from the semiconductor element 1 in the x direction. The two pad portions 231 and 232 are separated from each other in the y direction. In the example shown in FIG. 2, the pad portion 231 is arranged at the corner on the x2 direction side and the y1 direction side in plan view. The pad portion 232 is arranged at the corner on the x2 direction side and the y2 direction side in plan view. The two pad portions 231 and 232 are at the same potential. Note that the gate electrode 23 may not include the pad portion 232. Each of the pad portions 231 and 232 corresponds to the "second pad portion" described in the claims.

[0025] A drive signal is input to the semiconductor element 2 from the control element 3, and according to the drive signal, the conduction state and the cutoff state are switched (a switching operation is performed). The drive signal is input to the gate electrode 23. The semiconductor element 2 corresponds to the "second semiconductor element" described in the claims.

[0026] The control element 3 controls the switching operations of the two semiconductor elements 1 and 2. The control element 3 generates a drive signal for driving each of the semiconductor elements 1 and 2, and outputs the generated drive signal to each of the semiconductor elements 1 and 2. The control element 3 is, for example, an IC (integrated circuit). The control element 3 is a semiconductor element including a semiconductor material. The control element 3 is mounted on the lead 4C. The control element 3 overlaps a part of each of the semiconductor elements 1 and 2 when viewed in the y direction.

[0027] The control element 3 has a device front surface 3a and a device back surface 3b. The device front surface 3a and the device back surface 3b are spaced apart in the z direction. The device front surface 3a faces the z2 direction, and the device back surface 3b faces the z1 direction. The device back surface 3b faces the lead 4C.

[0028] The control element 3 includes a device electrode 31. The device electrode 31 is disposed on the device front surface 3a and is. The device electrode 31 includes a plurality of pad portions 311 to 318. Each of the plurality of pad portions 311 to 318 is an input end or an output end in the control element 3. Each of the pad portions 311 to 318 is a site where the connection member 5 is joined. The arrangement of each of the pad portions 311 to 318 in a plan view is not limited to the example shown in FIG. 2.

[0029] One end of a wire 5L is joined to the pad portion 311, and is electrically connected to the lead 4H via the wire 5L. One end of a wire 5J is joined to the pad portion 312, and is electrically connected to the lead 4C via the wire 5J. One end of a wire 5M is joined to the pad portion 313, and is electrically connected to the lead 4I via the wire 5M. One end of a wire 5N is joined to the pad portion 314, and is electrically connected to the lead 4J via the wire 5N. One end of a wire 5F is joined to the pad portion 315, and is electrically connected to the gate electrode 13 (pad portion 131) of the semiconductor element 1 via the wire 5F. One end of a wire 5H is joined to the pad portion 316, and is electrically connected to the gate electrode 23 (pad portion 231) of the semiconductor element 2 via the wire 5H. One end of a wire 5K is joined to the pad portion 317, and is electrically connected to the lead 4G via the wire 5K. One end of a wire 5E is joined to the pad portion 318, and is electrically connected to the lead 4A via the wire 5E.

[0030] The lead frame 4 has two semiconductor elements 1, 2 and a control element 3 mounted thereon. The lead frame 4 forms a conduction path in the semiconductor device A1 together with a plurality of connection members 5. The lead frame 4 is composed of a conductive material. The constituent material of the lead frame 4 is a metal containing, for example, Cu (copper). Note that the constituent material may be another metal other than Cu. Also, plating may be appropriately applied to the surface of the lead frame 4. As shown in FIG. 2, the lead frame 4 includes a plurality of leads 4A to 4J spaced apart from each other. A part of each of the leads 4A to 4J is exposed from the sealing member 6, and the exposed portion is a terminal when mounting the semiconductor device A1 on an external circuit board.

[0031] Lead 4A mounts the semiconductor element 1. One end of each of a plurality of wires 5B is joined to the lead 4A, and through the plurality of wires 5B, it is electrically connected to the source electrode 12 of the semiconductor element 1. Also, one end of each of a plurality of wires 5C is joined to the lead 4A, and through the plurality of wires 5C, it is electrically connected to the drain electrode 21 of the semiconductor element 2. Further, one end of a wire 5E is joined to the lead 4A, and through the wire 5E, it is electrically connected to the element electrode 31 (pad portion 318) of the control element 3. Lead 4B mounts the semiconductor element 2. One end of each of a plurality of wires 5D is joined to the lead 4B, and through the plurality of wires 5D, it is electrically connected to the source electrode 22 of the semiconductor element 2. Lead 4C mounts the control element 3. One end of a wire 5J is joined to the lead 4C, and through the wire 5J, it is electrically connected to the element electrode 31 (pad portion 312) of the control element 3. Lead 4D has one end of each of a plurality of wires 5A joined thereto, and through the plurality of wires 5A, it is electrically connected to the drain electrode 11 of the semiconductor element 1. Lead 4E has one end of a wire 5G joined thereto, and through the wire 5G, it is electrically connected to the gate electrode 13 (pad portion 132) of the semiconductor element 1. Lead 4F has one end of a wire 5I joined thereto, and through the wire 5I, it is electrically connected to the gate electrode 23 (pad portion 232) of the semiconductor element 2. Lead 4G has one end of a wire 5K joined thereto, and through the wire 5K, it is electrically connected to the element electrode 31 (pad portion 317) of the control element 3. Lead 4H has one end of a wire 5L joined thereto, and through the wire 5L, it is electrically connected to the element electrode 31 (pad portion 311) of the control element 3. Lead 4I has one end of a wire 5M joined thereto, and through the wire 5M, it is electrically connected to the element electrode 31 (pad portion 313) of the control element 3. Lead 4J has one end of a wire 5N joined thereto, and through the wire 5N, it is electrically connected to the element electrode 31 (pad portion 314) of the control element 3.

[0032] As shown in FIGS. 2 and 4, lead 4A includes a die pad portion 411 and a bonding portion 412. The die pad portion 411 and the bonding portion 412 are integrally formed with each other. Note that the die pad portion 411 and the bonding portion 412 may be separated.

[0033] The die pad portion 411 is the portion where the semiconductor element 1 is mounted. The semiconductor element 1 is joined via a joining material (not shown). The die pad portion 411 faces the back surface 1b of the element. The die pad portion 411 corresponds to the "first die pad portion" described in the claims.

[0034] The bonding portion 412 is the portion where any of the plurality of connection members 5 is joined. In the present embodiment, one end of each of the plurality of wires 5B, the plurality of wires 5C, and the wire 5E is joined to the bonding portion 412. The bonding portion 412 is electrically connected to the source electrode 12 of the semiconductor element 1 via the plurality of wires 5B, and is electrically connected to the drain electrode 21 of the semiconductor element 2 via the plurality of wires 5C. Further, the bonding portion 412 is electrically connected to the element electrode 31 (pad portion 318) of the control element 3 via the wire 5E. The bonding portion 412 is disposed between the semiconductor element 1 and the semiconductor element 2 in a plan view. The bonding portion 412 corresponds to the "first bonding portion" described in the claims.

[0035] As shown in FIGS. 2 and 4, the lead 4B includes a die pad portion 421 and a bonding portion 422. The die pad portion 421 and the bonding portion 422 are integrally formed. Note that the die pad portion 421 and the bonding portion 422 may be separated.

[0036] The die pad portion 421 is the portion where the semiconductor element 2 is mounted. The semiconductor element 2 is joined via a joining material (not shown). The die pad portion 421 faces the back surface 2b of the element. The die pad portion 421 corresponds to the "second die pad portion" described in the claims.

[0037] The bonding portion 422 is a portion where any of the plurality of connection members 5 is joined. In the present embodiment, one end of each of the plurality of wires 5D is joined to the bonding portion 422. The bonding portion 422 is electrically connected to the source electrode 22 of the semiconductor element 2 via the plurality of wires 5D. The bonding portion 422 corresponds to the "second bonding portion" described in the claims.

[0038] As shown in FIG. 2, both the lead 4A and the lead 4B are arranged in the y2 direction with respect to the lead 4C. Both the lead 4A and the lead 4B overlap the lead 4C when viewed in the y direction and do not overlap the lead 4C when viewed in the x direction. Also, the lead 4A and the lead 4B are adjacent to each other in the x direction. The lead 4A and the lead 4B overlap when viewed in the x direction.

[0039] The lead 4E and the lead 4F overlap each other when viewed in the x direction. As shown in FIG. 2, the lead 4E is arranged in the vicinity of the pad portion 132 in a plan view and is closer to the pad portion 132 than the other leads (excluding the lead 4A). As shown in FIG. 2, the lead 4F is arranged in the vicinity of the pad portion 232 in a plan view and is closer to the pad portion 132 than the other leads (excluding the lead 4B).

[0040] The bonding portion 422 of the lead 4D and the lead 4B overlaps each other when viewed in the x direction. Also, the lead 4D, the lead 4A, and the lead 4B overlap each other when viewed in the x direction and are arranged in this order in the x direction. The lead 4D is electrically connected to the drain electrode 11 of the semiconductor element 1, the lead 4A is electrically connected to the source electrode 12 of the semiconductor element 1 and the drain electrode 21 of the semiconductor element 2, and the lead 4B is electrically connected to the source electrode 22 of the semiconductor element 2. Therefore, the current path from the lead 4D to the lead 4B through the two semiconductor elements 1 and 2 is formed along the x direction.

[0041] Leads 4E, 4D, 4G, and 4H overlap each other when viewed in the y direction and are arranged in this order in the y direction. Also, lead 4F, the bonding portion 422 of lead 4B, lead 4I, and lead 4J overlap each other when viewed in the y direction and are arranged in this order in the y direction.

[0042] Leads 4G, 4H, 4I, and 4J each overlap lead 4C when viewed in the x direction. The two leads 4G, 4H are arranged in the x1 direction relative to lead 4C, and the two leads 4I, 4J are arranged in the x2 direction relative to lead 4C. Lead 4G and lead 4I overlap each other when viewed in the x direction. Lead 4H and lead 4J overlap each other when viewed in the x direction.

[0043] As shown in FIGS. 3 to 6, each of the leads 4A to 4J has a recess 49 formed therein. The recess 49 is a portion that is recessed from the surface facing the z1 direction to the z2 direction in each of the leads 4A to 4J. The recess 49 is formed along the outer peripheral edge of each of the leads 4A to 4J in a plan view, as shown in FIG. 3. The recess 49 is covered with the sealing member 6. In the examples shown in FIGS. 4 to 6, the wall surface of the recess 49 is curved, but it does not have to be curved. The recess 49 is provided to prevent the leads 4A to 4J from coming off.

[0044] In the present embodiment, lead 4A corresponds to the "first lead" described in the claims. Lead 4B corresponds to the "second lead" described in the claims. Lead 4C corresponds to the "third lead" described in the claims. Lead 4D corresponds to the "fourth lead" described in the claims. Lead 4E corresponds to the "fifth lead" described in the claims. Lead 4F corresponds to the "sixth lead" described in the claims. Each of the leads 4G to 4J corresponds to the "seventh lead" described in the claims.

[0045] Each of the plurality of connection members 5 electrically connects two spaced-apart members. Each connection member 5 is made of a conductive material. As shown in FIG. 2, the plurality of connection members 5 includes a plurality of wires 5A to 5N. Each of the wires 5A to 5N is a so-called bonding wire. The constituent material of each of the wires 5A to 5N may be any of, for example, a metal containing Au (gold), a metal containing Al (aluminum), or a metal containing Cu.

[0046] As shown in FIG. 2, one end of each of the plurality of wires 5A is joined to the pad portion 111 of the drain electrode 11 of the semiconductor element 1, and the other end is joined to the lead 4D. One end of each of the plurality of wires 5B is joined to the pad portion 121 of the source electrode 12 of the semiconductor element 1, and the other end is joined to the bonding portion 412 of the lead 4A. One end of each of the plurality of wires 5C is joined to the pad portion 211 of the drain electrode 21 of the semiconductor element 2, and the other end is joined to the bonding portion 412 of the lead 4A. One end of each of the plurality of wires 5D is joined to the pad portion 221 of the source electrode 22 of the semiconductor element 2, and the other end is joined to the bonding portion 422 of the lead 4B. One end of the wire 5E is joined to the pad portion 318 of the element electrode 31 of the control element 3, and the other end is joined to the bonding portion 412 of the lead 4A. One end of the wire 5F is joined to the pad portion 315 of the element electrode 31 of the control element 3, and the other end is joined to the pad portion 131 of the gate electrode 13 of the semiconductor element 1. One end of the wire 5G is joined to the lead 4E, and the other end is joined to the pad portion 132 of the gate electrode 13 of the semiconductor element 1. One end of the wire 5H is joined to the pad portion 316 of the element electrode 31 of the control element 3, and the other end is joined to the pad portion 231 of the gate electrode 23 of the semiconductor element 2. One end of the wire 5I is joined to the lead 4F, and the other end is joined to the pad portion 232 of the gate electrode 23 of the semiconductor element 2. One end of the wire 5J is joined to the pad portion 312 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4C. One end of wire 5K is joined to the pad portion 317 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4G. One end of wire 5L is joined to the pad portion 311 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4H. One end of wire 5M is joined to the pad portion 313 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4I. One end of wire 5N is joined to the pad portion 314 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4J.

[0047] In the example shown in FIG. 2, three wires 5A are joined to each of the three pad portions 111. Also, three wires 5B are joined to each of the two pad portions 121. Similarly, three wires 5C are joined to each of the three pad portions 211. Also, three wires 5D are joined to each of the two pad portions 221. Further, in wire 5E, the portion joined to the bonding portion 412 is located in the x direction between the portions joined to the bonding portion 412 of each wire 5B and the portions joined to the bonding portion 412 of each wire 5C. Note that the number of wires 5A to 5N is not limited to the numbers shown in FIG. 2, and may be appropriately changed in consideration of the area in plan view of each of the pad portions 111, 121, 131, 132, 211, 221, 231, 232, 311 to 318, the wire diameter of each of the wires 5A to 5N, and the amount of current flowing through each of the wires 5A to 5N.

[0048] In this embodiment, wire 5A corresponds to the "first connection member" described in the claims. Wire 5B corresponds to the "second connection member" described in the claims. Wire 5C corresponds to the "third connection member" described in the claims. Wire 5D corresponds to the "fourth connection member" described in the claims. Wire 5E corresponds to the "fifth connection member" described in the claims. Wire 5F corresponds to the "sixth connection member" described in the claims. Wire 5G corresponds to the "seventh connection member" described in the claims. Wire 5H corresponds to the "eighth connection member" described in the claims. Wire 5I corresponds to the "ninth connection member" described in the claims. Each of the wires 5K to 5N corresponds to the "tenth connection member" described in the claims.

[0049] The sealing member 6 is a protective member for the semiconductor elements 1 and 2 and the control element 3. The sealing member 6 covers the semiconductor elements 1 and 2, the control element 3, a part of the lead frame 4, and the plurality of connection members 5. The constituent material of the sealing member 6 is an electrically insulating resin material, for example, an epoxy resin. The sealing member 6 is, for example, rectangular in a plan view. Note that the shape of the sealing member 6 is not limited to the examples shown in FIGS. 1 to 6. The sealing member 6 has a resin front surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0050] As shown in FIGS. 4 to 6, the resin front surface 61 and the resin back surface 62 are separated in the z direction. The resin front surface 61 faces the z2 direction, and the resin back surface 62 faces the z1 direction. A part of each of the leads 4A to 4J (the surface facing the z1 direction) is exposed from the resin back surface 62. Each of the plurality of resin side surfaces 631 to 634 is sandwiched between the resin front surface 61 and the resin back surface 62 in the z direction and is connected to both of them. The resin side surfaces 631 and 632 are separated in the x direction. The resin side surface 631 faces the x1 direction, and the resin side surface 632 faces the x2 direction. The resin side surfaces 633 and 634 are separated in the y direction. The resin side surface 633 faces the y1 direction, and the resin side surface 634 faces the y2 direction.

[0051] Next, with reference to FIG. 7, the circuit configuration of the semiconductor device A1 according to the first embodiment will be described. In the following description, the reference potential is the ground voltage V GND in some cases .

[0052] FIG. 7 shows a circuit diagram in the case where the semiconductor device A1 is applied to a step-down DC / DC converter of a synchronous rectification type The DC / DC converter is a power supply circuit that steps down the input voltage Vin to generate a desired output voltage Vout. The output voltage Vout is supplied to the load LO. Note that the circuit diagram shown in FIG. 7 is an example.

[0053] As shown in FIG. 7, the semiconductor device A1 includes, in its circuit configuration, a plurality of external terminals T1 to T10, two semiconductor elements 1 and 2, and a control element 3. Also, as shown in FIG. 7, two external power supplies PS1 and PS2 and a plurality of discrete components (a plurality of capacitors C1 to C4 and an inductor L1) are connected to the semiconductor device A1. Note that one or more of the plurality of discrete components may be incorporated in the semiconductor device A1.

[0054] The external power supply PS1 generates a power supply voltage VCC for driving the control element 3. The high-potential side terminal of the external power supply PS1 is connected to the external terminal T1. The low-potential side terminal of the external power supply PS1 is connected to the first ground terminal GND1 and grounded to the reference potential. A capacitor C1 is connected in parallel to the external power supply PS1. The capacitor C1 is a bypass capacitor for stabilizing the power supply voltage VCC.

[0055] The external power supply PS2 generates an input voltage Vin. The high-potential side terminal of the external power supply PS2 is connected to the external terminal T3. The low-potential side terminal of the external power supply PS2 is connected to the second ground terminal GND2 and grounded to the reference potential. Note that although both the first ground terminal GND1 and the second ground terminal GND2 are ground terminals of the reference potential, the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 may be different. A capacitor C2 is connected in parallel to the external power supply PS2. The capacitor C2 is a bypass capacitor for stabilizing the input voltage Vin.

[0056] The inductor L1 has its first end connected to the external terminal T7 and its second end connected to the load LO and the capacitor C3. The capacitor C3 has its first end connected to the inductor L1 and its second end connected to the second ground terminal GND2. The inductor L1 and the capacitor C3 constitute an LC filter circuit. The capacitor C4 has its first end connected to the external terminal T7 and its second end connected to the external terminal T8. The capacitor C4, together with the diode D1 described later, constitutes a bootstrap circuit. The capacitor C4 generates a boost voltage VB.

[0057] The external terminal T1 is the input terminal of the power supply voltage VCC. The external terminal T1 is connected to the high-potential side terminal of the external power supply PS1. The external terminal T1 is connected to the control element 3 (connection terminal TC1 described later) inside the semiconductor device A1. The external terminal T1 corresponds to, for example, the lead 4H in the module structure of the semiconductor device A1.

[0058] The external terminal T2 is connected to the first ground terminal GND1 and grounded to the reference potential. The external terminal T2 is connected to the control element 3 (connection terminal TC2 described later) inside the semiconductor device A1. The external terminal T2 corresponds to, for example, the lead 4C in the module structure of the semiconductor device A1.

[0059] External terminal T3 is the input terminal of the input voltage Vin. External terminal T3 is connected to the high-potential side terminal of the external power supply PS2. Inside the semiconductor device A1, external terminal T3 is connected to the drain of the semiconductor element 1. External terminal T3 corresponds to, for example, lead 4D in the module structure of the semiconductor device A1.

[0060] External terminal T4 is connected to the second ground terminal GND2 and grounded to the reference potential. Inside the semiconductor device A1, external terminal T4 is connected to the source of the semiconductor element 2. External terminal T4 corresponds to, for example, lead 4B in the module structure of the semiconductor device A1.

[0061] External terminal T5 is the input terminal of the control signal SH. The control signal SH is a signal for controlling the switching operation of the semiconductor element 1. The control signal SH is, for example, a rectangular pulse wave in which the high level and the low level alternate. Inside the semiconductor device A1, external terminal T5 is connected to the control element 3 (connection terminal TC3 described later). External terminal T5 corresponds to, for example, lead 4I in the module structure of the semiconductor device A1.

[0062] External terminal T6 is the input terminal of the control signal SL. The control signal SL is a signal for controlling the switching operation of the semiconductor element 2. The control signal SL is, for example, a rectangular pulse wave in which the high level and the low level alternate. The control signal SL and the control signal SH have their high-level periods and low-level periods inverted with respect to each other. Inside the semiconductor device A1, external terminal T6 is connected to the control element 3 (connection terminal TC4 described later). External terminal T6 corresponds to, for example, lead 4J in the module structure of the semiconductor device A1.

[0063] External terminal T7 is the output terminal of the output voltage V SW . The output voltage V SWis a voltage signal generated by the switching operations of semiconductor element 1 and semiconductor element 2. External terminal T7 is connected to the connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 inside semiconductor device A1. External terminal T7 corresponds to lead 4A, for example, in the module structure of semiconductor device A1.

[0064] External terminal T8 is the input terminal for the boost voltage VB. The boost voltage VB is a voltage signal generated by capacitor C4 and diode D1 described later. External terminal T8 has the second terminal of capacitor C4 connected thereto. External terminal T8 is connected to control element 3 (connection terminal TC7 described later) inside semiconductor device A1. External terminal T8 corresponds to lead 4G, for example, in the module structure of semiconductor device A1.

[0065] External terminal T9 is the input terminal for drive signal GH2. Drive signal GH2 is a signal for driving semiconductor element 1 and is directly input from an external device (not shown). Drive signal GH2 is, for example, a rectangular pulse wave in which the high level and the low level alternate. External terminal T9 is connected to the gate of semiconductor element 1 inside semiconductor device A1. External terminal T9 corresponds to lead 4E, for example, in the module structure of semiconductor device A1.

[0066] External terminal T10 is the input terminal for drive signal GL2. Drive signal GL2 is a signal for driving semiconductor element 2 and is directly input from an external device (not shown). Drive signal GL2 is, for example, a rectangular pulse wave in which the high level and the low level alternate. Drive signal GH2 and drive signal GL2 have the high level period and the low level period inverted with respect to each other. External terminal T10 is connected to the gate of semiconductor element 2 inside semiconductor device A1. External terminal T10 corresponds to lead 4F, for example, in the module structure of semiconductor device A1.

[0067] Note that the correspondence between each external terminal T1 to T10 in the circuit configuration and each lead 4A to AJ in the module structure is not limited to the above. For example, the combination of the correspondence between each external terminal T1, T5, T6, T8 and each lead 4G to 4J can be appropriately changed. The combination of the correspondence can be appropriately changed according to the arrangement of the pad portions 311, 313, 314, 317 of the control element 3 in a plan view.

[0068] As described above, the two semiconductor elements 1 and 2 are composed of n-type MOSFETs. Each of the semiconductor elements 1 and 2 switches between a conductive state (on state) and a cutoff state (off state) according to the drive signals GH1, GH2, GL1, GL2 input to the gate. The two semiconductor elements 1 and 2 constitute a half-bridge type switching circuit. The semiconductor element 1 is the upper arm of the switching circuit, and the semiconductor element 2 is the lower arm of the switching circuit. The drain of the semiconductor element 1 is connected to the external terminal T3, and the source of the semiconductor element 1 is connected to the drain of the semiconductor element 2. The gate of the semiconductor element 1 is connected to the control element 3 (connection terminal TC5 described later) and is also connected to the external terminal T9.

[0069]

[0070] When a drive signal GH1 is input to the gate from the control element 3, the semiconductor element 1 performs a switching operation according to the drive signal GH1. When the drive signal GH1 input to the gate is at a high level, the semiconductor element 1 is in a conductive state, and when the drive signal GH1 input to the gate is at a low level, the semiconductor element 1 is in a cutoff state. Further, when a drive signal GH2 is input to the gate from the external terminal T9, the semiconductor element 1 performs a switching operation according to the drive signal GH2. When the drive signal GH2 input to the gate is at a high level, the semiconductor element 1 is in a conductive state, and when the drive signal GH2 input to the gate is at a low level, the semiconductor element 1 is in a cutoff state. Note that the semiconductor element 2 is assumed to be of a normally-off type, but it may be of a normally-on type. Also, the signal input to the gate of the semiconductor element 1 may be both of the two drive signals GH1 and GH2, or either one of them.

[0071] The drain of the semiconductor element 2 is connected to the source of the semiconductor element 1, and the source of the semiconductor element 2 is connected to the external terminal T4. The gate of the semiconductor element 2 is connected to the control element 3 (connection terminal TC6 described later) and is also connected to the external terminal T10.

[0072] When a drive signal GL1 is input to the gate from the control element 3, the semiconductor element 2 performs a switching operation according to the drive signal GL1. When the drive signal GL1 input to the gate is at a high level, the semiconductor element 2 is in a conductive state, and when the drive signal GL1 input to the gate is at a low level, the semiconductor element 2 is in a cutoff state. Further, when a drive signal GL2 is input to the gate from the external terminal T10, the semiconductor element 2 performs a switching operation according to the drive signal GL2. When the drive signal GL2 input to the gate is at a high level, the semiconductor element 2 is in a conductive state, and when the drive signal GL2 input to the gate is at a low level, the semiconductor element 2 is in a cutoff state. Note that the semiconductor element 2 is assumed to be of a normally-off type, but it may be of a normally-on type. Also, the signal input to the gate of the semiconductor element 2 may be both of the two drive signals GL1 and GL2, or either one of them.

[0073] The connection point between the source of the semiconductor element 1 and the drain of the semiconductor element 2 is connected to the external terminal T7 and is also connected to the control element 3 (connection terminal TC8 described later). By the switching operations of the semiconductor element 1 and the semiconductor element 2, an output voltage V SW is applied to the external terminal T7.

[0074] The control element 3 mainly controls the switching operations of the two semiconductor elements 1 and 2. Based on the control signals SH and SL, the control element 3 generates drive signals GH1 and GL1, and inputs the generated drive signals GH1 and GL1 to the semiconductor elements 1 and 2. The control element 3 includes a plurality of connection terminals TC1 to TC8, two drive circuits DR1 and DR2, and a diode D1 in its internal circuit. The control element 3 is an IC in which the two drive circuits DR1 and DR2 and the diode D1 are integrated into one chip.

[0075] The connection terminal TC1 is connected to the external terminal T1 and is the input terminal of the power supply voltage VCC in the control element 3. The connection terminal TC2 is connected to the external terminal T2 and is grounded to the reference potential. The connection terminal TC3 is connected to the external terminal T5 and is the input terminal of the control signal SH in the control element 3. The connection terminal TC4 is connected to the external terminal T6 and is the input terminal of the control signal SL in the control element 3. The connection terminal TC5 is the output terminal of the drive signal GH1. The connection terminal TC5 is connected to the gate of the semiconductor element 1. The connection terminal TC6 is the output terminal of the drive signal GL1. The connection terminal TC6 is connected to the gate of the semiconductor element 2. The connection terminal TC7 is connected to the external terminal T8 and is the input terminal of the boost voltage VB in the control element 3. The connection terminal TC8 is connected to the connection point between the semiconductor element 1 (source) and the semiconductor element 2 (drain).

[0076] Drive circuit DR1 generates a drive signal GH1 based on the input control signal SH. The drive signal GH1 is a signal for causing the semiconductor element 1 to perform a switching operation, and is a signal obtained by raising the control signal SH to a level necessary for the switching operation of the semiconductor element 1. The drive circuit DR1 outputs the generated drive signal GH1 from the connection terminal TC5. Since the connection terminal TC5 is connected to the gate of the semiconductor element 1, the drive signal GH1 is input to the gate of the semiconductor element 1. The drive signal GH1 is a signal that sets the boost voltage VB to a high level and the source voltage of the semiconductor element 1 to a low level. The source voltage of the semiconductor element 1 is input to the drive circuit DR1 via the connection terminal TC8. The gate voltage of the semiconductor element 1 is given with reference to the source voltage of the semiconductor element 1.

[0077] Drive circuit DR2 generates a drive signal GL1 based on the input control signal SL. The drive signal GL1 is a signal for causing the semiconductor element 2 to perform a switching operation, and is a signal obtained by raising the control signal SL to a level necessary for the switching operation of the semiconductor element 2. The drive circuit DR2 outputs the generated drive signal GL1 from the connection terminal TC6. Since the connection terminal TC6 is connected to the gate of the semiconductor element 2, the drive signal GL1 is input to the gate of the semiconductor element 2. The drive signal GL1 is a signal that sets the power supply voltage VCC to a high level and the ground voltage V GND to a low level. The gate voltage of the semiconductor element 2 is given with reference to the ground voltage V GND

[0078] The anode of the diode D1 is connected to the connection terminal TC1, and the cathode is connected to the connection terminal TC7. The diode D1, together with the capacitor C4, constitutes a bootstrap circuit. The bootstrap circuit generates the boost voltage VB and supplies it to the drive circuit DR1. Note that the diode D1 may be arranged outside the control element 3.

[0079] Next, an operation example of the semiconductor device A1 will be described.

[0080] ​ When control signals SH and SL are input from external terminals T5 and T6 to control element 3 in semiconductor device A1, drive signals GH1 and GL1 are generated by control element 3. Then, each drive signal GH1 and GL1 is input from control element 3 to each gate of semiconductor elements 1 and 2. Alternatively, each drive signal GH2 and GL2 is input from each external terminal T9 and T10 to each gate of semiconductor elements 1 and 2. As a result, a first period in which semiconductor element 1 is in a conducting state and semiconductor element 2 is in a blocking state, and a second period in which semiconductor element 1 is in a blocking state and semiconductor element 2 is in a conducting state are alternately repeated. At this time, an input voltage Vin is applied to external terminal T7 in the first period. On the other hand, in the second period, external terminal T7 is grounded to a reference potential (a ground voltage V GND is applied). Therefore , the output voltage V SW from external terminal T7 becomes a pulse wave whose high level is the input voltage Vin and whose low level is the ground voltage V GND . And the output voltage V SW is converted into an output voltage Vout of a DC voltage by being smoothed by inductor L 1 and capacitor C3. By operating as described above, semiconductor device A1 steps down (transforms) the input voltage Vin to the output voltage Vout.

[0081] The first period and the second period are alternately repeated at a predetermined cycle, and the step-down ratio can be changed according to the ratio of the first period and the second period in one cycle. For example, when the first period is 25% of one cycle (the second period is 75% of one cycle), the output voltage Vout is stepped down to 1 / 4 times the input voltage Vi n (Vout = Vin × (25 / 100)). Note that a dead time in which both semiconductor elements 1 and 2 are in a blocking state may be provided between the first period and the second period.

[0082] The functions and effects of semiconductor device A1 configured as described above are as follows.

[0083] According to the first embodiment, the semiconductor device A1 includes leads 4A, 4B, and 4C. The lead 4A and the lead 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the lead 4A and the lead 4B when viewed in the y direction. The semiconductor element 1 is mounted on the lead 4A, the semiconductor element 2 is mounted on the lead 4B, and the control element 3 is mounted on the lead 4C. As a result, the separation distance between the semiconductor element 1 and the semiconductor element 2 can be made shorter than that of the semiconductor device described in Patent Document 1. Specifically, in the semiconductor device described in Patent Document 1, in a plan view, two semiconductor elements (switching elements) are arranged on opposite sides of each other with a control element (control IC) interposed therebetween. Therefore, it is necessary to route the connection of the two semiconductor elements while avoiding the control element, and the wiring distance tends to be long. On the other hand, in the semiconductor device A1, since the control element 3 is not arranged between the semiconductor element 1 and the semiconductor element 2, the distance of the wiring connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the respective lengths of the wires 5B, 5C, and a part of the lead 4A) can be shortened. Therefore, the semiconductor device A1 can reduce parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0084] According to the first embodiment, both the leads 4A and 4B are arranged in the y2 direction with respect to the lead 4C and overlap the lead 4C when viewed in the y direction. Therefore, the lead 4A on which the semiconductor element 1 is mounted and the lead 4B on which the semiconductor element 2 is mounted can be arranged on one side (y2 direction) in the y direction, and the lead 4C on which the control element 3 is mounted can be arranged on the other side (y1 direction) in the y direction. When the semiconductor device A1 is energized, the semiconductor elements 1, 2 and the control element 3 generate heat. The amount of heat generated by the semiconductor elements 1, 2 is larger than the amount of heat generated by the control element 3. If the heat from the semiconductor elements 1, 2 is transmitted to the control element 3, the heat of the semiconductor elements 1, 2 may cause malfunction or performance degradation of the control element 3. However, the semiconductor device A1 arranges the leads 4A, 4B on one side (y2 direction side) in the y direction of the lead 4C, thereby separating and arranging the semiconductor elements 1, 2 and the control element 3. As a result, the semiconductor device A1 can suppress the heat transmitted from the semiconductor elements 1, 2 to the control element 3 and suppress malfunction or performance degradation of the control element 3.

[0085] According to the first embodiment, the leads 4D, 4A, and 4B overlap when viewed in the x direction and are arranged in this order in the x direction. Also, the pad portions 111, 121, 211, 221 of the semiconductor elements 1, 2 are each in a strip shape extending in the x direction. Thereby, the semiconductor device A1 can make the wiring of the current path (power system current path) through which the drain-source of the semiconductor element 1 and the drain-source of the semiconductor element 2 flow linear. The power system current path is the current path in the power conversion of the semiconductor device A1. In particular, when the semiconductor elements 1, 2 are driven at high frequency, since the wiring of the power system current path does not become right-angled wiring, it is effective for noise countermeasures.

[0086] According to the first embodiment, the lead 4A includes a die pad portion 411 and a bonding portion 412, which are integrally formed. Thereby, the heat from the semiconductor element 1 can be diffused not only to the die pad portion 411 but also to the bonding portion 412. Therefore, the semiconductor device A1 can suppress the rise in the junction temperature of the semiconductor element 1 due to the heat generation of the semiconductor element 1. The rise in the junction temperature is a cause of damage to the semiconductor element 1. That is, the semiconductor device A1 can suppress the damage of the semiconductor element 1. Similarly, the lead 4B includes a die pad portion 421 and a bonding portion 422, which are integrally formed. Thereby, the heat from the semiconductor element 2 can be diffused not only to the die pad portion 421 but also to the bonding portion 422. Therefore, the semiconductor device A1 can suppress the rise in the junction temperature of the semiconductor element 2 due to the heat generation of the semiconductor element 2. That is, the semiconductor device A1 can suppress the damage of the semiconductor element 2. They are integrally formed. Thereby, the heat from the semiconductor element 2 can be diffused not only to the die pad portion 421 but also to the bonding portion 422. Therefore, the semiconductor device A1 can suppress the rise in the junction temperature of the semiconductor element 2 due to the heat generation of the semiconductor element 2. That is, the semiconductor device A1 can suppress the damage of the semiconductor element 2.

[0087] According to the first embodiment, the pad portion 131 of the gate electrode 13 of the semiconductor element 1 is disposed on the edge side of the element main surface 1a that is close to the lead 4C in the y direction. Thereby, the semiconductor device A1 can shorten the separation distance between the pad portion 131 and the control element 3 in a plan view. For this reason, since the length of the wire 5F can be shortened, the parasitic inductance and parasitic resistance of the wire 5F can be suppressed. In particular, since the wire 5F is a transmission line for the drive signal GH1, the decrease in the responsiveness of the switching operation of the semiconductor element 1 and the malfunction of the switching operation can be suppressed. Similarly, the pad portion 231 of the gate electrode 23 of the semiconductor element 2 is disposed on the edge side of the element main surface 2a that is close to the lead 4C in the y direction. Thereby, the semiconductor device A1 can shorten the separation distance between the pad portion 231 and the control element 3 in a plan view. For this reason, since the length of the wire 5H can be shortened, the parasitic inductance and parasitic resistance of the wire 5H can be suppressed. In particular, since the wire 5H is a transmission line for the drive signal GL1, the decrease in the responsiveness of the switching operation of the semiconductor element 2 and the malfunction of the switching operation can be suppressed.

[0088] According to the first embodiment, the lead 4E is disposed in the vicinity of the pad portion 132 in a plan view, and is closest to the pad portion 132 among the other leads (excluding the lead 4A). Thereby, the length of the wire 5G connecting the lead 4E and the pad portion 132 can be shortened, so that the parasitic inductance and parasitic resistance of the wire 5G can be suppressed. In particular, when the drive signal GH2 is input from an external device to the semiconductor device A1, since the wire 5G is a transmission line of the drive signal GH2, a decrease in the responsiveness of the switching operation of the semiconductor element 1 and a malfunction of the switching operation can be suppressed. Further, the lead 4F is disposed in the vicinity of the pad portion 232 in a plan view, and is closest to the pad portion 132 among the other leads (excluding the lead 4B). Thereby, the length of the wire 5I connecting the lead 4F and the pad portion 232 can be shortened, so that the parasitic inductance and parasitic resistance of the wire 5I can be suppressed. In particular, when the drive signal GL2 is input from an external device to the semiconductor device A1, since the wire 5I is a transmission line of the drive signal GL2, a decrease in the responsiveness of the switching operation of the semiconductor element 2 and a malfunction of the switching operation can be suppressed.

[0089] <Second Embodiment> Next, the semiconductor device A2 according to the second embodiment will be described with reference to FIG. 8. FIG. 8 is a plan view showing the semiconductor device A2, and the sealing member 6 is indicated by an imaginary line (two-dot chain line).

[0090] As shown in FIG. 8, the semiconductor device A2 has a different lead frame 4 configuration compared to the semiconductor device A1. Specifically, the lead frame 4 of the semiconductor device A2 does not include the leads 4E and 4F, unlike the lead frame 4 of the semiconductor device A1.

[0091] As shown in FIG. 8, the lead frame 4 of the semiconductor device A2 has the lead 4D extended to the position where the lead 4E was disposed because there is no lead 4E. Similarly, as shown in FIG. 8, the bonding portion 422 of the lead 4B is extended to the position where the lead 4E was disposed because there is no lead 4F. Further, since there are no leads 4E and 4F, the plurality of connection members 5 do not include the wires 5G and 5I.

[0092] According to the second embodiment, the semiconductor device A2 includes leads 4A, 4B, and 4C, similar to the semiconductor device A1. The lead 4A and the lead 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the lead 4A and the lead 4B when viewed in the y direction. Therefore, similar to the semiconductor device A1, the semiconductor device A2 can shorten the distance of the wiring (in this embodiment, the respective lengths of the wires 5B, 5C, and a part of the lead 4A) that connects the semiconductor element 1 and the semiconductor element 2. Therefore, the semiconductor device A2 can reduce parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0093] According to the second embodiment, the lead 4D of the semiconductor device A2 is extended more than that of the semiconductor device A1. Thereby, the semiconductor device A2 can reduce the wiring resistance in the lead 4D more than the semiconductor device A1. In particular, since the lead 4D is a part of the power system current path described above, the semiconductor device A2 can suppress the power loss in power conversion more than the semiconductor device A1. Similarly, the bonding portion 422 of the lead 4B of the semiconductor device A2 is extended more than that of the semiconductor device A1. Thereby, the semiconductor device A2 can reduce the wiring resistance in the lead 4B more than the semiconductor device A1. In particular, since the lead 4B is a part of the power system current path described above, the semiconductor device A2 can suppress the power loss in power conversion more than the semiconductor device A1. Further, the semiconductor element 2 is mounted on the lead 4B, and heat from the semiconductor element 2 is transmitted. Therefore, by expanding the lead 4B (bonding portion 422), the heat dissipation efficiency from the semiconductor element 2 can be improved.

[0094] <Third Embodiment> Next, the semiconductor device A3 according to the third embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view showing the semiconductor device A3, in which the sealing member 6 is shown by an imaginary line (two-dot chain line). FIG. 10 is a cross-sectional view taken along the line X-X of FIG. 9. Note that, similar to the second embodiment, in the semiconductor device A3, the lead frame 4 may not include the leads 4E and 4F.

[0095] As shown in FIGS. 9 and 10, the semiconductor device A3 is different from the semiconductor device A1 in that a plurality of connection members 5 include clips 7A, 7B, 7C, and 7D instead of the wires 5A, 5B, 5C, and 5D. Note that, compared with the semiconductor device A1, in the semiconductor device A3 shown in FIG. 9, in the semiconductor element 1, a plurality of pad portions 111 (drain electrodes 11) and a plurality of pad portions 121 (source electrodes 12) are interchanged.

[0096] Each of the clips 7A to 7D is formed by bending a plate-shaped metal member. The constituent material of the clips 7A to 7D is, for example, a metal containing Cu or a metal containing Al. Alternatively, it may be a clad material such as CIC (Copper-Invar-Copper). Note that, in the example shown in FIG. 10, each of the clips 7A to 7D is bent vertically with respect to the upper surfaces of the respective leads 4A, 4B, and 4D, but may be inclined with respect to the z direction.

[0097] Clip 7A has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portion is joined to each of the plurality of pad portions 111. Clip 7B has a comb-like shape on one side in the x direction (the x1 direction side in FIG. 9), and the comb-like portion is joined to each of the plurality of pad portions 121. Clip 7C has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portion is joined to each of the plurality of pad portions 211. Clip 7D has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portion is joined to each of the plurality of pad portions 221. Note that the shapes of the clips 7A to 7D are not limited to the examples shown in FIG. 9.

[0098] According to the third embodiment, the semiconductor device A3 includes leads 4A, 4B, and 4C, similar to the semiconductor device A1. The lead 4A and the lead 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the lead 4A and the lead 4B when viewed in the y direction. Therefore, similar to the semiconductor device A1, the semiconductor device A3 can shorten the distance of the wiring (in this embodiment, the respective lengths of a part of each of the clips 7B, 7C, and the lead 4A) that connects the semiconductor element 1 and the semiconductor element 2. Therefore, the semiconductor device A3 can reduce parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0099] According to the third embodiment, the plurality of connection members 5 include clips 7A instead of wires 5A. The clips 7A can have a lower wiring resistance than the wires 5A. In particular, since the clips 7A are part of the power system current path described above, the semiconductor device A3 can suppress power loss in power conversion more than the semiconductor device A1. Similarly, the plurality of connection members 5 include clips 7B, 7C, and 7D instead of wires 5B, 5C, and 5D. Each of the clips 7B, 7C, and 7D can have a lower wiring resistance than the respective wires 5B, 5C, and 5D. In particular, since each of the clips 7B, 7C, and 7D is part of the power system current path described above, the semiconductor device A3 can suppress power loss in power conversion more than the semiconductor device A1.

[0100] In the third embodiment, a case where each of the clips 7A to 7D has a partially bent structure is shown, but the present invention is not limited to this. For example, as shown in FIG. 11, each of the clips 7A to 7D may have a structure in which a part of its thickness (dimension in the z direction) is changed. FIG. 11 is a cross-sectional view of the semiconductor device according to this modification, corresponding to the cross-section shown in FIG. 10. For example, as shown in FIG. 11, each of the clips 7A to 7D has a thin portion joined to the semiconductor element 1 or the semiconductor element 2 and a thick portion joined to any of the leads 4A, 4B, and 4D.

[0101] In the third embodiment, a case where the clip 7A has a comb-tooth-shaped portion and this comb-tooth-shaped portion is joined to a plurality of pad portions 111 (drain electrodes 11) is shown, but the present invention is not limited to this. For example, a plurality of strip-shaped clips 7A may be provided, and one clip 7A may be joined to each of the plurality of pad portions 111. The same applies to the clips 7B to 7D.

[0102] <Fourth Embodiment> Next, the semiconductor device A4 according to the fourth embodiment will be described with reference to FIG. 12. FIG. 12 is a plan view showing the semiconductor device A4, in which the sealing member 6 is indicated by an imaginary line (two-dot chain line). Note that, similar to the second embodiment, the lead frame 4 in the semiconductor device A4 may not include the leads 4E and 4F. Also, similar to the third embodiment, in the semiconductor device A4, each clip 7A to 7D may be used instead of each wire 5A to 5D.

[0103] As shown in FIG. 12, the semiconductor device A4 has a different configuration of each electrode (drain electrodes 11 and 21 and source electrodes 12 and 22) of the semiconductor elements 1 and 2 compared to the semiconductor device A1. Specifically, the planar view shapes of the respective pad portions 111, 121, 211, and 221 are different.

[0104] Each pad portion 111 of the semiconductor device A4 is tapered. Specifically, each pad portion 111 has a smaller dimension in the y direction from the edge on the x1-direction side to the edge on the x2-direction side in the x direction. Each pad portion 111 is substantially triangular in a plan view. Also, each of the pad portions 121, 211, and 221 is tapered. Specifically, each pad portion 121 has a smaller dimension in the y direction from the edge on the x2-direction side to the edge on the x1-direction side in the x direction. Each pad portion 211 has a smaller dimension in the y direction from the edge on the x1-direction side to the edge on the x2-direction side in the x direction. Each pad portion 221 has a smaller dimension in the y direction from the edge on the x2-direction side to the edge on the x1-direction side in the x direction. Each of the pad portions 121, 211, and 221 is substantially triangular in a plan view.

[0105] According to the fourth embodiment, the semiconductor device A4 includes leads 4A, 4B, and 4C, similar to the semiconductor device A1. The lead 4A and the lead 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the lead 4A and the lead 4B when viewed in the y direction. Therefore, similar to the semiconductor device A1, the semiconductor device A4 can shorten the distance of the wiring (in this embodiment, the lengths of the respective wires 5B, 5C and a part of the lead 4A) connecting the semiconductor element 1 and the semiconductor element 2. Therefore, the semiconductor device A4 can reduce parasitic inductance and parasitic resistance, and thus can achieve high efficiency and energy saving.

[0106] In the first to fourth embodiments, the case where the recesses 49 are formed in the leads 4A to 4J of the semiconductor devices A1 to A4 is shown, but the present invention is not limited thereto, and the recesses 49 may not be formed. Further, in each of the semiconductor devices A1 to A4, the recess 49 is shown as being formed along the outer peripheral edge of each of the leads 4A to 4J in plan view, but the present invention is not limited thereto. For example, as shown in FIG. 13, the recess 49 may be formed along the edge of each of the leads 4A to 4J in plan view that contacts any of the resin side surfaces 631 to 634. FIG. 13 is a perspective view showing the semiconductor device according to the modification, and shows the case when viewed from the bottom side. In this case, the sealing member 6 is formed with a recess 69 along the outer peripheral edge in plan view. The recess 49 and the recess 69 are connected. When the semiconductor device shown in FIG. 13 is mounted on a circuit board of an electronic device or the like by solder, it is easy to form a solder fillet. Therefore, the possibility of visually checking the soldering state of the semiconductor device, which is a leadless package, can be increased.

[0107] In the first to fourth embodiments, the case where each semiconductor device A1 to A4 has a SON-type package format has been shown, but the present invention is not limited thereto, and other package formats may be used. For example, it may be configured in package formats such as BGA (Ball Grid Array) type, LGA (Land Grid Array) type, QFP (Quad Flat Package) type, QFN (Quad Flat Non-lead) type, etc. It may be configured in a package format. Note that these package formats are merely examples and are not limited thereto. For example, FIG. 14 shows a semiconductor device (bottom view) formed in a QFN-type package format.

[0108] The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device of the present disclosure can be freely designed in various ways.

[0109] The semiconductor device according to the present disclosure includes embodiments related to the following supplementary notes. [Supplementary Note 1] A first semiconductor element having a first main surface and a first back surface spaced apart in the thickness direction, and a first drain electrode, a first source electrode, and a first gate electrode disposed on the first main surface; A second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, and a second drain electrode, a second source electrode, and a second gate electrode disposed on the second main surface; A control element electrically connected to the first gate electrode and the second gate electrode; A lead frame including a plurality of leads spaced apart from each other; and The plurality of leads include a first lead facing the first back surface and on which the first semiconductor element is mounted, a second lead facing the second back surface and on which the second semiconductor element is mounted, and a third lead on which the control element is mounted. The first lead and the second lead overlap each other when viewed in a first direction orthogonal to the thickness direction. The semiconductor device is characterized in that, when viewed in a second direction orthogonal to both the thickness direction and the first direction, the third lead overlaps both the first lead and the second lead. [Appendix 2] The first gate electrode is disposed at an edge portion far from the second semiconductor element in the first direction. The semiconductor device according to Appendix 1, wherein the second gate electrode is disposed at an edge portion far from the first semiconductor element in the first direction. [Appendix 3] The semiconductor device according to Appendix 2, wherein both the first drain electrode and the first source electrode are strip-shaped extending in the first direction and are arranged side by side in the second direction. [Appendix 4] The semiconductor device according to Appendix 3, wherein both the second drain electrode and the second source electrode are strip-shaped extending in the first direction and are arranged side by side in the second direction. [Appendix 5] The semiconductor device further includes a first connection member having one end joined to the first drain electrode. The plurality of leads further includes a fourth lead to which the other end of the first connection member is joined. The semiconductor device according to Appendix 4, wherein the fourth lead overlaps both the first lead and the second lead when viewed in the first direction and is located on the opposite side of the second lead across the first lead in the first direction. [Appendix 6] The semiconductor device further includes a second connection member having one end joined to the first source electrode. The first lead includes a first die pad portion to which the first semiconductor element is joined and a first bonding portion to which the other end of the second connection member is joined. The semiconductor device according to Appendix 5, wherein the first bonding portion is located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction. [Appendix 7] The semiconductor device further includes a third connection member having one end joined to the second drain electrode. The semiconductor device according to supplementary note 6, wherein the other end of the third connecting member is joined to the first bonding portion. [Supplementary note 8] The semiconductor device according to supplementary note 7, wherein the first die pad portion and the first bonding portion are integrally formed. [Supplementary note 9] Further comprising a fourth connecting member having one end joined to the second source electrode, The second lead includes a second die pad portion to which the second semiconductor element is joined and a second bonding portion to which the other end of the fourth connecting member is joined. The semiconductor device according to supplementary note 7 or 8, wherein the second die pad portion is closer to the first die pad portion than the second bonding portion when viewed in the thickness direction. [Supplementary note 10] The semiconductor device according to supplementary note 9, wherein the second die pad portion and the second bonding portion are integrally formed. [Supplementary note 11] Further comprising a fifth connecting member having one end joined to the control element, The semiconductor device according to supplementary note 9 or 10, wherein the other end of the fifth connecting member is joined to the first bonding portion. [Supplementary note 12] The semiconductor device according to supplementary note 11, wherein the other end of the fifth connecting member is joined between the other end of the second connecting member and the other end of the third connecting member in the first direction. [Supplementary note 13] Further comprising a sixth connecting member having one end joined to the control element, The first gate electrode has two first pad portions spaced apart from each other in the second direction, The semiconductor device according to any one of supplementary notes 9 to 12, wherein the other end of the sixth connecting member is joined to one of the two first pad portions. [Supplementary note 14] The semiconductor device according to supplementary note 13, wherein the two first pad portions are at the same potential in the first semiconductor element. [Supplementary note 15] Further comprising a seventh connection member having one end joined to the other of the two first pad portions, The semiconductor device according to appendix 13 or appendix 14, wherein the plurality of leads further includes a fifth lead to which the other end of the seventh connection member is joined. [Appendix 16] One of the two first pad portions is disposed on an edge side closer to the third lead in the second direction of the first main surface when viewed in the thickness direction, The semiconductor device according to appendix 15, wherein the other of the two first pad portions is disposed on an edge side farther from the third lead in the second direction of the first main surface when viewed in the thickness direction. [Appendix 17] The semiconductor device according to appendix 16, wherein the fifth lead is disposed adjacent to the fourth lead in the second direction. [Appendix 18] Further comprising an eighth connection member having one end joined to the control element, The second gate electrode has two second pad portions spaced apart from each other in the second direction, The semiconductor device according to any one of appendix 15 to appendix 17, wherein the other end of the eighth connection member is joined to one of the two second pad portions. [Appendix 19] The semiconductor device according to appendix 18, wherein the two second pad portions are at the same potential in the second semiconductor element. [Appendix 20] Further comprising a ninth connection member having one end joined to the other of the two second pad portions, The semiconductor device according to appendix 18 or appendix 19, wherein the plurality of leads further includes a sixth lead to which the other end of the ninth connection member is joined. [Appendix 21] One of the two second pad portions is disposed on an edge side closer to the third lead in the second direction of the second main surface when viewed in the thickness direction, The semiconductor device according to appendix 20, wherein the other of the two second pad portions is disposed on an edge side farther from the third lead in the second direction of the second main surface when viewed in the thickness direction. [Appendix 22] The semiconductor device according to Appendix 21, wherein the sixth lead is disposed adjacent to the second die pad portion in the second direction. [Appendix 23] The semiconductor device according to Appendix 22, wherein the fifth lead and the sixth lead overlap when viewed in the first direction. [Appendix 24] Further comprising a plurality of tenth connection members each having one end joined to the control element, The plurality of leads further includes a plurality of seventh leads to which the other ends of the plurality of tenth connection members are joined, The semiconductor device according to any one of Appendices 9 to 23, wherein all of the plurality of seventh leads overlap the third lead when viewed in the first direction. [Appendix 25] The semiconductor device according to Appendix 24, wherein among the plurality of seventh leads, there are those that overlap the fourth lead when viewed in the second direction and those that overlap the second die pad portion when viewed in the second direction. [Appendix 26] The semiconductor device according to any one of Appendices 1 to 25, wherein each constituent material of the first semiconductor element and the second semiconductor element is gallium nitride.

Explanation of Reference Numerals

[0110] A1 to A4: Semiconductor device 1: Semiconductor element 1a: Main surface of the element 1b: Back surface of the element 11: Drain electrode 111: Pad portion 12: Source electrode 121: Pad portion 13: Gate electrode 131, 132: Pad portions 2: Semiconductor element 2a: Main surface of the element 2b: Back surface of the element 21: Drain electrode 211: Pad portion 22: Source electrode 221: Pad portion 23: Gate electrode 231, 232: Pad portion 3: Control element 3a: Main surface of the element 3b: Back surface of the element 31: Element electrode 311~318: Pad portion 4: Lead frame 4A~4J: Lead 411, 421: Die pad portion 412, 422: Bonding portion 49: Concave portion 5: Connection member 5A~5N: Wire 6: Sealing member 7A~7D: Clip 61: Main surface of the resin 62: Back surface of the resin 631~634: Side surface of the resin 69: Concave portion C1~C4: Capacitor D1: Diode DR1, DR2: Drive circuit GND1: First ground terminal GND2: Second ground terminal L1: Inductor LO: Load PS1, PS2: External power supply T1~T10: External terminal TC1~TC8: Connection terminal

Claims

1. a first semiconductor element having a first main surface and a first back surface spaced apart in a thickness direction, the first main surface having a first drain electrode, a first source electrode, and a first gate electrode disposed thereon; a second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, the second main surface having a second drain electrode, a second source electrode, and a second gate electrode disposed thereon; a control element conductive to the first gate electrode and the second gate electrode; a lead frame including a plurality of spaced apart leads; a second connection member having one end joined to the first source electrode; a third connection member having one end joined to the second drain electrode; Equipped with the plurality of leads include a first lead facing the first rear surface and having the first semiconductor element mounted thereon, a second lead facing the second rear surface and having the second semiconductor element mounted thereon, and a third lead having the control element mounted thereon; the first lead and the second lead overlap each other when viewed in a first direction perpendicular to the thickness direction, the third lead overlaps both the first lead and the second lead when viewed in a second direction perpendicular to both the thickness direction and the first direction; the first lead includes a first die pad portion to which the first semiconductor element is joined, and a first bonding portion to which the other end of the second connection member is joined; the first bonding portion is located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction, The other end of the third connection member is joined to the first bonding portion. A semiconductor device comprising:

2. the first gate electrode is disposed at an edge portion farther from the second semiconductor element in the first direction; the second gate electrode is disposed at an edge portion farther from the first semiconductor element in the first direction; The semiconductor device according to claim 1 .

3. the first drain electrode and the first source electrode are both strip-shaped extending in the first direction and aligned in the second direction; The semiconductor device according to claim 2 .

4. the second drain electrode and the second source electrode are both strip-shaped extending in the first direction and aligned in the second direction; The semiconductor device according to claim 3 .

5. a first connection member having one end joined to the first drain electrode, the plurality of leads further includes a fourth lead to which the other end of the first connection member is joined; the fourth lead overlaps both the first lead and the second lead when viewed in the first direction, and is located on an opposite side of the second lead with the first lead interposed therebetween in the first direction; The semiconductor device according to claim 4.

6. the first die pad portion and the first bonding portion are integrally formed. The semiconductor device according to claim 5 .

7. a fourth connection member having one end joined to the second source electrode, the second lead includes a second die pad portion to which the second semiconductor element is joined and a second bonding portion to which the other end of the fourth connection member is joined; the second die pad portion is closer to the first die pad portion than the second bonding portion when viewed in the thickness direction; The semiconductor device according to claim 6.

8. the second die pad portion and the second bonding portion are integrally formed. The semiconductor device according to claim 7.

9. a fifth connection member having one end joined to the control element; The other end of the fifth connection member is joined to the first bonding portion.

9. The semiconductor device according to claim 7 or 8.

10. the other end of the fifth connection member is joined between the other end of the second connection member and the other end of the third connection member in the first direction; The semiconductor device according to claim 9.

11. a sixth connecting member having one end connected to the control element; the first gate electrode has two first pad portions spaced apart from each other in the second direction; The other end of the sixth connection member is joined to one of the two first pad portions. The semiconductor device according to claim 7 .

12. The two first pad portions are at the same potential in the first semiconductor element. The semiconductor device according to claim 11.

13. a seventh connecting member having one end joined to the other of the two first pad portions; The plurality of leads further includes a fifth lead to which the other end of the seventh connection member is joined. The semiconductor device according to claim 11 or 12.

14. the one of the two first pad portions is disposed on an edge side of the first main surface, which is closer to the third lead in the second direction, as viewed in the thickness direction; the other of the two first pad portions is disposed on an edge side of the first main surface farther from the third lead in the second direction as viewed in the thickness direction; The semiconductor device according to claim 13.

15. the fifth lead is disposed adjacent to the fourth lead in the second direction; The semiconductor device according to claim 14.

16. an eighth connecting member having one end joined to the control element; the second gate electrode has two second pad portions spaced apart from each other in the second direction; The other end of the eighth connection member is joined to one of the two second pad portions.

16. The semiconductor device according to claim 13,

17. The two second pad portions are at the same potential in the second semiconductor element. The semiconductor device according to claim 16.

18. Further, a ninth connecting member is provided, one end of which is joined to the other of the two second pad portions, The plurality of leads further includes a sixth lead to which the other end of the ninth connection member is joined. The semiconductor device according to claim 16 or 17.

19. the one of the two second pad portions is disposed on an edge side of the second main surface, which is closer to the third lead in the second direction, as viewed in the thickness direction; the other of the two second pad portions is disposed on an edge side of the second main surface farthest from the third lead in the second direction as viewed in the thickness direction; The semiconductor device according to claim 18.

20. the sixth lead is disposed adjacent to the second bonding portion in the second direction; 20. The semiconductor device according to claim 19.

21. the fifth lead and the sixth lead overlap when viewed in the first direction; The semiconductor device according to claim 20.

22. a plurality of tenth connection members, each having one end joined to the control element; the plurality of leads further includes a plurality of seventh leads to which the other ends of the plurality of tenth connection members are joined, all of the seventh leads overlap the third leads when viewed in the first direction; 22. The semiconductor device according to claim 7.

23. The seventh leads include one that overlaps the fourth lead when viewed in the second direction and one that overlaps the second bonding portion when viewed in the second direction. The semiconductor device according to claim 22.

24. 24. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are made of gallium nitride.

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