Three-dimensional memory device with drain selection gate cut structure and method for forming the same

Abstract

To provide a structure and a method for forming a three-dimensional (3D) memory device.SOLUTION: In one example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of staircases each having at least a laterally extending conductor / dielectric pair. The staircase region includes a drain select gate (DSG) cut structure extending along the lateral and vertical directions, and a plurality of support structures extending within the DSG structure along the vertical direction. At least one dimension along a lateral direction of the support structure is greater than a dimension along a second lateral direction perpendicular to the lateral direction.SELECTED DRAWING: Figure 1C

Description

Technical Field

[0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for forming 3D memory devices with drain select gate (DSG) cut structures.

Background Art

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cells approaches the lower limit, planar processes and manufacturing technologies become difficult and costly. As a result, the memory density for planar memory cells approaches the upper limit.

[0003] 3D memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals between the memory arrays.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of a 3D memory device and a method for forming a 3D memory device with a DSG cut structure are provided.

Means for Solving the Problems

[0005] In one example, a 3D memory device includes a core region and a stepped region having a plurality of steps each having at least a conductor / dielectric pair extending laterally. The stepped region includes a DSG cut structure extending along lateral and vertical directions and a plurality of support structures extending into the DSG structure along the vertical direction. At least one of the support structures has a dimension along the lateral direction that is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

[0006] In another example, a method for forming a 3D memory device includes the following operations. First, a dielectric stack having a plurality of first / second dielectric layer pairs is formed on a substrate. A DSG cut opening is formed in the core region of the dielectric stack. A staircase structure having a plurality of steps is formed extending laterally along the staircase region of the dielectric stack. In a process different from the DSG cut opening, a second DSG cut opening is formed in the staircase region and extends laterally. A DSG cut structure is formed in the DSG cut opening, and a second DSG cut structure is formed in the second DSG cut opening.

[0007] In a further example, a method for forming a 3D memory device includes the following operations. First, a dielectric stack having a plurality of first / second dielectric layer pairs is formed on a substrate. A channel structure is formed in the core region of the dielectric stack. A staircase structure is formed having a plurality of steps extending laterally along the staircase region of the dielectric stack. In the same process, a DSG cut opening is formed in the core region of the dielectric stack, and a second DSG cut opening is formed in the staircase region of the dielectric stack. A DSG cut structure is formed in the DSG cut opening, and a second DSG cut structure is formed in the second DSG cut opening.

[0008] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one of ordinary skill in the art to make and use the present disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0012] References to "one embodiment", "an embodiment", "an example embodiment", "some embodiments", etc. in the specification are to be noted as indicating that the described embodiments can include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Also, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in relation to one embodiment, it would be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments, whether or not explicitly described.

[0013] Generally, terms can be understood at least in part from their usage in context. For example, the term "one or more" as used herein can be used, at least in part depending on the context, to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a", "an", or "the" can also be understood, at least in part depending on the context, to convey a singular usage or a plural usage. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of elements, but rather, again, at least in part depending on the context, to allow for the presence of additional elements that are not necessarily explicitly described.

[0014] As used herein, the term "nominal / nominally" refers to the desired, or target, value of a characteristic or parameter for a component or process operation, as set during the design stage of a product or process, along with a range of values above and / or below that desired value. The range of values may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device in question. Based on that particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10 - 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0015] As used herein, a stepped structure refers to a set of surfaces that includes at least two horizontal planes (e.g., along the x - y plane) and at least two (e.g., first and second) vertical planes (e.g., along the z - axis), with each horizontal plane adjacent to a first vertical plane that extends upward from a first edge of the horizontal plane and adjacent to a second vertical plane that extends downward from a second edge of the horizontal plane. A "step" or "staircase" refers to a vertical change in height of a set of adjacent surfaces. In the present disclosure, the terms "staircase" and "step" refer to one level of the stepped structure and are used interchangeably. In the present disclosure, the horizontal direction can refer to a direction (e.g., the x - axis or y - axis) parallel to the top surface of a substrate (e.g., a substrate that provides a manufacturing platform for forming structures thereon), and the vertical direction can refer to a direction (e.g., the z - axis) perpendicular to the top surface of the structure.

[0016] NAND flash memory devices are widely used in various electronic products and are non-volatile, lightweight, low-power consuming, and high-performance. Currently, planar NAND flash memory devices have reached their storage limits. To further increase the storage capacity and reduce the storage cost per bit, 3D NAND memory devices have been proposed. Existing 3D NAND memory devices generally include multiple memory blocks. Adjacent memory blocks are generally separated by a gate line slit (GLS) where an array common source (ACS) is formed. To further control the memory cells in a memory block, a DSG cut structure, such as a top select gate (TSG) cut structure, is formed in the memory block. The TSG cut structure can be formed in both the core region and the staircase region of the 3D NAND memory device. The conductor layers, such as gate electrodes, divided by the TSG cut structure can be selected to perform various operations on the desired parts (e.g., memory cells) of the 3D NAND memory device.

[0017] As the demand for higher memory capacity continues, 3D NAND memory devices with a multi-deck structure have been proposed. Compared with existing 3D NAND memory devices, 3D NAND memory devices with a multi-deck structure generally have more levels (or pairs or tiers of conductor / dielectric layers) along the vertical direction. With the increase in the number of levels, the existing method of forming a TSG cut structure in the staircase region becomes difficult. For example, in an existing manufacturing process for forming a 3D NAND memory device with a dual-deck structure, before forming the channel structure, the staircases in the lower deck and the upper deck are formed separately. The TSG cut structure of the multi-deck structure is formed after the staircase of the upper deck is formed. The formation of the TSG cut structure generally includes patterning the staircase and the core region and depositing a dielectric material. In the multi-deck structure, since the number of levels increases, after the channel structure is partially / fully formed, the staircase of the entire multi-deck structure is formed. The TSG cut structure is formed before the formation of the staircase, for example, by patterning the core region and the staircase region and transferring the pattern onto the staircase. As a result, undesirable dielectric materials for forming the TSG cut structure, such as silicon oxide, may remain on the surface of the staircase. The remaining dielectric affects the electrical contact between the conductor layer and the contact on the conductor layer, which may impair the performance of the 3D NAND memory device.

[0018] The present disclosure provides a 3D memory device (e.g., a 3D NAND memory device) having a multi-deck structure with a TSG cut structure and a method for forming the 3D memory device. The 3D memory device includes a stack structure having at least two decks stacked along a vertical direction (e.g., the z-axis) on a substrate. In a staircase region of the 3D memory device, the staircase extends along a lateral direction (e.g., the x-axis). A TSG cut structure extends into the staircase along the lateral and vertical directions and divides the staircase into a pair of portions. A plurality of support structures (e.g., pillars or dummy channel structures) are aligned with the TSG cut structure along the lateral direction and overlap the TSG cut structure along a horizontal plane (e.g., extend through or into the TSG cut structure). The support structure can include a dielectric material such as silicon oxide and can extend from the top surface of the staircase to the bottom of the staircase region (e.g., to contact the substrate). The TSG cut structure includes the same dielectric material as the support structure and has a thickness / depth of at least four conductor / dielectric pairs along the vertical direction.

[0019] The length / depth of the support structure can be equal to or greater than the depth of the TSG cut structure. In some embodiments, the bottom surface of the TSG cut structure reaches or nominally reaches the bottom of the staircase region (or the top surface of the substrate). That is, the depth of the TSG cut structure can be equal to or nominally equal to the distance between the top surface of the staircase in which the TSG cut structure is disposed and the bottom of the staircase structure (or the top surface of the substrate). The lateral dimension of the support structure can be larger than that of a conventional support structure. In some embodiments, along a second lateral direction (e.g., the y-axis) perpendicular to the lateral direction, the dimension of the support structure is larger than that of the TSG cut structure. In some embodiments, the support structure has an elliptical shape and its dimension along the lateral direction is larger than that of the second lateral direction.

[0020] The present disclosure provides various methods for reducing or eliminating undesirable dielectric residues on steps in a 3D memory device and improving electrical contact between a conductor layer and a contact. In the present disclosure, in order to accommodate more levels with a stack structure, the order of forming a TSG cut structure, a support structure, and a channel structure in a step region, a core region, and the step region can be changed. The TSG cut structure and the support structure in the step region can be formed by the same operation or different operations. The TSG cut structures in the step region and the core region can be formed by the same operation or different operations. In some embodiments, the TSG cut structure and the channel structure in the core region are formed before the formation of the TSG cut structure and the support structure in the step region. For example, a portion of the stack structure in the step region can be patterned using, for example, a single photomask and the same etching process to form openings for the TSG cut structure and the support structure in the step region. The openings for forming the TSG cut structure and the support structure in the step region can also be formed by separate operations. In some embodiments, the openings for forming the TSG cut structure in the step region and the core region can be formed by the same patterning operation after the steps are formed.

[0021] To facilitate the illustration, as an example, a TSG cut structure is described to explain the formation of a DSG cut structure that can be at any suitable location in a 3D memory device. Typically, a TSG cut structure is formed at the top of the core region and the staircase region. However, in various embodiments / applications, the location of the TSG cut structure can be changed as a result of the manufacturing process. For example, the TSG cut structure can be at the top, center, or bottom in a 3D memory device, depending on the manufacturing process. In a 3D memory device formed by hybrid bonding, the TSG cut structure at the top of one wafer can be inverted and placed at the bottom / central portion of the bonded structure. That is, the structure and formation of the TSG cut structure are described herein, but the final location of the TSG cut structure in a 3D memory device should not be limited by the embodiment. Thus, the term "DSG cut structure" in the present disclosure is used to represent a cut structure that is formed by the disclosed method and can be placed at any suitable location in a 3D memory device. The DSG cut structure can be a TSG cut structure in a 3D memory device or another cut structure placed at the center or bottom of another 3D memory device. On the other hand, the description of the embodiments in the present disclosure emphasizes the structures and methods for forming the staircase region and the core region of a 3D memory device. There may be little or minimal description of other parts of the 3D memory device, such as the structures and methods for forming the transition region between the staircase region and the core region.

[0022] Figures 1A-1C illustrate an exemplary 3D memory device 100 having a dual deck structure according to some embodiments. The 3D memory device 100 can include a staircase region (“SS region”) and a core region (“core region”), and optionally, a transition region (“transition region”) therebetween. FIGS. 1A and 1B each show a cross-sectional view of the 3D memory device 100 along the A-A’ direction (e.g., along the x-z plane) as shown in FIG. 1C. FIGS. 1A and 1B show possible different structures of the 3D memory device 100. FIG. 1C shows a top view of the 3D memory device 100 along the x-y plane.

[0023] As shown in FIGS. 1A and 1C, the 3D memory device 100 can include a substrate 102 and a stack structure 104 on the substrate 102. The stack structure 104 can be a memory stack with a plurality of memory cells. The 3D memory device 100 (or the stack structure 104) can be divided into a staircase region, a core region, and a transition region (if any) between the staircase region and the core region. The 3D memory device 100 can include a plurality of alternating conductor layers 106 and dielectric layers 108 that extend in the core region, the staircase region, and the transition region (if any).

[0024] In the core region, the 3D memory device 100 can include one or more channel structures 117 and one or more dummy channel structures 116 that extend vertically (e.g., along the z-axis) in the stack structure 104. The 3D memory device 100 can include one or more source contact structures 124 that extend horizontally (e.g., along the x-axis) and vertically within the stack structure 104 in the core region and the staircase region. In the core region, the 3D memory device 100 can also include one or more TSG cut structures 110 that extend horizontally (e.g., along the x-axis) and vertically (e.g., along the z-axis). The TSG cut structures 110 can be formed on the plurality of dummy channel structures 116, which are distinguishable from the channel structures 117. In some embodiments, the dummy channel structures 116 do not have a drain structure and thus do not function as channel structures 117. The stack structure 104 can include a first memory stack (e.g., as a first deck) on the substrate 102 and a second memory stack (e.g., as a second deck) on the first memory stack.

[0025] In the staircase region, the 3D memory device 100 can include a plurality of staircases that extend along the lateral direction (e.g., the x-direction). In some embodiments, the 3D memory device 100 includes an insulating structure 118 in which the stack structure 104 is disposed. In the staircase region, the 3D memory device 100 can also include TSG cut structures 112 that extend in the x-z plane in the staircases and a plurality of support structures 114 and 126 that extend along the vertical direction (e.g., the z-axis). In some embodiments, one TSG cut structure 112 is aligned with each TSG cut structure 110 along the x-axis. In some embodiments, each TSG cut structure 112 is in contact with each TSG cut structure 110, for example, through a transition region (if any).

[0026] The substrate 102 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 102 is a thin substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the substrate 102 includes silicon.

[0027] The stack structure 104 can include a plurality of alternating conductor layers 106 and dielectric layers 108. Each conductor layer 106 and the corresponding dielectric layer 108 (e.g., immediately above or below the conductor layer 106) can be referred to as a conductor / dielectric layer pair, which can extend from the core region to the staircase region. The intersection of the channel structure 117 and the conductor layer 106 can form a plurality of memory cells, e.g., an array of memory cells, in the 3D memory device 100. The number of conductor / dielectric layer pairs in the stack structure 104 (e.g., 32, 64, 96, or 128) determines the number of memory cells in the 3D memory device 100. The conductor layer 106 and the dielectric layer 108 can be alternating in the vertical direction (e.g., the z-direction). In other words, except for those at the top or bottom of the stack structure 104, each conductor layer 106 can be adjacent to two dielectric layers 108 on both sides, and each dielectric layer 108 can be adjacent to two conductor layers 106 on both sides. The conductor layers 106 can each have the same thickness or different thicknesses. Similarly, the dielectric layers 108 can each have the same thickness or different thicknesses. The conductor layer 106 can include a conductor material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer 108 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer 106 includes a metal layer such as W, and the dielectric layer 108 includes silicon oxide.

[0028] The channel structure 117 can form an array and can each extend vertically above the substrate 102. The channel structure 117 can include a semiconductor channel that extends vertically through an alternating conductor / dielectric layer pair. The channel structure 117 can include a channel-forming structure of a plurality of channel-forming layers, for example, channel holes filled with a dielectric material (e.g., as a memory film) and / or a semiconductor material (e.g., as a semiconductor layer). In some embodiments, the memory film is a composite layer including a tunneling layer, a memory layer (also known as a "charge trapping layer"), and a blocking layer. Optionally, the remaining space of the channel hole can be partially or completely filled with a dielectric core including a dielectric material such as silicon oxide. The channel structure 117 can have a cylindrical (e.g., columnar) shape through the stack structure 104, or can have a trapezoidal shape for each memory stack and a staggered portion at the interface between adjacent memory stacks (e.g., along the sidewalls of the channel structure 117). The channel structure 117 can also have any other suitable shape, which is not limited by the embodiments of the present disclosure. According to some embodiments, the dielectric core, semiconductor layer, tunneling layer, memory layer, and blocking layer are arranged radially in this order from the center towards the sidewalls. The semiconductor layer can include silicon such as amorphous silicon, polysilicon, and / or single-crystalline silicon. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof.

[0029] In some embodiments, the channel structure 117 further includes a conductive plug (e.g., a semiconductor plug) at a lower portion (e.g., a lower end, not shown) of the channel structure 117. As used herein, the “upper end” of a component (e.g., the channel structure 117) is the end farther in the vertical direction from the substrate 102 when the substrate 102 is disposed on the lowermost surface of the 3D memory device 100, and the “lower end” of a component (e.g., the channel structure 117) is the end closer in the vertical direction to the substrate 102. The conductive plug can include a semiconductor material such as silicon, which can grow epitaxially from the substrate 102 (e.g., using selective epitaxial growth) or be deposited in any suitable direction onto the substrate 102. In some embodiments, it is understood that the conductive plug includes single crystal silicon, the same material as the substrate 102. In other words, the conductive plug can include an epitaxial semiconductor layer grown from the substrate 102. The conductive plug can also include a material different from the substrate 102. In some embodiments, the conductive plug includes at least one of silicon, germanium, and silicon germanium. In some embodiments, a portion of the conductive plug is above the top surface of the substrate 102 and in contact with the semiconductor channel. The conductive plug can make a conductive connection to the semiconductor channel. In some embodiments, the top surface of the conductive plug is disposed between the top surface and the bottom surface of the bottom dielectric layer 108 (e.g., the dielectric layer at the bottom of the stack structure 104). In some embodiments, the bottom surface of the conductive plug is below the top surface of the substrate 102. In some embodiments, the bottom surface of the conductive plug is in contact with the top surface of the substrate 102.

[0030] In some embodiments, the channel structure 117 further includes a drain structure (e.g., a channel plug) at the top of the channel structure 117 (e.g., the upper end, not shown). The drain structure can contact the upper end of the semiconductor channel and make a conductive connection to the semiconductor channel. The drain structure can include a semiconductor material (e.g., polysilicon) or a conductive material (e.g., metal). In some embodiments, the drain structure includes an opening filled with Ti / TiN or Ta / TaN as an adhesion layer and tungsten as a conductor material. By covering the upper end of the semiconductor channel during the manufacture of the 3D memory device 100, the drain structure can function as an etching stop layer that prevents the etching of the dielectric filled in the semiconductor channel, such as silicon oxide and silicon nitride. In subsequent operations, a conductive structure such as a via and / or a contact pad can be formed on the drain structure.

[0031] In some embodiments, the source contact structure 124 extends horizontally (e.g., along the x-axis) and vertically (e.g., along the z-axis) in the stack structure 104 to contact the substrate 102. In some embodiments, the source contact structure 124 extends in the core region and the staircase region. The source contact structure 124 can include an insulating spacer and a source contact in the insulating spacer. In some embodiments, the source contact structure 124 includes a doped region formed in the substrate 102 that is in conductive contact with the source contact. In some embodiments, the insulating spacer includes a suitable dielectric material such as silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the source contact includes one or more suitable conductive materials such as tungsten, polysilicon, doped silicon, silicide, aluminum, copper, and cobalt. A source voltage can be applied to the memory cell through the doped region and the source contact.

[0032] In some embodiments, memory cells between a pair of source contact structures 124 form memory fingers in a memory block, and the memory cells are arranged in rows and columns. The number of rows between two source contact structures 124 can be an odd number, such as any suitable number like 9. The TSG cut structure 110 can be formed along the central row of the memory fingers, for example, row 5, to divide the memory cells in the memory fingers into two parts. The TSG cut structure 110 can be disposed at the top of the stack structure 104. Along the z-axis in the core region, the TSG cut structure 110 can extend from the top surface of the stack structure 104 to at least the third conductor layer 106. In some embodiments, the depth of the TSG cut structure 110 is at least four conductor / dielectric layer pairs in the core region. In some embodiments, the TSG cut structure 110 includes at least one of silicon oxide and silicon oxynitride.

[0033] The dummy channel structure 116 can be aligned with the TSG cut structure in the x-z plane. In various embodiments, the dummy channel structure 116 can be disposed immediately below the TSG cut structure 110, or can extend through / within the TSG cut structure 110. As an example, FIGS. 1A-1C illustrate the structure of a 3D memory device 100 having a dummy channel structure 116 extending in the TSG cut structure 110. In some embodiments, the dummy channel structure 116 can be similar to the channel structure 117 (e.g., extending from the top surface of the stack structure 104 to the substrate 102), except that it lacks an electrical connection to the bit line. In another example, FIGS. 2A and 2B illustrate the structure of a 3D memory device 200 having a dummy channel structure 216 disposed below the TSG cut structure 110. In some embodiments, the dummy channel structure 116 can have a lower portion of the channel structure 117 (e.g., extending from the bottom of the TSG cut structure 110 to the substrate 102) and no drain structure. In both embodiments, the dummy channel structure 116 is disconnected from the electrical connection to the bit line by the TSG cut structure 110 and does not function as the channel structure 117. In various embodiments, the dummy channel structure 116 can be formed in the 3D memory device 200, and the dummy channel structure 216 can be formed in the 3D memory device 100. Details of the structure and manufacturing method are described as follows.

[0034] As shown in FIGS. 1A and 1C, the staircase region of the 3D memory device 100 can include a staircase structure in which a plurality of staircases extend horizontally (e.g., along the x-axis). In the staircase region, the TSG cut structure 112 can extend horizontally (e.g., along the x-axis) and vertically in the staircase. Along the x-axis, the TSG cut structure 112 can extend through at least a portion of the staircase according to the design of the 3D memory device 100. Along the z-axis in the staircase structure, the TSG cut structure 112 can extend from the top surface of each staircase to at least the fourth conductor layer 106 below each top surface. That is, the depth of the TSG cut structure 112 is at least four conductor / dielectric layer pairs in the staircase structure. In some embodiments, an insulating structure 118 is formed and the TSG cut structure 112 is partially disposed in the insulating structure 118. The insulating structure 118 can include a suitable dielectric material such as silicon dioxide and / or silicon oxynitride. The depth of the TSG cut structure 112 can also be considered to be from the top surface of the insulating structure 118 to at least the fourth conductor layer 106. For ease of explanation, in the present disclosure, the depth of the TSG cut structure 112 in the staircase structure is defined to be greater than or equal to four conductor / dielectric layer pairs. In the figures of the present disclosure, the contour of the TSG cut structure 112 represents a plurality of staircases to show the depth of the TSG cut structure 112, but the actual shape of the TSG cut structure 112 can be arbitrary according to the manufacturing process. The specific shape and depth of the TSG cut structure 112 along the x-z plane should not be limited by the embodiments of the present disclosure.

[0035] In the staircase region, the 3D memory device 100 includes a plurality of support structures 114 and 126. The support structure 114 is aligned with the TSG cut structure 112 (e.g., along the x-axis) and can at least partially overlap with the TSG cut structure 112 along the x-y plane. In some embodiments, the support structure 114 extends in the TSG cut structure 112. The number of support structures 114 that are aligned and overlap with the TSG cut structure 112 should not be limited by the embodiments of the present disclosure. Unlike the support structure 114, the support structure 126 can be in any suitable location in the staircase structure and may not overlap with the TSG cut structure 112. The support structures 114 and 126 can extend from the top surface of the staircase (or, if any, the top surface of the insulating structure 118) to the bottom of the staircase structure (or in contact with the substrate 102). In the present disclosure, for ease of illustration, different structures (e.g., support structures 114 and 126, TSG cut structure 112, and insulating structure 118) can be depicted using different shades / patterns. In an actual product, these structures can include the same material and may not have distinct boundaries (or the boundaries may coincide). The shading and patterns of the structures thus do not indicate differences in the material of the structures or the actual shape of the structures.

[0036] As shown in FIG. 1C, along the x-y plane, the dimension of at least one support structure 114 along the x-axis can be made larger than the dimension along the y-axis. In some embodiments, the dimension of each support structure 114 along the x-axis is larger than the dimension along the y-axis. The cross-section of the support structure 114 along the x-y plane can include any suitable shape such as a rectangle, an ellipse, and / or any other arbitrary shape. In various embodiments, the cross-section of the support structure 114 can also have other shapes where the dimensions along the x-axis and y-axis are nominally the same. For example, the cross-section of the support structure 114 can include a circle, a square, and / or any other arbitrary shape. In some embodiments, along the y-axis, the dimension of the support structure 114 can be made larger than the dimension of the support structure 114. In some embodiments, along the x-y plane, the cross-sectional area of the support structure 114 is larger than that of the existing support structure. The cross-section of the support structure 114 can be trapezoidal (e.g., the dimension along the x-axis gradually decreases towards the substrate 102) and / or columnar.

[0037] In some embodiments, the support structure 126 has the same shape and dimensions as the support structure 114. In some embodiments, the support structure has different shapes and dimensions from the support structure 114 according to the design of the 3D memory device 100. For example, as shown in FIG. 1C, along the x-y plane, the cross-section of some support structures 126 can be circular, and the cross-section of some other support structures 126 can be elliptical. In some embodiments, the cross-section of the support structure 126 is larger than that of the existing support structure. For example, the dimensions of the support structure 126 along the x-axis and y-axis can each be made larger than those of the existing support structure. In some embodiments, the cross-section of the support structure 126 is nominally equal to that of the existing support structure. In some embodiments, the support structures 114 and 126, and the TSG cut structure 112 each include at least one of silicon oxide and silicon oxynitride.

[0038] Along the z-axis, the dimension of the support structure 114 can be greater than or equal to the depth of the TSG cut structure 112. As shown in FIG. 1A, along the z-axis, the support structure 114 can extend through the TSG cut structure 112, for example, until it reaches the substrate 102. As described above, the depth of the TSG cut structure 112 in the staircase structure can be greater than or equal to four conductor / dielectric layer pairs. That is, the bottom surface of the TSG cut structure 112 can be nominally equal to or lower than the bottom surface of the fourth conductor layer 106 of each staircase, for example, along the z-axis. In various embodiments, the depth of the TSG cut structure 112 can be varied. FIG. 1B shows a TSG cut structure 112 having a different depth from that shown in FIG. 1A. As shown in FIG. 1B, the TSG cut structure 112 can extend from the top surface of the staircase to the bottom of the staircase structure (e.g., in contact with the substrate 102). That is, the depth of the TSG cut structure 112 in the staircase structure can be equal to the distance between the top surface of the staircase and the bottom of the staircase structure (e.g., the top surface of the substrate 102).

[0039] In the staircase region, the 3D memory device 100 can include a plurality of contacts 130 in contact with the staircase. For ease of depiction, the boundaries of the staircase are not shown in the figures of the present disclosure. The contacts 130 extend in the insulating structure 118 and can be in electrical contact with and connected to the conductor layer 106. The contacts 130 can convey a word line signal to the conductor layer 106. In some embodiments, the contacts 130 include a suitable conductive material such as tungsten, cobalt, aluminum, copper, polysilicon, and / or silicide.

[0040] FIGS. 2A and 2B show another 3D memory device 200 according to an embodiment of the present disclosure. FIG. 2A shows a cross-sectional view of the 3D memory device 200 along the B-B' direction (e.g., along the x-z plane) as shown in FIG. 2B. FIG. 2B shows a top view of the 3D memory device 200 along the x-y plane.

[0041] Unlike the 3D memory device 100, the 3D memory device 200 can include a plurality of support structures 214 having a cross-sectional area smaller than that of the support structure 114 along the x-y plane. The support structures 214 can be in any suitable location in the staircase region. For example, the support structures 214 can extend within / through the TSG cut structure 112 and outside the TSG cut structure 112. In some embodiments, along the y-axis, the dimension of the support structure 214 is less than that of the TSG cut structure 112. The cross-section of the support structure 214 along the x-y plane can be any suitable shape, such as a square, a circle, and / or any other shape. The cross-section of the support structure 214 can be trapezoidal (e.g., the dimension along the x-axis gradually decreases towards the substrate 102) and / or columnar. In some embodiments, each of the support structures 214 includes at least one of silicon oxide and silicon oxynitride.

[0042] The 3D memory devices 100 and 200 can each be part of a monolithic 3D memory device. The term "monolithic" means that the components of the 3D memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate. In a monolithic 3D memory device, there are additional manufacturing limitations due to the convolution of peripheral device processing and memory array device processing. For example, the manufacture of a memory array device (e.g., a NAND channel structure) is restricted by the thermal history associated with the peripheral devices formed on or to be formed on the same substrate.

[0043] Alternatively, the 3D memory devices 100 and 200 can each be part of a non-monolithic 3D memory device, with components (e.g., peripheral devices and memory array devices) formed separately on different substrates and then joined, for example, in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate 102) remains as the substrate of the joined non-monolithic 3D memory device, and the peripheral devices (e.g., any suitable digital, analog, and / or mixed-signal peripheral circuitry used to facilitate the operation of the 3D memory devices 100 and 200, such as page buffers, decoders, and latches, not shown) are inverted for hybrid bonding and face downward toward the memory array device (e.g., a NAND memory string). In some embodiments, the memory array device substrate (e.g., substrate 102) is inverted for hybrid bonding and faces downward toward the peripheral devices (not shown), such that in the joined non-monolithic 3D memory device, the memory array device is above the peripheral devices. The memory array device substrate (e.g., substrate 102) can be a thin substrate (which is not the substrate of the joined non-monolithic 3D memory device), and the back-end-of-line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the back side of the thin memory array device substrate.

[0044] In the present disclosure, the manufacturing processes shown in FIGS. 4A-4D, FIGS. 5A-5D, and FIGS. 6A-6D are each based on the structure of the 3D memory device formed in FIG. 3. FIGS. 3 and 4A-4D show cross-sectional views of the 3D memory device 100 at various stages of the manufacturing process according to some embodiments. FIG. 7 shows a flowchart of a method 700 for forming the 3D memory device 100. For ease of illustration, the 3D memory device 100 has a dual deck structure. In various embodiments, the 3D memory device can also have more than two memory stacks along the vertical direction (e.g., the z direction). The manufacture of the structure in a 3D memory device with more than two memory decks can be similar to the manufacture of the 3D memory device 100 and will not be described herein. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed before, after, or between any of the illustrated operations. Further, some of the operations can be performed simultaneously or in an order different from that shown in FIGS. 3 and 4A-4D.

[0045] As shown in FIG. 7, at the start of the process, method 700 begins with operation 702, where a lower dielectric stack and a lower channel hole portion are formed on a substrate in a core region. FIG. 3 shows the corresponding structure.

[0046] As shown in FIG. 3, a lower dielectric stack 304-1 can be formed on a substrate 302, and a lower channel hole portion 311 (or a first channel hole portion) can be formed in a core region of the lower dielectric stack 304-1. The lower dielectric stack 304-1 can be formed on the substrate 302 by alternately depositing a plurality of first dielectric layers 305 and a plurality of second dielectric layers 308 on the substrate 302. The first dielectric layer 305 and the second dielectric layer 308 can have different etching selectivities during a subsequent gate replacement process. In some embodiments, the first dielectric layer 305 and the second dielectric layer 308 include different materials. In some embodiments, the first dielectric layer 305 functions as a sacrificial layer in a gate replacement process. In some embodiments, the first dielectric layer 305 includes silicon nitride and the second dielectric layer 308 includes silicon oxide. The deposition of the first dielectric layer 305 and the second dielectric layer 308 can each include one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0047] A plurality of lower channel hole portions 311 can be formed to extend in the core region of the lower dielectric stack 304-1. Each of the lower channel hole portions 311 can expose the substrate 302 at its respective bottom. The lower channel hole portions 311 can be formed by an appropriate patterning / etching process that removes portions of the lower dielectric stack 304-1 to expose the substrate 302. The etching process can include wet etching and / or dry etching. In some embodiments, a sacrificial material such as polysilicon is deposited to fill the lower channel hole portions 311 prior to the deposition of the second dielectric stack. The deposition of the sacrificial material can include any suitable deposition method such as CVD, PVD, and / or ALD. In some embodiments, an appropriate planarization process, such as recess etching and / or chemical mechanical planarization (CMP), is performed to remove any excess dielectric material and / or sacrificial material on the lower dielectric stack 304-1.

[0048] Returning to FIG. 7, after forming the lower dielectric stack and the lower channel hole portion, method 700 proceeds to operation 704 where an upper dielectric stack is formed over the lower dielectric stack to form a dielectric stack. FIG. 3 shows the corresponding structure.

[0049] As shown in FIG. 3, the upper dielectric stack 304-2 can be deposited over the lower dielectric stack 304-1. Similar to the lower dielectric stack 304-1, the upper dielectric stack 304-2 can also include alternating first dielectric layers 305 and second dielectric layers 308, which can be deposited by the same method used to form the lower dielectric stack 304-1. A detailed description of the deposition of the upper dielectric stack 304-2 will not be repeated here. The upper dielectric stack 304-2 and the lower dielectric stack 304-1 form the dielectric stack 304, where the lower dielectric stack 304-1 is the lower deck and the upper dielectric stack 304-2 is the upper deck.

[0050] Returning to FIG. 7, after forming the dielectric stack, method 700 proceeds to operation 706 where a TSG cut structure is formed in the core region of the dielectric stack. FIG. 4A shows the corresponding structure.

[0051] As shown in FIG. 4A, a TSG cut structure 410 can be formed in the core region of the dielectric stack 304. To form the TSG cut structure 410, a TSG cut opening can be formed on top of the dielectric stack 304 (e.g., on the upper dielectric stack 304-2). The TSG cut opening can be a trench of a desired depth extending in the x-z plane. The TSG cut opening can be formed at an appropriate location, e.g., at the center of the memory finger to be formed. In some embodiments, along the x-z plane, the TSG cut opening is aligned with the lower channel hole portion 311 at the center of the memory finger to be formed. In some embodiments, the depth of the TSG cut opening along the z-axis is greater than or equal to four first / second dielectric layer pairs. The TSG cut opening can be formed by an appropriate etching process, e.g., dry etching and / or wet etching, to remove a portion of the dielectric stack 304. An appropriate dielectric material, e.g., silicon oxide and / or silicon oxynitride, can be deposited by one or more of CVD, PVD, and / or ALD to fill the TSG cut opening. In some embodiments, an appropriate planarization process, e.g., recess etching and / or CMP, is performed to remove any excess dielectric material on the dielectric stack 304.

[0052] Returning to FIG. 7, after the formation of the TSG cut structure, method 700 proceeds to operation 708 where a plurality of channel holes and a plurality of channel structures are formed in the dielectric stack. FIGS. 4A and 4B show the corresponding structures.

[0053] As shown in FIG. 4A, a plurality of upper channel hole portions (or second channel hole portions) can be formed in the dielectric stack 304 (e.g., upper dielectric stack 304-2) so as to extend along the z-axis. Each upper channel hole portion is aligned with its respective lower channel hole portion 311 along the z-axis, and can fully or partially expose the lower channel hole portion 311 (e.g., and / or the sacrificial material in the lower channel hole portion 311). In some embodiments, the plurality of upper channel hole portions extend through the TSG cut structure 410. The upper channel hole portion and its respective lower channel hole portion 311 can form a channel hole 411. The upper channel hole portion can be formed by an appropriate patterning / etching process, such as dry etching and / or wet etching. In some embodiments, the sacrificial material in the lower channel hole portion 311 is removed by an appropriate etching process, such as wet etching and / or dry etching.

[0054] As shown in FIG. 4B, a plurality of channel structures (not shown) and a plurality of dummy channel structures 416 can be formed in each channel hole 411. A conductive plug (not shown) can be formed at the bottom of the channel hole 411. The conductive plug includes a semiconductor material and can be formed by an epitaxial growth process and / or a deposition process. In some embodiments, the conductive plug is formed by epitaxial growth (e.g., selective epitaxial growth) and is referred to as an epitaxial portion. In some embodiments, the conductive plug includes single crystal silicon and is formed by epitaxial growth from the substrate 302. In some embodiments, the conductive plug includes polysilicon formed by a deposition process. The formation of the epitaxially grown epitaxial portion can include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The formation of the deposited epitaxial portion can include, but is not limited to, CVD, PVD, and / or ALD.

[0055] A plurality of channel-forming materials can then be deposited on the conductive plug in the channel hole 411. In some embodiments, a memory film and a semiconductor layer are deposited in the channel hole 411. Specifically, the memory film can include a blocking layer, a memory layer, and a tunneling layer. Optionally, a dielectric core is deposited in the channel hole 411 to partially or completely fill the space. In some embodiments, the dielectric core, semiconductor layer, tunneling layer, memory layer, and blocking layer are arranged radially in this order from the center to the sidewall of the channel hole 411. In some embodiments, the semiconductor layer is in contact with the conductive plug, and a semiconductor channel is formed in the semiconductor layer. In some embodiments, the blocking layer, memory layer, tunneling layer, semiconductor layer, and dielectric core can be continuously deposited in this order using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0056] In some embodiments, the drain structure is formed on top of the channel hole 411. In some embodiments, portions of the memory film, semiconductor layer, and dielectric core on top of the channel hole are removed by CMP, grinding, wet etching, and / or dry etching to form a recess on top of the channel hole so that the top surface of the semiconductor channel can be positioned at a desired location in the channel hole 411. Then, a conductive material such as metal and / or silicon is deposited into the recess by one or more thin film deposition processes such as CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof to form the drain structure. Then, a channel structure can be formed outside the TSG cut structure 410, and a dummy channel structure 416 can be formed aligned with (or extending within) the TSG cut structure 410. Optionally, a planarization process, such as dry / wet etching and / or CMP, is performed to remove any excess material on top of the dielectric stack 304. In subsequent manufacturing operations, bitlines can be formed and electrically connected to the channel structure. In some embodiments, no bitlines are formed that are electrically connected to the dummy channel structure 416.

[0057] Returning to FIG. 7, after formation of the channel structure, method 700 proceeds to operation 710 where a staircase structure is formed in the staircase region of the dielectric stack. FIG. 4B shows the corresponding structure.

[0058] As shown in FIG. 4B, a staircase structure including a plurality of steps extending along the x-axis can be formed in the staircase region of the dielectric stack 304. The staircase structure can be formed by repeatedly etching a plurality of alternating first dielectric layers 305 and second dielectric layers 308 using an etching mask, for example, a patterned PR layer on the dielectric stack 304. Each first dielectric layer 305 and the underlying second dielectric layer 308 can be referred to as a dielectric pair. In some embodiments, one or more dielectric pairs can form one level / step. During the formation of the staircase structure, the PR layer is trimmed (e.g., etched gradually and inwardly from the boundaries of the stack structure, generally from all directions), and is used as an etching mask for etching the exposed portion of the dielectric stack 304. The amount of trimmed PR can be directly related to (e.g., decisive for) the dimensions of the steps. Trimming of the PR layer can be obtained using appropriate etching, for example, isotropic dry etching such as wet etching. One or more PR layers can be continuously formed and trimmed to form the staircase structure. After trimming of the PR layer, each dielectric pair can be etched using an appropriate etchant to remove a portion of both the first dielectric layer 305 and the underlying second dielectric layer 308. The etched first dielectric layer 305 and second dielectric layer 308 can form a step. The PR layer can then be removed. In some embodiments, an insulating structure 418 is deposited to surround the dielectric stack 304 such that the dielectric stack 304 is in the insulating structure 418. The insulating structure 418 can include any suitable insulating material such as silicon oxide and can be deposited by a suitable deposition process such as CVD, PVD, and / or ALD.

[0059] Returning to FIG. 7, after the formation of the staircase structure, method 700 proceeds to operation 712, where a second TSG cut structure and a plurality of support structures are formed in the staircase structure in the same operation. FIG. 4C shows the corresponding structure.

[0060] As shown in FIG. 4C, a second TSG cut structure 412 and a plurality of support structures 414 and 426 are formed in the stepped region of the dielectric stack 304 in the same operation. To form the second TSG cut structure 412 and the support structures 414 and 426, a second TSG cut opening and a plurality of support openings can be formed in the stepped region. In some embodiments, the second TSG cut opening and the support openings are formed in the stepped structure and the insulating structure 418 (if any) by the same patterning / etching process. In some embodiments, a photomask having a pattern for the second TSG cut opening and the support openings is used to pattern portions of the dielectric stack 304 and the insulating structure 418 (if any) in the stepped region. An appropriate etching process, such as dry etching and / or wet etching, is performed to remove portions of the dielectric stack 304 and the insulating structure 418 (if any) to simultaneously form the second TSG cut opening and the support openings. Along the z-axis, the second TSG cut opening can extend from the top surface of the dielectric stack 304 (or, if any, the insulating structure 418) to at least the fourth first dielectric layer 305 below the top surface of each step. In some embodiments, the second TSG cut opening extends from the top surface of the dielectric stack 304 (or, if any, the insulating structure 418) to the bottom of the stepped structure (or the substrate 302).

[0061] Along the z-axis, the support openings can extend from the top surface of the dielectric stack 304 (or, if any, the insulating structure 418) to the bottom of the stepped structure (or the substrate 302). In some embodiments, a first portion of the support opening extends into and aligns with the second TSG cut opening in the x-z plane, and a second portion of the support opening extends outside the second TSG cut opening. The first portion of the support opening can have dimensions and a shape corresponding to the support structure 114, and the second portion of the support opening can have dimensions and a shape corresponding to the support structure 126.

[0062] Execute a suitable deposition process, CVD, PVD, and / or ALD to deposit a dielectric material in the second TSG cut opening and the support opening, and simultaneously form the second TSG cut structure 412 and the support structures 414 and 426. In some embodiments, the dielectric material includes silicon oxide. Optionally, perform a planarization process, such as dry / wet etching and / or CMP, to remove any excess material on the top surface of the dielectric stack 304.

[0063] In various embodiments, the order and / or process of forming the TSG cut structure 410, the dummy channel structure 416, the second TSG cut structure 412, and the support structures 414 and 426 can be varied. For example, the TSG cut opening in the core region may not be filled with a dielectric material before the formation of the dummy channel structure 416. That is, before depositing the dielectric material that fills the TSG cut opening, the channel hole 411 can first be filled with a memory film, a semiconductor layer, and a dielectric core. Thus, the dummy channel structure 416 can extend only under the TSG cut structure 410 instead of extending through the TSG cut structure 410 as shown in FIGS. 4A - 4C. The specific order of forming the TSG cut structure 410 and the dummy channel structure 416 (and the channel structure) should not be limited by the embodiments of the present disclosure. In another example, the TSG cut opening, the second TSG cut opening, and the support opening can be filled with the same dielectric material by the same deposition process, and the TSG cut structure 410, the second TSG cut structure 412, and the support structures 414 and 426 can be formed simultaneously.

[0064] Returning to FIG. 7, after the formation of the second TSG cut structure and the support structure, method 700 proceeds to operation 714 where a memory stack, a source contact structure, and contacts are formed. FIG. 4D shows the corresponding structure.

[0065] As shown in FIG. 4D, a memory stack 404 having a plurality of conductor layers 406 and dielectric layers 308 alternatingly can be formed. The memory stack can also be referred to as a stack structure. A source contact structure (referring to source contact structure 124 back to FIG. 1C) and a plurality of contacts (referring to contacts 130 back to FIG. 1C) can also be formed. To form the memory stack 404, a plurality of slit openings extending along the x-axis can be formed in the dielectric stack 304 in the core region and the staircase region. Each of the slit openings can expose a plurality of first dielectric layers 305 at the sidewalls and the substrate 302 at the bottom. Each of the slit openings can be formed by an appropriate patterning / etching process such as dry etching and / or wet etching.

[0066] An isotropic etching process can then be performed to remove the first dielectric layer 305 through each slit opening. A plurality of lateral recesses can be formed in the dielectric stack 304. A conductor material can then be deposited to fill the lateral recesses and a plurality of conductor layers 406 can be formed. The conductor layers 406 and the dielectric layers 308 can be alternately arranged along the z-axis above the substrate 302 to form a plurality of conductor / dielectric layer pairs. In some embodiments, the conductor material is deposited by at least one of CVD, PVD, and ALD. The memory stack 404 is then formed.

[0067] In some embodiments, for example, a doping process such as ion implantation is used to form doped regions in the substrate 302 at the bottom of each slit opening. In some embodiments, an insulating material such as silicon oxide is deposited on the sidewalls of each slit opening to form insulating spacers. Optionally, an appropriate recess etching process, such as dry etching and / or wet etching, can be performed to remove any excess portions of the insulating material to expose the substrate 302. A conductive material can be deposited to fill each slit opening to form source contacts. In some embodiments, the source contacts include an appropriate conductive material such as tungsten, polysilicon, silicide, cobalt, aluminum, copper, etc. Each of the insulating spacers can be deposited by one or more of CVD, PVD, ALD, and each of the source contacts can be deposited by one or more of CVD, PVD, ALD, and electroplating. Optionally, a planarization process, such as CMP and / or recess etching, can be performed to remove any excess material on the memory stack 404.

[0068] FIGS. 3 and 5A-5D illustrate cross-sectional views of a 3D memory device 200 at various stages of a manufacturing process according to some embodiments. FIG. 8 illustrates a flowchart of a method 800 for forming a 3D memory device 200. For ease of illustration, a manufacturing process for a 3D memory device 200 having a dual deck structure is described, similar to the description of method 700. It is understood that the operations shown in method 800 are not exhaustive and that other operations can be performed before, after, or between any of the illustrated operations. Further, some of the operations can be performed simultaneously or in an order different from that shown in FIGS. 3, 4A, 4B, and 5A-5C. For ease of illustration, the description of operations that are similar or the same as any of operations 702-714 is not repeated here.

[0069] As shown in FIG. 8, operations 802-810 can be the same as or similar to operations 702-710. FIG. 3 shows the structure of the 3D memory device formed by operations 802 and 804. FIG. 5A shows the structure of the 3D memory device formed by operations 806-810. However, as an example, in FIGS. 5A-5D, the TSG cut structure 510 in the core region is formed after the formation of the dummy channel structure 516. As shown in FIG. 5A, the TSG cut opening 513 can first be formed in the core region. The upper channel hole portions can then be formed and brought into contact with the respective lower channel hole portions 311 to form a plurality of channel holes 515. In some embodiments, the dummy channel structure 516 is formed in the channel holes 515 below the TSG cut opening 513, and a channel structure (not shown) is formed in the channel holes 515 outside the TSG cut opening 513. Then, using the same or a similar deposition method for forming the dummy channel structure 416, a channel formation structure the same as or similar to that of the dummy channel structure 416 can be formed in each channel hole 515. A dielectric material can then be deposited into the TSG cut opening to form the TSG cut structure 510. Optionally, a recess etching process (e.g., wet etching and / or dry etching) can be performed to remove the channel formation material deposited in the TSG cut opening before depositing the dielectric material for forming the TSG cut structure 510. The materials and deposition methods for forming the dummy channel structure 516 and the TSG cut structure 510 can be the same as or similar to those for forming the dummy channel structure 416 and the TSG cut structure 410. Detailed descriptions will not be repeated here. In some embodiments, the channel structure (e.g., similar to the channel structure 117) is formed by the same operation for forming the dummy channel structure 516. In some embodiments, a staircase structure is formed in the staircase region of the 3D memory device (or the dielectric stack 304). The formation of the staircase structure can be the same as or similar to that described in operation 710, and detailed descriptions will not be repeated here.Optionally, the insulating structure 418 is formed on the dielectric stack 304 such that the dielectric stack 304 is in the insulating structure 418.

[0070] Returning to FIG. 8, after forming a staircase structure in the staircase region, method 800 proceeds to operation 812 where a second TSG cut structure is formed in the staircase region. FIGS. 5B and 5C show the corresponding structures.

[0071] As shown in FIG. 5B, a second TSG cut opening 511 can be formed in the staircase region of the 3D memory device (or dielectric stack 304). Along the z-axis, the second TSG cut opening 511 can extend from at least the top surface of the staircase (or, if present, the top surface of the insulating structure 418) to at least the bottom surface of the fourth first dielectric layer 305 of each staircase. In some embodiments, the depth of the second TSG cut opening 511 in the staircase structure is greater than four first / second dielectric layer pairs. In some embodiments, the depth of the second TSG cut opening 511 is greater than or equal to the distance between the top surface of each staircase (or the top surface of the insulating structure 418) and the bottom of the fourth first dielectric layer 305 of the staircase. An appropriate etching process, similar or the same as the etching process described in operation 712, can be performed to remove a portion of the dielectric stack 304 (or, if present, the insulating structure 418) to form the second TSG cut opening 511. As shown in FIG. 5C, after the second TSG cut opening 511 is formed, an appropriate dielectric material can be deposited to form the second TSG cut structure 512. The material and deposition method for forming the second TSG cut structure 512 can be the same or similar to those for forming the second TSG cut structure 412, and the detailed description will not be repeated here.

[0072] Returning to FIG. 8, after forming a second TSG cut structure in the staircase region, method 800 proceeds to operation 814 where a plurality of support structures are formed in the staircase region. FIG. 5C shows the corresponding structure.

[0073] As shown in FIG. 5C, a plurality of support structures 514 are formed in the stepped region and extend at least from the top surface of the steps to the bottom of the stepped structure (or the top surface of the substrate 302). To form the support structures 514, a plurality of support openings are first formed in the stepped region and can extend at least from the top surface of the steps to the bottom of the stepped structure (or the top surface of the substrate 302). In some embodiments, the support openings extend from the top surface of the insulating structure 418 to the substrate 302. The location and dimensions of the support openings can be referred to the description of the support structure 214, and the detailed description will not be repeated herein. For example, an appropriate etching process similar or the same as the etching process in operation 712 can be performed to remove portions of the insulating structure 418, the dielectric stack 304, and the second TSG cut structure 512 (if formed) to form the support openings. Along the z-axis, the support openings can extend from the top surface of the steps in the stepped region of the dielectric stack 304 (or the insulating structure 418 if any) to the bottom of the stepped structure (or the substrate 302). An appropriate dielectric material can be deposited to fill the support openings and form the support structures 514. The material and deposition method for forming the support structures 514 can be the same or similar to those for forming the support structures 414, and the detailed description will not be repeated here.

[0074] As shown in method 800, unlike method 700, the second TSG cut opening 511 (where the second TSG cut structure 512 is formed) and the support opening (where the support structure 514 is formed) are formed by different patterning / etching processes. That is, separate photomasks can be used to form the second TSG cut opening 511 and the support opening in the staircase region. In various embodiments, the order of forming the second TSG cut opening 511 and the support opening can be changed in different manufacturing processes. For example, in some embodiments, the support opening is formed before the second TSG cut opening 511. In some embodiments, in operations 812 and 814, instead of being filled with a dielectric material in separate operations, the second TSG cut opening 511 and the support opening are filled with the same dielectric material, such as silicon oxide, by the same deposition process, such as CVD, PVD, and / or ALD. The specific order of forming and filling the second TSG cut opening 511 and the support opening should not be limited by the embodiments of the present disclosure.

[0075] Returning to FIG. 8, after the formation of the second TSG cut structure and the support structure, method 800 proceeds to operation 816, where a memory stack, source contact structures, and contacts are formed. FIG. 5D shows the corresponding structure.

[0076] As shown in FIG. 5D, a memory stack 504 having a plurality of alternating conductor layers 406 and dielectric layers 308 can be formed. A plurality of source contact structures (similar or the same as 124) and a plurality of contacts (similar or the same as 130) can be formed in the 3D memory device. The manufacturing processes and materials for forming these structures can be the same as those described in operation 714, and the detailed description will not be repeated here.

[0077] Figures 3 and 6A-6D show cross-sectional views of the 3D memory device 200 at various stages of other manufacturing processes according to some embodiments. FIG. 9 shows a flowchart of a method 900 for forming the 3D memory device 200. For ease of illustration, a manufacturing process of the 3D memory device 200 having a dual deck structure will be described, similar to the description of methods 800 and 700. It is understood that the operations shown in method 900 are not exhaustive, and other operations can be performed before, after, or between any of the illustrated operations. Further, some of the operations can be performed simultaneously or in an order different from that shown in FIGS. 3 and 6A-6D. For ease of illustration, the description of operations that are the same or similar to any of operations 702-714 will not be repeated here. As shown in FIG. 9, operations 902 and 904 can be the same or similar to operations 702 and 704. FIG. 3 shows the structure of the 3D memory device formed by operation 904.

[0078] Returning to FIG. 9, after the formation of the dielectric stack, method 900 proceeds to operation 906, where channel holes are formed in the core region and a channel structure is formed in the channel holes. FIGS. 6A and 6B show the corresponding structures.

[0079] As shown in FIG. 6A, an upper channel hole portion is formed in the upper dielectric stack, aligned and in contact with each lower channel hole portion to form a channel hole 615. A channel structure (e.g., similar to 117) and a dummy channel structure (e.g., similar to 216) can subsequently be formed in the channel hole 615. The patterning / etching process for forming the channel hole 615 is the same or similar to the patterning / etching process for forming the channel hole 411, and the detailed description will not be repeated here. In some embodiments, alignment marks are used for the patterning / etching of the upper channel hole portions such that each upper channel hole portion is aligned (or at least partially overlaps) with its respective lower channel hole portion.

[0080] As shown in FIG. 6B, a channel structure 617 is formed in each channel hole 615. The material and method for forming the channel structure 617 are the same as or similar to those for forming the dummy channel structure 416, and detailed descriptions will not be repeated here.

[0081] Returning to FIG. 9, after the formation of the channel structure, method 900 proceeds to operation 908, where a staircase structure is formed in the staircase region of the dielectric stack. FIG. 6B shows the corresponding structure.

[0082] As shown in FIG. 6B, a staircase structure having a plurality of staircases extending along the x-axis is formed in the staircase region of the 3D memory device (or dielectric stack 304). The formation of the staircase structure can be the same as that described in operation 710, and detailed descriptions will not be repeated here. Optionally, an insulating structure 418 is formed on the staircase structure such that the dielectric stack 304 is in the insulating structure 418.

[0083] Returning to FIG. 9, after the formation of the staircase structure, method 900 proceeds to operation 910, where a TSG cut structure is formed in the core region and a second TSG cut structure is formed in the staircase region of the dielectric stack. FIG. 6C shows the corresponding structure.

[0084] As shown in FIG. 6C, a TSG cut structure 610 and a second TSG cut structure 612 are each formed in a core region and a staircase region by the same manufacturing operation. To form the TSG cut structure 610 and the second TSG cut structure 612, in some embodiments, a TSG cut opening (where the TSG cut structure 610 is formed) and a second TSG cut opening (where the second TSG cut structure 612 is formed) are each formed in the core region and the staircase region by the same patterning / etching process. In some embodiments, a single photomask is used to pattern the TSG cut opening and the second TSG cut opening simultaneously. In some embodiments, to form the TSG cut opening, an appropriate etching process is used to remove a portion of the dielectric stack 304 in the core region, including the upper portion of the channel structure 617 and a portion of the first / second dielectric layer pair. The dummy channel structure 616 can be formed after the formation of the TSG cut opening (e.g., formed by the channel structure 617 after the top is removed). The same etching process can be used to remove a portion of the dielectric stack 304 in the staircase region to form the second TSG cut opening. In some embodiments, the depth and dimensions of the TSG cut opening and the second TSG cut opening can refer to those described in FIGS. 5A - 5C, and the detailed description will not be repeated here. In some embodiments, the etching process used to form the TSG cut opening and the second TSG cut opening includes dry etching and / or wet etching. An appropriate deposition process is then performed to fill the TSG cut opening and the second TSG cut opening with an appropriate dielectric material to form the TSG cut structure 610 and the second TSG cut structure 612. The dielectric material and deposition method can refer to those described in operation 712, and the detailed description will not be repeated here.

[0085] Returning to FIG. 9, after the formation of the TSG cut structure and the second TSG cut structure, method 900 proceeds to operation 912, where a plurality of support structures are formed in the staircase region of the dielectric stack. FIG. 6D shows the corresponding structure.

[0086] As shown in FIG. 6D, a plurality of support structures 614 are formed in the stepped region of the 3D memory device (or dielectric stack 304) and extend along the z-axis in the stepped structure, the second TSG cut structure 612, and the insulating structure 418 (if formed). In some embodiments, a separate photomask (e.g., different from the photomask used to form the TSG cut opening and the second TSG cut opening) is used to pattern / etch the support opening in which the support structure 614 is formed. The formation of the support structure 614 is similar to that of the support structure 514, and the detailed description will not be repeated here.

[0087] Returning to FIG. 9, after the formation of the support structure, method 900 proceeds to operation 914, where a memory stack, source contact structures, and contacts are formed. FIG. 6D shows the corresponding structures.

[0088] As shown in FIG. 6D, a memory stack 604 having alternating plural conductor layers 406 and dielectric layers 308 can be formed. A plurality of source contact structures (similar or the same as 124) and a plurality of contacts (similar or the same as 130) can be formed in the 3D memory device. The manufacturing processes and materials for forming these structures can be the same as those in operation 714, and the detailed description will not be repeated here.

[0089] Embodiments of the present disclosure provide a 3D memory device. The 3D memory device includes a core region and a stepped region having a plurality of steps each having at least a conductor / dielectric pair extending laterally. The stepped region includes a DSG cut structure extending along the lateral and vertical directions and a plurality of support structures extending into the DSG structure along the vertical direction. At least one of the support structures has a lateral dimension that is larger than a second lateral dimension perpendicular to the lateral direction.

[0090] In some embodiments, along the second lateral direction, at least one dimension of the support structure is larger than the dimension of the DSG structure.

[0091] In some embodiments, along the horizontal plane, at least one of the support structures has one of an elliptical or rectangular shape.

[0092] In some embodiments, the plurality of support structures each include an ellipse and are evenly arranged along the lateral direction.

[0093] In some embodiments, the dimensions of the DSG structure are equal to at least four pairs of conductor / dielectric pairs along the vertical direction.

[0094] In some embodiments, along the vertical direction, the dimensions of the plurality of support structures are greater than or equal to the dimensions of the DSG structure.

[0095] In some embodiments, the plurality of support structures extend to the bottom of the stepped region.

[0096] In some embodiments, the DSG structure extends from the surfaces of the plurality of steps to the bottom of the stepped region.

[0097] In some embodiments, the DSG cut structure and the plurality of support structures include at least one of silicon oxide or silicon oxynitride.

[0098] In some embodiments, the 3D memory device further includes a second support structure outside the DSG structure. The dimension of the second support structure along the lateral direction is greater than the dimension along the second lateral direction.

[0099] In some embodiments, the second support structure and the plurality of support structures have the same shape, the same dimensions, and the same material.

[0100] Embodiments of the present disclosure provide a method for forming a 3D memory device. The method includes the following operations. First, a dielectric stack having a plurality of first / second dielectric layer pairs is formed on a substrate. A DSG cut opening is formed in a core region of the dielectric stack. A staircase structure having a plurality of steps is formed and extends laterally in a staircase region of the dielectric stack. In a process different from the DSG cut opening, a second DSG cut opening is formed in the staircase region and extends laterally. A DSG cut structure is formed in the DSG cut opening, and a second DSG cut structure is formed in the second DSG cut opening.

[0101] In some embodiments, the method further includes forming, in the same process of forming the second DSG cut opening, a plurality of support openings that extend along a vertical direction in the staircase region and at least partially overlap with the second DSG cut opening. In some embodiments, the method further includes forming a plurality of support structures in the plurality of support openings.

[0102] In some embodiments, the method further includes forming, in a different process of forming the second DSG cut opening, a plurality of support openings that extend along a vertical direction in the staircase region. In some embodiments, the method further includes forming a plurality of support structures in the plurality of support openings.

[0103] In some embodiments, forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures includes depositing a dielectric material in the DSG cut opening, the second DSG cut opening, and the plurality of support openings, respectively.

[0104] In some embodiments, the dielectric material is deposited in the same process of forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures.

[0105] In some embodiments, the DSG cut opening is formed before the formation of the staircase structure.

[0106] In some embodiments, forming the second DSG cut opening includes removing a portion of a dielectric stack including at least four first / second dielectric layer pairs.

[0107] In some embodiments, forming the second DSG cut opening includes removing a portion of the dielectric stack to expose the substrate.

[0108] In some embodiments, forming the plurality of support openings includes removing a plurality of portions of the dielectric stack to expose the substrate.

[0109] In some embodiments, forming the dielectric stack includes forming a first dielectric stack on the substrate and forming a second dielectric stack on the first dielectric stack.

[0110] In some embodiments, the method further includes forming a first channel hole portion in a core region in the first dielectric stack before forming the DSG cut opening and forming a second channel hole portion in the second dielectric stack after forming the DSG cut opening. The second channel hole portion contacts the first channel hole portion, and the first and second channel hole portions form a channel hole.

[0111] In some embodiments, the method further includes depositing a channel forming structure in the channel hole.

[0112] In some embodiments, the method further includes forming a slit structure in the dielectric stack, the slit structure extending along a lateral direction to expose the substrate. In some embodiments, the method further includes removing a first dielectric layer to form a plurality of lateral recesses and depositing a conductor material in the plurality of lateral recesses to form a plurality of conductor layers.

[0113] Embodiments of the present disclosure provide a method for forming a 3D memory device. The method includes the following operations. First, a dielectric stack having a plurality of first / second dielectric layer pairs is formed on a substrate. A channel structure is formed in a core region of the dielectric stack. A staircase structure is formed having a plurality of steps extending laterally in a staircase region of the dielectric stack. In the same process, a DSG cut opening is formed in the core region of the dielectric stack, and a second DSG cut opening is formed in the staircase region of the dielectric stack. A DSG cut structure is formed in the DSG cut opening, and a second DSG cut structure is formed in the second DSG cut opening.

[0114] In some embodiments, the method further includes forming a plurality of support openings extending vertically along the staircase region in a different process for forming the DSG cut opening and the second DSG cut opening. In some embodiments, the method further includes forming a plurality of support structures in the plurality of support openings.

[0115] In some embodiments, forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures includes depositing a dielectric material in the DSG cut opening, the second DSG cut opening, and the plurality of support openings, respectively.

[0116] In some embodiments, the dielectric material is deposited in the same process for forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures.

[0117] In some embodiments, the DSG cut opening and the second DSG cut opening are formed after the formation of the staircase structure.

[0118] In some embodiments, forming the second DSG cut opening includes removing a portion of a dielectric stack including at least four first / second dielectric layer pairs.

[0119] In some embodiments, forming a plurality of support openings includes removing a plurality of portions of the dielectric stack to expose the substrate.

[0120] In some embodiments, forming a DSG cut opening includes removing the top of the channel structure.

[0121] In some embodiments, forming a dielectric stack includes forming a first dielectric stack on a substrate and forming a second dielectric stack on the first dielectric stack.

[0122] In some embodiments, the method further includes forming a first channel hole portion in a core region in the first dielectric stack prior to forming the staircase structure. In some embodiments, the method further includes forming a second channel hole portion in the second dielectric stack in contact with the first channel hole portion, the first and second channel hole portions forming a channel hole. In some embodiments, the method further includes depositing a channel forming structure in the channel hole.

[0123] In some embodiments, the method further includes forming a slit structure in the dielectric stack that extends along a lateral direction to expose the substrate, removing a first dielectric layer to form a plurality of lateral recesses, and depositing a conductor material in the plurality of lateral recesses to form a plurality of conductor layers.

[0124] The foregoing description of specific embodiments will make the general nature of the disclosure apparent, such that others may, by applying knowledge within the scope of the art, readily modify and / or adapt such specific embodiments without undue experimentation and without departing from the general concept of the disclosure. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in the art in light of the teachings and guidance presented herein.

[0125] The embodiments of the present disclosure have been described above with the aid of functional components that illustrate the implementation of specified functions and their relationships. The boundaries of these functional components have been arbitrarily defined herein for the sake of convenience of description. Alternative boundaries can be defined as long as the specified functions and their relationships are properly executed.

[0126] The summary and abstract sections do not describe all of the disclosure as contemplated by the inventor, but can describe one or more exemplary embodiments and are thus not intended to limit the disclosure and the appended claims in any way.

[0127] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Description of Reference Numerals

[0128] 100 3D memory device 102 Substrate 104 Stack structure 106 Conductor layer 108 Dielectric layer 110 TSG cut structure 112 TSG cut structure 114 Support structure 116 dummy channel structure 117 channel structure 118 insulation structure 124 source contact structure 126 support structure 130 contact 200 3D memory device 214 support structure 216 dummy channel structure 302 substrate 304 dielectric stack 304-1 lower dielectric stack 304-2 upper dielectric stack 305 first dielectric layer 308 second dielectric layer 311 lower channel hole portion 404 memory stack 410 TSG cut structure 411 channel hole 412 second TSG cut structure 414 support structure 416 dummy channel structure 418 insulation structure 426 support structure 510 TSG cut structure 511 second TSG cut opening 512 second TSG cut structure 513 TSG cut opening 514 support structure 515 channel hole 516 dummy channel structure 604 memory stack 610 TSG cut structure 612 second TSG cut structure 614 support structure 615 channel hole 616 dummy channel structure 617 channel structure

Claims

1. A core area; a staircase region including a plurality of staircases each including at least a conductor / dielectric pair extending laterally therethrough, a drain select gate (DSG) cut structure extending along the lateral and vertical directions; a plurality of support structures extending within the DSG structure along the vertical direction, at least one of the support structures having a dimension along the lateral direction that is greater than a dimension along a second lateral direction perpendicular to the lateral direction; A staircase region including A three-dimensional (3D) memory device comprising:

2. 10. The 3D memory device of claim 1, wherein along the second lateral direction, the dimension of the at least one of the support structures is greater than a dimension of the DSG structure.

3. 3. The 3D memory device of claim 2, wherein along a lateral plane, said at least one of said support structures has one of an oval or a rectangle.

4. 4. The 3D memory device of claim 3, wherein each of the plurality of support structures comprises an oval shape and is evenly spaced along the lateral direction.

5. 5. The 3D memory device of claim 1, wherein the DSG structure has a dimension equal to at least four conductor / dielectric pairs along the vertical direction.

6. 6. The 3D memory device of claim 5, wherein along the vertical direction, a dimension of the plurality of support structures is equal to or greater than the dimension of the DSG structure.

7. The 3D memory device of claim 6 , wherein the plurality of support structures extend to a bottom of the staircase region.

8. 8. The 3D memory device of claim 1, wherein the DSG structure extends from a surface of the plurality of steps to a bottom of the step region.

9. 9. The 3D memory device of claim 1, wherein the DSG cut structure and the plurality of support structures comprise at least one of silicon oxide or silicon oxynitride.

10. 10. The 3D memory device of claim 1, further comprising a second support structure outside the DSG structure, the second support structure having a dimension along the lateral direction that is greater than a dimension along the second lateral direction.

11. 11. The 3D memory device of claim 10, wherein the second support structure and the plurality of support structures have the same shape, the same dimensions, and the same material.

12. forming a dielectric stack on a substrate, the dielectric stack including a plurality of first / second dielectric layer pairs; forming a drain select gate (DSG) cut opening in a core region of the dielectric stack; forming a staircase structure including a plurality of steps extending along a lateral direction in a staircase region of the dielectric stack; forming a second DSG cut opening in the staircase region, the second DSG cut opening extending along the lateral direction in a process different from that of the DSG cut opening; forming a DSG cut structure in the DSG cut opening and a second DSG cut structure in the second DSG cut opening; 16. A method for forming a three-dimensional (3D) memory device, comprising:

13. forming a plurality of support openings in the staircase region, the support openings extending along a vertical direction in the staircase region and at least partially overlapping the second DSG cut openings in the same process of forming the second DSG cut openings; forming a plurality of support structures in the plurality of support openings; The method of claim 12 further comprising:

14. forming a plurality of support openings extending along a vertical direction in the step region in a different process of forming the second DSG cut opening; forming a plurality of support structures in the plurality of support openings; The method of claim 12 further comprising:

15. 15. The method of claim 13 or 14, wherein forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures comprises depositing a dielectric material in the DSG cut opening, the second DSG cut opening, and the plurality of support openings, respectively.

16. 16. The method of claim 15, wherein the dielectric material is deposited in the same process that forms the DSG cut structure, the second DSG cut structure, and the plurality of support structures.

17. The method of claim 12 , wherein the DSG cut opening is formed prior to forming the stair structure.

18. 13. The method of claim 12, wherein forming the second DSG cut opening comprises removing a portion of the dielectric stack including at least four first / second dielectric layer pairs.

19. 20. The method of claim 18, wherein forming the second DSG cut opening comprises removing a portion of the dielectric stack to expose the substrate.

20. 15. The method of claim 13 or 14, wherein forming the plurality of support openings comprises removing portions of the dielectric stack to expose the substrate.

21. The step of forming the dielectric stack comprises: forming a first dielectric stack on the substrate; forming a second dielectric stack on the first dielectric stack; 21. The method of any one of claims 12 to 20, comprising:

22. forming a first channel hole portion in the core region in the first dielectric stack before forming the DSG cut opening; forming a second channel hole portion in the second dielectric stack after forming the DSG cut opening; Further comprising: the second channel hole portion contacts the first channel hole portion; the first and second channel hole portions form a channel hole; 22. The method of claim 21.

23. The method of claim 22, further comprising depositing a channel forming structure in the channel hole.

24. forming a slit structure in the dielectric stack, the slit structure extending along the lateral direction to expose the substrate; removing the first dielectric layer to form a plurality of lateral recesses; depositing a conductive material into the plurality of lateral recesses to form a plurality of conductive layers; 23. The method of any one of claims 12 to 22, further comprising:

25. forming a dielectric stack on a substrate, the dielectric stack including a plurality of first / second dielectric layer pairs; forming a channel structure in a core region of the dielectric stack; forming a staircase structure including a plurality of steps extending along a lateral direction in a staircase region of the dielectric stack; forming a drain select gate (DSG) cut opening in a core region of the dielectric stack and a second DSG cut opening in a staircase region of the dielectric stack in the same process; forming a DSG cut structure in the DSG cut opening and a second DSG cut structure in the second DSG cut opening; 16. A method for forming a three-dimensional (3D) memory device, comprising:

26. forming a plurality of support openings extending along a vertical direction in the staircase region in different processes for forming the DSG cut opening and the second DSG cut opening; forming a plurality of support structures in the plurality of support openings; 26. The method of claim 25, further comprising:

27. 27. The method of claim 26, wherein forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures comprises depositing a dielectric material in the DSG cut opening, the second DSG cut opening, and the plurality of support openings, respectively.

28. 30. The method of claim 27, wherein the dielectric material is deposited in the same process that forms the DSG cut structure, the second DSG cut structure, and the plurality of support structures.

29. 26. The method of claim 25, wherein the DSG cut opening and the second DSG cut opening are formed after forming the staircase structure.

30. 26. The method of claim 25, wherein forming the second DSG cut opening comprises removing a portion of the dielectric stack including at least four first / second dielectric layer pairs.

31. 27. The method of claim 26, wherein forming the plurality of support openings comprises removing portions of the dielectric stack to expose the substrate.

32. 26. The method of claim 25, wherein forming the DSG cut opening comprises removing a top of the channel structure.

33. The step of forming the dielectric stack comprises: forming a first dielectric stack on the substrate; forming a second dielectric stack on the first dielectric stack; 33. The method of any one of claims 25 to 32, comprising:

34. Before forming the staircase structure, forming a first channel hole portion in the core region of the first dielectric stack; forming a second channel hole portion in the second dielectric stack in contact with the first channel hole portion, the first and second channel hole portions forming a channel hole; depositing a channel forming structure in the channel hole; 34. The method of claim 33, further comprising:

35. forming a slit structure in the dielectric stack, the slit structure extending along the lateral direction to expose the substrate; removing the first dielectric layer to form a plurality of lateral recesses; depositing a conductive material into the plurality of lateral recesses to form a plurality of conductive layers; 35. The method of any one of claims 25 to 34, further comprising:

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