Semiconductor device

Abstract

To suppress deterioration in characteristics of transistors in a drive circuit.SOLUTION: A semiconductor device comprises a circuit 200, a transistor 101_1, and a transistor 101_2. The transistor 101_1 and the transistor 101_2 are on / off-controlled by selective input of a signal from the circuit 200 to gates thereof. The transistor 101_1 or the transistor 101_2 is turned on or off, and thereby, wiring 112 and wiring 111 become in a conduction state or a non-conduction state.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a driving method thereof, or a method of manufacturing them. In particular, it relates to a semiconductor device having a driving circuit formed on the same substrate as a pixel portion, a display device, a liquid crystal display device, a light-emitting device, or a driving method thereof. Or, it relates to an electronic device having the semiconductor device, the display device, the liquid crystal display device, or the light-emitting device.

Background Art

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, a technique of forming a driving circuit such as a gate driver on the same substrate as a pixel portion using a transistor composed of a non-single crystal semiconductor greatly contributes to cost reduction and reliability improvement, and thus is actively developed.

[0003] A transistor composed of a non-single crystal semiconductor causes deterioration such as a variation in threshold voltage or a decrease in mobility. As this transistor deteriorates, it becomes difficult for the driving circuit to operate, and there is a problem that an image cannot be displayed. Therefore, Patent Document 1, Patent Document 2, and Non-Patent Document 1 disclose a shift register capable of suppressing the deterioration of a transistor (hereinafter also referred to as a pull-down transistor) having a function of maintaining the output signal of a flip-flop at a low level or a function of lowering the output signal to a low level. In these documents, two pull-down transistors are used. These two pull-down transistors are ​​They are connected in between. Then, one pull-down transistor and the other pull-down transistor turn on alternately (also referred to as the on state). By doing so, the time for each pull-down transistor to turn on becomes shorter, so that deterioration of the characteristics of the pull-down transistor can be suppressed. And each pull-down transistor turns on alternately. By doing so, the time for each pull-down transistor to turn on becomes shorter, so that deterioration of the characteristics of the pull-down transistor can be suppressed. And each pull-down transistor turns on alternately. By doing so, the time for each pull-down transistor to turn on becomes shorter, so that deterioration of the characteristics of the pull-down transistor can be suppressed. And each pull-down transistor turns on alternately. By doing so, the time for each pull-down transistor to turn on becomes shorter, so that deterioration of the characteristics of the pull-down transistor can be suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the configuration of the conventional technology, the voltage of the gate of the transistor (hereinafter also referred to as the pull-up transistor) for controlling the output signal to the high level may be higher than the positive power supply voltage or the high-level voltage of the clock signal. For this reason, a large voltage may be applied to the pull-up transistor. Or, the gate of the pull-up transistor is connected In the configuration of the conventional technology, the voltage of the gate of the transistor (hereinafter also referred to as the pull-up transistor) for controlling the output signal to the high level may be higher than the positive power supply voltage or the high-level voltage of the clock signal. For this reason, a large voltage may be applied to the pull-up transistor. Or, the gate of the pull-up transistor is connected In the configuration of the conventional technology, the voltage of the gate of the transistor (hereinafter also referred to as the pull-up transistor) for controlling the output signal to the high level may be higher than the positive power supply voltage or the high-level voltage of the clock signal. For this reason, a large voltage may be applied to the pull-up transistor. Or, the gate of the pull-up transistor is connected In the configuration of the conventional technology, the voltage of the gate of the transistor (hereinafter also referred to as the pull-up transistor) for controlling the output signal to the high level may be higher than the positive power supply voltage or the high-level voltage of the clock signal. For this reason, a large voltage may be applied to the pull-up transistor. Or, the gate of the pull-up transistor is connected A large voltage may be applied to the transistor to be used. Or, even if the transistor deteriorates, the channel width of the transistor may increase so that the shift register operates. Or, when the channel width of the transistor increases, there is a case where it is likely to short between the gate of the transistor and the source or drain. Or, when the channel width of the transistor increases, the parasitic capacitance in each transistor constituting the shift register may increase.

[0007] One aspect of the present invention is to solve the problem of suppressing the characteristic deterioration of the transistor. Or, one aspect of the present invention is to solve the problem of reducing the channel width of the transistor. In particular, it is an object to suppress the characteristic deterioration of the pull-up transistor or to reduce the channel width. Or, one aspect of the present invention is to solve the problem of increasing the amplitude of the output signal. Or, one aspect of the present invention is to solve the problem of lengthening the on-time of the transistor included in the pixel. Or, one aspect of the present invention is to solve the problem of improving the insufficient writing to the pixel. Or, one aspect of the present invention is to solve the problem of shortening the fall time of the output signal. Or, one aspect of the present invention is to solve the problem of shortening the rise time of the output signal. Or, it is an object to prevent a video signal from being written from a pixel belonging to one row to a pixel belonging to another row. Or, it is an object to reduce the variation in the fall time of the output signal of the drive circuit. Or, it is an object to make the influence of the feed-through to each pixel constant. Or, it is an object to reduce crosstalk. Or, one aspect of the present invention is to solve the problem of reducing the layout area. Or, one aspect of the present invention is to solve the problem of narrowing the frame of the display device. ​​​​​​​​​​​​​​​​ Or, one aspect of the present invention aims to improve the definition of a display device. Or, one aspect of the present invention aims to increase the yield. Or, one aspect of the present invention aims to reduce the manufacturing cost Or, one aspect of the present invention aims to reduce the ringing of an output signal Or, one aspect of the present invention aims to reduce the delay of an output signal Or, one aspect of the present invention aims to reduce the power consumption. Or, one aspect of the present invention aims to reduce the current capacity of an external circuit. Or, one aspect of the present invention aims to reduce the size of an external circuit or the size of a display device having the external circuit It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention is not required to solve all of these problems.

Means for Solving the Problems

[0008] One aspect of the present invention includes a drive circuit that receives a first signal and outputs a second signal, and a pixel having a liquid crystal element wherein a voltage applied to the liquid crystal element is set according to the second signal. The drive circuit includes a first transistor and a second transistor having a gate, a source, and a drain, and the first signal is input to one of the gate, the source, and the drain A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the first transistor, and controls whether to set the voltage state of the second signal by turning on or off A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turns on or off to control whether to set the voltage state of the second signal. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turns on or off to control whether to set the voltage state of the second signal. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turns on or off to set the voltage state of the second signal. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turns on or off A fourth transistor that controls whether to set the voltage state of the second signal, and a gate having a source, a drain, and a gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and a fifth transistor that controls whether to turn off the fourth transistor by turning on or off having a source, a drain, and a gate, one of the source and the drain being electrically connected to the gate of the third transistor, and a sixth transistor that controls whether to turn off the third transistor by turning on or off A liquid crystal display device having A liquid crystal display device having A liquid crystal display device having According to an aspect of the present invention, a drive circuit that receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor and a second transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off

[0009] According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning on or off According to one aspect of the present invention, a drive circuit receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit includes a first transistor having a gate, a source, and a drain, and the first input signal is input to the gate and one of the source and the drain. A second transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off. A fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, and the other of the source and the drain being supplied with a first voltage, and turning a fifth transistor that controls whether to turn off a fourth transistor by doing so, having a gate, a source, and a drain, with a third input signal input to the gate, and one of the source and the drain being electrically connected to the gate of the third transistor, and a second voltage being applied to the other of the source and the drain, and a sixth transistor that controls whether to turn off the third transistor by turning on or off, is a liquid crystal display device having the same. by turning on or off, a liquid crystal display device having a sixth transistor that controls whether to turn off the third transistor by turning on or off.

[0010] One aspect of the present invention is a drive circuit that receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which the first input signal is input to the gate and one of the source and the drain; a third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off; a fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off; a fifth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, the third input signal being input to the other of the source and the drain, and controlling whether to turn off the fourth transistor by turning on or off. a drive circuit that outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain, and a first transistor to which the first input signal is input to the gate and one of the source and the drain, and a second transistor; a third transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by turning on or off; a fourth transistor having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off; a fifth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, the third input signal being input to the other of the source and the drain, and controlling whether to turn off the fourth transistor by turning on or off. a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by turning on or off; a fourth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, the third input signal being input to the other of the source and the drain, and controlling whether to turn off the fourth transistor by turning on or off; a fifth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, the third input signal being input to the other of the source and the drain, and controlling whether to turn off the fourth transistor by turning on or off. and a fifth transistor having a gate, a source, and a drain, the second input signal being input to the gate, one of the source and the drain being electrically connected to the gate of the fourth transistor, the third input signal being input to the other of the source and the drain, and controlling whether to turn off the fourth transistor by turning on or off. by turning on or off, controls whether to turn off the fourth transistor. and a sixth transistor having a gate, a source, and a drain, to which a third input signal is input to the gate, and one of the source and the drain is electrically connected to the gate of the third transistor, and a second input signal is input to the other of the source and the drain, and the sixth transistor turns on or off to control whether or not to turn off the third transistor. The liquid crystal display device has this. .

[0011] One aspect of the present invention includes a drive circuit that receives a first input signal, a second input signal, and a third input signal and outputs an output signal, and a liquid crystal element. A pixel having a voltage applied thereto according to the output signal is provided. The drive circuit includes a first transistor and a second transistor having a gate, a source, and a drain, and a first input signal is input to the gate and one of the source and the drain. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the first transistor, and turning on or off to control whether or not to set the voltage state of the output signal; A fourth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turning on or off to control whether or not to set the voltage state of the output signal; A fifth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor; and a gate, a source, and a drain and a pixel having a liquid crystal element, and a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain and a first input signal is input to the gate and one of the source and the drain of the first transistor and the second transistor. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the first transistor, and turning on or off to control whether or not to set the voltage state of the output signal. A fourth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turning on or off to control whether or not to set the voltage state of the output signal. A fifth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor. A first transistor and a second transistor having a gate, a source, and a drain, and a first input signal is input to the gate and one of the source and the drain. A third transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the first transistor, and turning on or off to control whether or not to set the voltage state of the output signal. A fourth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and turning on or off to control whether or not to set the voltage state of the output signal. A fifth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor. A gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor. Turning on or off to control whether or not to set the voltage state of the output signal. A fourth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor. A fifth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor. One of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain. Turning on or off to control whether or not to turn off the fourth transistor. A fifth transistor having a gate, a source, and a drain, the gate of which is electrically connected to the other of the source and the drain of the second transistor, and one of the source and the drain is electrically connected to the gate of the fourth transistor, and a third input signal is input to the other of the source and the drain, and turning on or off to control whether or not to turn off the fourth transistor. One terminal is electrically connected to the other of the source and drain of the first transistor, and the source and one of the drain is electrically connected to the gate of the third transistor, and the source and drain the other is input with a second input signal, and a sixth transistor that controls whether to turn off the third transistor by turning on or off. It is a liquid crystal display device having

[0012] In addition, in one aspect of the present invention, the channel width of the third transistor can also be configured to be equal to the channel width of the fourth transistor.

[0013] Also, in one aspect of the present invention, the channel width of the first transistor is smaller than the channel width of the third transistor, and the channel width of the second transistor can also be configured to be smaller than the channel width of the fourth transistor.

[0014] One aspect of the present invention includes a drive circuit that inputs a first signal and outputs a second signal, and a pixel having a liquid crystal element, and a voltage applied to the liquid crystal element is set according to the second signal. The drive circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which the first signal is input to the gate and one of the source and drain, and has a gate, a source, and a drain, and the gate is electrically connected to the other of the source and drain of the first transistor, and a third transistor that controls whether to set the voltage state of the second signal by turning on or off, and has a gate, a source, and a drain, and the gate is electrically connected to the other of the source and drain of the second transistor, and a fourth transistor that controls whether to set the voltage state of the second signal by turning on or off, and a positive ​​​​​​​​​having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the gate of a fourth transistor, and controlling whether to turn off the fourth transistor by becoming conductive or non-conductive, a first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the gate of a third transistor, and controlling whether to turn off the third transistor by becoming conductive or non-conductive, and a liquid crystal display device having a second diode. There is.

[0015] One aspect of the present invention is that a first input signal, a second input signal, and a third input signal are input, a drive circuit that outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain, a first transistor and a second transistor to which a first input signal is input to the gate and one of the source and the drain, having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the first transistor, and a third transistor that controls whether to set the voltage state of the output signal by turning on or off, having a gate, a source, and a drain, the gate being electrically connected to the other of the source and the drain of the second transistor, and a fourth transistor that controls whether to set the voltage state of the output signal by turning on or off, having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the gate of the fourth transistor, a first diode to which a second input signal is input to the other of the positive electrode and the negative electrode, and controlling whether to turn off the fourth transistor by becoming conductive or non-conductive, having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the gate of a third transistor, and controlling whether to turn off the third transistor by becoming conductive or non-conductive, a second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the gate of a third transistor, electrically connected to the gate of the transistor, and a third input signal is input to the other of the positive electrode and the negative electrode , and a second diode that controls whether to turn off the third transistor by becoming conductive or non-conductive . A liquid crystal display device having the above is provided.

[0016] One aspect of the present invention includes a drive circuit that receives a first signal and outputs a second signal, and a pixel having a liquid crystal element . The voltage applied to the liquid crystal element is set according to the second signal. The drive circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which the first signal is input to the gate and one of the source and the drain . The drive circuit also includes a first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the second signal by becoming conductive or non-conductive . A second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the second signal by becoming conductive or non-conductive . A third transistor having a gate, a source, and a drain, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the second diode, and controlling whether to turn off the second diode by turning on or off . A fourth transistor having a gate, a source, and a drain, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the first diode, and controlling whether to turn off the first diode by turning on or off . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided. . A liquid crystal display device having the above is provided.

[0017] One aspect of the present invention is a digital signal processing apparatus for detecting a first input signal, a second input signal, and a third input signal; A driving circuit that outputs an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in response to the output signal. a pixel to which a voltage is set, and the driving circuit has a gate, a source, and a drain. a first transistor having a gate and one of a source and a drain to which a first input signal is input; a first transistor and a second transistor, and a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being connected to the first transistor; The transistor is electrically connected to the other of the source and drain of the transistor and is in a conductive or non-conductive state. a first diode for controlling whether or not to set the voltage state of the output signal by switching the positive pole of the first diode; and a negative electrode, one of the positive electrode and the negative electrode being connected to the other of the source and drain of the second transistor. It is electrically connected to the output terminal and sets the voltage state of the output signal by being in a conductive or non-conductive state. a second diode that controls whether or not the gate is turned on; A second input signal is input to the input port, and one of the source and drain is connected to the positive electrode of the second diode. and a negative electrode, and a first voltage is applied to the other of the source and drain. , which controls whether the second diode is put into a non-conducting state by being turned on or off. a third transistor having a gate, a source, and a drain, the gate of which is connected to a third input signal; is input, and one of the source and drain is electrically connected to one of the positive and negative electrodes of the first diode. and a second voltage is applied to the other of the source and drain to turn the transistor on or off. a fourth transistor for controlling whether or not the first diode is put into a non-conducting state by the fourth transistor; 1. A liquid crystal display device having the above structure.

[0018] One aspect of the present invention is a digital signal processing apparatus for detecting a first input signal, a second input signal, and a third input signal; A driving circuit that outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The driving circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which a first input signal is input to one of the gate, the source, and the drain. The driving circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which a first input signal is input to one of the gate, the source, and the drain. A first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming conductive or non-conductive. A first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming conductive or non-conductive. A first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming conductive or non-conductive. A second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming conductive or non-conductive. A second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming conductive or non-conductive. A third transistor having a gate, a source, and a drain, a second input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third input signal being input to the other of the source and the drain, and controlling whether to turn off the second diode by turning on or off. A third transistor having a gate, a source, and a drain, a second input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third input signal being input to the other of the source and the drain, and controlling whether to turn off the second diode by turning on or off. A third transistor having a gate, a source, and a drain, a second input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third input signal being input to the other of the source and the drain, and controlling whether to turn off the second diode by turning on or off. A third transistor having a gate, a source, and a drain, a second input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third input signal being input to the other of the source and the drain, and controlling whether to turn off the second diode by turning on or off. A fourth transistor having a gate, a source, and a drain, a third input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the first diode, and a second input signal being input to the other of the source and the drain, and controlling whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, a third input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the first diode, and a second input signal being input to the other of the source and the drain, and controlling whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, a third input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the first diode, and a second input signal being input to the other of the source and the drain, and controlling whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, a third input signal being input to the gate, one of the source and the drain being electrically connected to one of the positive electrode and the negative electrode of the first diode, and a second input signal being input to the other of the source and the drain, and controlling whether to turn off the first diode by turning on or off. It is a liquid crystal display device having the above components.

[0019] One aspect of the present invention is that a first input signal, a second input signal, and a third input signal are input. A driving circuit that outputs an output signal, and a pixel having a liquid crystal element, wherein a voltage applied to the liquid crystal element is set according to the output signal. The driving circuit has a gate, a source, and a drain, and includes a first transistor and a second transistor to which a first input signal is input to one of the gate, the source, and the drain. The driving circuit has a gate, a source, and a drain, and includes a first transistor and a second transistor to which a first input signal is input to one of the gate, the source, and the drain. A first diode having a positive electrode and a negative electrode, wherein one of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and controls whether to set the voltage state of the output signal by becoming conductive or non-conductive. A first diode having a positive electrode and a negative electrode, wherein one of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and controls whether to set the voltage state of the output signal by becoming conductive or non-conductive. A first diode having a positive electrode and a negative electrode, wherein one of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and controls whether to set the voltage state of the output signal by becoming conductive or non-conductive. A second diode having a positive electrode and a negative electrode, wherein one of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and controls whether to set the voltage state of the output signal by becoming conductive or non-conductive. A second diode having a positive electrode and a negative electrode, wherein one of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and controls whether to set the voltage state of the output signal by becoming conductive or non-conductive. A third transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the second transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the second diode, and the other of the source and the drain receives a third input signal, and controls whether to turn off the second diode by turning on or off. A third transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the second transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the second diode, and the other of the source and the drain receives a third input signal, and controls whether to turn off the second diode by turning on or off. A third transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the second transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the second diode, and the other of the source and the drain receives a third input signal, and controls whether to turn off the second diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. A fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to one of the positive electrode and the negative electrode of the first diode, and the other of the source and the drain receives a second input signal, and controls whether to turn off the first diode by turning on or off. It is a liquid crystal display device having the above components.

[0020] One aspect of the present invention is a driving circuit that receives a first signal and outputs a second signal, and a liquid crystal element. It has a pixel in which a voltage applied to the liquid crystal element is set according to a second signal, and a drive circuit has a gate, a source, and a drain, and a first transistor and a second transistor to which a first signal is input to one of the gate, the source, and the drain, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and a first diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and a second diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and a second diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third diode that controls whether to make the second diode non-conductive by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the first diode, and a fourth diode that controls whether to make the first diode non-conductive by becoming conductive or non-conductive, and is a liquid crystal display device having One aspect of the present invention is that a first input signal, a second input signal, and a third input signal are input, and a drive circuit that outputs an output signal, and a pixel that has a liquid crystal element and in which a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain, and a first transistor to which a first input signal is input to one of the gate, the source, and the drain and a second transistor, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and a first diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and a second diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third diode that controls whether to make the second diode non-conductive by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the first diode, and a fourth diode that controls whether to make the first diode non-conductive by becoming conductive or non-conductive, and is a liquid crystal display device having One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third diode that controls whether to make the second diode non-conductive by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the first diode, and a fourth diode that controls whether to make the first diode non-conductive by becoming conductive or non-conductive, and is a liquid crystal display device having

[0021] A first input signal, a second input signal, and a third input signal are input, and a drive circuit that outputs an output signal, and a pixel that has a liquid crystal element and in which a voltage applied to the liquid crystal element is set according to the output signal. The drive circuit has a gate, a source, and a drain, and a first transistor to which a first input signal is input to one of the gate, the source, and the drain and a second transistor, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the first transistor, and a first diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and a positive electrode and a negative electrode. One of the positive electrode and the negative electrode is electrically connected to the other of the source and the drain of the second transistor, and a second diode that controls whether to set the voltage state of the second signal by becoming conductive or non-conductive, and is a liquid crystal display device having One of the positive electrode and the negative electrode is electrically connected to one of the positive electrode and the negative electrode of the second diode, and a third diode that controls whether to make the second diode non-conductive by becoming conductive or non-conductive, and a positive electrode and a negative A first transistor and a second transistor, a first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state, a second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state, a third diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to one of the positive electrode and the negative electrode of the second diode, a second input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the second diode non-conductive by becoming a conductive state or a non-conductive state, a fourth diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to one of the positive electrode and the negative electrode of the first diode, a third input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the first diode non-conductive by becoming a conductive state or a non-conductive state, and a liquid crystal display device having the above. One of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state. A first diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the first transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state. A second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state. One of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state. A second diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to the other of the source and the drain of the second transistor, and controlling whether to set the voltage state of the output signal by becoming a conductive state or a non-conductive state. One of the positive electrode and the negative electrode of the second diode, and a second input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the second diode non-conductive by becoming a conductive state or a non-conductive state. A third diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to one of the positive electrode and the negative electrode of the second diode, a second input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the second diode non-conductive by becoming a conductive state or a non-conductive state. A third diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to one of the positive electrode and the negative electrode of the second diode, a second input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the second diode non-conductive by becoming a conductive state or a non-conductive state. One of the positive electrode and the negative electrode of the first diode, and a third input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the first diode non-conductive by becoming a conductive state or a non-conductive state. A fourth diode having a positive electrode and a negative electrode, one of the positive electrode and the negative electrode being electrically connected to one of the positive electrode and the negative electrode of the first diode, a third input signal being input to the other of the positive electrode and the negative electrode, and controlling whether to make the first diode non-conductive by becoming a conductive state or a non-conductive state. A liquid crystal display device having the above. It is a liquid crystal display device.

[0022] One aspect of the present invention is an electronic device having at least the liquid crystal display device described above and an operation switch for controlling the operation of the liquid crystal display device. It is an electronic device having at least the liquid crystal display device described above and an operation switch for controlling the operation of the liquid crystal display device.

[0023] Note that various forms of switches can be used. As an example of the switch, an electrical switch or a mechanical switch can be used. That is, the switch only needs to be able to control current and is not limited to a specific one. As an example of the switch, an electrical switch or a mechanical switch can be used. That is, the switch only needs to be able to control current and is not limited to a specific one. The switch only needs to be able to control current and is not limited to a specific one.

[0024] As an example of a switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology like a digital micromirror device (DMD). The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation. In addition, as a switch, a CMOS-type switch may be used by using both an N-channel transistor and a P-channel transistor. Note that a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms or have various elements. As an example of a display element, a display device, a light-emitting element, or a light-emitting device, there are EL (Electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), digital micromirror devices (DMDs). As an example of a switch, there are transistors (such as bipolar transistors, MOS transistors, etc.), diodes (such as PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology like a digital micromirror device (DMD). The switch has electrodes that can be mechanically moved, and by moving the electrodes, conduction and non-conduction are controlled for operation. In addition, as a switch, a CMOS-type switch may be used by using both an N-channel transistor and a P-channel transistor. Note that a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms or have various elements. As an example of a display element, a display device, a light-emitting element, or a light-emitting device, there are EL (Electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements,

[0025] In addition, as a switch, a CMOS-type switch may be used by using both an N-channel transistor and a P-channel transistor. Note that a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms or have various elements. As an example of a display element, a display device, a light-emitting element, or a light-emitting device, there are EL (Electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements),

[0026] LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), digital micromirror devices (DMDs). As an example of a display element, a display device, a light-emitting element, or a light-emitting device, there are EL (Electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), digital micromirror devices (DMDs). As an example of a display element, a display device, a light-emitting element, or a light-emitting device, there are EL (Electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, , such as carbon nanotubes, which have a display medium whose contrast, brightness, reflectivity, transmittance, etc. change due to electromagnetic effects. As display devices, there are plasma displays, or piezoelectric ceramic displays, etc. As an example of a display device using an EL element , there is an EL display, etc. As an example of a display device using an electron-emitting element, there are a field emission display (FED) or a surface-conduction electron-emitter display (SED) :Surface-conduction Electron-emitter Display), etc. As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electronic ink or an electrophoretic element, there is electronic paper, etc.

[0027] As an example of a liquid crystal element, there is an element that controls the transmission or non- transmission of light by the optical modulation action of liquid crystal. The element can be structured by a pair of electrodes and a liquid crystal layer. Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Specifically, as an example of a liquid crystal element, there are nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer-dispersed liquid crystal (PDLC), ferroelectric liquid include TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, guest-host mode, Blue Phase mode, etc. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used. ed Nematic) mode, IPS (In-Plane-Switching) mode, d, FFS (Fringe Field Switching) mode, MVA (Mul ti-domain Vertical Alignment) mode, PVA (Pat terned Vertical Alignment) mode, ASV (Advanc ed Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Com pensated Birefringence) mode, ECB (Electrica lly Controlled Birefringence) mode, FLC (Fer roelectric Liquid Crystal) mode, AFLC (AntiF erroelectric Liquid Crystal) mode, PDLC (Pol ymer Dispersed Liquid Crystal) mode, guest-host mode, Blue Phase mode, etc. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used. not limited to these, and various liquid crystal elements and their driving methods can be used.

[0028] In addition, as the transistor, transistors with various structures can be used. Therefore, there is no limitation on the type of transistor used. As an example of the transistor, a thin film transistor (TFT) having an amorphous semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. ) etc. can be used. ) etc. can be used.

[0029] As an example of a transistor, ZnO, a-InGaZnO, SiGe, GaAs , IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, a transistor having a compound semiconductor or an oxide semiconductor such as AlZnSnO (AZTO) or a thin film transistor obtained by thinning these compound semiconductors or oxide semiconductors can be used .

[0030] As an example of a transistor, a transistor formed using an inkjet method or a printing method can be used .

[0031] As an example of a transistor, a transistor having an organic semiconductor or a carbon nanotube can be used .

[0032] In addition, as the transistor, transistors with various structures can be used For example, as the transistor, a MOS transistor, a junction transistor, a bipolar transistor, etc. can be used

[0033] As an example of a transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used .

[0034] As an example of a transistor, a transistor having a structure in which gate electrodes are arranged above and below the channel can be applied .

[0035] As an example of a transistor, a structure in which a gate electrode is arranged above the channel region, a structure in which a gate electrode is arranged below the channel region, a normal stagger structure, an inverse stagger structure can be used , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a transistor such as a structure in which the channel regions are connected in series can be used.

[0036] Note that, as an example of the transistor, a transistor having a structure in which a source electrode and a drain electrode overlap with a channel region (or a part thereof) can be used.

[0037] Note that, as an example of the transistor, a structure provided with an LDD region can be applied.

[0038] Note that transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. Examples of the substrate include a semiconductor substrate, a single crystal substrate (e.g., a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate , a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate , a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material , or a base film. Examples of the glass substrate include barium borosilicate glass, aluminosilicate glass, or soda lime glass. Examples of the flexible substrate include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), plastics typified by polyethersulfone (PES), or synthetic resins having flexibility such as acryl. Examples of the laminated film include polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, or a laminated film. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, or there is paper or the like. In particular, by manufacturing transistors using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, variations in characteristics, size, shape, etc. are small, and a transistor with high current capacity and small size can be manufactured. When a circuit is configured with such transistors, low power consumption or high integration of the circuit can be achieved. Moreover, transistors may be formed using a certain substrate and then transferred to another substrate and arranged on the other substrate. Examples of the substrate to which the transistors are transferred include, in addition to the substrates on which the above-described transistors can be formed, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are difficult to break, impart heat resistance, reduce weight, or reduce thickness. In addition, it is possible to form all of the circuits necessary to realize a predetermined function on the same substrate (for example, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). In this way, cost reduction by reducing the number of parts or improvement in reliability by reducing the number of connection points with circuit components can be achieved.

[0039] Note that it is also possible not to form all of the circuits necessary to realize a predetermined function on the same substrate. For example, there is paper, cellophane, stone, wood, cloth (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), leather, or rubber. By using these substrates, transistors with good characteristics, transistors with low power consumption, manufacture of durable devices, heat resistance, weight reduction, or thinning can be achieved. In addition, all of the circuits necessary to achieve a predetermined function can be formed on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). In this way, cost reduction by reducing the number of components or reliability improvement by reducing the number of connection points with circuit components can be achieved.

[0040] Note that all of the circuits necessary to implement a given function can be formed on the same substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). This can reduce costs by reducing the number of components or improve reliability by reducing the number of connection points with circuit components.

[0041] Note that it is also possible not to form all of the circuits necessary to achieve a predetermined function on the same substrate. ​​It is possible. That is, a part of the circuit necessary to realize a predetermined function is formed on a certain substrate. And another part of the circuit necessary to realize a predetermined function can be formed on another substrate. For example, a part of the circuit necessary to realize a predetermined function can be formed on a glass substrate, and another part of the circuit necessary to realize a predetermined function can be formed on a single crystal substrate (or SOI substrate). And a single crystal substrate (also referred to as an IC chip) on which another part of the circuit necessary to realize a predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass) to arrange the IC chip on the glass substrate. Or, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board, etc. In this way, since a part of the circuit is formed on the same substrate as the pixel portion, cost reduction due to reduction in the number of components or reliability improvement due to reduction in the number of connection points with circuit components can be achieved. In particular, circuits in parts with a large driving voltage or circuits in parts with a high driving frequency often consume a large amount of power. Therefore, such a circuit is formed on a substrate different from the pixel portion (for example, a single crystal substrate) to constitute an IC chip. By using this IC chip, an increase in power consumption can be prevented.

[0042] Note that as a transistor, an element having at least three terminals including a gate, a drain, and a source can also be used. The element has a channel between the drain region and the source region. ​​​​​​​​​It has a near region and can conduct current through a drain region, a channel region, and a source region. Here, since the source and the drain can change depending on the structure or operation conditions of the transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the region that functions as the source and the region that functions as the drain may not be called the source or the drain. In that case, as an example, one of the source and the drain may be denoted as the first terminal, the first electrode, or the first region, and the other of the source and the drain may be denoted as the second terminal, the second electrode, or the second region. Also, the gate may be denoted as the third terminal or the third electrode.

[0043] Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, as an example, one of the emitter and the collector may be denoted as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector may be denoted as the second terminal, the second electrode, or the second region. When a bipolar transistor is used as the transistor, the term "gate" can be rephrased as "base".

[0044] Note that when it is explicitly described that A and B are connected, it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and is not limited to the connection relationship shown in the figure or the text. ​​​​It shall include those other than the relationship.

[0045] As an example of the case where A and B are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, etc.) that enables the electrical connection between A and B can be connected between A and B by one or more. and so on) can be connected between A and B by one or more.

[0046] As an example of the case where A and B are functionally connected, a circuit (for example, a logic circuit (such as an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (such as a DA conversion circuit, an AD conversion circuit, a gamma correction circuit, etc.), a voltage level conversion circuit (a power supply circuit (such as a boost circuit, a buck circuit, etc.), a level shifter circuit that changes the voltage level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, such as an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) that enables the functional connection between A and B can be connected between A and B by one or more. and so on) can be connected between A and B by one or more. In addition, as an example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, it shall be considered that A and B are functionally connected. and so on) can be connected between A and B by one or more. In addition, as an example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, it shall be considered that A and B are functionally connected. and so on) can be connected between A and B by one or more. In addition, as an example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, it shall be considered that A and B are functionally connected. and so on) can be connected between A and B by one or more. In addition, as an example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, it shall be considered that A and B are functionally connected. and so on) can be connected between A and B by one or more. In addition, as an example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, it shall be considered that A and B are functionally connected. and so on) can be connected between A and B by one or more. Note that, as an example, even if there is another circuit between A and B, when the signal output from A is transmitted to B, A and B shall be considered to be functionally connected.

[0047] In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, the case where they are connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, the case where they are functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, the case where they are connected without another element or another circuit sandwiched between A and B). and so on) can be connected between A and B by one or more. and so on) can be connected between A and B by one or more. and so on) can be connected between A and B by one or more. (that is, the case where they are connected without another element or another circuit sandwiched between A and B). ​​shall be considered not to be. That is, when it is explicitly described as being electrically connected, it shall be considered the same as when it is only explicitly described as being connected.

[0048] Note that when it is explicitly described that B is formed on A or B is formed above A, it is not limited to B being formed in direct contact with A. It shall include the case where they are not in direct contact, that is, the case where another object is interposed between A and B. Here, A and B shall be considered as objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0049] Therefore, for example, when it is explicitly described that layer B is formed on (or above) layer A, it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed in direct contact with layer A and layer B is formed in direct contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi-layer.

[0050] Furthermore, the same applies to the case where it is explicitly described that B is formed above A. It is not limited to B being in direct contact with A, and it shall include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed in direct contact with layer A and layer B is formed in direct contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi-layer. ​​​​​​​​​​​​​​

[0051] In addition, when it is explicitly described that B is formed on A, B is formed above A, or B is formed over A, it shall include the case where B is formed obliquely above. .

[0052] The same applies to the case where B is below A or B is beneath A.

[0053] For those explicitly described as singular, it is desirable to be singular. However, it is not limited thereto, and it is also possible to be plural. Similarly, for those explicitly described as plural, it is desirable to be plural. However, it is not limited thereto, and it is also possible to be singular.

[0054] In the figures, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0055] The figures schematically show ideal examples and are not limited to the shapes or values shown in the figures. For example, it can include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0056] Technical terms are often used for the purpose of describing specific embodiments or examples. However, one aspect of the present invention is not limited to be interpreted by technical terms. .

[0057] In addition, words that are not defined (including scientific and technical words such as technical terms or academic terms) shall be construed in accordance with the ordinary meaning in the relevant technical field. ​It can be used with a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. Dictionaries, etc. The terms defined by are preferably interpreted in a meaning that is not inconsistent with the background of the related art.

[0058] Note that terms such as first, second, third, etc. are used to describe various elements, members, regions, layers, zones separately from others. Therefore, terms such as first, second, third, etc. do not limit the number of elements, members, regions, layers, zones, etc. Furthermore, for example, "the first" can be replaced with "the second" or "the third", etc. Note that terms such as "above", "upward", "below", "downward", "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", or "in" indicating a spatial arrangement are often used to simply show the relationship between one element or feature and another element or feature by means of a figure. However, it is not limited to this, and the terms indicating these spatial arrangements

[0059] can include other directions in addition to the direction depicted in the figure. For example, when explicitly shown as B above A, it is not limited to B being above A. Since the device in the figure can be inverted or rotated 180°, it is possible to include B being below A. Thus, the term "above" can include the direction of "below" in addition to the direction of "above". However, it is not limited to this, and since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", "in", or "in" in addition to the directions of "above" and "below". That is, depending on the situation, appropriate Note that terms indicating a spatial arrangement such as "above", "upward", "below", "downward", "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", or "in" are often used to simply show the relationship between one element or feature and another element or feature by means of a figure. However, it is not limited to this, and the terms indicating these spatial arrangements can include other directions in addition to the direction depicted in the figure. For example, when explicitly shown as B above A, it is not limited to B being above A. Since the device in the figure can be inverted or rotated 180°, it is possible to include B being below A. Thus, the term "above" can include the direction of "below" in addition to the direction of "above". However, it is not limited to this, and since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", "in", or "in" in addition to the directions of "above" and "below". That is, depending on the situation, appropriate Since the device in the figure can be inverted or rotated 180°, it is possible to include B being below A. Thus, the term "above" can include the direction of "below" in addition to the direction of "above". However, it is not limited to this, and since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", "in", or "in" in addition to the directions of "above" and "below". That is, depending on the situation, appropriate Since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", "in", or "in" in addition to the directions of "above" and "below". That is, depending on the situation, appropriate Since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "sideways", "right", "left", "diagonal", "back", "front", "inside", "outside", "in", or "in" in addition to the directions of "above" and "below". That is, depending on the situation, appropriate It can be interpreted as

[0060] One aspect of the present invention has a function of inputting a first signal and outputting a second signal, and includes a gate, a source, and a drain, and a first transistor and a second transistor to which the first signal is input to one of the gate, the source, and the drain, a third transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the first transistor, and controls whether to set the voltage state of the second signal by turning on or off, a fourth transistor having a gate, a source, and a drain, wherein the gate is electrically connected to the other of the source and the drain of the second transistor, and controls whether to set the voltage state of the second signal by turning on or off, a fifth transistor having a gate, a source, and a drain, wherein one of the source and the drain is electrically connected to the gate of the fourth transistor, and controls whether to turn off the fourth transistor by turning on or off, a sixth transistor having a gate, a source, and a drain, wherein one of the source and the drain is electrically connected to the gate of the third transistor, and controls whether to turn off the third transistor by turning on or off. It is as described above. [Advantages of the Invention] One aspect of the present invention can suppress deterioration of transistor characteristics. Or, one aspect of the present invention can reduce the channel width of a transistor. In particular, it is possible to suppress deterioration of the characteristics of a pull-up transistor or reduce the channel width. Or, the present invention

[0061] ​​​​​​​​​One aspect can increase the amplitude of a signal. Or, one aspect of the present invention is that a pixel can increase the on-time of a transistor it has. Or, one aspect of the present invention is that it can improve the insufficient writing to a pixel. Or, one aspect of the present invention is that it can shorten the fall time of a signal. Or, one aspect of the present invention is that it can shorten the rise time of a signal. Or, it can prevent a video signal belonging to a pixel in one row from being written to a pixel belonging to another row. Or, it can reduce the variation in the fall time of a signal. Or, it can make the influence of feed-through to a pixel constant. Or, it can reduce crosstalk. Or, one aspect of the present invention can reduce the layout area. Or, one aspect of the present invention can narrow the bezel of a display device. Or, one aspect of the present invention can make the display device have high definition. Or, one aspect of the present invention can increase the yield. Or, one aspect of the present invention can reduce the cost. Or, one aspect of the present invention can reduce the ringing of a signal. Or, one aspect of the present invention can reduce the delay of a signal. Or, one aspect of the present invention can reduce the power consumption. Or, one aspect of the present invention can reduce the current capacity of an external circuit. Or, one aspect of the present invention can reduce the size of an external circuit or the size of a display device having the external circuit.

[0062]

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Embodiments for Carrying Out the Invention

[0063] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the implementation It should not be construed as being limited to the description of the form. In the following-described configuration, for the same part or parts having similar functions, the same reference numerals are used to indicate them between different drawings, and detailed descriptions of the same part or parts having similar functions are omitted.

[0064] Note that the content described in one embodiment (even some of the content) can be applied to, combined with, or replaced with the other content described in that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content). That is, operations such as application, combination, or replacement can be performed.

[0065] Note that the content described in the embodiments refers to the content described using various drawings in each embodiment or the content described using the text described in the specification.

[0066] Note that the drawings (even a part) described in one embodiment can be combined with other parts of that drawing, other drawings (even a part) described in that embodiment, and / or drawings (even a part) described in one or more other embodiments to form even more drawings. That is, more drawings can be configured by combination.

[0067] Note that in the drawings or text described in one embodiment, it is possible to extract a part of it to form an aspect of the invention. Therefore, when a drawing or text describing a certain part is provided, the content obtained by extracting a part of the drawing or text is also disclosed as an aspect of the invention and can be configured to form an aspect of the invention. For example, active elements (such as transistors, diodes, etc.), wiring, passive elements ​(Capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, modules, devices, solids, liquids, gases, operating methods, manufacturing methods, etc. are described singly or in plural in the drawings (cross-sectional views, plan views, circuit diagrams, block diagrams, flowcharts, process diagrams, perspective views , elevation views, layout diagrams, timing charts, structure diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, state diagrams, waveform diagrams, photographs, chemical formulas, etc.) or in the text, and a part thereof can be extracted to form an aspect of the invention. As an example, from a circuit diagram composed of P (P is an integer) circuit elements (transistors, capacitive elements, etc.), M (M is an integer and M < P) circuit elements (transistors, capacitive elements, etc.) are extracted to form an aspect of the invention. Another example is that from a cross-sectional view composed of P layers, M layers can be extracted to form an aspect of the invention. Another example is that from a flowchart composed of P elements, M elements can be extracted to form an aspect of the invention. (Embodiment 1)

[0068] An example of this embodiment is a first transistor in which a first terminal is electrically connected to a first wiring and a second terminal is electrically connected to a second wiring, and a second transistor in which a first terminal is electrically connected to the first wiring and a second terminal is electrically connected to the second wiring, and a first circuit electrically connected to the gate of the first transistor and electrically connected to the gate of the second transistor. The first circuit causes a first signal to be in a second voltage state and a second signal to be in a first voltage state, and then the gate of the first transistor A function to increase the voltage, and when the first signal becomes the second voltage state and the third signal becomes the first voltage state, a function to increase the voltage of the gate of the second transistor. It has.

[0069] An example of the semiconductor device of this embodiment will be described. The semiconductor device of this embodiment is an example and can be used in various drive circuits such as a shift register, a gate driver, or a source driver. Note that the semiconductor device of this embodiment can be referred to as a drive circuit or a circuit. It is possible.

[0070] First, the circuit configuration of the semiconductor device of this embodiment will be described with reference to FIG. 1(A). The semiconductor device in FIG. 1(A) has a circuit 100 and a circuit 200. The circuit 100 has a plurality of transistors such as transistors 101_1 to 101_2. Note that the transistors 101_1 to 101_2 are assumed to be N-channel type. An N-channel type transistor turns on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth

[0071] ). However, it is not limited to this, and the transistor 10 1_1 and / or the transistor 101_2 can be P-channel type. A P-channel type transistor turns on when the potential difference (Vgs) between the gate and the source is lower than the threshold voltage ( Vth). ). Next, the connection relationship of the semiconductor device in FIG. 1(A) will be described. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 1 ).

[0072] Next, the connection relationship of the semiconductor device in FIG. 1(A) will be described. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 1 The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 1 It is connected to 11. The first terminal of the transistor 101_2 is connected to the wiring 112, and the second terminal of the transistor 101_2 is connected to the wiring 111. The circuit 200 is connected to the wiring 1 13, the wiring 114, the wiring 115, the wiring 116_1 to 116_2, the wiring 117, the wiring 118 , the gate of the transistor 101_1, the gate of the transistor 101_2, and the wiring 111 and is connected thereto. However, it is not limited thereto. For example, the circuit 200 can be connected to various other wirings or various nodes according to its configuration. Or, the circuit 2 00 does not have to be connected to all of the above-described wirings, and it is possible that it is not connected to any of the above-described wirings.

[0073] Note that the connection point between the gate of the transistor 101_1 and the circuit 200 is indicated as the node n1, and the connection point between the gate of the transistor 101_2 and the circuit 200 is indicated as the node n2.

[0074] Note that the wiring 111 is often extended and arranged in the pixel portion. Or, the wiring 111 is often connected to the gate of a transistor (for example, a selection transistor or a switching transistor ) included in the pixel. However, it is not limited thereto. For example, assume that a plurality of semiconductor devices are connected in series. In this case, the wiring 111 can be connected to the wiring 115 of another stage (for example, the next stage) of the semiconductor device. As another example, the wiring 111 can be connected to the wiring 117 of another stage (for example, the previous stage) of the semiconductor device.

[0075] Next, signals, voltages, etc. input to or output from each wiring will be described.

[0076] ​As an example, a signal OUT is output from the wiring 111. The signal OUT can be, for example, a signal having a first voltage state and a second voltage state. For example, the signal OUT is often a digital signal having a high level and a low level, and can function as an output signal of a semiconductor device. Therefore, the wiring 111 can function as a signal line or an output signal line. In particular, when the wiring 111 extends to the pixel portion, the signal OUT can function as a gate signal, a scanning signal, or a selection signal. Therefore, the wiring 111 can function as a gate signal line (hereinafter also referred to as a gate line) or a scanning line. For example, in the case of a liquid crystal display device, the wiring 111 can be connected to a pixel having a liquid crystal element, and the voltage applied to the liquid crystal element can be set according to the voltage of the wiring 111. However, it is not limited to this. For example, assume that a plurality of semiconductor devices are connected in series. In this case, when the wiring 111 is connected to the wiring 115 of a semiconductor device in another stage (for example, the next stage), the signal OUT can function as a transfer signal or a start signal. As another example, when the wiring 111 is connected to the wiring 117 of a semiconductor device in another stage (for example, the previous stage), the signal OUT can function as a reset signal. For example, it can be a signal having a first voltage state and a second voltage state. For example, the signal O UT is often a digital signal having a high level and a low level, and a semiconductor device can function as an output signal. Therefore, the wiring 111 can function as a signal line or as an output signal line. In particular, when the wiring 111 extends to the pixel portion and is arranged, the signal OUT can function as a gate signal, a scanning signal, or a selection signal. Therefore, the wiring 111 can function as a gate signal line (hereinafter also referred to as a gate line) or a scanning line. For example, in the case of a liquid crystal display device the wiring 111 is connected to a pixel having a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the voltage of the wiring 111. However, it is not limited to this. For example if a plurality of semiconductor devices are connected in series. In this case, when the wiring 111 is connected to the wiring 115 of a semiconductor device in another stage ( for example, the next stage), the signal OUT can function as a transfer signal or a start signal. As another example, when the wiring 11 1 is connected to the wiring 117 of a semiconductor device in another stage (for example, the previous stage), the signal OUT can function as a reset signal.

[0077] As an example, a signal CK1 is input to the wiring 112. The signal CK1 can be, for example, a signal having a first voltage state and a second voltage state. For example, the signal CK 1 can often be a digital signal that repeats between a high level and a low level and has two states of a high level and a low level. , and can function as a clock signal. Therefore, wiring 112 can function as a signal line , a clock line, a clock signal line, or a clock supply line. However, it is not limited to this. For example, either voltage V1 or voltage V2 can be supplied to wiring 112. Therefore, wiring 112 can function as a power supply line . . For example, either voltage V1 or voltage V2 can be supplied to wiring 112. Therefore, wiring 112 can function as a power supply line .

[0078] As an example, let's assume that signal CK2 is input to wiring 113. Signal CK2 can be a signal having, for example , a first voltage state and a second voltage state. For example, signal CK 2 is often a digital signal that repeats between a high level and a low level, and can function as an inverted clock signal. Note that signal CK2 can be an inverted signal of signal CK1, or a signal whose phase is approximately shifted by 180° from signal CK1 . Therefore, wiring 113 can function as a signal line, an inverted clock line, an inverted clock signal line, or an inverted clock supply line. However, it is not limited to this. For example, either voltage V1 or voltage V2 can be supplied to wiring 113. Therefore, wiring 113 can function as a power supply line . . For example, either voltage V1 or voltage V2 can be supplied to wiring 113. Therefore, wiring 113 can function as a power supply line .

[0079] As an example, let's assume that voltage V2 is supplied to wiring 114. Voltage V2 often has a value approximately equal to a high-level signal and can function as a power supply voltage, a reference voltage, or a positive power supply voltage . Therefore, wiring 114 can function as a power supply line . However, it is not limited to this. For example, signal C can be input to wiring 114 . Signals such as K1 or signal CK2 can be input. Therefore, wiring 114 can have the function as a signal line.

[0080] As an example, let's assume that signal SP is input to wiring 115. Signal SP can be a signal having, for example, a first voltage state and a second voltage state. For example, signal SP is often a digital signal and can have the function as a start signal. Therefore, wiring 115 can have the function as a signal line. However, it is not limited to this. For example, assume that a plurality of semiconductor devices are connected in series. In this case, when wiring 115 is connected to wiring 111 of a semiconductor device in another stage (for example, the previous stage), signal SP can have the function as a transfer signal, a gate signal, or a scan signal. Therefore , wiring 115 can have the function as an output signal line, a gate signal line, or a scan line. is possible.

[0081] As an example, let's assume that signal SEL1 is input to wiring 116_1. Signal SEL1 can be a signal having, for example, a first voltage state and a second voltage state. For example signal SEL1 is often a digital signal that repeats two states of high level and low level every certain period (for example, every frame period) and can have the function as a control signal, a clock signal, or a clock control signal. Therefore, wiring 116_1 can have the function as a signal line, a control line, or a clock line. However, it is not limited to this. For example, signal SEL1 can repeat high level and low level every several frames, every time the power is turned on, or every time the RAM. is possible.

[0082] As an example, assume that a signal SEL2 is input to the wiring 116_2. The signal SEL2 can be, for example, a signal having a first voltage state and a second voltage state. For example the signal SEL2 is often a digital signal that repeats between a high level and a low level at each certain period (for example, each frame period). And the signal SEL2 is often an inverted signal of the signal SEL1, or a signal whose phase is shifted by 180° from the signal SEL1, and can function as a control signal, an inverted clock signal, or an inverted clock control signal. Therefore, it can function as a signal line, a control line, or an inverted clock line. For example, when the signal SEL1 is either a high level or a low level, the signal SE L2 can be the other of the high level and the low level. However, it is not limited to this. For example, the signal SEL2 can repeat between a high level and a low level every several frames, every time the power is turned on, or every time the RAM is accessed.

[0083] As an example, assume that a signal RE is input to the wiring 117. The signal RE can be, for example, a signal having a first voltage state and a second voltage state. For example, the signal RE is often a digital signal and can function as a reset signal. Therefore, the wiring 117 can function as a signal line. However, it is not limited to this. For example, assume that a plurality of semiconductor devices are connected in series. In this case, when the wiring 117 is connected to the wiring 111 of another stage (for example, the next stage) of the semiconductor device, the signal RE can function as a transfer signal, a gate signal, or a scan signal. Thus ​​​And the wiring 117 can function as an output signal line, a gate signal line, or a scanning line. It is possible.

[0084] For example, assume that a voltage V1 is supplied to the wiring 118. The voltage V1 often has a value approximately equal to that of a low-level signal, and can function as a power supply voltage, a reference voltage, a ground voltage, or a negative power supply voltage. Therefore, the wiring 118 can function as a power supply line or a ground. However, it is not limited to this. For example, it is possible to input signals such as signal CK1, signal CK2, signal SEL1, or signal SEL2 to the wiring 118. Therefore, the wiring 118 can function as a signal line. In this case, since it becomes possible to apply a reverse bias to the transistor, the deterioration of the transistor can be suppressed. Often, it is approximately equal to the value of a low-level signal, and can function as a power supply voltage, a reference voltage, a ground voltage, or a negative power supply voltage. Therefore, the wiring 118 can function as a power supply line or a ground. However, it is not limited to this. For example, it is possible to input signals such as signal CK1, signal CK2, signal SEL1, or signal SEL2 to the wiring 118. Therefore, the wiring 118 can function as a signal line. In this case, since it becomes possible to apply a reverse bias to the transistor, the deterioration of the transistor can be suppressed.

[0085] In addition, these wirings can have various other functions, and do not necessarily have all of the above functions.

[0086] Note that "generally" includes various errors such as errors due to noise, process variations, variations in the device fabrication process, and / or measurement errors.

[0087] Note that generally, voltage may refer to the potential difference between two points, and potential may refer to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, since the difference between the potential at a certain point and the reference potential (for example, the ground potential) is often shown as the voltage at that certain point, in this specification, although potential may refer to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point, in an electronic circuit, the difference between the potential at a certain point and the reference potential (for example, the ground potential) is often shown as the voltage at that certain point. Therefore, in this specification, the difference between the potential at a certain point and the reference potential (for example, the ground potential) is often shown as the voltage at that certain point. When indicating the voltage at a certain point, unless otherwise specified, it shall indicate the potential difference between the potential at a certain point and the reference potential. It shall indicate the potential difference between the potential at a certain point and the potential that serves as the reference.

[0088] As an example, let the voltage of the first state, that is, the low-level signal, be V1, and the voltage of the second state, that is, the high-level signal, be V2. And assume V2 > V1. Therefore, when referring to the voltage V1, the voltage V1 is approximately equal to the low level of the signal. On the other hand, when referring to the voltage V2, the voltage V2 is approximately equal to the high level of the signal. However, it is not limited to this. For example, the voltage of the low-level signal can be lower than V1 or higher than V1. Or, the voltage of the high-level signal can be lower than V2 or higher than V2. For example, depending on the circuit configuration, even when referring to the high-level signal or high-level voltage, the voltage may be lower than V2 or higher than V2. Or, depending on the circuit configuration, even when referring to the low-level signal or low-level voltage, the voltage may be lower than V1 or higher than V1. Moreover, the signal CK1 and / or the signal CK2 can be balanced or unbalanced (also referred to as non-balanced). Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced (also referred to as non-balanced). Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced (also referred to as non-balanced). Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced (also referred to as non-balanced). Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced (also referred to as non-balanced). Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases.

[0089] It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced. Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. Balance means that within one cycle, the period of being at the high level and the period of being at the low level are approximately equal. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. Unbalance means that the period of being at the high level and the period of being at the low level are different. Here, different means outside the range of approximately equal cases. It should be noted that different here means outside the range of approximately equal cases.

[0090] When signals CK1 and CK2 are unbalanced, signal CK2 may not be the inverted signal of signal CK1. In this case, the lengths of the periods during which signal CK1 is at a high level and the period during which signal CK2 is at a high level can be approximately equal. However, it is not limited to this. Next, the functions of each circuit or each transistor will be described. Circuit 100, as an example, has a function of controlling the conduction state between wiring 112 and wiring 111 according to the voltage of node n1 and / or the voltage of node n2. Or, circuit 100 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 111. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, circuit 100 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 111. Or, circuit 100 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 111. Or, circuit 100 has a function of controlling the timing of increasing the voltage of wiring 111. Or, circuit 100 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 111. Or, circuit 100 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 111. Or, circuit 100 has a function of controlling the timing of raising the voltage of node n1 and / or the voltage of node n2 by a bootstrap operation. As described above, circuit 100 is a control circuit, a buffer

[0091]

[0092] ​​​​​​​​​​​​​​​It is possible to have functions such as a circuit or a switch, etc. However, it is not limited to this. Note that circuit 100 does not necessarily have all of the above functions. Circuit 200, as an example, has a function of controlling the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 in response to an input signal or voltage (signal CK2, signal SP, signal RE,

[0093] the voltage of node n1, the voltage of node n2, and / or signal OUT, etc.). Or, circuit 200 has a function of controlling the timing of supplying a high-level signal or voltage V2 to node n1 and / or node n2. Or, circuit 200 has a function of controlling the timing of increasing the voltage of node n1 and / or the voltage of node n2. Or, circuit 200 has a function of controlling the timing of supplying a low-level signal or voltage V1 to node n1 and / or node n2. Or, circuit 200 has a function of controlling the timing of decreasing or maintaining the voltage of node n1 and / or the voltage of node n2. Or, circuit 200 has a function of controlling the timing of not supplying a signal or voltage, etc. to node n1 and / or node n2. Or, circuit 200 has a function of controlling the timing of floating node n1 and / or node n2. Or, circuit 200 has a function of controlling the timing of supplying a low-level signal or voltage V1 to wiring 111. Or, circuit 200 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 111. As described above, circuit 200 can have a function as a control circuit. However, it is not limited to this. Note that circuit 200 does not necessarily have all of the above functions. That is not limited to this. Note that the circuit 200 does not necessarily have all of the above functions. .

[0094] As an example, the transistor 101_1 has a function of controlling the conduction state between the wiring 112 and the wiring 111 according to the voltage of the node n1. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying the voltage of the wiring 112 to the wiring 111. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to the wiring 112, the transistor 101_1 has a function of controlling the timing of supplying the signal or voltage supplied to the wiring 112 to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying a high level signal (such as signal CK1) to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of increasing the voltage of the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying a low level signal (such as signal CK1) to the wiring 111. For example, the transistor 101_1 has a function of controlling the timing of supplying a low level signal (such as signal CK1) to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of decreasing or maintaining the voltage of the wiring 111. Alternatively, the transistor 101_1 has a function of performing a bootstrap operation. Alternatively, the transistor 101_1 has a function of increasing the voltage of the node n1 by a bootstrap operation. Alternatively, the transistor 101_1 has a function of controlling whether to set the voltage state of the signal OUT by turning on or off. As described above, the transistor 101_1 can have functions such as a buffer or a switch. However, it is not limited to this. Note that the transistor 101_1 can have functions such as a buffer or a switch. However, it is not limited to this. Note that the transistor 101_1 can have functions such as a buffer or a switch. However, it is not limited to this. Note that the transistor 101_1 does not need to have all of the above functions.

[0095] For example, the transistor 101_2 is connected to the wiring 112 in response to the voltage of the node n2. The transistor 101_2 has a function of controlling electrical continuity between the wiring 111 and the transistor 101_2. The timing of supplying the voltage of the wiring 112 to the wiring 111 is controlled. When a signal or voltage (e.g., voltage V2 or signal CK1) is supplied to 112, The transistor 101_2 transfers a signal or a voltage supplied to the wiring 112 to the wiring 111. The transistor 101_2 has a function of controlling the timing of supplying the high The function of controlling the timing of supplying a level signal (for example, signal CK1) to the wiring 111 Alternatively, the transistor 101_2 may be configured to increase the voltage of the wiring 111 at a timing Alternatively, the transistor 101_2 has a function of controlling a low-level signal (e.g., For example, the timing of supplying a signal CK1 to the wiring 111 is controlled. The transistor 101_2 determines the timing to decrease or maintain the voltage of the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the bootstrap operation. Alternatively, the transistor 101_2 has a function of boosting the voltage of the node n2. The transistor 101_2 has a function of increasing the potential by a strap operation. This function controls whether to set the voltage state of the signal OUT by turning it on or off. As described above, the transistor 101_2 functions as a buffer, a switch, or the like. However, the present invention is not limited to this. 101_2 does not need to have all of the above functions.

[0096] Next, an example of the operation of the semiconductor device in Fig. 1(A) will be described with reference to the timing chart in Fig. 2 The timing chart in Fig. 2 shows the signal SEL1, signal SEL2, signal CK 1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, and the voltage (Va2) of node n2, and signal OUT. Note that the operation of the semiconductor device in Fig. 1(A) is not limited to the timing chart in Fig. 2 and can be controlled by various timings .

[0097] Note that the timing chart in Fig. 2 has a plurality of periods (hereinafter also referred to as frame periods), and each period has a plurality of sub-periods (hereinafter also referred to as 1 gate selection periods). For example, the timing chart in Fig. 2 has a plurality of periods such as period T1 and period T2 Period T1 has a plurality of sub-periods such as period A1, period B1, period C1, period D1, and period E1, and period T2 has a plurality of sub-periods such as period A2, period B2, period C2, period D2, and period E2. However, it is not limited to this. For example the timing chart in Fig. 2 may have a period different from period T1 and period T2 or one of period T1 and period T2 may be omitted. Or, period T1 may have various periods in addition to periods A1 to E1, or any one of periods A1 to E 1 may be omitted. Or, period T2 may have various periods in addition to periods A2 to E2, or any one of periods A2 to E2 may be omitted .

[0098] ​​Incidentally, as an example, it is assumed that period T1 and period T2 are arranged alternately. However, it is not limited to this, and period T1 and period T2 can be arranged in various orders.

[0099] Incidentally, as an example, in period T1, period A1, period B1, and period C1 are arranged in order. Thereafter, until the end of period T1 (or until the start of period T2), period D1 and period E 1 are arranged alternately. However, it is not limited to this. For example, in the period from the start of period T1 to the start of period A1, period D1 and / or period E1 can be arranged.

[0100] Incidentally, as an example, in period T2, period A2, period B2, and period C2 are arranged in order. Thereafter, until the end of period T2 (or until the start of period T1), period D2 and period E 2 are arranged alternately. However, it is not limited to this. For example, in the period from the start of period T2 to the start of period A2, period D2 and / or period E2 can be arranged.

[0101] First, the operation of period T1 will be described. In period T1, signal SEL1 becomes high level, and signal SEL2 becomes low level.

[0102] In period A1, as shown in FIG. 3(A), signal SP becomes high level. Then, circuit 200 supplies a high-level signal or voltage V2 to node n1. Therefore, the voltage of node n 1 starts to rise. On the other hand, circuit 200 supplies a low-level signal or voltage V1 to node n2. Therefore, the voltage of node n2 decreases to approximately V1. ​​​Or, it is maintained at approximately V1. As a result, transistor 101_2 turns off. After that, the voltage of node n1 continues to rise, and eventually, the voltage of node n1 reaches V1 + Vth1 01_1 (Vth101_1: threshold voltage of transistor 101_1) + Vx. At this time, Vx is a value greater than 0. Then, transistor 101_1 turns on. Therefore, wiring 112 and wiring 111 become conductive through transistor 101_1. Thus, the low-level signal CK1 is supplied from wiring 112 to wiring 111 through transistor 101_1. As a result, signal OUT becomes low level. After that, the voltage of node n 1 further rises. Eventually, circuit 200 stops supplying a signal or voltage to node n1, so circuit 200 and node n1 become non-conductive. As a result, node n1 becomes floating, and the voltage of node n1 is maintained at the value of V1 + Vth101_1 + Vx. However, it is not limited to this. For example, during period A1, circuit 200 can continue to supply the voltage of V1 + V th101_1 + Vx to node n1. During period A1, circuit 200 can supply a low-level signal or voltage V1 to wiring 111, or it can also not supply a signal or voltage, etc. to wiring 111.

[0103]

[0104] Next, during period B1, as shown in Fig. 3(B), signal SP becomes low level. Then, circuit 200 remains without supplying a signal or voltage, etc. to node n1. Therefore, node n 1 remains floating, and the voltage of node n1 is V1 + Vth101_1. The value of +Vx remains the same. That is, since transistor 101_1 remains on, the wir ing 112 and the wiring 111 remain in a conductive state through the transistor 101_1. On the other hand the circuit 200 supplies a low-level signal or voltage V1 to the node n2. Therefore, the volt age of the node n2 generally remains at V1. As a result, the transistor 101_2 remains off . At this time, the signal CK1 rises from the low level to the high level. Then the high-level signal CK1 is supplied from the wiring 112 to the wiring 11 1 through the transistor 101_1, so the voltage of the wiring 111 starts to rise. Then, since the node n1 remains in a floating state , the voltage of the node n1 rises to the value of V2 + Vth101_1 + Vx due to the parasitic capacitance between the gate and the second terminal of the transistor 101_1. This is the so-called bootstrapping operation. In this way, it becomes possible for the voltage of the wiring 111 to rise to V2 . In this manner, the signal OUT becomes high level .

[0105] Note that in the period B1, the circuit 200 often does not supply a signal or voltage or the like to the wiring 111 . However, it is not limited to this, and the circuit 200 can supply a high-level signal or voltage V 2 or the like to the wiring 111

[0106] Next, in the period C1, as shown in FIG. 3(C), the signal RE becomes high level. Then the circuit 200 supplies a low-level signal or voltage V1 to the node n1, the node n2, and / or the wiring 111. Therefore, the voltage of the node n1, the voltage of the node n2, and / or the voltage of the wiring 111 generally becomes V1. As a result, the transistor 101_1, and Since transistor 101_2 turns off, wiring 112 and wiring 111 become non-conductive. Then, signal OUT becomes low level.

[0107] Note that in period C1, the timing at which signal CK1 becomes low level may be earlier than the timing at which the voltage of node n1 decreases. That is, signal CK1 may become low level before transistor 101_1 turns off. Therefore, the low-level signal CK1 may be supplied from wiring 112 to wiring 111 via transistor 101_1. In such a case, the channel width of transistor 101_1 is often larger than the channel width of other transistors when there are other transistors, so the fall time of signal OUT can be shortened. Therefore, in period C1, there are cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. Next, in period D1 and period E1, as shown in FIG. 3(D), circuit 200 supplies a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. Then, the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 generally remains at V1. Therefore, transistors 101_1 and 101 _2 remain off, so wiring 112 and wiring 111 remain in a non-conductive state. Thus, in period C1, there are cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. from circuit 200 to wiring 111, cases where a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1, and cases where a low-level signal or voltage V1 is supplied from circuit 200 to wiring 111 and a low-level signal is supplied from wiring 112 to wiring 111 via transistor 101_1. There are.

[0108] Next, in period D1 and period E1, as shown in FIG. 3(D), circuit 200 supplies a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. Then, the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 generally remains at V1. Therefore, transistors 101_1 and 101 _2 remain off, so wiring 112 and wiring 111 remain in a non-conductive state. Therefore, transistors 101_1 and transistor 101 _2 remain off, so wiring 112 and wiring 111 remain in a non-conductive state. As a result, the signal OUT remains at a low level.

[0109] Note that in one of the periods D1 and E1, the circuit 200 supplies a low-level signal or voltage V1 to the node n1, the node n2, and / or the wiring 111, and in the other period, the circuit 200 can refrain from supplying a signal or voltage to the node n1, the node n2, and / or the wiring 111.

[0110] Next, the operation in the period T2 will be described. In the period T2, the signal SEL1 becomes a low level, and the signal SEL2 becomes a high level.

[0111] In the period A2, as shown in FIG. 4(A), the signal SP becomes a high level. Then, the circuit 200 supplies a low-level signal or voltage V1 to the node n1. Therefore, the voltage of the node n1 decreases so as to be approximately V1. Or, it is maintained at approximately V1. As a result, the transistor 101_1 turns off. On the other hand, the circuit 200 supplies a high-level signal or voltage V2 to the node n2. Therefore, the voltage of the node n2 starts to rise. After that, the voltage of the node n2 continues to rise, and eventually, the voltage of the node n2 rises to V1 + Vth101_2 (Vth101_2: the threshold voltage of the transistor 101_2) + Vx. Then, since the transistor 101_2 turns on, the wiring 112 and the wiring 111 become conductive through the transistor 101_2. Therefore, the low-level signal CK1 is supplied from the wiring 112 to the wiring 111 through the transistor 101_2. As a result, the signal OUT becomes a low level. After that, the voltage of the node n2 further rises. Eventually, Path 200 stops supplying signals or voltages to node n2, so circuit 200 and node n2 become non-conductive. As a result, node n2 becomes floating, and the voltage of node n2 is maintained at the value of V1 + Vth101_2 + Vx. However, it is not limited to this. For example circuit 200 can continue to supply the voltage of V1 + Vth101_2 + Vx to node n2 in this way.

[0112] Note that during period A2, circuit 200 can supply a low-level signal or voltage V1 to wiring 111 or can refrain from supplying signals or voltages, etc. to wiring 111 as well.

[0113] Next, during period B2, as shown in FIG. 4(B), signal SP becomes low level. Then circuit 200 supplies a low-level signal or voltage V1 to node n1. Thus, the voltage of node n1 remains approximately at V1. As a result, transistor 101_1 remains off. On the other hand, circuit 200 refrains from supplying signals or voltages, etc. to node n2. Therefore, node n2 remains floating, so the voltage of node n2 remains at the value of V1 + Vth101_2 + Vx. That is, transistor 101_2 remains on so that wiring 112 and wiring 111 remain conductive through transistor 101_2. At this time, signal CK1 rises from low level to high level. Then the high-level signal CK1 is supplied from wiring 112 to wiring 111 through transistor 101_2, so the voltage of wiring 111 starts to rise. Then, since node n2 remains floating the voltage of node n2 is the voltage between the gate and the second terminal of transistor 101_2 At this time, the high-level signal CK1 is supplied from wiring 112 to wiring 111 through transistor 101_2, so the voltage of wiring 111 starts to rise. Then, since node n2 remains floating the voltage of node n2 is the voltage between the gate and the second terminal of transistor 101_2 while node n2 remains floating, so the voltage of node n2 is the voltage between the gate and the second terminal of transistor 101_2 Due to the parasitic capacitance between them, it rises to the value of V2 + Vth101_2 + Vx. This is the so-called bootstrapping operation. In this way, the voltage of wiring 111 can rise to V2. In this way, the signal OUT becomes high level.

[0114] Note that in period B2, circuit 200 often does not supply a signal or voltage etc. to wiring 111. However, it is not limited to this, and circuit 200 can supply a high-level signal or voltage V 2 etc. to wiring 111.

[0115] Next, in period C2, as shown in FIG. 4(C), the signal RE becomes high level. Then, circuit 200 supplies a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. Therefore, the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 becomes V1. As a result, since transistors 101_1 and transistor 101_2 turn off, wiring 112 and wiring 111 become non-conductive. And the signal OUT becomes low level.

[0116] Note that in period C2, the timing at which the signal CK1 becomes low level may be earlier than the timing at which the voltage of node n1 decreases. That is, the signal CK1 may become low level before transistor 101_2 turns off. Therefore, the low-level signal CK1 may be supplied from wiring 112 to wiring 111 via transistor 101_1. In such a case, the channel width of transistor 101_1 is often larger than the channel width of other transistors when having other transistors, for example, so the signal OU ​​​The falling time of T can be shortened. Therefore, in period C2, circuit 200 there are cases where a low-level signal or voltage V1 is supplied to wiring 111 from circuit 200, cases where a low-level signal is supplied to wiring 111 from wiring 112 via transistor 101_1, and cases where a low-level signal is supplied to wiring 111 from circuit 200 and a low-level signal is also supplied to wiring 111 from wiring 112 via transistor 101_1.

[0117] Next, in period D2 and period E2, as shown in FIG. 4(D), circuit 200 supplies a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. Then, the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 will remain approximately at V1. Therefore, transistors 101_1 and 101_2 remain off, so wiring 112 and wiring 111 remain in a non-conductive state. Thus, signal OUT remains at a low level.

[0118] Note that in one of period D2 and period E2, circuit 200 supplies a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111, and in the other period, circuit 200 can refrain from supplying a signal or voltage to node n1, node n2, and / or wiring 111.

[0119] As described above, in period T1, transistor 101_2 turns off, and in period T2, transistor 101_1 can turn off. Therefore, the number of times transistors 101_1~101_2 turn on, and the large The number of times Vgs is applied and / or the time during which transistors 101_1 to 101_2 are turned on can be reduced respectively, so that the characteristic degradation of transistors 101_1 to 101_2 can be suppressed.

[0120] Alternatively, by being able to suppress the characteristic degradation of the transistor, various merits can be obtained. For example, when wiring 111 is connected to a pixel, the video signal held by the pixel may be affected by the waveform of signal OUT. For example, when the voltage of the high level of signal OUT does not rise to V2, the time during which the transistor (for example, a selection transistor or a switching transistor) included in the pixel is turned on becomes short. As a result, insufficient writing of the video signal to the pixel may occur, and the display quality may deteriorate. Or, when the fall time and the rise time of signal OUT become long, the video signal to a pixel belonging to another row may be written to the pixel belonging to the selected row. As a result, the display quality deteriorates. Or, when the fall time of signal OUT varies, the influence of the feed-through on the video signal held by the pixel may vary. As a result, display unevenness caused by crosstalk or the like may occur.

[0121] However, the semiconductor device of the present embodiment can suppress the characteristic degradation of the transistor. Therefore, since the voltage of the high level of signal OUT can be raised to V2, the time during which the transistor included in the pixel is turned on can be lengthened. As a result, since the video signal can be written to the pixel in sufficient time, the display quality can be improved. Or, the fall time and rise time of the signal OUT can be shortened. Therefore, the video signal for the pixels in the selected row is written to the pixels in another row. As a result, the display quality can be improved. Or, since the variation in the fall time of the signal OUT can be suppressed, the pixels can be protected. This can reduce the variation in the effect of feedthrough on the video signal carried by the Display unevenness can be suppressed.

[0122] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or It is possible to make it a P-channel type. Therefore, the number of steps is reduced compared to CMOS circuits. In particular, it is possible to reduce the number of defects, improve the yield, improve the reliability, or reduce the cost. If all transistors, including the elemental part, are N-channel type, the semiconductor layer of the transistor a non-single crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor However, transistors using these semiconductors tend to deteriorate. However, the semiconductor device of the present embodiment is capable of suppressing the deterioration of the transistor. It is possible.

[0123] Or, since the deterioration of the transistor can be suppressed, when the transistor deteriorates Therefore, it is not necessary to increase the channel width of the transistor. This allows the channel width of the star to be reduced.

[0124] In the period T1, the transistor 101_1 is turned on (period A1 and period The period B1) is called a first period or a first sub-period, during which the transistor 101_1 is turned off. The periods (period C1, period D1, and period E1) can be referred to as the second period or the second sub-period. Similarly, in period T2, the periods during which transistor 101_2 is on ( period A2 and period B2) can be referred to as the third period or the third sub-period, and the periods during which transistor 101_2 is off (period C2, period D2, and period E2) can be referred to as the fourth period or the fourth sub- period.

[0125] Note that the periods during which transistor 101_1 is on (period A1 and period B1) are often shorter than the periods during which transistor 101_1 is off (periods C1 - E1). Or, the periods during which transistor 101_2 is on (period A2 and period B2) are often shorter than the periods during which transistor 101_2 is off (periods C2 - E2). Or, the periods during which transistor 101_1 is on and the periods during which transistor 101_2 is on are often approximately equal in length. However, it is not limited to this. Note that in period T1, period B1 has the function as a selection period, and periods A1, period C 1, period D1, and period E1 can have the function as non-selection periods. Similarly, in period T2, period B2 has the function as a selection period, and periods A2, period C2

[0126] Note that in period T1, period B1 has the function as a selection period, and periods A1, period C 1, period D1, and period E1 can have the function as non-selection periods. Similarly, in period T2, period B2 has the function as a selection period, and periods A2, period C2

[0127] Note that periods A1 and A2 can function as a set period or a start period. Periods B1 and B2 can function as a selection period. Or, periods C1 and C2 can function as a reset period.​​​​ Yes.

[0128] Note that the periods T1 and T2 can function as frame periods. . Note that the frame frequency is preferably approximately 60 Hz (or 50 Hz). However, it is not limited to this. For example, by setting the frame frequency higher than 60 Hz, blurring or afterimages of the video can be improved. However, if the frame frequency is too high, the driving frequency becomes high, resulting in an increase in power consumption. Therefore, to suppress the increase in power consumption, the frame frequency is preferably 60 Hz (or 50 Hz) or higher and 360 Hz or lower. More preferably, it is preferably 60 Hz (or 50 Hz) or higher and 240 Hz or lower. Even more preferably, it is preferably 60 Hz (or 50 Hz) or higher and 120 H z (or 100 Hz) or lower. On the other hand, by setting the frame frequency lower than 60 Hz, the external circuit can be made simpler in configuration. Or, power consumption can be reduced. Therefore, a semiconductor device according to an aspect of the present invention can be applied to mobile devices such as mobile phones. However, if the frame frequency is too low, the holding capacitance of the pixel increases, and the aperture ratio of the pixel decreases. Therefore, to suppress the decrease in the aperture ratio, the frame frequency is preferably 15 Hz or higher and 60 Hz (or 50 Hz) or lower. More preferably, it is preferably 30 Hz or higher and 60 Hz (or 50 Hz) or lower.

[0129] Note that the periods A1 to E1 and the periods A2 to E2 can function as sub-periods or one gate selection period.

[0130] ​​​Note that a period or sub - period can be rephrased as a step, process, or operation. For example, when referring to a first period, it can be rephrased as a first step, a first process, or a first operation.

[0131] Note that the time from the start time of period T1 to the start time of period A1 is preferably approximately equal to the time from the start time of period T2 to the start time of period A2. However, it is not limited to this.

[0132] Note that signals CK1 and CK2 can be unbalanced. As an example in FIG. 5(A), when the period of being at a high level is shorter than the period of being at a low level within one cycle, the timing chart is shown. By making the period of being at a high level shorter than the period of being at a low level, in period C1 or period C2, it becomes possible to supply the low - level signal CK1 to wiring 1 11, so that the fall time of signal OUT can be shortened. In particular, when wiring 111 extends and is formed in the pixel portion, it is possible to prevent the writing of an incorrect video signal to the pixel. However, it is not limited to this. For example, within one cycle, it is possible that the period of being at a high level is longer than the period of being at a low level.

[0133] Note that a multiphase clock signal can be used in the semiconductor device. For example, an n - phase (n is a natural number) clock signal can be used in the semiconductor device. The n - phase clock signal means n clock signals whose periods are shifted by 1 / n cycle each. In FIG. 5(B), as an example, the timing chart when a 3 - phase clock signal is used in the semiconductor device is shown. However, it is not limited to this.

[0134] In addition, the larger n is, the lower the clock frequency is, which leads to a reduction in power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Or the external circuit may become large. Therefore, it is preferable that n<8. It is preferable that n<6. It is further preferable that n=4 or Preferably, n=3, but is not limited to this.

[0135] The transistors 101_1 and 101_2 are not turned on at the same time. In this case, for example, the circuit 200 may provide high-level It is possible to provide a bell signal or voltage V2.

[0136] The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are It is preferable that the transistor sizes are approximately equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the degree of deterioration of the selected transistors can be made approximately equal. Even if the input voltage is switched, the waveform of the signal OUT can be made roughly the same. For this reason, the channel length of the transistor 101_1 and the channel length of the transistor 101_2 It is preferable that the values ​​are approximately equal to each other, but the present invention is not limited to this.

[0137] Note that when describing the channel width of a transistor, it is expressed as W / L (W is the channel It can be expressed as the ratio of the width of the channel to the width of the channel.

[0138] Note that since transistors 101_1 and 101_2 drive a large load such as a gate signal line, the channel widths of transistors 101_1 and 101_2 are preferably larger. For example, the channel widths of transistors 101_1 and 101_2 are preferably in the range of 1000 μm to 30000 μm. More preferably, they are in the range of 2000 μm to 20000 μm. Even more preferably, they are in the range of 3000 μm to 8000 μm or 10000 μm to 18000 μm. However, it is not limited thereto.

[0139] In addition, in the configuration described in FIG. 1(A), as shown in FIG. 1(B), circuit 100 can have a plurality of transistors such as transistors 101_1 to 101_N (N is a natural number of 2 or more). The first terminals of transistors 101_1 to 101_N are connected to wiring 112. The second terminals of transistors 101_1 to 101_N are connected to wiring 111. The gates of transistors 101_1 to 101_N are connected to circuit 200. The connection points between the gates of transistors 101_1 to 101_N and circuit 200 are respectively shown as nodes n1 to nN. However, it is not limited thereto.

[0140] Note that as N increases, the number of times the transistors turn on or the time the transistors are on can be reduced respectively. Therefore, the larger N is, the more the degradation of the transistors can be suppressed. However, if N is too large, the number of transistors will increase too much and the circuit scale will become large. Therefore, N is preferably 6 or less. Yes. More preferably, it is preferably 4 or less. Even more preferably, N = 2, or N = It is preferably 3.

[0141] In addition, in the configuration described in FIGS. 1(A) to 1(B), as shown in FIG. 1(C), the first terminal of the transistor 101_1 and the first terminal of the transistor 101_2 can be connected to separate wirings. In an example of FIG. 1(C), the wiring 112 is divided into a plurality of wirings such as wirings 112A to 112 B. Then, the first terminal of the transistor 101_1 is connected to the wiring 112A, and the first terminal of the transistor 101_2 is connected to the wiring 112B. It should be noted that the wirings 112A to 112B can have the same function as the wiring 112. Therefore, signals such as the signal CK1 can be input to the wirings 112A to 112B. However, it is not limited to this. For example, different voltages or different signals can be supplied to the wiring 112A and the wiring 112B.

[0142] In addition, in the configuration described in FIGS. 1(A) to 1(C), as shown in FIG. 1(D), a capacitive element 102_1 is connected between the gate and the second terminal of the transistor 101_1, and a capacitive element 102_2 is connected between the gate and the second terminal of the transistor 101_2. This makes it easier for the voltage of the node n1 or the voltage of the node n2 to rise during the bootstrap operation. Therefore, the Vgs of the transistor 101_1 and the transistor 101_2 can be increased, so the channel width of these transistors can be reduced. Or, the fall time or the rise time of the signal OUT can be ​​​​​It can be shortened, but not limited thereto. For example, as the capacitive element, MIS capacitance can be used.

[0143] Note that the material of one electrode of the capacitive elements 102_1 to 102_2 is preferably the same as the material of the gates of the transistors 101_1 to 101_2. The material of the other electrode of the capacitive elements 102_1 to 102 _2 is preferably the same as the material of the source or drain of the transistors 101_1 to 101_2. By doing so, the layout area can be reduced . Or the capacitance value can be increased. However, it is not limited thereto .

[0144] Note that the capacitance value of the capacitive element 102_1 and the capacitance value of the capacitive element 102_2 are preferably approximately equal . Or the area where one electrode and the other electrode of the capacitive element 102_1 overlap is preferably approximately equal to the area where one electrode and the other electrode of the capacitive element 102_2 overlap . By doing so, even if the transistors 101_1 and the transistors 10 1_2 are switched and used with each other, since it is possible to make the Vgs of the transistor 101_1 and the Vgs of the transistor 1 01_2 approximately equal, the waveform of the signal OUT can be made approximately equal. However, it is not limited thereto.

[0145] Note that in the configuration described in FIGS. 1(A) to (D), as shown in FIG. 1(E), the transistor 101_1 is replaced with a diode 101a_1 in which one terminal (hereinafter also referred to as the positive electrode) is connected to the node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 111, and the transistor 101_2 is replaced with a diode in which one terminal is connected to the node n2 and the other terminal is the wiring 1 111. It can be replaced with the diode 101a_2 connected to 11. However, this is not limited thereto. For example, in the configuration described in FIGS. 1(A) to (D), as shown in FIG. 1(F), by connecting the first terminal of the transistor 101_1 to the node n1, it is possible to configure the transistor 101_1 in a diode-connected manner. Similarly, by connecting the first terminal of the transistor 101_2 to the node n2, the transistor 101_2 can be configured in a diode-connected manner.

[0146] In addition, in the configuration described in FIGS. 1(A) to (F), as shown in FIG. 6(A), separately from the signal OUT, it is possible to generate a signal for transfer. For example, assume that a plurality of semiconductor devices are connected in series. In this case, the transfer signal often enters the next-stage semiconductor device as a start signal without being input to the gate signal line. Therefore, the delay or the smear of the transfer signal is often smaller than that of the signal OUT. Therefore, since the semiconductor device can be driven using a signal with a small delay or smear, the delay of the output signal of the semiconductor device can be reduced. Or, since the charging timing of the node n1 or the node n2 can be advanced, the operating range can be widened. However, this is not limited thereto.

[0147] For this purpose, as shown in FIG. 6(A), the semiconductor device of the present embodiment can have a circuit 150. The circuit 150 has a plurality of transistors, namely, transistors 151_1 to 151_2. The transistors 151_1 to 151_2 are the same as the transistors 101_ It is preferably the same polarity as 1~101_2 and is an N-channel type. However it is not limited to this, and the transistors 151_1~151_2 can be of P-channel type as well.

[0148] The first terminal of the transistor 151_1 is connected to the wiring 112, and the second terminal of the transistor 151_1 is connected to the wiring 119, and the gate of the transistor 151_1 is connected to the node n1. The first terminal of the transistor 151_2 is connected to the wiring 112, and the second terminal of the transistor 151_2 is connected to the wiring 119, and the gate of the transistor 151_2 is connected to the

[0149] node n2. For example, assuming that a plurality of semiconductor devices are connected in series, the wiring 119 is often connected to the wiring 115 of a semiconductor device in another stage (for example, the next stage). In this case, the wiring 11 1 can be formed to extend into the pixel portion. Or it can be connected to the gate of a transistor (for example, a switching transistor, a selection transistor) that the pixel has. However, it is not limited to this. For example, the wiring 119 can be disposed to extend into the pixel portion. Or the wiring 119 can be connected to the gate of a

[0150] transistor that the pixel has. Or the wiring 119 can be connected to the wiring 117 of a semiconductor device in another stage (for example, the previous stage). It is possible to have a function as a signal. Thus, wiring 119 can be a signal line or an output It is possible to have a function as a signal line. For example, assume that a plurality of semiconductor devices are connected in series In this case, since wiring 119 is often connected to the wiring 115 of a semiconductor device in another stage (e.g., the next stage), signal SOUT can have a function as a transfer signal or a start signal However, it is not limited to this. For example, when wiring 119 is extended and arranged in the pixel portion, or when wiring 119 is connected to the gate of a pixel transistor signal SOUT can have a function as a gate signal, a scanning signal, or a selection signal. Thus, wiring 119 can have a function as a gate signal line or a scanning line Another example is when wiring 119 is connected to the wiring 117 of a semiconductor device in another stage (e.g., the previous stage), signal SOUT can have a function as a reset signal

[0151] Circuit 150, as an example, has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n1 and / or the voltage of node n2. Or, circuit 150 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112 circuit 150 has a function of controlling the timing of supplying the signal or voltage etc. supplied to wiring 112 to wiring 119 Or, circuit 150 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, circuit 150 has a function of controlling the timing of increasing the voltage of wiring 119. Or ​​​​​​​ Circuit 150 has a function of controlling the timing for supplying a low-level signal (such as signal CK1) to wiring 119. Or, circuit 150 has a function of controlling the timing for decreasing or maintaining the voltage of wiring 119. Or, circuit 150 has a function of controlling the timing for raising the voltage of node n1 and / or the voltage of node n2 by a bootstrap operation. As described above, circuit 150 can function as a control circuit, a buffer circuit, or a switch, etc., but is not limited thereto. Note that circuit 150 does not necessarily have all of the above functions.

[0152] As an example, transistor 151_1 has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n1. Or, transistor 151_1 has a function of controlling the timing for supplying the voltage of wiring 112 to wiring 119. For example, when a signal or a voltage (such as voltage V2 or signal CK1, etc.) is supplied to wiring 112, transistor 151_1 has a function of controlling the timing for supplying the signal or voltage etc. supplied to wiring 112 to wiring 119. Or, transistor 151_1 has a function of controlling the timing for supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_1 has a function of controlling the timing for raising the voltage of wiring 119. Or, transistor 151_1 has a function of controlling the timing for supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_1 has a function of controlling the timing for decreasing or maintaining the voltage of wiring 119. It has a function of controlling the ring. Or, transistor 151_1 has a function of performing a bootstrap operation. Or, transistor 151_1 has a function of raising the voltage of node n1 by a bootstrap operation. As described above, transistor 151_1 can have a function as a buffer, a switch, etc. However, it is not limited to this. Note that transistor 151_1 does not necessarily have all of the above functions. It has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n2. Or, transistor 151_2 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. As described above, transistor 151_1 can have a function as a buffer, a switch, etc. However, it is not limited to this. Note that transistor 151_1 does not necessarily have all of the above functions. It has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n2. Or, transistor 151_2 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. As described above, transistor 151_1 can have a function as a buffer, a switch, etc. However, it is not limited to this. Note that transistor 151_1 does not necessarily have all of the above functions. It has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n2. Or, transistor 151_2 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2.

[0153] Transistor 151_2, as an example, has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n2. Or, transistor 151_2 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the conduction state between wiring 112 and wiring 119 according to the voltage of node n2. Or, transistor 151_2 has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of supplying the voltage of wiring 112 to wiring 119. For example, when a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. When a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. When a signal or voltage (such as voltage V2 or signal CK1) is supplied to wiring 112, transistor 151_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 112 to wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of supplying a high-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of raising the voltage of wiring 119. Or, transistor 151_2 has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of supplying a low-level signal (such as signal CK1) to wiring 119. Or, transistor 151_2 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of controlling the timing of decreasing or maintaining the voltage of wiring 119. Or, transistor 151_2 has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of performing a bootstrap operation. Or, transistor 151_2 has a function of boosting the voltage of node n2. It has a function of being raised by the strap operation. As described above, transistor 151_ 2 can have functions such as a buffer or a switch. However, this is not limited thereto. Note that transistor 151_2 does not necessarily have all of the above functions.

[0154] As shown in the timing chart of FIG. 7, the schematic diagrams of the semiconductor devices of FIGS. 8(A) to (D), and the schematic diagrams of the semiconductor devices of FIGS. 9(A) to (D), transistors 151_1 to 151_2 often operate at substantially the same timing as transistors 101_1 to 101_2. For example, in periods A1 to B1, when transistor 101_1 turns on, transistor 151_1 also turns on. Subsequently, in periods C1 to E1, when transistor 101_1 turns off, transistor 151_1 also turns off. And in periods A2 to B2, when transistor 101_2 turns on, transistor 151_2 also turns on. Subsequently, in periods C2 to E2, when transistor 101_2 turns off, transistor 151_2 also turns off. Therefore, signal SOUT often switches between high level and low level at substantially the same timing as signal OUT. However, this is not limited thereto.

[0155] Note that the channel width of transistor 151_1 and the channel width of transistor 151_2 are preferably substantially equal. In this way, by making the transistor sizes substantially equal, the current supply capabilities can be made substantially equal. Or, the degrees of deterioration of the transistors can be made substantially equal. Therefore, the selected transistors ​​​​​Even if the input voltage is switched, the waveform of the signal SOUT can be made roughly the same. For this reason, the channel length of the transistor 151_1 and the channel length of the transistor 151_2 are The length is preferably approximately equal, but is not limited to this.

[0156] The signal SOUT is used as a transfer signal, and the signal OUT is used as a gate signal and a scanning signal. When the line 119 is used as a select signal, the load of the line 119 is smaller than the load of the line 111. Therefore, the channel width of the transistor 151_1 is often smaller than that of the transistor 1 It is preferable that the channel width of the transistor 151_2 is smaller than that of the transistor 151_1. The channel width is preferably smaller than that of the transistor 101_2. But, it is not limited to this.

[0157] The channel length of the transistor 151_1 is the same as that of the transistor 101_1. It is preferable that the channel length of the transistor 151_2 is approximately equal to that of the transistor 151_1. It is preferable that the channel length of the first transistor 101_1 is approximately equal to that of the second transistor 101_2. However, this is not limited to this. It won't be done.

[0158] The channel width of the transistor 151_1 and the channel width of the transistor 151_2 are The thickness is preferably 100 μm to 5000 μm. More preferably, the thickness is 300 μm to 2 000 μm. More preferably, it is 500 μm to 1000 μm. However, the present invention is not limited to this.

[0159] In the configuration described in FIG. 6(A), as shown in FIG. 6(B), similarly to FIG. 1(B), , Circuit 150 can have a plurality of transistors, namely transistors 151_1 to 151_N (N is a natural number of 2 or more). The first terminals of transistors 151_1 to 151_N are connected to wiring 112. The second terminals of transistors 151_1 to 151_N are connected to wiring 119. The gates of transistors 151_1 to 151_N are each connected to any one of nodes n1 to nN. However, it is not limited to this.

[0160] In addition, in the configuration described in FIGS. 6(A) to (B), as shown in FIG. 6(C), similar to FIG. 1(C), the first terminal of transistor 151_1 and the first terminal of transistor 151_2 can be connected to separate wirings. In an example of FIG. 6(C), wiring 112 is divided into a plurality of wirings, namely wirings 112C to 112D. Then, the first terminal of transistor 151 _1 is connected to wiring 112C, and the first terminal of transistor 151_2 is connected to wiring 112D. However, it is not limited to this.

[0161] In addition, in the configuration described in FIGS. 6(A) to (C), as shown in FIG. 6(D), similar to FIG. 1(D), a capacitive element 152_1 is connected between the gate and the second terminal of transistor 151_1, and a capacitive element 152_2 can be connected between the gate and the second terminal of transistor 151_2. However, it is not limited to this.

[0162] It is preferable that the capacitance value of capacitive element 152_1 and the capacitance value of capacitive element 152_2 are approximately equal. Or, the area where one electrode and the other electrode of capacitive element 152_1 overlap is approximately equal to the area where one electrode and the other electrode of capacitive element 152_2 overlap. ​​​​This is preferable. By doing so, even when transistors 151_1 and 151_2 are switched and used interchangeably, it is possible to make the Vgs of transistor 151_1 and the Vgs of transistor 151_2 approximately equal, so that the waveform of signal SOUT can be made approximately equal. However, it is not limited to this. In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(E), similar to FIG. 1(E), transistor 151_1 can be replaced with a diode 151a_1 having one terminal connected to node n1 and the other terminal connected to wiring 119. Similarly, transistor 151_2 can be replaced with a diode 151a_2 having one terminal connected to node n2 and the other terminal connected to wiring 119. However, it is not limited to this. For example, in the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(F), similar to FIG. 1(F), by connecting the first terminal of transistor 151_1 to node n1, it is possible to form a configuration in which transistor 151_1 is diode-connected. Similarly, by connecting the first terminal of transistor 151_2 to node n2, it is possible to form a configuration in which transistor 151_2 is diode-connected.

[0163] In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(G), the second terminal of transistor 151_1 and the second terminal of transistor 151_2 can be connected to separate wirings. In an example of FIG. 6(G), wiring 119 is divided into a plurality of wirings such as wiring 119A to 119B. And the second terminal of transistor 151_1 is connected to wiring 119A, and the second terminal of transistor 151_2 is connected to wiring 119B. However, it is not limited to this. is connected to wiring 119A, and the second terminal of transistor 151_2 is connected to wiring 119B. However, it is not limited to this. In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(F), similar to FIG. 1(F), by connecting the first terminal of transistor 151_1 to node n1, it is possible to form a configuration in which transistor 151_1 is diode-connected. Similarly, by connecting the first terminal of transistor 151_2 to node n2, it is possible to form a configuration in which transistor 151_2 is diode-connected. In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(F), similar to FIG. 1(F), by connecting the first terminal of transistor 151_1 to node n1, it is possible to form a configuration in which transistor 151_1 is diode-connected. Similarly, by connecting the first terminal of transistor 151_2 to node n2, it is possible to form a configuration in which transistor 151_2 is diode-connected. In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(F), similar to FIG. 1(F), by connecting the first terminal of transistor 151_1 to node n1, it is possible to form a configuration in which transistor 151_1 is diode-connected. Similarly, by connecting the first terminal of transistor 151_2 to node n2, it is possible to form a configuration in which transistor 151_2 is diode-connected. In the configuration described in FIGS. 6(A) to (D), as shown in FIG. 6(F), similar to FIG. 1(F), by connecting the first terminal of transistor 151_1 to node n1, it is possible to form a configuration in which transistor 151_1 is diode-connected. Similarly, by connecting the first terminal of transistor 151_2 to node n2, it is possible to form a configuration in which transistor 151_2 is diode-connected.

[0164] In the configuration described in FIGS. 6(A) to (F), as shown in FIG. 6(G), the second terminal of transistor 151_1 and the second terminal of transistor 151_2 can be connected to separate wirings. In an example of FIG. 6(G), wiring 119 is divided into a plurality of wirings such as wiring 119A to 119B. And the second terminal of transistor 151_1 is connected to wiring 119A, and the second terminal of transistor 151_2 is connected to wiring 119B. However, it is not limited to this. In the configuration described in FIGS. 6(A) to (F), as shown in FIG. 6(G), the second terminal of transistor 151_1 and the second terminal of transistor 151_2 can be connected to separate wirings. In an example of FIG. 6(G), wiring 119 is divided into a plurality of wirings such as wiring 119A to 119B. And the second terminal of transistor 151_1 is connected to wiring 119A, and the second terminal of transistor 151_2 is connected to wiring 119B. However, it is not limited to this. The second terminal of the transistor 151_2 is connected to the wiring 119B and is connected to the wiring 119A. However, it is not limited to this. That is, it is not limited to this.

[0165] (Embodiment 2) An example of this embodiment includes a first transistor in which a first terminal is electrically connected to a first wiring and a second terminal is electrically connected to a second wiring, and a second transistor in which a first terminal is electrically connected to the first wiring and a second terminal is electrically connected to the second wiring. There is also a first circuit that is electrically connected to the gate of the first transistor and the gate of the second transistor, a second circuit that is electrically connected to the gate of the first transistor, the gate of the second transistor, and the second wiring, and a third circuit that is electrically connected to the gate of the first transistor, the gate of the second transistor, and the second wiring. The first circuit has a function of raising the voltage of the gate of the first transistor when a first signal is in a first voltage state and a second signal is in a second voltage state, and a function of raising the voltage of the gate of the second transistor when the first signal is in the first voltage state and a third signal is in the second voltage state. The second circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when any one of the gate of the first transistor, the gate of the second transistor, and the second wiring is in the first voltage state. The third circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when a fourth signal is in the second voltage state. The first circuit has a function of raising the voltage of the gate of the first transistor when a first signal is in a first voltage state and a second signal is in a second voltage state, and a function of raising the voltage of the gate of the second transistor when the first signal is in the first voltage state and a third signal is in the second voltage state. The second circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when any one of the gate of the first transistor, the gate of the second transistor, and the second wiring is in the first voltage state. The third circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when a fourth signal is in the second voltage state. The first circuit has a function of raising the voltage of the gate of the first transistor when a first signal is in a first voltage state and a second signal is in a second voltage state, and a function of raising the voltage of the gate of the second transistor when the first signal is in the first voltage state and a third signal is in the second voltage state. The second circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when any one of the gate of the first transistor, the gate of the second transistor, and the second wiring is in the first voltage state. The third circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when a fourth signal is in the second voltage state. The first circuit has a function of raising the voltage of the gate of the first transistor when a first signal is in a first voltage state and a second signal is in a second voltage state, and a function of raising the voltage of the gate of the second transistor when the first signal is in the first voltage state and a third signal is in the second voltage state. The second circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when any one of the gate of the first transistor, the gate of the second transistor, and the second wiring is in the first voltage state. The third circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when a fourth signal is in the second voltage state. The first circuit has a function of raising the voltage of the gate of the first transistor when a first signal is in a first voltage state and a second signal is in a second voltage state, and a function of raising the voltage of the gate of the second transistor when the first signal is in the first voltage state and a third signal is in the second voltage state. The second circuit has a function of outputting a signal or voltage in the first voltage state to any one of the gate of the first transistor, the gate of the second transistor, and the second wiring when any one of the gate of the first transistor, the gate of the second transistor, and the second wiring is in the first voltage state. It has a function of outputting a signal or voltage in a first voltage state to either the wiring of 2. It is.

[0166] An example of this embodiment is that the first terminal is electrically connected to the first wiring, and the second terminal is electrically connected to the second wiring, a first transistor, the first terminal is electrically connected to the first wiring, and the second terminal is electrically connected to the second wiring, a second transistor and the first terminal is electrically connected to the third wiring, the second terminal is electrically connected to the gate of the first transistor, and the gate is electrically connected to the third wiring, a third transistor and the first terminal is electrically connected to the third wiring, the second terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the third wiring, a fourth transistor and the first terminal is electrically connected to the fourth wiring, the second terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the fifth wiring, a fifth transistor and the first terminal is electrically connected to the fourth wiring, the second terminal is electrically connected to the gate of the first transistor, and the gate is electrically connected to the sixth wiring, a sixth transistor.

[0167] An example of the semiconductor device of this embodiment will be described. The semiconductor device of this embodiment can be used for the circuit 200 described in Embodiment 1. Note that the content described in Embodiment 1 is omitted in its description. Note that the content described in this embodiment can be appropriately combined with the content described in Embodiment 1.

[0168] First, an example of the circuit 200 will be described with reference to FIG. 10. In an example of FIG. 10, the circuit 200 has circuits 300, 400, and 500. Circuit 300 shows a part of circuit 200 and circuit 400 shows a part of circuit 200, and circuit 500 shows a part of circuit 200 Some or all of the circuits of circuits 300, 400, and 500 can be shared with each other in each of circuits 300 , 400, and 500.

[0169] Circuit 300 is connected to, as an example, wiring 115, wiring 116_1, wiring 116_2, wiring 118 , node n1, and node n2. Circuit 400 is connected to, as an example, wiring 111 , wiring 113, wiring 114, wiring 118, node n1, and node n2. Circuit 500 is connected to, as an example, wiring 111, wiring 117, wiring 118, node n1, and node n2. However, it is not limited thereto. For example, circuits 300, 400, and circuit 500 can be connected to various other wirings or various nodes according to their configurations .

[0170] Note that circuits 300, 400, and 500 do not necessarily need to be connected to all of the above-described wirings, and it is possible that they are not connected to any of the above-described wirings. For example, circuit 300 can be connected to wiring 113 and / or wiring 114. As another example, circuit 300 can be not connected to wiring 118. As another example , circuit 400 can be not connected to either wiring 113 or wiring 114 . As another example, circuit 500 can be not connected to wiring 111. However , it is not limited thereto.

[0171] ​Circuit 300, as an example, in response to an input signal (e.g., signal SP, signal SEL1, and / or / or signal SEL2, etc.), has a function of controlling the voltage of node n1 and / or the voltage of node n2. Or, circuit 300 has a function of controlling the timing of supplying a high-level signal or voltage V2, etc. to node n1 and / or node n2. Also / Or, circuit 300 has a function of controlling the timing of raising the voltage of node n1 and / or the voltage of node n2. Or, circuit 300 has a function of controlling the timing of supplying a low-level signal or voltage V1, etc. to node n1 and / or node n2. Also / Or, circuit 300 has a function of controlling the timing of reducing or maintaining the voltage of node n1 and / or the voltage of node n2. Or, circuit 300 has a function of controlling the timing of not supplying a signal or voltage, etc. to node n1 and / or node n2. Or, circuit 300 has a function of controlling the timing of floating node n1 and / or node n2. As described above, circuit 300 has a function as a control circuit. However, it is not limited thereto. Note that circuit 300 does not necessarily have all of the above functions.

[0172] Circuit 400, as an example, in response to an input signal or supplied voltage (e.g., signal CK2, wiring 114, wiring 118, signal OUT, the voltage of node n1, the voltage of node n2, and / or / the voltage of wiring 111, etc.), has a function of controlling the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111. Or, circuit 400 has a function of controlling the timing of supplying a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. ​​​​​​​​​​​​​ has a function of controlling. Or, circuit 400 controls the timing to reduce or maintain the voltage of node n1, the voltage of node n2 , and / or the voltage of wiring 111. Or, circuit 400 has a function of controlling the timing not to supply a signal or voltage etc. to node n1 and / or node n2. Or, circuit 400 has a function of controlling the timing to float node n1 and / or node n2 . As described above, circuit 400 has a function as a control circuit. However, it is not limited to this. Note that circuit 400 does not necessarily have all of the above functions . . . .

[0173] Circuit 500, as an example, has a function of controlling the conduction state between wiring 118 and node n1, the conduction state between wiring 118 and node n2, and / or the conduction state between wiring 118 and wiring 111 according to an input signal (such as signal RE etc.). Or, circuit 500 has a function of controlling the timing to supply the voltage of wiring 118 to node n1, node n2, and / or wiring 111. For example, when a signal or voltage etc. (such as signal CK2 or voltage V1 etc.) is supplied to wiring 118, circuit 500 has a function of controlling the timing to supply the signal or voltage etc. supplied to wiring 118 to node n1, node n2, and / or wiring 111. Or, circuit 500 has a function of controlling the timing to supply a low-level signal or voltage V1 to node n1, node n2, and / or wiring 111. Or, circuit 500 has a function of controlling the timing to reduce or maintain the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 111 . . . . . . . . . . Thus, as described above, circuit 500 functions as a control circuit or a switch, etc. However, it is not limited thereto. Note that circuit 500 does not necessarily have all of the above functions.

[0174] Note that circuits 300, 400, and 500 often represent a part of circuit 200. Therefore, circuit 200 can have a function that combines some or all of the functions of circuits 300, 400, and 500. Alternatively, circuits 300, 400, and circuit 500 can each have some or all of the functions of circuit 200. However, it is not limited thereto.

[0175] Next, an example of the operation of the semiconductor device in FIG. 10 will be described. Note that the operation of the semiconductor device in FIG. 10 often has much in common with the operation of the semiconductor device in FIG. 1, and thus will be described with reference to the timing chart in FIG. 2. Note that the semiconductor device in FIG. 10 is not limited to the timing chart in FIG. 2 and can be controlled by various timings.

[0176] First, the operation in period T1 will be described. In period T1, signal SEL1 becomes high level, and signal SEL2 becomes low level.

[0177] In period A1, as shown in FIG. 11(A), signal SP becomes high level. Then, circuit 300 supplies voltage V2 or a high-level signal to node n1. On the other hand, circuit 3 00 supplies a low-level signal or voltage V1 to node n2. Thereafter, when the voltage at node n1 becomes equal to or higher than V1+Vth101_1 as described in Embodiment 1, the circuit ​​​​Path 300 stops supplying signals or voltages to node n1. Thus, path 300 and node n1 become non-conductive. However, it is not limited to this. For example, path 300 can continue to supply a voltage of V1 +Vth101 or higher to node n1.

[0178] During period A1, path 400 often does not supply signals or voltages to node n1. Path 400 can supply a low-level signal or voltage V1 to node n2 and / or wiring 111, or it can refrain from doing so. During period A1, path 500 often does not supply signals or voltages to node n1, node n2, and / or

[0179] wiring 111. Next, during period B1, as shown in Fig. 11(B), path 300 remains without supplying signals or voltages to node n1. Thus, path 300 and node n1 remain in a non-conductive state. On the other hand, path 300 supplies a low-level signal or voltage V1 to node n2.

[0180] During period B1, path 400 often does not supply signals or voltages to node n1 and wiring 111. Path 400 can supply a low-level signal or voltage V1 to node n2, or it can refrain from doing so. During period B1, path 500 often does not supply signals or voltages to node n1, node n2, and / or wiring 111.

[0181] During period B1, path 400 often does not supply signals or voltages to node n1 and wiring 111. Path 400 can supply a low-level signal or voltage V1 to node n2, or it can refrain from doing so. During period B1, path 500 often does not supply signals or voltages to node n1, node n2, and / or wiring 111.

[0182] During period B1, path 500 often does not supply signals or voltages to node n1, node n2, and / or wiring 111.

[0183] ​Next, in period C1, as shown in FIG. 11(C), the signal RE becomes high level. That is, the circuit 500 supplies a low-level signal or voltage V1 to node n1, node n2, and / or or, the wiring 111.

[0184] Note that in period C1, the circuit 300 can supply a low-level signal or voltage V1 to node n1, and / or node n2, or can not supply it.

[0185] Note that in period C1, the circuit 400 can supply a low-level signal or voltage V1 to node n1, node n2, and / or the wiring 111, or can not supply it. is possible.

[0186] Next, in periods D1 and E1, as shown in FIG. 12(A), the circuit 400 supplies a low level signal or voltage V1 to node n1, node n2, and / or the wiring 111. However, it is not limited to this. For example, in one of the periods D1 and E1, the circuit 400 supplies voltage V1 or a low level signal to node n1, node n2, and / or or the wiring 111, and in the other period, the circuit 400 can supply no voltage or signal to node n1, node n2, and / or the wiring 111. is possible.

[0187] Note that in periods D1 and E1, the circuit 300 can supply a low-level signal or voltage V1 to node n1 and / or node n2, or can not supply it. is possible.

[0188] Note that in periods D1 and E1, the circuit 500 supplies a signal or voltage or the like to node n1 , node n2, and / or often does not supply to wiring 111.

[0189] Next, the operation in period T2 will be described. In period T2, the signal SEL1 becomes low level and the signal SEL2 becomes high level.

[0190] In period A2, as shown in FIG. 12(B), the signal SP becomes high level. Then, circuit 300 supplies a low-level signal or voltage V1 to node n1. On the other hand, circuit 3 00 supplies voltage V2 or a high-level signal to node n2. Thereafter, as described in Embodiment 1 when the voltage of node n2 becomes equal to or higher than V1 + Vth101_2, circuit 3 00 stops supplying the signal or voltage to node n2. Thus, circuit 300 and node n2 become non-conductive. However, it is not limited thereto. For example, circuit 300 can continue to supply a voltage equal to or higher than V1 + Vth101_2 to node n2.

[0191] Note that in period A2, circuit 400 often does not supply a signal or voltage or the like to node n2. Note that circuit 400 can supply a low-level signal or voltage V1 to node n1, and / or or wiring 111, and can also not supply it. or wiring 111, and can also not supply it.

[0192] Note that in period A2, circuit 500 often does not supply a signal or voltage or the like to node n1, node n2, and / or wiring 111.

[0193] Next, in period B2, as shown in FIG. 12(C), circuit 300 supplies a low-level signal or voltage V1 to node n1. On the other hand, circuit 300 supplies a signal or voltage or the like to node It will not be supplied to node n2. Therefore, the circuit 300 and the node n2 remain in a non-conductive state. It becomes like this.

[0194] During period B2, the circuit 400 often does not supply signals or voltages to the node n2 and the wiring 11. The circuit 400 can supply a low-level signal or voltage V1 to the node n1, and can also not supply it. It becomes like this.

[0195] During period B2, the circuit 500 often does not supply signals or voltages to the node n1, the node n2, and / or the wiring 111. It becomes like this.

[0196] Next, during period C2, as shown in FIG. 13(A), the signal RE becomes high level. Then, the circuit 500 supplies a low-level signal or voltage V1 to the node n1, the node n2, and / or the wiring 111. It becomes like this.

[0197] During period C2, the circuit 300 can supply a low-level signal or voltage V1 to the node n1 and / or the node n2, and can also not supply it. It becomes like this.

[0198] During period C2, the circuit 400 can supply a low-level signal or voltage V1 to the node n1, the node n2, and / or the wiring 111, and can also not supply it. It becomes like this. It becomes like this.

[0199] Next, during period D2 and period E2, as shown in FIG. 13(B), the circuit 400 supplies a low-level signal or voltage V1 to the node n1, the node n2, and / or the wiring 111. However, it is not limited to this. For example, during one of the periods D2 and E2. It becomes like this. Then, circuit 400 supplies voltage V1 or a low-level signal to node n1, node n2, and / or to wiring 111. In the other period, circuit 400 can refrain from supplying voltage or a signal to node n 1, node n2, and / or wiring 111.

[0200] Note that in period D2 and period E2, circuit 300 can supply a low-level signal or voltage V1 to node n1 and / or node n2, and can also refrain from supplying.

[0201] Note that in period D2 and period E2, circuit 500 often does not supply a signal or voltage or the like to node n1 , node n2, and / or wiring 111.

[0202] Next, a specific example of circuit 300 will be described with reference to FIG. 14(A). Circuit 300 includes a plurality of transistors such as transistors 301_1 to 301_2 and transistors 30 2_1 to 302_2. Transistors 301_1 to 30 1_2 and transistors 302_1 to 302_2 preferably have the same polarity as transistors 101_1 to 101 _2 and are assumed to be N-channel type. However, this is not limiting, and transistors 301_1 to 301_2 and transistors 302_1 to 30 2_2 can be P-channel type.

[0203] The first terminal of transistor 301_1 is connected to wiring 115, the second terminal of transistor 301_ 1 is connected to node n1, and the gate of transistor 301_1 is connected to wiring 1 15. The first terminal of transistor 301_2 is connected to wiring 115, and the ​​The second terminal of transistor 301_2 is connected to node n2, and the gate of transistor 301_2 is connected to wiring 115. The first terminal of transistor 302_1 is connected to wiring 1 18, the second terminal of transistor 302_1 is connected to node n2, and the gate of trans istor 302_1 is connected to wiring 116_1. The first terminal of transistor 302_2 is connected to wiring 118, the second terminal of transistor 302_2 is connected to node no d n1, and the gate of transistor 302_2 is connected to wiring 116_2.

[0204] Transistor 301_1, as an example, has a function of controlling the conduction state between wiring 115 and node n1. Or, transistor 301_1 has a function of controlling the timing of supplying the voltage of wiring 115 to node n1. For example, when a signal or voltage (e.g., signal SP, voltage V2, etc.) is supplied to wiring 115, transistor 301_1 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 11 5 to node n1. Or, transistor 301_1 has a function of controlling the timing of supplying a high-level signal (e.g., signal SP) or voltage V 2 to node n1. Or, transistor 3 01_1 has a function of controlling the timing of raising the voltage of node n1. Or it has a function of controlling the timing of not supplying a signal or voltage, etc. to node n1. Also transistor 301_1 has a function of controlling the timing of floating node n1. As described above, transistor 301_1 has functions such as a switch, a rectifying element, a diode , or a transistor configured as a diode-connected structure. Or transistor 301_1 has a function as a switch, a rectifying element, a diode, or a transistor configured in a diode-connected structure. Or transistor The switch 301_1 has a function of controlling whether to turn off the transistor 101_1 by turning on or off. Alternatively, the transistor 301_1 has a function of controlling whether to turn the diode 101a_1 (shown in FIG. 1(E)) into a non-conductive state by turning on or off. However, it is not limited thereto. Note that the transistor 301_1 does not necessarily have all of the above functions. Or the transistor 301_1 has a function of controlling whether to turn off the transistor 101_1 by turning on or off. Alternatively, the transistor 301_1 has a function of controlling whether to turn the diode 101a_1 (shown in FIG. 1(E)) into a non-conductive state by turning on or off. However, it is not limited thereto. Note that the transistor 301_1 does not necessarily have all of the above functions. The transistor 301_2, as an example, has a function of controlling the conduction state between the wiring 115 and the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of supplying the voltage of the wiring 115 to the node n2. For example, when a signal or voltage (such as signal SP, voltage V2, etc.) is supplied to the wiring 115, the transistor 301_2 has a function of controlling the timing of supplying the signal or voltage supplied to the wiring 115 to the node n2. Or the transistor 301_2 has a function of controlling the timing of supplying a high-level signal (such as signal SP) or voltage V2 to the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of raising the voltage of the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of not supplying a signal or voltage or the like to the node n2. Further, the transistor 301_2 has a function of controlling the timing of floating the node n2. As described above, the transistor 301_2 has functions such as a switch, a rectifying element, a diode,

[0205] or a transistor having a diode-connected configuration. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. The transistor 301_2, as an example, has a function of controlling the conduction state between the wiring 115 and the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of supplying the voltage of the wiring 115 to the node n2. For example, when a signal or voltage (such as signal SP, voltage V2, etc.) is supplied to the wiring 115, the transistor 301_2 has a function of controlling the timing of supplying the signal or voltage supplied to the wiring 115 to the node n2. Or the transistor 301_2 has a function of controlling the timing of supplying a high-level signal (such as signal SP) or voltage V2 to the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of raising the voltage of the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of not supplying a signal or voltage or the like to the node n2. Further, the transistor 301_2 has a function of controlling the timing of floating the node n2. As described above, the transistor 301_2 has functions such as a switch, a rectifying element, a diode, or a transistor having a diode-connected configuration. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. The transistor 301_2, as an example, has a function of controlling the conduction state between the wiring 115 and the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of supplying the voltage of the wiring 115 to the node n2. For example, when a signal or voltage (such as signal SP, voltage V2, etc.) is supplied to the wiring 115, the transistor 301_2 has a function of controlling the timing of supplying the signal or voltage supplied to the wiring 115 to the node n2. Or the transistor 301_2 has a function of controlling the timing of supplying a high-level signal (such as signal SP) or voltage V2 to the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of raising the voltage of the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of not supplying a signal or voltage or the like to the node n2. Further, the transistor 301_2 has a function of controlling the timing of floating the node n2. As described above, the transistor 301_2 has functions such as a switch, a rectifying element, a diode, or a transistor having a diode-connected configuration. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. The transistor 301_2, as an example, has a function of controlling the conduction state between the wiring 115 and the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of supplying the voltage of the wiring 115 to the node n2. For example, when a signal or voltage (such as signal SP, voltage V2, etc.) is supplied to the wiring 115, the transistor 301_2 has a function of controlling the timing of supplying the signal or voltage supplied to the wiring 115 to the node n2. Or the transistor 301_2 has a function of controlling the timing of supplying a high-level signal (such as signal SP) or voltage V2 to the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of raising the voltage of the node n2. Alternatively, the transistor 301_2 has a function of controlling the timing of not supplying a signal or voltage or the like to the node n2. Further, the transistor 301_2 has a function of controlling the timing of floating the node n2. As described above, the transistor 301_2 has functions such as a switch, a rectifying element, a diode, or a transistor having a diode-connected configuration. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Or the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. Alternatively, the transistor 301_2 has a function of controlling whether to turn off the transistor 101_2 by turning on or off. has a function of controlling whether the diode 101a_2 (shown in FIG. 1(E)) is turned off or not. However, it is not limited thereto. Note that the transistor 301_2 does not necessarily have all of the above functions.

[0206] The transistor 302_1 has, for example, a function of controlling the conduction state between the wiring 118 and the node n2. Or, the transistor 302_1 has a function of controlling the timing of supplying the voltage of the wiring 118 to the node n2. For example, when a signal or a voltage (such as a signal SEL2, a voltage V1, etc.) is supplied to the wiring 118, the transistor 302_1 has a function of controlling the timing of supplying the signal or the voltage supplied to the wiring 118 to the node n2. Or, the transistor 302_1 has a function of controlling the timing of supplying a low-level signal or the voltage V1 to the node n2. Or, the transistor 302_1 has a function of controlling the timing of decreasing or maintaining the voltage of the node n2. Or, the transistor 302_1 controls whether the transistor 101_2 is turned off or not. That is, it controls the timing of turning off the transistor 101_2. As described above, the transistor 302_1 has a function as a switch. However, it is not limited thereto. Note that the transistor 302_1 does not necessarily have all of the above functions.

[0207] The transistor 302_2 has, for example, a function of controlling the conduction state between the wiring 118 and the node n1. Or, the transistor 302_2 has a function of controlling the timing of supplying the voltage of the wiring 118 to the node n1. For example, when a signal or a voltage (such as a signal SEL2, a voltage V1, etc.) is supplied to the wiring 118, ​​​​​​​​​​​​​​​For example, when signals such as SEL1 and voltage V1 are supplied, transistor 302_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 118 to node n1. Or, transistor 302_2 has a function of controlling the timing of supplying a low-level signal or voltage V1 to node n1 . Or, transistor 302_2 has a function of controlling the timing of decreasing or maintaining the voltage of node n1 . Or, transistor 302_2 controls whether to turn off transistor 101_1 . That is, it controls the timing of turning off transistor 101_1. As described above, transistor 302_2 has a function as a switch. However, it is not limited to this. Note that transistor 302_2 does not necessarily have all of the above functions. Next, an example of the operation of the semiconductor device in FIG. 14(A) will be described. Note that the operation of the semiconductor device in FIG. 14(A) has many commonalities with the operation of the semiconductor device in FIG. 1(A), so it will be described with reference to the timing chart in FIG. 2

[0208] . Note that the semiconductor device in FIG. 14(A) is not limited to the timing chart in FIG. 2 and can be controlled by various timings . .

[0209] During period A1, as shown in FIG. 15(A), signal SP becomes high level. Then, transistors 301_1 and 301_2 turn on, so wiring 115 and node n1 are in a conductive state, and wiring 115 and node n2 are in a conductive state. Therefore, the high-level signal SP is supplied from wiring 115 to node n1 via transistor 301_1 is supplied. At this time, signal SEL2 becomes a low level. Then, transistor 302 _2 turns off, so wiring 118 and node n1 become non-conductive. Thus, the voltage of node n1 starts to rise. Eventually, the voltage of node n1 reaches a value (V2 - Vth301_1) obtained by subtracting the threshold voltage (Vth301_1) of transistor 301_1 from the voltage of the gate of transistor 301_1 (for example, the high-level voltage (V2) of signal SP). Then, since transistor 301_1 turns off, wiring 115 and node n1 become non-conductive state. On the other hand, the high-level signal SP is supplied from wiring 115 to node n2 via transistor 301_2 . At this time, signal SEL1 becomes a high level. Then , since transistor 302_1 turns on, wiring 118 and node n2 become conductive state. Thus, voltage V1 is supplied from wiring 118 to node n2 via transistor 302_1 . As a result, the voltage of node n2 is determined by the resistance ratio between transistor 301_2 and transistor 3 02_1. Therefore, by making the channel width of transistor 302_1 larger than the channel width of transistor 301_2 , it is possible to make the voltage of node n2 a low value (for example, V1).

[0210] During periods B1 to E1, as shown in FIGS. 15(B) to (C) and FIG. 16(A), the signal SP becomes a low level. Then, transistors 301_1 and transistor 301 _2 turn off, so wiring 115 and node n1 become non-conductive, and wiring 115 and node n2 become non-conductive. At this time, signal SEL1 becomes a high level, and signal SE L2 becomes a low level. Then, transistor 302_1 turns on, and transistor Since 302_2 is turned off, wiring 118 and node n2 are in a conductive state, and wiring 118 and node n1 are in a non-conductive state. Therefore, voltage V1 is supplied from wiring 118 to node n2 through transistor 302_1.

[0211] During period A2, as shown in FIG. 16(B), signal SP becomes high level. Then, since transistors 301_1 and 301_2 are turned on, wiring 115 and node n1 are in a conductive state, and wiring 115 and node n2 are in a conductive state. The high-level signal SP is supplied from wiring 115 to node n1 through transistor 301_1 . At this time, signal SEL2 becomes high level. Then, transistor 302_2 turns on , so wiring 118 and node n1 are in a conductive state. Therefore, voltage V1 is supplied from wiring 118 to node n1 through transistor 302_2. As a result, the voltage of node n1 is determined by the resistance ratio of transistor 301_1 and transistor 302_2 . Therefore, by making the channel width of transistor 302_2 larger than the channel width of transistor 301_1, it is possible to make the voltage of node n1 a low value (for example, V1). On the other hand, the high-level signal SP is supplied from wiring 115 to node n2 through transistor 301_ 2. At this time, signal SEL1 becomes low level. Then, transistor 302_1 turns off, so wiring 118 and node n2 are in a non-conductive state . Therefore, the voltage of node n2 starts to rise. Eventually, the voltage of node n2 is from the voltage of the gate of transistor 301_2 (for example, the high-level voltage (V2) of signal SP) . The value obtained by subtracting the threshold voltage (Vth301_2) of the transistor 301_2 from (V2 - Vth30 1_2) rises. Then, since the transistor 301_2 turns off, the wiring 115 and the node n2 become non-conductive.

[0212] During the period B2 to period E2, as shown in FIGS. 16(C) and 17(A) to (C), the signal SP becomes a low level. Then, since the transistor 301_1 and the transistor 301 _2 turn off, the wiring 115 and the node n1 become non-conductive, and the wiring 115 and the node n2 become non-conductive. At this time, the signal SEL1 becomes a low level, and the signal SE L2 becomes a high level. Then, the transistor 302_1 turns off, and the transistor 302_2 turns on, so the wiring 118 and the node n2 become non-conductive, and the wiring 11 8 and the node n1 become conductive. Therefore, the voltage V1 is supplied from the wiring 118 to the node n1 through the transistor 302_2.

[0213] As described above, one of the signal SEL1 and the signal SEL2 is set to a high level. In this way, one of the voltage of the node n1 and the voltage of the node n2 is maintained at a low value (for example, V1). Thus, it is possible to select which of the transistor 101_1 and the transistor 101_2 is turned on. However, it is not limited to this. For example, it is possible to set both the signal SEL1 and the signal SEL2 to a low level. In this case, both the voltage of the node n1 and the voltage of the node n2 can be increased. Therefore, both the transistor 101_1 and the transistor 101_2 turn on, so the wiring 112 and the wiring 111 are connected by the transistor 101_1 and transistor 101_2 are turned on in parallel. Thus, signal O The fall time or rise time of UT can be shortened.

[0214] Note that the channel width of transistor 301_1 and the channel width of transistor 301_2 are preferably approximately equal. In this way, by making the transistor sizes approximately equal the current supply capabilities can be made approximately equal. Or, the degree of deterioration of the transistors can be made approximately equal. Thus, the voltage at node n1 and the voltage at node n2 can be made approximately equal, so the waveform of signal OUT can be made approximately equal Note that for the same reason, the channel length of transistor 301_1 and the channel length of transistor 301_2 are preferably approximately equal. However, it is not limited to this

[0215] Note that the channel width of transistor 301_1 and the channel width of transistor 301_2 are preferably 500 μm to 3000 μm. More preferably, it is preferably 800 μm to 2500 μm. Even more preferably, it is preferably 1000 μm to 2000 μm However, it is not limited to this.

[0216] Note that the channel width of transistor 302_1 and the channel width of transistor 302_2 are preferably approximately equal. In this way, by making the transistor sizes approximately equal the current supply capabilities can be made approximately equal. Or, the degree of deterioration of the transistors can be made approximately equal. Thus, the voltage at node n1 and the voltage at node ​Since the voltage of dn2 can be made approximately equal, the waveform of signal OUT can be made approximately equal. For the same reason, the channel lengths of transistor 302_1 and transistor 302_2 are preferably approximately equal. However, this is not limited thereto.

[0217] In addition, the channel width of transistor 302_1 is preferably larger than the channel width of transistor 301_2. Thus, in period A2, the voltage of node n1 can be set to a low value ( for example, V1). Preferably, the channel width of transistor 302_1 is preferably approximately 10 times or less the channel width of transistor 301_2. More preferably, it is preferably 7 times or less. Even more preferably, it is preferably 3 times or less. However, this is not limited thereto.

[0218] In addition, the channel width of transistor 302_2 is preferably larger than the channel width of transistor 301_1. Thus, in period A1, the voltage of node n2 can be set to a low value ( for example, V1). Preferably, the channel width of transistor 302_2 is preferably approximately 10 times or less the channel width of transistor 301_1. More preferably, it is preferably 7 times or less. Even more preferably, it is preferably 3 times or less. However, this is not limited thereto.

[0219] In addition, the channel widths of transistor 301_1 and transistor 301_2 are preferably 600 μm to 3500 μm. More preferably, 1000 μm to It is preferably 3000 μm. More preferably, it is preferably in the range of 1500 μm to 2500 μm. However, it is not limited thereto.

[0220] In addition, in the configuration described in FIG. 14(A), as shown in FIG. 14(B), the first terminal of transistor 3 02_1 and the first terminal of transistor 302_2 can be connected to different wirings. In an example of FIG. 14(B), wiring 118 is divided into a plurality of wirings such as wiring 118A to 118B. Then, the first terminal of transistor 302_1 is connected to wiring 118B, and the first terminal of transistor 302_2 is connected to wiring 118A. However, it is not limited thereto. Note that wirings 118A to 118B can have the same function as wiring 118. Therefore, signals such as signal CK1 can be input to wirings 118A to 118B. However, it is not limited thereto. For example, different voltages or different signals can be supplied to wirings 11 8A to 118B.

[0221] In addition, in the configuration described in FIGS. 14(A) to (B), as shown in FIG. 14(C), transistor 302_1 can be replaced with diode 302a_1 having one terminal connected to node n2 and the other terminal connected to wiring 116_1. Similarly, transistor 302_2 can be replaced with diode 302a_2 having one terminal connected to node n1 and the other terminal connected to wiring 116_2. For example, diode 3 02a_1 has a function of controlling whether to turn off transistor 101_2 by becoming in a conductive state or a non-conductive state. Or diode 302a_2 is in a conductive state or non- conductive state. However, it is not limited thereto. has a function of controlling whether to turn off the transistor 101_1 by becoming conductive. Or the diode 302a_1 has a function of controlling whether to turn off the diode 101a_2 (shown in FIG. 1(E)) by becoming conductive or non-conductive. Or the diode 302a_2 has a function of controlling whether to turn off the diode 101a_1 (shown in FIG. 1(E)) by becoming conductive or non-conductive. However, it is not limited to this. For example, in the configuration described in FIGS. 14(A) to (B), as shown in FIG. 14(D), the first terminal of the transistor 302_1 is connected to the wiring 116_1, and the gate of the transistor 302_1 is connected to the node n2, so that the transistor 302_1 can be configured as a diode-connected transistor. Similarly, the first terminal of the transistor 302_2 is connected to the wiring 116_2, and the gate of the transistor 302_2 is connected to the node n1, so that the transistor 302_2 can be configured as a diode-connected transistor. Moreover, in the configuration described in FIGS. 14(A) to (D), as shown in FIG. 14(E), the first terminal of the transistor 302_1 can be connected to the wiring 116_2. Or the first terminal of the transistor 302_2 can be connected to the wiring 116_1. By doing so, during the period when the transistor 302_1 is turned off, a high-level signal can be supplied to the first terminal. Or during the period when the transistor 302_2 is turned off, a high-level signal can be supplied to the first terminal. Therefore, a reverse bias can be applied to the transistor.

[0222] ​​​​​​​​​​​​​​​​​ The deterioration of the characteristics can be alleviated. However, it is not limited to this.

[0223] In addition, in the configuration described in FIGS. 14(A) to (E), as shown in FIG. 18(A), the first terminal of the transistor 301_1 and the first terminal of the transistor 301_2 can be connected to separate wirings. In an example of FIG. 18(A), the wiring 115 can be divided into a plurality of wirings such as wirings 115A to 115B. In this case, as an example, the wiring 115A can be connected to one of the wirings 119A and 119B shown in FIG. 6(G), and the wiring 1 15B can be connected to the other of the wirings 119A and 119B. However , it is not limited to this. Note that the wirings 115A to 115B can have the same function as the wiring 115. Therefore, signals such as the signal SP can be input to the wirings 115A to 115B. However, it is not limited to this. For example, different voltages or different signals can be supplied to the wirings 115A to 115 B.

[0224] In addition, in the configuration described in FIGS. 14(A) to (E) and FIG. 18(A), as shown in FIG. 18(B), the gates of the transistor 301_1 and the gates of the transistor 301_2 can be connected to the wiring 114. However, it is not limited to this. For example, the gates of the transistor 301_1 and the gates of the transistor 301_2 can be connected to the wiring 113. As another example, when the gates of the transistor 301_1 and the gates of the transistor 301_2 are connected to the wiring 115, the first terminal of the transistor 301_ 1 and the first terminal of the transistor 301_2 are the wiring 113 or the wiring 1 14. It can be connected to 14.

[0225] In addition, in the configurations described in FIGS. 14(A) to (E) and FIGS. 18(A) to (B), FIG. 18 (C) to (D), as shown, the circuit 300 can have a plurality of transistors such as transistors 303_1 to 303_2. Transistors 303_1 to 303_2 Preferably have the same polarity as transistors 301_1 to 301_2, and are often of the N-channel type. However, it is not limited to this, and transistors 303_1 to 303_2 can be of the P-channel type.

[0226] The first terminal of transistor 303_1 is connected to the second terminal of transistor 301_1, the second terminal of transistor 303_1 is connected to node n1, and the gate of transistor 30 3_1 is connected to the second terminal of transistor 301_1. The first terminal of transistor 3 03_2 is connected to the second terminal of transistor 301_2, the second terminal of transistor 30 3_2 is connected to node n2, and the gate of transistor 303_2 is connected to the second terminal of transistor 301_2. However, it is not limited to this.

[0227] Transistor 303_1, as an example, has a function of controlling the timing to make node n1 in a floating state. Or transistor 303_1 has a function of preventing charge leakage from node n1. Or transistor 303_1 has a function of preventing a decrease in the voltage of node n1. Or transistor 303_1 has a function as a rectifying element, a diode, or a transistor having a diode-connected configuration. However, it is not limited to this. ​It is not limited. Note that the transistor 303_1 does not necessarily have all of the above functions. Yes.

[0228] The transistor 303_2 has, for example, a function of controlling the timing to float the node n2. Or, the transistor 303_2 has a function of preventing charge leakage from the node n2. Or, the transistor 303_2 has a function of preventing a decrease in the voltage of the node n2. As described above, the transistor 303_2 has a function as a rectifying element, a diode, or a transistor having a diode-connected configuration, etc. However, it is not limited thereto. Note that the transistor 303_2 does not necessarily have all of the above functions. Yes. No.

[0229] In addition, in the configurations described in FIGS. 14(A) to (E) and FIGS. 18(A) to (D), as shown in FIGS. 18(E) to (F), the second terminal of the transistor 302_1 can be connected to the second terminal of the transistor 3 01_2 and the first terminal of the transistor 303_2. Or, the second terminal of the transistor 302_2 can be connected to the second terminal of the transistor 301_1 and the first terminal of the transistor 303_1. However, it is not limited thereto. Yes. No.

[0230] In addition, in the configurations described in FIGS. 14(A) to (E) and FIGS. 18(A) to (F), as shown in FIGS. 19(A) to (B), the gate of the transistor 303_1 can be connected to the wiring 115. Or, the gate of the transistor 303_2 can be connected to the wiring 115. However, it is not limited thereto. For example, the transistor 303_ Yes. Yes. The gate of transistor 303_1 and transistor 303_2 can be connected to separate wirings. . As another example, the gate of transistor 303_1 and the gate of transistor 303_2 can be connected to wiring 114. As another example, the gate of transistor 303_ 1 can be connected to wiring 116_1, and the gate of transistor 303_2 can be connected to wiring 1 16_2.

[0231] Note that in the configurations described in FIGS. 14(A) to (E), FIGS. 18(A) to (F), and FIGS. 19(A) to (B), as shown in FIGS. 19(C) to (D), transistor 303_1 can be connected to the first terminal side of transistor 301_1. Or, transistor 303_ 2 can be connected to the first terminal side of transistor 301_2. In an example of FIGS. 19(C) to (D), the first terminal of transistor 303_1 is connected to wiring 11 5, the second terminal of transistor 303_1 is connected to the first terminal of transistor 301_1, and the gate of transistor 301_1 is connected to wiring 115. The first terminal of transistor 303_ 2 is connected to wiring 115, the second terminal of transistor 303_2 is connected to the first terminal of transistor 301_2, and the gate of transistor 301_ 2 is connected to wiring 115. However, it is not limited thereto.

[0232] Note that in the configurations described in FIGS. 14(A) to (E), FIGS. 18(A) to (F), and FIGS. 19(A) to (D), as shown in FIG. 19(E), transistor 303_1 can be replaced with resistor element 304 _1. Or, transistor 303_2 can be replaced with resistor element 304 . It is possible to replace it with _2. As the resistance elements 304_1 and 304_2 not only transistors or diodes, but also materials such as transparent electrodes (e.g., pixel electrodes, ITO, IZO) can be used. However, it is not limited to this.

[0233] In addition, in the configurations described in FIGS. 14(A) to (E), FIGS. 18(A) to (F), and FIGS. 19(A) to (E), as shown in FIG. 19(F), a transistor configured in a diode connection can be replaced with a diode. The diodes 301d_1 to 301d_2 have the same functions as the transistors 301_1 to 301_2. The diodes 303d_ 1 to 303d_2 have the same functions as the transistors 303_1 to 303_2. However it is not limited to this. For example, a transistor configured in a diode connection can be replaced with a circuit having a rectifying function. In this case, it is preferable that the circuit has at least one diode or a transistor configured in a diode connection, but it is not limited to this.

[0234] In addition, for example, when a transistor is used as a diode, assume that the transistor is a P-channel type. In this case, as an example, as shown in FIG. 17(C), in the transistors 301p_1 to 301p_2 and the transistors 303p_1 to 303p_2 the gate and the second terminal are often connected. The transistors 301p_1 to 30 1p_2 have the same functions as the transistors 301_1 to 301_2 and are assumed to be P-channel type. The transistors 303p_1 to 303p_2 are the transistors 303_1 ​​​​​It shall have the same functions as ~303_2 and be of P-channel type. However, it is not limited to this. It is not limited thereto.

[0235] In addition, in the configurations described in FIGS. 14(A) to (E), FIGS. 18(A) to (F), FIG. 17(C), and FIGS. 19(A) to (D), as shown in FIG. 20(A), as the transistor, a P-channel type transistor can be used. Transistors 101p_1 to 101p _2 have the same functions as transistors 101_1 to 101_2 and are of P-channel type. Transistors 302p_1 to 302p_2 have the same functions as transistors 302_1 to 302_2 and are of P-channel type. And, as shown in FIG. 20(B), when the polarity of the transistor is of P-channel type, voltage V1 is supplied to wiring 113, and voltage V2 is supplied to wiring 118. Signals CK1, signal CK2, signal SP, signal SEL1, signal SEL2 , signal RE, the voltage of node n1, the voltage of node n2, and signal OUT are noted to be inverted compared with the timing chart of FIG. 2.

[0236] (Embodiment 3) In this embodiment, an example of a semiconductor device will be described. The semiconductor device of this embodiment can be used for the circuit 400 described in Embodiment 2. Note that the contents described in Embodiments 1 to Embodiment 2 are omitted in their descriptions. Note that the contents described in this embodiment can be appropriately combined with the contents described in Embodiments 1 to Embodiment 2.

[0237] First, an example of the circuit 400 will be described with reference to FIG. 21(A). In one example of FIG. 21(A), the circuit 400 includes a circuit 600, a plurality of It has a transistor and transistor 402. Transistors 401_1, 401_2, and transistor 402 preferably have the same polarity as transistors 101_1 to 101_2 and are N-channel type. However, it is not limited to this. Transistors 401_1, 401_2, and transistor 402 can be P-channel type. Note that circuit 400 does not necessarily have all of these transistors, and it is possible to omit some of these transistors. Preferably, they have the same polarity as transistors 101_1 to 101_2 and are N-channel type. However, it is not limited to this. Transistors 401_1, 401_2, and transistor 402 can be P-channel type. Note that circuit 400 does not necessarily have all of these transistors, and it is possible to omit some of these transistors. The first terminal of transistor 401_1 is connected to wiring 118, and the second terminal of transistor 401_1 is connected to node n1. The first terminal of transistor 401_2 is connected to wiring 118, and the second terminal of transistor 401_2 is connected to node n2. The first terminal of transistor 402 is connected to wiring 118, and the second terminal of transistor 402 is connected to wiring 111. Circuit 600 is connected to wiring 111, wiring 114, wiring 118, node n1, node n2, the gate of transistor 401_1, the gate of transistor 401_2, and / or the gate of transistor 402. However, it is not limited to this.

[0238] For example, circuit 600 can be connected to various other wirings or various other nodes according to its configuration. Or, circuit 600 does not necessarily have to be connected to all of the above-mentioned wirings, and it is possible not to be connected to any of the above-mentioned wirings. The first terminal of transistor 401_1 is connected to wiring 118, and the second terminal of transistor 401_1 is connected to node n1. The first terminal of transistor 401_2 is connected to wiring 118, and the second terminal of transistor 401_2 is connected to node n2. The first terminal of transistor 402 is connected to wiring 118, and the second terminal of transistor 402 is connected to wiring 111. Circuit 600 is connected to wiring 111, wiring 114, wiring 118, node n1, node n2, the gate of transistor 401_1, the gate of transistor 401_2, and / or the gate of transistor 402. However, it is not limited to this. For example, circuit 600 can be connected to various other wirings or various other nodes according to its configuration. Or, circuit 600 does not necessarily have to be connected to all of the above-mentioned wirings, and it is possible not to be connected to any of the above-mentioned wirings. For example, circuit 600 can be connected to various other wirings or various other nodes according to its configuration. Or, circuit 600 does not necessarily have to be connected to all of the above-mentioned wirings, and it is possible not to be connected to any of the above-mentioned wirings. Note that the connection point between the gate of transistor 401_1 and circuit 600 is shown as node m1.

[0239] Note that the connection point between the gate of transistor 401_1 and circuit 600 is shown as node m1. ​The connection point between the gate of transistor 401_2 and circuit 600 is denoted as node m2, and the connection point between the gate of transistor 402 and circuit 600 is denoted as node k.

[0240] Note that transistor 401_1, as an example, has a function of controlling the conduction state between wiring 118 and node n1. Or, transistor 401_1 has a function of controlling the timing of supplying the voltage of wiring 118 to node n1. For example, when a signal or voltage (such as signal CK2 or voltage V1, etc.) is supplied to wiring 118, transistor 401_1 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 118 to node n1. Or, transistor 401_1 has a function of controlling the timing of supplying a low-level signal or voltage V 1 to node n1. Or, transistor 4 01_1 has a function of controlling the timing of decreasing or maintaining the voltage of node n1. As described above, transistor 401_1 can have a function as a switch. However, it is not limited to this. Note that transistor 401_1 does not necessarily have all of the above functions.

[0241] Note that transistor 401_2, as an example, has a function of controlling the conduction state between wiring 118 and node n2. Or, transistor 401_2 has a function of controlling the timing of supplying the voltage of wiring 118 to node n2. For example, when a signal or voltage (such as signal CK2 or voltage V1, etc.) is supplied to wiring 118, transistor 401_2 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 118 to node n2. It has a function of controlling. Or, transistor 401_2 has a function of controlling the timing of supplying a low-level signal or voltage V 1 to node n2. Or, transistor 4 01_2 has a function of controlling the timing of decreasing or maintaining the voltage of node n2 . As described above, transistor 401_2 can have a function as a switch . However, it is not limited thereto. Note that transistor 401_2 does not necessarily have all of the above functions .

[0242] Note that transistor 402, as an example, has a function of controlling the conduction state between wiring 118 and wiring 111 . Or, transistor 402 has a function of controlling the timing of supplying the voltage of wiring 118 to wiring 111 . For example, when a signal or voltage (such as signal CK2 or voltage V1) is supplied to wiring 118, transistor 402 has a function of controlling the timing of supplying the signal or voltage supplied to wiring 11 8 to wiring 111 . Or, transistor 402 has a function of controlling the timing of supplying a low-level signal or voltage V1 to wiring 111 . Or, transistor 402 has a function of controlling the timing of decreasing or maintaining the voltage of wiring 11 1. As described above, transistor 402 can have a function as a switch . However, it is not limited thereto. Note that transistor 402 does not necessarily have all of the above functions .

[0243] Circuit 600, as an example, according to the voltage of node n1, the voltage of node n2, and / or the voltage of wiring 1 11, the voltage of node m1, the voltage of node m2, and / or the voltage of node k It has a function of controlling pressure. Or, circuit 600 has a function of controlling the timing of supplying a high-level signal, a low-level signal, voltage V1, voltage V2, etc. to node k. Or, circuit 600 has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions. It has a function of controlling the timing of supplying a high-level signal, a low-level signal, voltage V1, voltage V2, etc. to node k. Or, circuit 600 has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions. It has a function of controlling the timing of supplying a high-level signal, a low-level signal, voltage V1, voltage V2, etc. to node k. Or, circuit 600 has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions. It has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions. It has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions. It has a function of controlling the timing of increasing, decreasing, or maintaining the voltage of node m1, the voltage of node m2, and / or the voltage of node k. However, it is not limited to this. Note that circuit 600 does not necessarily have all of the above functions.

[0244] Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings. Next, an example of the operation of the semiconductor device in Fig. 21(A) will be described with reference to the timing chart in Fig. 21(B). The timing chart in Fig. 21(B) shows an example of signal SEL1, signal SEL2, signal CK1, signal CK2, signal SP, signal RE, the voltage (Va1) of node n1, the voltage (Va2) of node n2, the voltage (Vb1) of node m1, the voltage (Vb2) of node m2, the voltage (Vc) of node k, and signal OUT. Note that the semiconductor device in Fig. 21(A) is not limited to the timing chart in Fig. 21(B) and can be controlled by various timings.

[0245] During period A1, as shown in Fig. 22(A), circuit 300 supplies a high-level signal or voltage V2 to node n1, so the voltage of node n1 increases to V1 + Vth101_1 + Vx. At this time, Vx is a value greater than 0. Circuit 300 supplies a low-level signal or voltage V1 to node n2, so the voltage of node n2 decreases. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 600 During period A1, as shown in Fig. 22(A), circuit 300 supplies a high-level signal or voltage V2 to node n1, so the voltage of node n1 increases to V1 + Vth101_1 + Vx. At this time, Vx is a value greater than 0. Circuit 300 supplies a low-level signal or voltage V1 to node n2, so the voltage of node n2 decreases. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 600 During period A1, as shown in Fig. 22(A), circuit 300 supplies a high-level signal or voltage V2 to node n1, so the voltage of node n1 increases to V1 + Vth101_1 + Vx. At this time, Vx is a value greater than 0. Circuit 300 supplies a low-level signal or voltage V1 to node n2, so the voltage of node n2 decreases. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 600 During period A1, as shown in Fig. 22(A), circuit 300 supplies a high-level signal or voltage V2 to node n1, so the voltage of node n1 increases to V1 + Vth101_1 + Vx. At this time, Vx is a value greater than 0. Circuit 300 supplies a low-level signal or voltage V1 to node n2, so the voltage of node n2 decreases. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 600 During period A1, as shown in Fig. 22(A), circuit 300 supplies a high-level signal or voltage V2 to node n1, so the voltage of node n1 increases to V1 + Vth101_1 + Vx. At this time, Vx is a value greater than 0. Circuit 300 supplies a low-level signal or voltage V1 to node n2, so the voltage of node n2 decreases. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 600 As an example, according to these voltages (the voltage of node n1, the voltage of node n2, and the voltage of wiring 111 ), a low-level signal or voltage V1 is supplied to node m1, a high-level signal or voltage V2 is supplied to node m2, and a high-level signal or voltage V2 is supplied to node k . Thus, since transistor 401_1 turns off, wiring 118 and node n 1 are in a non-conductive state. Since transistor 401_2 turns on, wiring 118 and node n d2 are in a conductive state. Thus, voltage V1 is supplied from wiring 118 to node n2 through transistor 401_ 2. Since transistor 402 turns on, wiring 118 and wiring 111 are in a conductive state. Thus, voltage V1 is supplied from wiring 118 to wiring 111 through transistor 4 02. However, it is not limited thereto. For example, circuit 60 0 can supply a low-level signal or voltage V1 to node m2 and / or node k . Thus, since transistor 401_2 can turn off, wiring 118 and node n2 can be in a non-conductive state. Or, since transistor 40 2 can turn off, wiring 118 and wiring 111 can be in a non-conductive state .

[0246] During period B1, as shown in FIG. 22(B), by the bootstrap operation, the voltage of node n1 rises to V2 + Vth101_1+Vx. Since circuit 300 supplies a low-level signal or voltage V1 to node n2, the voltage of node n2 is maintained at a low value (e.g., V1 ). Also, since a high-level signal CK1 is supplied to wiring 111, the voltage of wiring 1 11 rises. Circuit 600 supplies these voltages (the voltage of node n1, the voltage of node n2 According to the voltage (and the voltage of wiring 111), a low-level signal or voltage V1 is supplied to node m 1, a high-level signal or voltage V2 is supplied to node m2, and a low-level signal or voltage V1 is supplied to node k. Thus, transistor 401_1 turns off, and wiring 118 and node n1 become non-conductive. Transistor 401_2 turns on, and wiring 118 and node n2 become conductive. Thus, voltage V1 is supplied from wiring 118 to node n2 through transistor 401_2. Transistor 402 turns off, so wiring 118 and wiring 111 become non-conductive. However, it is not limited to this . For example, circuit 600 can supply a low-level signal or voltage V1 to node m2. Thus, transistor 401_2 can turn off, so wiring 11 8 and node n2 can become non-conductive.

[0247] During periods C1 to E1, as shown in FIGS. 22(C) and 23(A), a low-level signal or voltage V1 is supplied to node n1, node n2, and wiring 111. Therefore, the voltage of node n1, the voltage of node n2, and the voltage of wiring 111 decrease or are maintained at a low value (e.g., V1). Circuit 600, as an example, supplies a high-level signal or voltage V2 to node m1, a high-level signal or voltage V2 to node m2, and a high-level signal or voltage V2 to node k according to these voltages (the voltage of node n1, the voltage of node n2, and the voltage of wiring 111). Thus, transistor 401_1 turns on, so wiring 118 and node n1 become conductive. Thus, voltage V2 is supplied from wiring 11 to node n1 through transistor 401_1. It is supplied from 8 to node n1 via transistor 401_1. Transistor 401_ 2 is turned on, so wiring 118 and node n2 are in a conductive state. Therefore, voltage V1 is supplied from wiring 118 to node n2 via transistor 401_2. The transist tor 402 is turned on, so wiring 118 and wiring 111 are in a conductive state. Therefore, voltage V1 is supplied from wiring 118 to wiring 111 via transistor 402. However, it is not limited to this. For example, circuit 600 can supply a low-level signal or voltage V1 to node m 1, node m2, and / or node k. Therefore, since transistor 401_1 can be turned off, wiring 118 and node n1 can be in a non-conductive state . Or, since transistor 401_2 can be turned off, wiring 118 and node n2 can be in a non-conductive state . Or, since transistor 402 can be turned off, wiring 118 and wiring 111 can be in a non-conductive state . In addition, in one of period E1 and period D1, circuit 600 supplies a high-level signal or voltage V2 to node m1, node m2, and / or node k, and in the other period, circuit 600 can supply a low-level signal or voltage V1 to node m1, node m2, and / or

[0248] node k. By doing so, the time or number of times each transistor is turned on is reduced, so the deterioration of the transistor can be suppressed . In period A2, as shown in FIG. 23(B), circuit 300 outputs a low-level signal or voltage as shown in FIG. 23(B). Circuit 300 can supply a low-level signal or voltage or voltage V1 to node m1, node m2, and / or node k. By doing so, the time or number of times each transistor is turned on is reduced, so the deterioration of the transistor can be suppressed .

[0249] In period A2, as shown in FIG. 23(B), circuit 300 outputs a low-level signal or voltage Since V1 is supplied to node n1, the voltage of node n1 decreases. Circuit 300 supplies a high-level signal or voltage V2 to node n2, so the voltage of node n2 increases and becomes V1 + Vth101_2 + Vx. At this time, Vx is a value greater than 0. Also, since a low-level signal CK1 is supplied to wiring 111, the voltage of wiring 111 decreases. Circuit 60 0 supplies, as an example, a high-level signal or voltage V2 to node m1, a low-level signal or voltage V1 to node m2, and a high-level signal or voltage V2 to node k according to these voltages (the voltage of node n1, the voltage of node n2, and the voltage of wiring 11 1). Thus, transistor 401_1 turns on, and wiring 118 and node n1 become conductive. Therefore, voltage V1 is supplied from wiring 118 to node n1 through transistor 401_1. Transistor 401_2 turns off, so wiring 11 8 and node n2 become non-conductive. Transistor 402 turns on, so wiring 11 8 and wiring 111 become conductive. Therefore, voltage V1 is supplied from wiring 118 to wiring 111 through transistor 402. However, it is not limited to this. For example, circuit 6 00 can supply a low-level signal or voltage V1 to node m1 and / or node k . Thus, transistor 401_1 can turn off, so wiring 118 and node n1 can become non-conductive. Or, since transistor 4 02 can turn off, wiring 118 and wiring 111 can become non-conductive.

[0250] During period B2, as shown in FIG. 23(C), circuit 300 supplies a low-level signal or voltage ​Since V1 is supplied to node n1, the voltage of node n1 is maintained at a low value (e.g., V1). By the bootstrap operation, the voltage of node n2 rises to V2 + Vth101_ 2 + Vx. Also, since a high-level signal CK1 is supplied to wiring 111, the voltage of wiring 1 11 rises. Circuit 600 supplies, as an example, a high-level signal or voltage V 2 to node m1, a low-level signal or voltage V1 to node m2, and a low-level signal or voltage V1 to node k according to these voltages (the voltage of node n1, the voltage of node n2, and the voltage of wiring 111). Thus, transistor 401_1 turns on so that wiring 118 and node n1 are in a conductive state. Thus, voltage V1 is supplied from wiring 1 18 to node n1 through transistor 401_1. Transistor 401 _2 turns off so that wiring 118 and node n2 are in a non-conductive state. Transistor 4 02 turns off so that wiring 118 and wiring 111 are in a non-conductive state. However, it is not limited to this. For example, circuit 600 can supply a low-level signal or voltage V1 to node m1. Thus, transistor 401_1 can turn off and wiring 118 and node n1 can be in a non-conductive state. During period C2 to E2, as shown in FIGS. 24(A) and 24(B), since a low-level signal or voltage V1 is supplied to node n1, node n2, and wiring 111, the voltage of node n1, the voltage of node n2, and the voltage of wiring 111 decrease or are maintained at a low value (e.g.,

[0251] V1). Circuit 600 supplies, as an example, these voltages (the voltage of node n1, node n2, and wiring 111). node n2, and wiring 111 decrease or are maintained at a low value (e.g., V1). Circuit 600 supplies, as an example, these voltages (the voltage of node n1, node According to the voltage of node n2 and the voltage of wiring 111, a high-level signal or voltage V2 is supplied to node m1, a high-level signal or voltage V2 is supplied to node m2, and a high-lev el signal or voltage V2 is supplied to node k. Therefore, transistor 401_1 turns on , and wiring 118 and node n1 are in a conductive state. Therefore, voltage V2 is supplied from wiring 11 8 to node n1 via transistor 401_1. Since transistor 401_ 2 turns on, wiring 118 and node n2 are in a conductive state. Therefore, voltage V1 is supplied from wiring 118 to node n2 via transistor 401_2. Since transistor 402 turns on , wiring 118 and wiring 111 are in a conductive state. Therefore, voltage V1 is supplied from wiring 118 to wiring 111 via transistor 402. However, it is not limited to this. For example, circuit 600 can supply a low-level signal or voltage V1 to node m 1, node m2, and / or node k. Therefore, since transistor 401_1 can turn off , wiring 118 and node n1 can be in a non-conductive state . Or, since transistor 401_2 can turn off , wiring 118 and node n2 can be in a non-conductive state. Or, since transistor 402 can turn off , wiring 118 and wiring 111 can be in a non-conductive state .

[0252] In addition, in one of period E2 and period D2, circuit 600 supplies a high-level signal or voltage V2 to node m1, node m2, and / or node k, and in the other period , circuit 600 supplies a low-level signal or voltage V1 to node m1, node m2, and / or Or it can be supplied to node k. By doing so, since the time or number of times the transistor turns on is reduced, deterioration of the transistor can be suppressed. The time or number of times the transistor turns on is reduced, so deterioration of the transistor can be suppressed.

[0253] Note that the channel width of transistor 401_1 and the channel width of transistor 401_2 are preferably approximately equal. In this way, the change in the voltage of node n1 during period T1 and the change in the voltage of node n2 during period T2 can be made approximately equal. Thus, the waveform of signal OUT can be made approximately equal. For the same reason, the channel length of transistor 401_1 and the channel length of transistor 401_2 are preferably approximately equal. However, it is not limited to this.

[0254] Note that the channel width of transistor 401_1 and the channel width of transistor 401_2 are preferably 100 μm to 4000 μm. More preferably, it is preferably 500 μm to 30 00 μm. Even more preferably, it is preferably 1000 μm to 2000 μm. However, it is not limited to this.

[0255] Note that the channel width of transistor 402 is preferably 500 μm to 5000 μm. More preferably, it is preferably 1000 μm to 3000 μm. Even more preferably, it is preferably 2000 μm to 3000 μm. However, it is not limited to this.

[0256] Note that in the configuration described in FIG. 21(A), as shown in FIG. 25(A), a plurality of transistors can be connected in parallel. And the plurality of transistors are It is possible to turn on either sequentially or randomly. As an example, FIG. 25(A) shows a configuration in which two transistors are connected in parallel. In this case, the two transistors can repeat turning on and off every one gate selection period or every half cycle of the clock signal. In transistors 401_1, 401_2, and 4 02, transistors 411_1 to 411_2 and transistor 412 are connected in parallel respectively. The first terminal of transistor 411_1 is connected to wiring 118 , the second terminal of transistor 411_1 is connected to node n1, and the gate of transistor 411_1 is connected to circuit 600. The first terminal of transistor 411_2 is connected to wiring 118, the second terminal of transistor 411_2 is connected to node n2 , and the gate of transistor 411_2 is connected to circuit 600. The first terminal of transistor 412 is connected to wiring 118, the second terminal of transistor 412 is connected to wiring 111 , and the gate of transistor 412 is connected to circuit 600. However, it is not limited to this. For example, it is possible to add only any one of transistors 411_1 to 411_2 and transistor 412.

[0257] Note that in FIG. 25(A), by omitting transistors 401_1, 411_1, tra nsistors 401_2, and 411_2, circuit 400 can have only circuit 600, transistor 402, and transistor 412. Or, in FIG. 25(A), by omitting transistors 401_1, 411 _1, transistor 402, and transistor 412, circuit 40 It is possible to have only the circuit 600, the transistor 401_2, and the transistor 411_2. Alternatively, in FIG. 25(A), by omitting the transistor 401_2, the transistor 411_2, the transistor 402, and the transistor 412, the circuit 400 can have only the circuit 600, the transistor 401_1, and the transistor 411_1. However, it is not limited to this.

[0258] In FIG. 25(A), the channel width of the transistor 401_1 is preferably substantially equal to the channel width of the transistor 411_1. The channel width of the transistor 401_2 is preferably substantially equal to the channel width of the transistor 411_2. The channel width of the transistor 402 is preferably substantially equal to the channel width of the transistor 412. Therefore, for example, the channel width of the transistor 411_1 and the channel width of the transistor 411_2 are preferably 100 μm to 4000 μm. More preferably, they are preferably 500 μm to 3000 μm. Even more preferably, they are preferably 1000 μm to 2000 μm. The channel width of the transistor 412 is preferably 500 μm to 5000 μm. More preferably, it is preferably

[0259] 1000 μm to 3000 μm. Even more preferably, it is preferably 2000 μm to 3000 μm. However, it is not limited to this. The gate of 411_1 can be connected to wiring 113. Or, the first terminal of transistor 411_2 is connected to wiring 115_2, and the gate of transistor 411_2 can be connected to wiring 113. Or, the gate of transistor 412 can be connected to wiring 113. By doing so, the circuit for controlling the conduction states of transistors 411_1 to 411_2 and transistor 412 can be omitted. However, it is not limited to this. For example, the second terminal of transistor 401_1, the second terminal of transistor 401_2, and / or the second terminal of transistor 402 can be connected to wiring 113. By doing so, a reverse bias can be applied to the transistor, so that the characteristic degradation of the transistor can be suppressed.

[0260] In addition, in the configurations described in FIGS. 21(A) and 25(A) to (B), as shown in FIG. 26(A), the gates of transistors 401_1 to 401_2 and the gate of transistor 402 can be connected to each other. Note that the connection points between the gates of transistors 401_1 to 401_2 and the gate of transistor 402 and circuit 600 are shown as node j. In this case, circuit 600 can supply a low-level signal or voltage V1 to node j in periods A1 to B1 and periods A2 to B2. On the other hand, circuit 600 can supply a high-level signal or voltage V2 to node j in periods C1 to E1 and periods C2 to E2. Therefore, transistors 401_1, transistor 401_2, and transistor 402 are in It can turn off and can turn on during period C1 to E1 and period C2 to E2. In this way, the circuits for controlling the conduction states of transistor 401_1, transistor 401_2, and transistor 4 02 can be made common, so the circuit scale can be simplified. However, it is not limited to this. For example, circuit 600 can supply a low-level signal or voltage V1 to node j in one of period D1 and period E1, and one of period D2 and period E2. Or, circuit 600 can supply a low-level signal or voltage V1 to node j in one of period C1 to E1 and period C2 to E2. By doing so, the transistor can repeat turning on and off every one gate selection period or every one frame, so the deterioration of the transistor characteristics can be suppressed. As another example, as shown in FIG. 26(B), the gate of transistor 402 can be connected to only one of the gate of transistor 401_1 and the gate of transistor 401_2.

[0261] In addition, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (B), as shown in FIG. 26(C), the first terminal of transistor 401_1, the first terminal of transistor 401_2, and the first terminal of transistor 402 can be connected to separate wirings. In FIG. 26(A), as an example, wiring 118 is divided into a plurality of wirings such as wiring 118C to 118F. And circuit 600 is connected to wiring 118C, the first terminal of transistor 401_1 is connected to wiring 118D, the first terminal of transistor 4 01_2 is connected to wiring 118E, and the first terminal of transistor 402 is connected to wiring 118F. is connected to wiring 118F. However, it is not limited thereto. Note that wirings 118C to 11 8F can have the same function as wiring 118. Therefore, a voltage such as voltage V1 can be input to wirings 118C to 1 18F. However, it is not limited thereto. For example, different voltages or different signals can be supplied to wirings 118C to 118F .

[0262] Note that in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(A), transistor 401_1 can be replaced with diode 401a_1 in which one terminal (hereinafter also referred to as the positive electrode ) is connected to node n1 and the other terminal (hereinafter also referred to as the negative electrode) is connected to node m1. Alternatively, transistor 401_2 can be replaced with diode 401a_2 in which one terminal (hereinafter also referred to as the positive electrode ) is connected to node n2 and the other terminal (hereinafter also referred to as the negative electrode) is connected to node m2. Alternatively, transistor 402 can be replaced with diode 402a in which one terminal (hereinafter also referred to as the positive electrode ) is connected to wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to node k. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 , and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and transistor 401_2 's second terminal is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 , and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 and the second terminal of transistor 401_1 is connected to node n1, whereby transistor 401_1 can be configured to be diode-connected. Alternatively, the first terminal of transistor 401_2 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1 is connected to node m2, and the second terminal of transistor 401_2 is connected to node n2, whereby transistor 401_2 can be configured to be diode-connected. Alternatively, the first terminal of transistor 402 is connected to wiring 111, and the second terminal of transistor 402 is connected to node k, whereby transistor 402 can be configured to be diode-connected. However, it is not limited thereto. For example, in the configurations described in FIGS. 21(A), 25(A) to (B), and 26(A) to (C), as shown in FIG. 27(B), the first terminal of transistor 401_1 is connected to node m1​ By connecting the second terminal of to node n2, transistor 401_2 can be configured in a diode-connected configuration. The first terminal of transistor 402 is connected to node k, and by connecting the second terminal of transistor 402 to wiring 111, transistor 402 can be configured in a diode-connected configuration.

[0263] Next, a specific example of circuit 600 will be described with reference to FIG. 28(A). Circuit 600 includes circuits 601_1 to 601_2 and circuit 602. Circuits 601_1 to 601_2 and circuit 602 can, for example, function as a NOT circuit or an inverter. The input terminal of circuit 601_1 is connected to node n1, and the output terminal of circuit 601_1 is connected to node m1. The input terminal of circuit 601_2 is connected to node n2, and the output terminal of circuit 601_2 is connected to node m2. The input terminal of circuit 602 is connected to wiring 111, and the output terminal of circuit 602 is connected to node k.

[0264] Another example of circuit 600 will be described with reference to FIG. 28(B). Circuit 600 includes circuit 6 03. Circuit 603 can, for example, function as a two-input NOR circuit. One input terminal of circuit 603 is connected to node n1, and the other input terminal of circuit 603 is connected to node n2, and the output terminal of circuit 603 is connected to node j.

[0265] Another example of circuit 600 will be described with reference to FIG. 28(C). Circuit 600 includes circuits 6 11_1 to 611_2 and circuit 612. Circuits 611_1 to 611_2 and The path 612 can, for example, have the function as a logic circuit combining a 2 - input AND circuit and a NOT circuit. One input terminal of the circuit 611_1 is connected to the wiring 113, the other input terminal of the circuit 611_1 is connected to the node n1, and the output terminal of the circuit 611_1 is connected to the node m1. One input terminal of the circuit 611_2 is connected to the wiring 113, the other input terminal of the circuit 611_2 is connected to the node n2, and the output terminal of the circuit 611_2 is connected to the node m2. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k. For another example of the circuit 600, refer to FIG. 28(D) for description. The circuit 600 has a circuit 613. The circuit 613 can have the function as a logic circuit combining a 3 - input AND circuit and a NOT circuit. The first input terminal of the circuit 613 is connected to the wiring 113, the second input terminal of the circuit 613 is connected to the node n1, the third input terminal of the circuit 613 is connected to the node n2, and the output terminal of the circuit 613 is connected to the node j. For another example of the circuit 600, refer to FIG. 28(E) for description. The circuit 600 has circuits 621_1 to 621_2 and a circuit 622. The circuits 621_1 to 621_2 and the circuit 622 can, for example, have the function as 2 - input NOR circuits. One input terminal of the circuit 621_1 is connected to the wiring 113, the other input terminal of the circuit 621_1 is connected to the node n1, and the output terminal of the circuit 621_1 is connected to the node m1. One input terminal of the circuit 611_2 is connected to the wiring 113, the other input terminal of the circuit 611_2 is connected to the node n2, and the output terminal of the circuit 611_2 is connected to the node m2. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k. One input terminal of the circuit 611_2 is connected to the wiring 113, the other input terminal of the circuit 611_2 is connected to the node n2, and the output terminal of the circuit 611_2 is connected to the node m2. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k. One input terminal of the circuit 612 is connected to the wiring 113, the other input terminal of the circuit 612 is connected to the wiring 111, and the output terminal of the circuit 612 is connected to the node k.

[0266] For another example of the circuit 600, refer to FIG. 28(D) for description. The circuit 600 has a circuit 613. The circuit 613 can have the function as a logic circuit combining a 3 - input AND circuit and a NOT circuit. The first input terminal of the circuit 613 is connected to the wiring 113, the second input terminal of the circuit 613 is connected to the node n1, the third input terminal of the circuit 613 is connected to the node n2, and the output terminal of the circuit 613 is connected to the node j. For another example of the circuit 600, refer to FIG. 28(D) for description. The circuit 600 has a circuit 613. The circuit 613 can have the function as a logic circuit combining a 3 - input AND circuit and a NOT circuit. The first input terminal of the circuit 613 is connected to the wiring 113, the second input terminal of the circuit 613 is connected to the node n1, the third input terminal of the circuit 613 is connected to the node n2, and the output terminal of the circuit 613 is connected to the node j. For another example of the circuit 600, refer to FIG. 28(D) for description. The circuit 600 has a circuit 613. The circuit 613 can have the function as a logic circuit combining a 3 - input AND circuit and a NOT circuit. The first input terminal of the circuit 613 is connected to the wiring 113, the second input terminal of the circuit 613 is connected to the node n1, the third input terminal of the c...

Claims

1. The first to tenth transistors are included, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; a gate electrode of the second transistor is always electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the sixth transistor; one of a source electrode or a drain electrode of the sixth transistor is always electrically connected to one of a source electrode or a drain electrode of the seventh transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to a second power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to a third signal line; a gate electrode of the seventh transistor is always electrically connected to the third signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to a gate electrode of the sixth transistor; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the clock signal line; a gate electrode of the eighth transistor is always electrically connected to the clock signal line; one of a source electrode and a drain electrode of the ninth transistor is always electrically connected to a gate electrode of the sixth transistor; a gate electrode of the ninth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the tenth transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the tenth transistor is always electrically connected to the clock signal line; a gate electrode of the tenth transistor is always electrically connected to one of a source electrode or a drain electrode of the seventh transistor; when the other of the source electrode or the drain electrode of the fourth transistor is in a conductive state with the gate electrode of the first transistor at least via a channel formation region of the fourth transistor, a potential at which the first transistor is turned off is input to the gate electrode of the first transistor at least via the channel formation region of the fourth transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off is input to the gate electrode of the first transistor at least via the channel formation region of the fifth transistor, when the other of the source electrode or the drain electrode of the ninth transistor is in a conductive state with the gate electrode of the sixth transistor at least via a channel formation region of the ninth transistor, a potential at which the sixth transistor is turned off is input to the gate electrode of the sixth transistor at least via the channel formation region of the ninth transistor, an area where a first conductive layer functioning as one of a source electrode or a drain electrode of the first transistor overlaps with a second conductive layer functioning as a gate electrode of the first transistor is larger than an area where a third conductive layer functioning as the other of the source electrode or the drain electrode of the first transistor overlaps with the second conductive layer, in a plan view; the first conductive layer has a first region overlapping the second conductive layer and sandwiched between the third conductive layers in a plan view; the third conductive layer has a second region overlapping the second conductive layer and sandwiched between the first conductive layers in a plan view; A semiconductor device, wherein a width of the first conductive layer in the first region is greater than a width of the third conductive layer in the second region.

2. The first to tenth transistors are included, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a first gate signal line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a clock signal line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the first gate signal line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to a first power supply line; a gate electrode of the second transistor is always electrically connected to a second gate signal line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the other of the source electrode and the drain electrode of the third transistor is always electrically connected to a first signal line; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a second signal line; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the fifth transistor is always electrically connected to a gate electrode of the sixth transistor; one of a source electrode or a drain electrode of the sixth transistor is always electrically connected to one of a source electrode or a drain electrode of the seventh transistor; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to a second power supply line; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to a third signal line; a gate electrode of the seventh transistor is always electrically connected to the third signal line; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to a gate electrode of the sixth transistor; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the clock signal line; a gate electrode of the eighth transistor is always electrically connected to the clock signal line; one of a source electrode and a drain electrode of the ninth transistor is always electrically connected to a gate electrode of the sixth transistor; a gate electrode of the ninth transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the tenth transistor is always electrically connected to an output signal line; the other of the source electrode and the drain electrode of the tenth transistor is always electrically connected to the clock signal line; a gate electrode of the tenth transistor is always electrically connected to one of a source electrode or a drain electrode of the seventh transistor; when the other of the source electrode or the drain electrode of the fourth transistor is in a conductive state with the gate electrode of the first transistor at least via a channel formation region of the fourth transistor, a potential at which the first transistor is turned off is input to the gate electrode of the first transistor at least via the channel formation region of the fourth transistor, when the other of the source electrode or the drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor at least via a channel formation region of the fifth transistor, a potential at which the first transistor is turned off is input to the gate electrode of the first transistor at least via the channel formation region of the fifth transistor, when the other of the source electrode or the drain electrode of the ninth transistor is in a conductive state with the gate electrode of the sixth transistor at least via a channel formation region of the ninth transistor, a potential at which the sixth transistor is turned off is input to the gate electrode of the sixth transistor at least via the channel formation region of the ninth transistor, an area where a first conductive layer functioning as one of a source electrode or a drain electrode of the first transistor overlaps with a second conductive layer functioning as a gate electrode of the first transistor is larger than an area where a third conductive layer functioning as the other of the source electrode or the drain electrode of the first transistor overlaps with the second conductive layer, in a plan view; the first conductive layer has a first region overlapping the second conductive layer and sandwiched between the third conductive layers in a plan view; the third conductive layer has a second region overlapping the second conductive layer and sandwiched between the first conductive layers in a plan view; a width of the first conductive layer in the first region is greater than a width of the third conductive layer in the second region; The W / L (W is a channel width, L is a channel length) of the first transistor is larger than the W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; the W / L of the first transistor is greater than the W / L of the fifth transistor; the W / L of the first transistor is greater than the W / L of the sixth transistor; the W / L of the first transistor is greater than the W / L of the seventh transistor; the W / L of the first transistor is greater than the W / L of the eighth transistor; the W / L of the first transistor is greater than the W / L of the ninth transistor; A semiconductor device in which the W / L of the first transistor is larger than the W / L of the tenth transistor.

3. In claim 1 or 2, the first conductive layer is always electrically connected to the gate signal line via a fourth conductive layer; The fourth conductive layer comprises indium, tin, and oxygen.

4. In claim 3, the first conductive layer has a third region overlapping with the fourth conductive layer in a plan view; A semiconductor device, wherein a width of the first conductive layer in the third region is greater than a width of the third conductive layer in the second region.

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