Manufacturing method of semiconductor device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: An insulating film IF1 is formed inside a trench TR and on the upper surface TS of the semiconductor substrate SUB. A field plate electrode FP is formed on the insulating film IF1 so as to fill the inside of the trench TR. A field plate electrode FP is retreated toward the bottom of the trench TR by an etching process. The etching process is performed on the upper surface of the field plate electrode FP using a mixed gas containing CF4 gas and O2 gas. A silicon oxide film is formed on the upper surface of the field plate electrode FP by a thermal oxidation process.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a gate electrode and a field plate electrode inside a trench.

Background Art

[0002] In a semiconductor device including a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure in which a gate electrode is embedded inside a trench is applied. As one type of trench gate structure, a split gate structure is known in which a field plate electrode is formed at the lower part of the trench and a gate electrode is formed at the upper part of the trench. A source potential is supplied from a source electrode to the field plate electrode. By expanding the depletion layer in the drift region by this field plate electrode, it becomes possible to increase the concentration of the drift region, and it becomes possible to reduce the resistance of the drift region.

[0003] For example, Patent Document 1 discloses a MOSFET having a split gate structure. The field plate electrode and the gate electrode of Patent Document 1 are formed as follows. First, after forming a field plate electrode inside the trench, the upper surface of the field plate electrode is recessed. Next, a gate insulating film is formed inside the trench by thermal oxidation treatment, and an insulating film is formed on the upper surface of the field plate electrode. Next, a gate electrode is formed on the field plate electrode so as to fill the inside of the trench.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Inside the trench, a part of the field plate electrode may be formed in a protruding shape. When such a portion exists, the electric field tends to concentrate, and there is a problem that the breakdown voltage between the gate electrode and the field plate electrode deteriorates and a leakage current is likely to occur. Therefore, a technique is required that can ensure the breakdown voltage between the gate electrode and the field plate electrode and improve the reliability of the semiconductor device.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0008] A method for manufacturing a semiconductor device according to an embodiment includes: (a) a step of preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after the step (b), a step of forming a first insulating film inside the trench and on the upper surface of the semiconductor substrate; (d) after the step (c), a step of forming a field plate electrode on the first insulating film so as to fill the inside of the trench; (e) after the step (d), a step of retracting the field plate electrode toward the bottom of the trench by an etching process; (f) after the step (e), a step of performing an etching process using a mixed gas containing CF4 gas and O2 gas on the upper surface of the field plate electrode; (g) after the step (f), a step of forming a first silicon oxide film on the upper surface of the field plate electrode by a first thermal oxidation process.

Effects of the Invention

[0009] According to one embodiment, the reliability of the semiconductor device can be improved.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0012] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane composed of the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0013] (Embodiment 1) <Structure of Semiconductor Device> Hereinafter, the semiconductor device 100 in Embodiment 1 will be described with reference to FIGS. 1 to 5. The semiconductor device 100 includes a MOSFET having a trench gate structure as a semiconductor element. The MOSFET in Embodiment 1 has a split gate structure including a gate electrode GE and a field plate electrode FP.

[0014] The main feature of Embodiment 1 lies in the manufacturing process of performing an etching process using a mixed gas containing CF4 gas and O2 gas on the upper surface of the field plate electrode FP in FIG. 12, and the manufacturing processes before and after it. Details of such features will be described after the description of the "method for manufacturing a semiconductor device" described later.

[0015] FIGS. 1 and 2 are plan views of a semiconductor chip which is the semiconductor device 100. FIGS. 3 and 4 are enlarged principal part plan views of the region 1A shown in FIGS. 1 and 2. FIGS. 2 and 4 show the lower structures of FIGS. 1 and 3, mainly showing the trench gate structure formed in the semiconductor substrate SUB. Also, the positions of the holes CH1, CH2, and CH3 indicated by broken lines in FIG. 3 coincide with the positions of the holes CH1, CH2, and CH3 shown in FIG. 4. FIG. 5 is a cross-sectional view taken along the lines A-A and B-B shown in FIGS. 3 and 4.

[0016] FIG. 1 mainly shows a wiring pattern formed above the semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and an outer peripheral region OR surrounding the cell region CR in a plan view. A plurality of main semiconductor elements such as MOSFETs are formed in the cell region CR. The outer peripheral region OR is used for connecting a gate wiring GW to the gate electrode GE and for functioning as a termination region and the like.

[0017] As shown in FIGS. 1 and 2, most of the cell region CR is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and the gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and the gate wiring GW exposed at the opening become the source pad SP and the gate pad GP. By connecting an external connection member on the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring board, or the like. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clip made of a copper plate.

[0018] As shown in FIG. 4, a plurality of trenches TR are formed in the semiconductor substrate SUB of the cell region CR. The plurality of trenches TR are formed in a stripe shape, each extending in the Y direction and adjacent to each other in the X direction.

[0019] As also shown in the cross-section taken along line A-A of FIG. 5, inside the trench TR, a field plate electrode FP is formed at the lower part of the trench TR, and a gate electrode GE is formed at the upper part of the trench TR. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0020] As also shown in the cross-section taken along line B-B of FIG. 5, a part of the field plate electrode FP in the cell region CR forms a lead-out portion FPa. The field plate electrode FP constituting the lead-out portion FPa is formed not only at the lower part of the trench TR but also at the upper part of the trench TR inside the trench TR.

[0021] As shown in FIG. 2, the plurality of trenches TR formed in the outer peripheral region OR extend in the Y direction and the X direction so as to surround the cell region CR in a plan view. Inside the trench TR in the outer peripheral region OR, a field plate electrode FP constituting the lead-out portion FPa is formed.

[0022] In the cell region CR, a hole CH3 is formed in the lead-out portion FPa. The lead-out portion FPa is electrically connected to the source electrode SE through the hole CH3. Also, in the cell region CR, a hole CH1 is formed on the body region PB and the source region NS, which will be described later. The body region PB and the source region NS are electrically connected to the source electrode SE through the hole CH1. In the outer peripheral region OR, a hole CH2 is formed in the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW through the hole CH2.

[0023] Hereinafter, the cross-sectional structure of the semiconductor device 100 will be described with reference to FIG. 5.

[0024] As shown in FIG. 5, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate while introducing phosphorus (P) by an epitaxial growth method. In that case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0025] An n-type drain region ND is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the lower surface BS of the semiconductor substrate SUB toward the upper surface TS of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is composed of, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film or a silver film, or a laminated film formed by appropriately laminating these metal films. The drain region ND and the drain electrode DE are formed across the cell region CR and the outer peripheral region OR. A drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0026] A plurality of trenches TR are formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB.

[0027] As shown in the cross section taken along the line A-A of FIG. 5, inside the trench TR, a field plate electrode FP is formed at the lower part of the trench TR via an insulating film IF1. The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0028] The gate insulating film GI is formed inside the trench TR on the insulating film IF1. The insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the insulating film IF1. A gate electrode GE is formed on the field plate electrode FP via the insulating film IF2. The field plate electrode FP and the gate electrode GE are each composed of, for example, a polycrystalline silicon film into which an n-type impurity is introduced. Also, the impurity concentration of this polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0029] Also, a part of the gate electrode GE is formed between the field plate electrode FP and the semiconductor substrate SUB and in a space surrounded by the insulating film IF1, the insulating film IF2 and the gate insulating film GI.

[0030] The insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. By these films, the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP are electrically insulated from each other. The insulating film IF1, the insulating film IF2, and the gate insulating film GI are made of, for example, a silicon oxide film.

[0031] In the semiconductor substrate SUB, a p-type body region PB reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB is formed. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR from the upper surface TS of the semiconductor substrate SUB. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0032] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0033] In the interlayer insulating film IL, a hole CH1 is formed which penetrates the interlayer insulating film IL and the source region NS and reaches the body region PB. At the bottom of the hole CH1, a high-concentration diffusion region PR is formed in the body region PB. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The high-concentration diffusion region PR is provided mainly to reduce the contact resistance with the plug PG and to prevent latch-up.

[0034] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR through the hole CH1, and supplies a source potential to these impurity regions.

[0035] As shown in the cross-section taken along line B-B of FIG. 5, a part of the field plate electrode FP forms a lead-out portion FPa of the field plate electrode FP. The position of the upper surface of the insulating film IF1 in contact with the lead-out portion FPa is higher than the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the lead-out portion FPa.

[0036] The insulating film IF2 is formed so as to cover the lead-out portion FPa exposed from the insulating film IF1. Further, a body region PB is formed in the semiconductor substrate SUB adjacent to the lead-out portion FPa, but a source region NS is not formed in this body region PB.

[0037] A hole CH3 that penetrates the interlayer insulating film IL and reaches the lead-out portion FPa is formed in the interlayer insulating film IL. The source electrode SE is electrically connected to the lead-out portion FPa through the hole CH3, and supplies a source potential to the field plate electrode FP.

[0038] Although not shown here, a hole CH2 that penetrates the interlayer insulating film IL and reaches the gate electrode GE is formed in the interlayer insulating film IL. The gate wiring GW is electrically connected to the gate electrode GE through the hole CH2, and supplies a gate potential to the gate electrode GE.

[0039] A plug PG is embedded inside each of the holes CH1, CH2, and CH3. The plug PG is composed of, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is composed of, for example, a laminated film of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0040] The source electrode SE and the gate wiring GW are composed of, for example, a second barrier metal film and a second conductive film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium tungsten film. The second conductive film is, for example, a copper or aluminum alloy film added with silicon.

[0041] <Method of manufacturing a semiconductor device> Hereinafter, each manufacturing step included in the method of manufacturing the semiconductor device 100 will be described with reference to FIGS. 6 to 25.

[0042] As shown in FIG. 6, first, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by an epitaxial growth method.

[0043] Next, an oxide silicon film is formed on the semiconductor substrate SUB, for example, by a film formation process using a CVD (Chemical Vapor Deposition) method. Next, the oxide silicon film is patterned by photolithography technology and anisotropic etching treatment to form a hard mask HM. Next, an anisotropic etching treatment is performed using the hard mask HM as a mask to form a trench TR in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by an isotropic etching treatment using, for example, a solution containing hydrofluoric acid.

[0044] As shown in FIG. 7, first, an insulating film IF1 is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, an oxide silicon film formed by a thermal oxidation process. Note that the insulating film IF1 may be a laminated film of a first oxide silicon film formed by a thermal oxidation process and a second oxide silicon film formed by a film formation process using a CVD method on the first oxide silicon film.

[0045] Next, a conductive film CF1 is formed on the insulating film IF1, for example, by a film formation process using a CVD method. The conductive film CF1 is, for example, an n-type polycrystalline silicon film.

[0046] As shown in FIG. 8, by the etching process, the thickness of the conductive film CF1 located inside the trench TR is reduced, and the conductive film CF1 located outside the trench TR is removed.

[0047] As shown in FIG. 9, in order to fill the inside of the trench TR, a conductive film CF2 is formed on the insulating film IF1 and the conductive film CF1 by a film formation process using, for example, the CVD method. The conductive film CF2 is also formed on the insulating film IF1 outside the trench TR. The conductive film CF2 is, for example, an n-type polycrystalline silicon film. In the manufacturing process of FIG. 8, as approaching the top of the trench TR, the thickness of the conductive film CF1 becomes smaller. Therefore, compared with the case where the conductive film CF1 is not formed, the conductive film CF2 can be formed in a state with a low aspect ratio. For this reason, it is easy to embed the conductive film CF2 well inside the trench TR.

[0048] As shown in FIG. 10, the conductive film CF2 located outside the trench TR is removed by a polishing process using, for example, the CMP (Chemical Mechanical Polishing) method so that the conductive film CF1 and the conductive film CF2 remain inside the trench TR. The conductive film CF1 and the conductive film CF2 remaining inside the trench TR constitute the field plate electrode FP. In this way, the field plate electrode FP is formed on the insulating film IF1 so as to fill the inside of the trench TR.

[0049] Note that the field plate electrode FP can also be formed only by the conductive film CF2. In that case, without forming the conductive film CF1, the conductive film CF2 is formed on the insulating film IF1 so as to fill the inside of the trench TR. The conductive film CF2 located outside the trench TR is removed so that the conductive film CF2 remains inside the trench TR. The conductive film CF2 remaining inside the trench TR constitutes the field plate electrode FP. In this case, the manufacturing process can be simplified compared with the case where the field plate electrode FP is constituted by the conductive film CF1 and the conductive film CF2.

[0050] However, from the viewpoint of embedding the conductive film CF2 well inside the trench TR, as described with reference to FIGS. 8 to 10, it is preferable to form a conductive film CF1, which has been processed in a sidewall shape in advance, inside the trench TR.

[0051] As shown in FIG. 11, the other part of the field plate electrode FP is selectively retracted so that a part of the field plate electrode FP remains as the lead-out part FPa.

[0052] Specifically, first, as shown in the cross-section taken along line B-B in FIG. 11, a resist pattern RP1 is formed to selectively cover a part of the field plate electrode FP that will become the lead-out part FPa. Next, an etching process (etch-back process) such as dry etching or plasma etching using, for example, SF6 gas is performed on the other part of the field plate electrode FP that will not become the lead-out part FPa, with the resist pattern RP1 as a mask. That is, as shown in the cross-section taken along line A-A in FIG. 11, the other part of the field plate electrode FP exposed from the resist pattern RP1 is selectively retracted toward the bottom of the trench TR. A part of the field plate electrode FP that is not retracted becomes the lead-out part FPa.

[0053] As shown in FIG. 12, an etching process (smoothing process) using a mixed gas containing, for example, CF4 gas and O2 gas is performed on the upper surface of the field plate electrode FP. By the etching process in FIG. 12, the upper surface of the field plate electrode FP is smoothed. That is, the surface roughness of the upper surface of the field plate electrode FP after the etching process in FIG. 11 is reduced by the etching process in FIG. 12. Thereafter, an ashing process is performed to remove the resist pattern RP1.

[0054] As shown in FIG. 13, a silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation treatment. This thermal oxidation treatment is a wet oxidation treatment and is performed using, for example, water vapor. Also, by this thermal oxidation treatment, the thickness of the insulating film IF1 formed above the field plate electrode FP increases.

[0055] By this thermal oxidation treatment, the upper part of the field plate electrode FP is rounded. Also, in the X direction, the width of the upper part of the field plate electrode FP becomes narrower by the thickness of the silicon oxide film OX1.

[0056] Note that the upper part of the field plate electrode FP is a portion including the upper surface of the field plate electrode FP and a part of the side surface of the field plate electrode FP continuous with this upper surface. In other words, the upper part of the field plate electrode FP is the portion of the field plate electrode FP that is exposed from the insulating film IF1.

[0057] Also, FIG. 13 shows the starting point 10 of the isotropic etching treatment performed on the insulating film IF1 and the silicon oxide film OX1. The etching in the isotropic etching treatment proceeds over the entire surface of the insulating film IF1 and the silicon oxide film OX1, but the starting point 10 described here means a position that particularly greatly affects the shape of the insulating film IF1 at the location finally in contact with the field plate electrode FP.

[0058] As shown in FIG. 14, the insulating film IF1 and the silicon oxide film OX1 located on the upper surface TS of the semiconductor substrate SUB are removed by isotropic etching treatment using a solution containing hydrofluoric acid. At the same time, the insulating film IF1 located inside the trench TR is retracted toward the bottom of the trench TR so that the position of the upper surface of the insulating film IF1 located inside the trench TR in cross-sectional view is lower than the position of the upper surface of the field plate electrode FP. Note that at the end of the above isotropic etching treatment, the upper surface of the insulating film IF1 forms a curved surface that rises as it approaches the semiconductor substrate SUB and also rises as it approaches the field plate electrode FP.

[0059] As shown in FIG. 15, by thermal oxidation treatment, a gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR located on the insulating film IF1, and an insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the insulating film IF1.

[0060] As shown in FIG. 16, a conductive film CF3 is formed on the gate insulating film GI, on the insulating film IF2, and on the insulating film IF1 by a film formation process using, for example, the CVD method so as to fill the inside of the trench TR. The conductive film CF3 is, for example, an n-type polycrystalline silicon film.

[0061] As shown in FIG. 17, first, a polishing process using the CMP method is performed on the conductive film CF3. As a result, the thickness of the conductive film CF3 becomes smaller and the upper surface of the conductive film CF3 is planarized. Next, an anisotropic etching process is performed on the conductive film CF3 to remove the conductive film CF3 located outside the trench TR. Thereby, as shown in the cross section taken along line A-A in FIG. 17, the conductive film CF3 remaining inside the trench TR on the field plate electrode FP is formed as the gate electrode GE.

[0062] Note that, in order to completely remove the conductive film CF3 located outside the trench TR, the anisotropic etching process is performed with overetching. Therefore, as shown in the cross section taken along line A-A in FIG. 17, the position of the upper surface of the gate electrode GE is lower than the position of the upper surface TS of the semiconductor substrate SUB. Further, as shown in the cross section taken along line B-B in FIG. 17, the conductive film CF3 formed on the insulating film IF1 and on the insulating film IF2 in contact with the lead-out portion FPa is removed by the anisotropic etching process.

[0063] As shown in FIG. 18, an insulating film IF3 is formed on the gate insulating film GI, on the gate electrode GE, on the insulating film IF2, and on the insulating film IF1 by a film formation process using, for example, the CVD method so as to cover the trench TR.

[0064] As shown in FIG. 19, an anisotropic etching process is performed on the insulating film IF3. As a result, the insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB, and the insulating film IF2 on the field plate electrode FP are removed. Also, as shown in FIG. 19, the insulating film IF3 remains on a part of the gate electrode GE and on the insulating film IF1 in contact with the lead-out portion FPa.

[0065] As shown in FIG. 20, first, an impurity such as boron (B) is introduced by photolithography technology and ion implantation method, so that a p-type body region PB is selectively formed in the semiconductor substrate SUB. The body region PB is formed so that the depth from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR.

[0066] Next, an impurity such as arsenic (As) is introduced by photolithography technology and ion implantation method, so that as shown in the A-A cross section of FIG. 20, an n-type source region NS is selectively formed in the body region PB of the cell region CR. Note that, as shown in the B-B cross section of FIG. 20, the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Thereafter, the semiconductor substrate SUB is heat-treated to activate the impurities contained in the source region NS and the body region PB.

[0067] As shown in FIG. 21, first, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, CVD method so as to cover the trench TR.

[0068] Next, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Specifically, first, a resist pattern having a pattern that opens above the source region NS is formed on the interlayer insulating film IL. Next, by performing anisotropic etching using the resist pattern as a mask, a hole CH1 that penetrates the interlayer insulating film IL and the source region NS and reaches the inside of the body region PB is formed. Next, an impurity such as boron (B) is introduced into the body region PB at the bottom of the hole CH1 by ion implantation to form a p-type high-concentration diffusion region PR. Thereafter, the resist pattern is removed by ashing treatment.

[0069] Next, a resist pattern having a pattern that opens above the extraction portion FPa and above the gate electrode GE is formed on the interlayer insulating film IL. Next, by performing anisotropic etching using the resist pattern as a mask, a hole CH3 that penetrates the interlayer insulating film IL and reaches the extraction portion FPa is formed. Although not shown here, a hole CH2 is also formed in the manufacturing process of forming the hole CH3. The hole CH2 penetrates the interlayer insulating film IL and reaches the gate electrode GE. Thereafter, the resist pattern is removed by ashing treatment.

[0070] Note that the order of forming the hole CH1 and the order of forming the holes CH2 and CH3 may be either one first.

[0071] As shown in FIG. 22, plugs PG are formed inside each of the holes CH1, CH2, and CH3, and a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL.

[0072] First, a first barrier metal film is formed on the inside of the holes CH1, CH2, CH3 and on the interlayer insulating film IL by a film forming process using a sputtering method or a CVD method. The first barrier metal film is composed of, for example, a laminated film of a titanium nitride film and a titanium film. Next, a first conductive film is formed on the first barrier metal film by a film forming process using a CVD method. The first conductive film is composed of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the holes CH1, CH2, CH3 are removed by a polishing process using a CMP method or an anisotropic etching process. Thereby, a plug PG composed of the first barrier metal film and the first conductive film is formed so as to fill the inside of the holes CH1, CH2, CH3.

[0073] Next, a second barrier metal film is formed on the interlayer insulating film IL by a film forming process using a sputtering method. The second barrier metal film is composed of, for example, a titanium tungsten film. Next, a second conductive film is formed on the second barrier metal film by a film forming process using a sputtering method. The second conductive film is, for example, an aluminum alloy film added with copper or silicon. Next, the second barrier metal film and the second conductive film are patterned to form a source electrode SE and a gate wiring GW.

[0074] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. By forming an opening in a part of the protective film, the regions that become the source pad SP and the gate pad GP among the source electrode SE and the gate wiring GW are exposed.

[0075] Thereafter, through the following manufacturing processes, the structure shown in FIG. 5 is obtained. First, the lower surface BS of the semiconductor substrate SUB is polished as necessary. Next, by introducing, for example, arsenic (As) or the like into the lower surface BS of the semiconductor substrate SUB by ion implantation, an n-type drain region ND is formed. When the semiconductor substrate SUB is composed of a laminate of an n-type silicon substrate and an n-type semiconductor layer, since the high-concentration n-type silicon substrate forms the drain region ND, the formation of the drain region ND by the above-described ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by a film formation process using a sputtering method.

[0076] <Regarding the thermal oxidation treatment of FIG. 13> Hereinafter, with reference to FIG. 23, while making a comparison with Examination Example 1, the reason for performing the thermal oxidation treatment of FIG. 13 will be described. Note that the problems shown in Examination Example 1 are not known findings, but are newly obtained findings by the inventors of the present application.

[0077] FIG. 23 shows the step of retracting the field plate electrode FP of FIG. 11, the step of retracting the insulating film IF1 of FIG. 14, and the step of forming the gate electrode GE of FIG. 17. In Examination Example 1, the etching treatment on the upper surface of the field plate electrode FP as described in FIG. 12 and the formation of the silicon oxide film OX1 by the thermal oxidation treatment as described in FIG. 13 are not performed.

[0078] As shown in FIG. 23, in Examination Example 1, the isotropic etching treatment for the insulating film IF1 proceeds from the starting point 11. Therefore, among the upper surfaces of the insulating film IF1 located inside the trench TR, the position of the portion in contact with the field plate electrode FP is retracted downward more than the position of the portion in contact with the side portion of the semiconductor substrate SUB. Thereafter, when the gate insulating film GI and the insulating film IF2 are formed and the gate electrode GE is formed from the conductive film CF3, the shape of the lower end portion of the gate electrode GE tends to be protruded in the vicinity of the retracted insulating film IF1. In such a protruding portion, the electric field tends to concentrate.

[0079] In FIG. 23, a concern location 20 is shown as a location where an electric field is likely to concentrate. Further, in the vicinity of the concern location 20, it is difficult for oxygen gas to reach, and the thickness of the insulating film IF2 is likely to become locally thin. Therefore, in Study Example 1, there is a problem that it is difficult to ensure the dielectric breakdown voltage between the gate electrode GE and the field plate electrode FP at the concern location 20.

[0080] Also, if the upper part of the field plate electrode FP is protruded, such a protruded location also becomes a concern location 21 where the electric field is likely to concentrate. At the concern location 21 as well, there is a problem that it is difficult to ensure the dielectric breakdown voltage between the gate electrode GE and the field plate electrode FP.

[0081] In Embodiment 1, by performing the thermal oxidation treatment of FIG. 13, a silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP. Therefore, the isotropic etching treatment performed on the insulating film IF1 and the silicon oxide film OX1 proceeds from a starting point 10 which is at a higher position than the starting point 11 of Study Example 1.

[0082] As a result, at the end of the isotropic etching treatment of FIG. 13, as shown in FIG. 14, the upper surface of the insulating film IF1 forms a curved surface shape that rises as it approaches the semiconductor substrate SUB and also rises as it approaches the field plate electrode FP.

[0083] Note that when a film formation treatment using the CVD method is applied to form the insulating film IF1, since the CVD film has a faster etching rate during the isotropic etching treatment than the thermally oxidized film, the above-described curved surface shape is more likely to be formed. Thereafter, as shown in the cross section A-A of FIG. 17, even when the gate electrode GE is formed from the conductive film CF3, the shape of the lower end portion of the gate electrode GE does not become protruded. Therefore, the concentration of the electric field at the concern location 20 of Study Example 1 is alleviated.

[0084] Further, even if the thickness of the insulating film IF2 is small in the vicinity of the insulating film IF1, the insulating film IF1 can compensate for the thickness. Therefore, the breakdown voltage between the gate electrode GE and the field plate electrode FP can be ensured, and the reliability of the semiconductor device 100 can be improved.

[0085] Also, by performing the thermal oxidation treatment of FIG. 13, the upper part of the field plate electrode FP is rounded. Therefore, the electric field concentration at the concern location 21 in the study example 1 is alleviated. Even at the concern location 21, the breakdown voltage between the gate electrode GE and the field plate electrode FP can be ensured.

[0086] <Regarding the etching process of FIG. 12> Hereinafter, with reference to FIGS. 24 to 26, the reason for performing the etching process of FIG. 12 will be described while comparing with Study Example 2. Note that the problems shown in Study Example 2 are not known knowledge but new findings obtained by the inventors of the present application.

[0087] FIG. 24 shows the process of forming the conductive film CF2 in FIG. 9, the process of retracting the field plate electrode FP in FIG. 11, and the process of forming the silicon oxide film OX1 in FIG. 13. In Study Example 2, the etching process on the upper surface of the field plate electrode FP as described in FIG. 12 is not performed.

[0088] As shown in FIG. 24, the conductive film CF2 is formed from both side surfaces of the trench TR in the X direction and is blocked near the central portion of the trench TR. In FIG. 24, the blocked interface is shown as the joining surface (seam) 30 of the conductive film CF2. Near the central portion of the trench TR, voids 40 are likely to occur due to the shape of the trench TR and the aspect ratio during the formation of the conductive film CF2. Also, at the joining surface 30, the atomic bond is weak, and minute voids may be intermittently formed under the influence of the surface roughness of the conductive film CF2.

[0089] In the void 40 and the joint surface 30, in the anisotropic etching process shown in FIG. 11, the etching rate tends to be faster compared to other parts of the conductive film CF2. Therefore, as shown in FIGS. 24 and 25, when performing the anisotropic etching process of FIG. 11, a divot (concave portion) 50 is likely to be formed in the conductive film CF2 near the center of the trench TR.

[0090] In this state, when the thermal oxidation process of FIG. 13 is performed to form the silicon oxide film OX1, starting from the divot 50, oxidation proceeds into the inside of the field plate electrode FP. Then, the shape of the upper part of the field plate electrode FP is likely to become protruded, and a concern portion 21 as in the first study example is likely to occur. Therefore, a problem arises that it is difficult to ensure the breakdown voltage between the gate electrode GE and the field plate electrode FP. Further, when oxidation proceeds into the inside of the field plate electrode FP starting from the divot 50 in this way, stress is applied in the lateral direction due to the volume expansion during oxidation, and crystal defects may occur in the semiconductor substrate SUB between the trenches TR.

[0091] Also, in a subsequent manufacturing process, on the upper part of the field plate electrode FP, the silicon oxide film OX1 is removed and the insulating film IF2 is formed. At this time, since the insulating film IF2 enters deeper into the field plate electrode FP, it becomes more difficult to ensure the breakdown voltage at the concern portion 21.

[0092] In the first embodiment, as shown in FIG. 25, before forming the silicon oxide film OX1, the etching process of FIG. 12 is performed on the upper surface of the field plate electrode FP. By the etching process of FIG. 12, the upper surface of the field plate electrode FP is smoothed, and the thermal oxidation process of FIG. 13 can be performed in a state where the divot 50 is removed.

[0093] The etching process of FIG. 12 is performed, for example, using a mixed gas containing CF4 gas and O2 gas, and is performed without applying a bias potential.

[0094] Although not shown in the drawings, the etching process of FIG. 11 and the etching process of FIG. 12 are performed by a plasma processing apparatus having a stage for mounting the semiconductor substrate SUB. In the above plasma processing apparatus, plasma is generated by exciting, ionizing, or dissociating atoms or molecules in the processing gas. Usually, when plasma is generated, high-frequency power is supplied from a high-frequency power source to the stage. As a result, a bias potential is formed above the semiconductor substrate SUB, and charged particles such as ions in the plasma are attracted to the semiconductor substrate SUB (with bias potential).

[0095] However, the etching process of FIG. 12 is performed with the semiconductor substrate SUB mounted on the stage, but without supplying high-frequency power to the stage (without bias potential). Note that the etching process of FIG. 11 is performed with the semiconductor substrate SUB mounted on the stage and with high-frequency power supplied to the stage (with bias potential).

[0096] As shown in FIG. 26, when the etching process of FIG. 12 is started, a reaction product 60 such as SiOF is generated. In the etching process, the etching of the field plate electrode FP and the reaction product 60 and the generation of the reaction product 60 are repeated. Since the etching rate of the field plate electrode FP is faster than the etching rate of the reaction product 60, the reaction product 60 deposited inside the divot 50 functions as a mask.

[0097] When the etching process is continued in that state, the field plate electrode FP exposed from the reaction product 60 is preferentially etched. When the etching process is further continued and the field plate electrode FP is etched to a position substantially the same as the depth position of the divot 50, the upper surface of the field plate electrode FP is smoothed, the deposition distribution of the reaction product 60 is made uniform, and the progress of the etching slows down. Thereafter, the reaction product 60 is removed by a cleaning process, and the etching process is terminated. In the above cleaning process, for example, an aqueous solution containing sulfuric acid and an aqueous solution containing ammonia and hydrogen peroxide water are used.

[0098] Thus, it can be said that the etching process of FIG. 12 is a chemical dry etching process using the reaction product 60.

[0099] By performing the etching process of FIG. 12, even if the divot 50 is formed on the upper surface of the field plate electrode FP in the etching process of FIG. 11, the divot 50 can be removed. That is, the surface roughness of the upper surface of the field plate electrode FP after the etching process of FIG. 11 is reduced by the etching process of FIG. 12.

[0100] Therefore, the problem that oxidation enters the inside of the field plate electrode FP starting from the divot 50 can be suppressed. Further, the upper surface of the field plate electrode FP is smoothed, and the upper part of the field plate electrode FP is rounded. Therefore, the concern portion 21 is less likely to occur, so the breakdown voltage between the gate electrode GE and the field plate electrode FP can be ensured, and the reliability of the semiconductor device 100 can be improved.

[0101] Also, by increasing the ratio of O2 gas, the generation of the reaction product 60 can be promoted. Therefore, in the etching process of FIG. 12, it is preferable that the ratio of O2 gas contained in the mixed gas is larger than the ratio of CF4 gas contained in the mixed gas.

[0102] Also, in order to promote the generation of the reaction product 60, it is preferable to perform the etching process of FIG. 12 at as low a temperature as possible.

[0103] In the etching process using a mixed gas containing CF4 gas and O2 gas having the above-described characteristic of a high O2 gas ratio, the etching rate with respect to the field plate electrode FP is relatively slow, and the selectivity with respect to a silicon oxide film such as the insulating film IF1 is not high. Therefore, for example, it is difficult to secure the thickness of the insulating film IF1 and the recession amount of the field plate electrode FP shown in FIG. 11 only by the etching process of FIG. 12.

[0104] In the etching process of FIG. 11, the etching rate for the field plate electrode FP is faster than the etching rate for the field plate electrode FP in the etching process of FIG. 12. Also, in the etching process of FIG. 11, the selectivity with respect to the insulating film IF1 is higher compared to the etching process of FIG. 12. Therefore, it is preferable to perform most of the recession of the field plate electrode FP by the etching process of FIG. 11.

[0105] Also, the etching process of FIG. 12 can be performed as a substantial chemical dry etching process by setting the bias potential to zero. Therefore, there is no need to change to another plasma processing apparatus for performing the chemical dry etching process after the etching process of FIG. 11. Since the etching process of FIG. 11 and the etching process of FIG. 12 can be continuously performed in the same plasma processing apparatus, throughput can be reduced.

[0106] (Modification example) Hereinafter, a modification example of Embodiment 1 will be described with reference to FIG. 27.

[0107] In the modification example, the formation of the silicon oxide film OX1 in FIG. 13 may be omitted. In that case, as shown in FIG. 27, the next manufacturing process after the etching process of FIG. 12 is the isotropic etching process of FIG. 14. Therefore, in the modification example, the effects of the isotropic etching process starting from the starting point 10, which is higher than the starting point 11 in Study Example 1, and the effect of rounding the upper part of the field plate electrode FP cannot be obtained.

[0108] However, in the modification example, as in Embodiment 1, the etching process of FIG. 12 is performed on the upper surface of the field plate electrode FP. Therefore, during the thermal oxidation process of FIG. 15, the problem that the insulating film IF2 enters the inside of the field plate electrode FP starting from the divot 50 can be suppressed. Also, by the etching process of FIG. 12, the upper surface of the field plate electrode FP is smoothed and the upper part of the field plate electrode FP is rounded, so that the concern portion 21 is less likely to occur.

[0109] Therefore, in the modification example, compared with Study Example 1 and Study Example 2, the breakdown voltage between the gate electrode GE and the field plate electrode FP can be ensured, and the reliability of the semiconductor device 100 can be improved. In addition, since the formation of the silicon oxide film OX1 in FIG. 13 is omitted, the manufacturing process can be simplified compared with Embodiment 1.

[0110] As described above, the present invention has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0111] 100 Semiconductor device 10, 11 Starting points 20, 21 Concerned locations 30 Joining surface (seam) 40 Void 50 Divot (recess) 60 Reaction product 1A Region BS Lower surface of semiconductor substrate CF1, CF2, CF3 Conductive film CH1, CH2, CH3 Hole CR Cell region DE Drain electrode FP Field plate electrode FPa Lead-out portion GE Gate electrode GI Gate insulating film GP Gate pad GW Gate wiring HM Hard mask IF1, IF2, IF3 Insulating film IL Interlayer insulating film ND Drain region NS Source region NV Drift region OR Outer peripheral region OX1 Silicon oxide film PB Body region PG Plug PR High-Concentration Diffusion Region RP1 Resist Pattern SE Source Electrode SP Source Pad SUB Semiconductor Substrate TR Trench TS Upper Surface of Semiconductor Substrate

Claims

1. (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after the step (b), forming a first insulating film inside the trench and on the upper surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film so as to fill the inside of the trench; (e) after the step (d), retreating the field plate electrode toward the bottom of the trench by an etching process; (f) After the step (e), an etching process is performed on the upper surface of the field plate electrode using a mixed gas containing CF ４ gas and O ２ gas. (g) after the step (f), forming a first silicon oxide film on the upper surface of the field plate electrode by a first thermal oxidation process; A method for manufacturing a semiconductor device, comprising the above steps.

2. In the method for manufacturing a semiconductor device according to Claim 1, The ratio of the O gas contained in the mixed gas ２ is greater than the ratio of the CF gas contained in the mixed gas, a method for manufacturing a semiconductor device. ４ ​

3. In the method for manufacturing a semiconductor device according to Claim 1, the etching process in the step (f) is performed by a first plasma processing apparatus having a stage for mounting the semiconductor substrate, the etching process in the step (f) is performed in a state where the semiconductor substrate is mounted on the stage and high-frequency power is not supplied to the stage. A method for manufacturing a semiconductor device.

4. In the method for manufacturing a semiconductor device according to Claim 3, the etching process in the step (e) is performed by the first plasma processing apparatus, the etching process in the step (e) is performed in a state where the semiconductor substrate is mounted on the stage and high-frequency power is supplied to the stage, the etching rate of the field plate electrode in the etching process in the step (e) is faster than the etching rate of the field plate electrode in the etching process in the step (f). A method for manufacturing a semiconductor device.

5. In the method for manufacturing a semiconductor device according to Claim 4, In the etching process in the step (e), SF ６ gas is used, a method of manufacturing a semiconductor device.

6. In the method for manufacturing a semiconductor device according to Claim 1, the surface roughness of the upper surface of the field plate electrode after the step (e) is reduced by the step (f). A method for manufacturing a semiconductor device.

7. In the method for manufacturing a semiconductor device according to Claim 1, the step (d) is Step (d1): After the step (c), forming a first conductive film on the first insulating film by a first film formation process using a CVD method; Step (d2): After the step (d1), reducing the thickness of the first conductive film located inside the trench and removing the first conductive film located outside the trench; Step (d3): After the step (d2), forming a second conductive film on the first insulating film and on the first conductive film by a second film formation process using a CVD method so as to fill the inside of the trench; Step (d4): After the step (d3), removing the second conductive film located outside the trench so that the first conductive film and the second conductive film remain inside the trench; which includes; In the step (d4), the first conductive film and the second conductive film left inside the trench constitute the field plate electrode. A method of manufacturing a semiconductor device.

8. In the method of manufacturing a semiconductor device according to claim 1, the step (d) includes: Step (d5): After the step (c), forming a second conductive film on the first insulating film by a film formation process using a CVD method so as to fill the inside of the trench; Step (d6): After the step (d5), removing the second conductive film located outside the trench so that the second conductive film remains inside the trench; which includes; In the step (d6), the second conductive film left inside the trench constitutes the field plate electrode. A method of manufacturing a semiconductor device.

9. In the method of manufacturing a semiconductor device according to claim 1, Step (h): After the step (g), removing the first insulating film and the first silicon oxide film located on the upper surface of the semiconductor substrate, and retreating the first insulating film located inside the trench toward the bottom of the trench so that the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode; Step (i): After the step (h), forming a gate insulating film inside the trench located on the first insulating film by a second thermal oxidation process, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film. (j)After the step (i), a step of forming a third conductive film on the gate insulating film, on the second insulating film, and on the first insulating film so as to fill the inside of the trench; (k)After the step (j), a step of forming, as a gate electrode, the third conductive film remaining inside the trench on the field plate electrode by removing the third conductive film located outside the trench; A method of manufacturing a semiconductor device, further comprising:

10. In the method of manufacturing a semiconductor device according to Claim 1, (l)Between the step (f) and the step (g), removing the first insulating film located on the upper surface of the semiconductor substrate, and retreating the first insulating film located inside the trench toward the bottom of the trench so that the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode; (m)After the step (l), as the step (g), a step of forming a gate insulating film inside the trench located on the first insulating film by the first thermal oxidation treatment, and forming a first silicon oxide film so as to cover the field plate electrode exposed from the first insulating film; (n)After the step (m), a step of forming a third conductive film on the gate insulating film, on the first silicon oxide film, and on the first insulating film so as to fill the inside of the trench; (o)After the step (n), a step of forming, as a gate electrode, the third conductive film remaining inside the trench on the field plate electrode by removing the third conductive film located outside the trench; A method of manufacturing a semiconductor device, further comprising:

Images