Semiconductor device

Abstract

To provide a semiconductor device with improved electrical characteristics and an integration degree.SOLUTION: A semiconductor device includes: a lower stacked structure including a first lower word line, a first lower channel film penetrating the first lower word line, and a lower data storage structure connected to the first lower channel film; an interlayer insulation film on the lower stacked structure; an upper stacked structure arranged on the interlayer insulation film and including an upper word line, an upper channel film penetrating the upper word line, and an upper data storage structure connected to the upper channel film; a lower connection contact on the first lower word line, a connected conductive line on the lower connection contact, and a penetration contact on the connected conductive line.SELECTED DRAWING: Figure 3C

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a word line.

Background Art

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing cost, semiconductor elements have come to the forefront as important elements in the electronics industry. Semiconductor elements can be classified into semiconductor memory elements that store logical data, semiconductor logic elements that perform arithmetic processing on logical data, and hybrid semiconductor elements that include memory elements and logic elements.

[0003] Recently, in response to the high-speed operation and low power consumption of electronic devices, the semiconductor elements incorporated therein are also required to have a high operation speed and / or a low operation voltage, etc. In order to meet these requirements, more highly integrated semiconductor elements are necessary. However, as the high integration of semiconductor elements deepens, the electrical characteristics and production yield of semiconductor elements can decrease. Therefore, much research is underway to improve the electrical characteristics and production yield of semiconductor elements.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device with improved electrical characteristics and integration degree.

Means for Solving the Problems

[0006] A semiconductor device according to some embodiments includes a lower stacked structure including a first lower word line, a first lower channel film penetrating the first lower word line, and a lower data storage structure connected to the first lower channel film, an interlayer insulating film on the lower stacked structure, and an upper stacked structure disposed on the interlayer insulating film and including an upper word line, an upper channel film penetrating the upper word line, and an upper data storage structure connected to the upper channel film, a lower connection contact on the first lower word line, a connection conductive line on the lower connection contact, and a through contact on the connection conductive line, wherein the lower connection contact is superimposed on the upper word line, and the through contact does not have to be superimposed on the upper word line.

[0007] A semiconductor device according to some embodiments includes a first lower word line, a first lower channel film penetrating the first lower word line, a first lower connection contact in contact with the first lower word line, a second lower word line disposed at a level higher than the first lower word line, a second lower channel film penetrating the second lower word line, a second lower connection contact in contact with the second lower word line, a first upper word line disposed at a level higher than the second lower word line, a first upper channel film penetrating the first upper word line, and a first upper connection contact in contact with the first upper word line, wherein the first lower word line includes a first lower electrode portion surrounding the first lower channel film and a second lower electrode portion in contact with the first lower connection contact, the second lower word line includes a first lower electrode portion surrounding the second lower channel film and a second lower electrode portion in contact with the second lower connection contact, the first upper word line includes a first upper electrode portion surrounding the first upper channel film and a second upper electrode portion in contact with the first upper connection contact, and the length of the second lower electrode portion of the second lower word line may be smaller than the length of the second lower electrode portion of the first lower word line and the length of the second upper electrode portion of the first upper word line.

[0008] A semiconductor device according to some embodiments includes a lower stacked structure, an interlayer insulating film on the lower stacked structure, an upper stacked structure on the interlayer insulating film, an upper insulating film on the upper stacked structure, a first connecting conductive line and a second connecting conductive line in the interlayer insulating film, a first upper conductive line, a second upper conductive line, and a third upper conductive line in the upper insulating film, a first lower connecting contact in contact with the lower surface of the first connecting conductive line, a second lower connecting contact in contact with the lower surface of the second connecting conductive line, an upper connecting contact electrically connecting the first upper conductive line and the upper stacked structure, a first through contact in contact with the lower surface of the second upper conductive line and the upper surface of the first connecting conductive line, and a second through contact in contact with the lower surface of the third upper conductive line and the upper surface of the second connecting conductive line. The lower stacked structure includes a first lower word line in contact with the lower surface of the first lower connecting contact and a second lower word line in contact with the lower surface of the second lower connecting contact. The second connecting conductive line includes a first portion in contact with the upper surface of the second lower connecting contact and a second portion in contact with the lower surface of the second through contact. The first connecting conductive line may be disposed between the first and second portions of the second connecting conductive line.

[0009] A semiconductor device according to some embodiments includes a first word line, a first channel film penetrating the first word line, a second word line on the first word line, a second channel film on the first channel film penetrating the second word line, a data storage structure connected to the first and second channel films, a bit line connected to the first and second channel films, a first through insulating pattern penetrating the second word line, and a first connecting contact electrically connected to the first word line. The first connecting contact includes a first connecting portion in contact with the first word line and an upper portion penetrating the second word line and the first through insulating pattern. The width of the first connecting portion may be larger than the width of the upper portion.

Advantages of the Invention

[0010] According to an embodiment of the inventive concept, the size of the semiconductor device can be minimized in response to minimizing the area occupied by the connection region.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 4

Figure 5A

Figure 5B

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Best Mode for Carrying Out the Invention

[0012] FIG. 1 is a schematic circuit diagram showing a semiconductor device according to some embodiments.

[0013] Referring to FIG. 1, the semiconductor device can include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0014] The memory cell array 1 can include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC can be three-dimensionally arranged, and each memory cell MC can be connected to one word line WL, one bit line BL, and one source line SL. In some embodiments, each of the memory cells MC can be composed of one transistor including a memory film (or data storage film).

[0015] The row decoder 2 can decode an externally input address to select any one of the word lines WL in the memory cell array 1. The address decoded by the row decoder 2 can be provided to a load driver (not shown), and the load driver can provide a predetermined voltage to the selected word line WL and the non-selected word lines WL in response to the control of a control circuit.

[0016] The sense amplifier 3 can sense and amplify the voltage difference between the selected bit line BL and a reference bit line according to the address decoded from the column decoder 4 and output it.

[0017] The column decoder 4 can provide a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can decode an externally input address to select any one of the bit lines BL.

[0018] The control logic 5 can generate control signals for controlling write or read operations to write data to or read data from the memory cell array 1.

[0019] FIGS. 2A, 2B, and 2C are schematic perspective views of a semiconductor device according to some embodiments.

[0020] Referring to FIG. 2A, the semiconductor device can include a peripheral circuit structure PS on a substrate 100 and a cell array structure CS on the peripheral circuit structure PS.

[0021] The peripheral circuit structure PS can include a core and peripheral circuits formed on the substrate 100. The core and peripheral circuits can include the row and column decoders (2, 4 in FIG. 1), sense amplifiers (3 in FIG. 1), and control logic (5 in FIG. 1) described with reference to FIG. 1.

[0022] The substrate 100 can have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can intersect each other. As an example, the first direction D1 and the second direction D2 can be horizontal directions perpendicular to each other. The peripheral circuit structure PS and the cell array structure CS can be sequentially stacked on the substrate 100 in a third direction D3. The third direction D3 can intersect the first direction D1 and the second direction D2. As an example, the third direction D3 can be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0023] The cell array structure CS can include bit lines BL, source lines SL, word lines WL, and memory cells MC therebetween. Each of the memory cells MC can be connected to one word line WL, one bit line BL, and one source line SL.

[0024] Referring to FIG. 2B, the semiconductor device can include a cell array structure CS on a substrate 100 and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS can be disposed between the substrate 100 and the peripheral circuit structure PS. The peripheral circuit structure PS can include a core and peripheral circuits.

[0025] Referring to FIG. 2C, the semiconductor device can have a C2C (Chip to Chip) structure. The peripheral circuit structure PS can include a first substrate 10. A lower metal pad LMP can be provided on the top of the peripheral circuit structure PS. The lower metal pad LMP can be electrically connected to the core and peripheral circuits. The lower metal pad LMP can be coupled to an upper metal pad UMP of the cell array structure CS.

[0026] The cell array structure CS can include a second substrate 200a, and an upper metal pad UMP can be provided at the bottom of the cell array structure CS. The upper metal pad UMP can be connected to a bit line BL, a source line SL, and a word line WL. The upper metal pad UMP can be electrically connected to a memory cell MC.

[0027] FIG. 3A is a plan view of a semiconductor device according to some embodiments. FIG. 3B is a cross-sectional view taken along line A-A' of FIG. 3A. FIG. 3C is a cross-sectional view taken along line B-B' of FIG. 3A. FIG. 3D is a perspective view showing a word line and a channel film. FIG. 3E is a plan view showing a connecting conductive line.

[0028] Referring to FIGS. 3A, 3B, 3C, and 3D, the semiconductor device can include a substrate SUB. The substrate SUB can be a semiconductor substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate can be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate SUB can have a plate shape that extends along a plane defined by a first direction D1 and a second direction D2.

[0029] A lower insulating film 110 can be provided on the substrate SUB. The lower insulating film 110 can include an insulating material. In some embodiments, the lower insulating film 110 can include a plurality of insulating films. In some embodiments, peripheral transistors can be disposed between the substrate SUB and the lower insulating film 110.

[0030] A lower stacked structure LSS can be provided on the lower insulating film 110. The lower stacked structure LSS can include a lower word line LWL, a lower channel film LCL, a gate insulating film GI, an intervening insulating pattern IIP, a first capping pattern CP1, a second capping pattern CP2, a lower bit line LBL, a lower data storage structure LDS, and a first cover insulating film 120.

[0031] A lower data storage structure LDS can be provided on the first lower insulating film 110. The lower data storage structure LDS can be a capacitor including a first electrode EL1, a second electrode EL2, and a capacitor insulating film CI. The first electrode EL1 can be spaced apart from the second electrode EL2. The capacitor insulating film CI can be provided between the first electrode EL1 and the second electrode EL2.

[0032] The first electrode EL1 can be provided on both sides of the second electrode EL2. The capacitor insulating film CI can be provided on both sides of the second electrode EL2. The first and second electrodes EL1, EL2 can include a conductive material. The capacitor insulating film CI can include an insulating material.

[0033] In some embodiments, the lower data storage structure LDS can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse. In this case, the lower data storage pattern DSP can include a phase-change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0034] The lower bit line LBL can be provided on the first lower insulating film 110. The lower bit line LBL can extend in the third direction D3. The lower bit lines LBL can be arranged on both sides of the lower data storage structure LDS. The lower data storage structure LDS can be arranged between the lower bit lines LBL. The lower bit lines LBL arranged on one side of the lower data storage structure LDS can be arranged spaced apart from each other in the first direction D1. The lower bit line LBL can include a conductive material.

[0035] The lower word line LWL can be provided between the lower bit line LBL and the lower data storage structure LDS. The lower word lines LWL can be provided on both sides of the lower data storage structure LDS. The lower data storage structure LDS can be arranged between the lower word lines LWL. The lower word line LWL can include a first lower word line LWL1, a second lower word line LWL2, and a third lower word line LWL3 arranged on one side of the lower data storage structure LDS. The lower word line LWL can include a conductive material.

[0036] The number of lower word lines LWL included in the lower stacked structure LSS may not be limited to what is shown. In some embodiments, the number of lower word lines LWL may be two or less, or four or more.

[0037] The first to third lower word lines LWL1, LWL2, and LWL3 can be superimposed in the third direction D3. The second lower word line LWL2 can be arranged at a higher level than the first lower word line LWL1. The distance in the third direction D3 between the second lower word line LWL2 and the substrate SUB may be greater than the distance in the third direction D3 between the first lower word line LWL1 and the substrate SUB. The third lower word line LWL3 can be arranged at a higher level than the second lower word line LWL2.

[0038] The lower channel film LCL can electrically connect the lower bit line LBL and the lower data storage structure LDS. The lower channel film LCL can extend in the second direction D2. Each of the lower channel films LCL can include a first source / drain region SD1, a channel region CH, and a second source / drain region SD2. The first source / drain region SD1 can be connected to the lower bit line LBL. The second source / drain region SD2 can be connected to the first electrode EL1 of the lower data storage structure LDS. The channel region CH can be arranged between the first source / drain region SD1 and the second source / drain region SD2.

[0039] The lower channel film LCL can include at least one of a single-crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, or a two-dimensional material. The single-crystal semiconductor can be, for example, single-crystal silicon. The polycrystalline semiconductor can be, for example, polysilicon. The oxide semiconductor can be, for example, IGZO (Indium Gallium Zinc Oxide). The two-dimensional material can be, for example, MoS2, WS2, MoSe2, or WSe2. The first and second source / drain regions SD1, SD2 can be doped with impurities.

[0040] The lower channel film LCL can include a first lower channel film LCL1 surrounded by a first lower word line LWL1, a second lower channel film LCL2 surrounded by a second lower word line LWL2, and a third lower channel film LCL3 surrounded by a third lower word line LWL3. The first to third lower channel films LCL1, LCL2, LCL3 connected to one lower bit line LBL can be stacked in the third direction D3.

[0041] The second lower channel film LCL2 can be arranged at a higher level than the first lower channel film LCL1. The third lower channel film LCL3 can be arranged at a higher level than the second lower channel film LCL3. The first lower channel films LCL1 can be arranged spaced apart from each other in the first direction D1. The second lower channel films LCL2 can be arranged spaced apart from each other in the first direction D1. The third lower channel films LCL3 can be arranged spaced apart from each other in the first direction D1.

[0042] At least a part of the gate insulating film GI of the lower stacked structure LSS can be provided between the lower word line LWL and the lower channel film LCL. The lower word line LWL and the lower channel film LCL can be separated by the gate insulating film GI of the lower stacked structure LSS. The gate insulating film GI of the lower stacked structure LSS can include an insulating material.

[0043] The first capping pattern CP1 of the lower stacked structure LSS can be provided between the lower word line LWL and the lower bit line LBL. The lower word line LWL and the lower bit line LBL can be separated by the first capping pattern CP1 of the lower stacked structure LSS. The first capping pattern CP1 of the lower stacked structure LSS can include an insulating material.

[0044] The second capping pattern CP2 of the lower stacked structure LSS can be provided between the lower word line LWL and the lower data storage structure LDS. The lower word line LWL and the lower data storage structure LDS can be separated by the second capping pattern CP2 of the lower stacked structure LSS. The second capping pattern CP2 of the lower stacked structure LSS can include an insulating material.

[0045] The semiconductor device can include a cell region CR where a lower bit line LBL, a lower data storage structure LDS, and a lower channel film LCL are disposed, and a connection region OR connected to the cell region CR.

[0046] Each of the lower word lines LWL can include a first lower electrode portion LEP1 disposed in the cell region CR and a second lower electrode portion LEP2 disposed in the connection region OR.

[0047] The first lower electrode portion LEP1 can extend in a first direction D1. The first lower electrode portion LEP1 can surround the lower channel film LCL. The lower channel film LCL can extend in a second direction D2 and penetrate the first lower electrode portion LEP1. The first lower electrode portions LEP1 of the first to third lower word lines LWL1, LWL2, LWL3 can be superimposed in a third direction D3.

[0048] The second lower electrode portion LEP2 can extend in the second direction D2. The second lower electrode portions LEP2 of the first to third lower word lines LWL1, LWL2, LWL3 can be superimposed in the third direction D3. The length L1 of the second lower electrode portion LEP2 of the first lower word line LWL1 in the second direction D2 may be greater than the length L2 of the second lower electrode portion LEP2 of the second lower word line LWL2 in the second direction D2. The length L2 of the second lower electrode portion LEP2 of the second lower word line LWL2 in the second direction D2 may be greater than the length L3 of the second lower electrode portion LEP2 of the third lower word line LWL3 in the second direction D2.

[0049] The intervening insulating pattern IIP of the lower stacked structure LSS can be provided between the lower word lines LWL. The intervening insulating pattern IIP of the lower stacked structure LSS can be provided between the first electrodes EL1 of the lower data storage structure LDS. The intervening insulating pattern IIP of the lower stacked structure LSS can include an insulating material.

[0050] The first cover insulating film 120 can surround the lower bit line LBL, the lower word line LWL, the lower data storage structure LDS, and the lower channel film LCL. The first cover insulating film 120 can include an insulating material. In some embodiments, the first cover insulating film 120 can include a plurality of insulating films.

[0051] An interlayer insulating film 130 can be provided on the lower stacked structure LSS. The interlayer insulating film 130 can include an insulating material. In some embodiments, the interlayer insulating film 130 can include a plurality of insulating films.

[0052] Lower bit line contacts LBC, lower data contacts LDC, lower bit line connection lines LBO, lower data connection lines LDO, first connection conductive lines CL1, second connection conductive lines CL2, and third connection conductive lines CL3 can be provided in the interlayer insulating film 130. The lower bit line contacts LBC, the lower data contacts LDC, the lower bit line connection lines LBO, the lower data connection lines LDO, the first connection conductive lines CL1, the second connection conductive lines CL2, and the third connection conductive lines CL3 can include a conductive material. In some embodiments, the lower bit line connection lines LBO, the lower data connection lines LDO, the first connection conductive lines CL1, the second connection conductive lines CL2, and the third connection conductive lines CL3 can be arranged at the same level.

[0053] The lower bit line contact LBC can be connected to the lower bit line LBL. The lower bit line connection line LBO can be connected to the lower bit line contact LBC. The lower data contact LDC can be connected to the lower data storage structure LDS. The lower data connection line LDO can be connected to the lower data contact LDC.

[0054] A first lower connection contact LCO1 connecting the second lower electrode portion LEP2 of the first lower word line LWL1 and the first connection conductive line CL1, a second lower connection contact LCO2 connecting the second lower electrode portion LEP2 of the second lower word line LWL2 and the second connection conductive line CL2, and a third lower connection contact LCO3 connecting the second lower electrode portion LEP2 of the third lower word line LWL3 and the third connection conductive line CL3 can be provided. The first to third lower connection contacts LCO1, LCO2, LCO3 can extend in the third direction D3. The first to third lower connection contacts LCO1, LCO2, LCO3 can extend through the interlayer insulating film 130 and the first cover insulating film 120. The first to third lower connection contacts LCO1, LCO2, LCO3 can include a conductive material.

[0055] An upper stacked structure USS can be provided on the interlayer insulating film 130. The upper stacked structure USS can include an upper word line UWL, an upper channel film UCL, a gate insulating film GI, an intervening insulating pattern IIP, a first capping pattern CP1, a second capping pattern CP2, an upper bit line UBL, an upper data storage structure UDS, and a second cover insulating film 140.

[0056] Although the semiconductor device is illustrated as including a lower stacked structure LSS and an upper stacked structure USS, the present invention is not limited thereto. In some embodiments, the semiconductor device can include a first stacked structure, a second stacked structure on the first stacked structure, and a third stacked structure on the second stacked structure. The semiconductor device can include a connecting conductive line between the first and second stacked structures and a connecting conductive line between the second and third stacked structures. In some embodiments, the semiconductor device can include four or more stacked structures.

[0057] An upper data storage structure UDS can be provided on the interlayer insulating film 130. The upper data storage structure UDS can be superimposed on the lower data storage structure LDS along the third direction D3. The upper data storage structure UDS can be a capacitor including a first electrode EL1, a second electrode EL2, and a capacitor insulating film CI.

[0058] In some embodiments, the upper data storage structure UDS can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse.

[0059] The upper bit line UBL can be provided on the interlayer insulating film 130. The upper bit line UBL can extend in the third direction D3. The upper bit line UBL can be superimposed on the lower bit line LBL along the third direction D3. The upper bit line UBL can include a conductive material.

[0060] The upper word line UWL can be provided between the upper bit line UBL and the upper data storage structure UDS. The upper word line UWL can be superimposed on the lower word line LWL along the third direction D3. The upper word line UWL can include a first upper word line UWL1, a second upper word line UWL2, and a third upper word line UWL3 disposed on one side of the upper data storage structure UDS. The upper word line UWL can include a conductive material.

[0061] The first to third upper word lines UWL1, UWL2, and UWL3 can be superimposed on the first to third lower word lines LWL1, LWL2, and LWL3 along the third direction D3. The second upper word line UWL2 can be arranged at a higher level than the first upper word line UWL1. The third upper word line UWL3 can be arranged at a higher level than the second upper word line UWL2.

[0062] The upper channel film UCL can electrically connect the upper bit line UBL and the upper data storage structure UDS. The upper channel film UCL can extend in the second direction D2. Each of the upper channel films UCL can include a first source / drain region SD1, a channel region CH, and a second source / drain region SD2. The upper channel film UCL can include at least one of a single-crystalline semiconductor, a polycrystalline semiconductor, an oxide semiconductor, or a two-dimensional material.

[0063] The upper channel film UCL can include a first upper channel film UCL1 surrounded by the first upper word line UWL1, a second upper channel film UCL2 surrounded by the second upper word line UWL2, and a third upper channel film UCL3 surrounded by the third upper word line UWL3.

[0064] At least a part of the gate insulating film GI of the upper stacked structure USS can be provided between the upper word line UWL and the upper channel film UCL. The upper word line UWL and the upper channel film UCL can be separated by the gate insulating film GI of the upper stacked structure USS. The gate insulating film GI of the upper stacked structure USS can include an insulating material.

[0065] The first capping pattern CP1 of the upper stacked structure USS can be provided between the upper word line UWL and the upper bit line UBL. The upper word line UWL and the upper bit line UBL can be separated by the first capping pattern CP of the upper stacked structure USS. The first capping pattern CP1 of the upper stacked structure USS can include an insulating material.

[0066] The second capping pattern CP2 of the upper stacked structure USS can be provided between the upper word line UWL and the upper data storage structure UDS. The upper word line UWL and the upper data storage structure UDS can be separated by the second capping pattern CP2 of the upper stacked structure USS. The second capping pattern CP2 of the upper stacked structure USS can include an insulating material.

[0067] The upper bit line UBL, the upper data storage structure UDS, and the upper channel film UCL can be arranged in the cell region CR. Each of the upper word lines UWL can include a first upper electrode portion UEP1 arranged in the cell region CR and a second upper electrode portion UEP2 arranged in the connection region OR.

[0068] The first upper electrode portion UEP1 can extend in the first direction D1. The first upper electrode portion UEP1 can surround the upper channel film UCL. The upper channel film UCL can extend in the second direction D2 and penetrate the first upper electrode portion UEP1. The first upper electrode portions UEP1 of the first to third upper word lines UWL1, UWL2, UWL3 can be superimposed in the third direction D3.

[0069] The second upper electrode part UEP2 can extend in the second direction D2. The second upper electrode part UEP2 of the first to third upper word lines UWL1, UWL2, UWL3 can be superimposed in the third direction D3. The length L4 of the second upper electrode part UEP2 of the first upper word line UWL1 in the second direction D2 may be greater than the length L5 of the second upper electrode part UEP2 of the second upper word line UWL2 in the second direction D2 and the length L2 of the second lower electrode part LEP2 of the second lower word line LWL2 in the second direction D2. The length L5 of the second upper electrode part UEP2 of the second upper word line UWL2 in the second direction D2 may be greater than the length L6 of the second upper electrode part UEP2 of the third upper word line UWL3 in the second direction D2 and the length L3 of the second lower electrode part LEP2 of the third lower word line LWL3 in the second direction D2.

[0070] The intervening insulating pattern IIP of the upper stacked structure USS can be provided between the upper word lines UWL. The intervening insulating pattern IIP of the upper stacked structure USS can be provided between the first electrodes EL1 of the upper data storage structure UDS. The intervening insulating pattern IIP of the upper stacked structure USS can include an insulating material.

[0071] The second cover insulating film 140 can surround the upper bit line UBL, the upper word line UWL, the upper data storage structure UDS, and the upper channel film UCL. The second cover insulating film 140 can include an insulating material. In some embodiments, the second cover insulating film 140 can include a plurality of insulating films.

[0072] The upper insulating film 150 can be provided on the upper stacked structure USS. The upper insulating film 150 can include an insulating material. In some embodiments, the upper insulating film 150 can include a plurality of insulating films.

[0073] In the upper insulating film 150, an upper bit line contact UBC, an upper data contact UDC, an upper bit line connection line UBO, an upper data connection line UDO, a first upper conductive line UL1, a second upper conductive line UL2, a third upper conductive line UL3, a fourth upper conductive line UL4, a fifth upper conductive line UL5, and a sixth upper conductive line UL6 can be provided. The upper bit line contact UBC, the upper data contact UDC, the upper bit line connection line UBO, the upper data connection line UDO, the first upper conductive line UL1, the second upper conductive line UL2, the third upper conductive line UL3, the fourth upper conductive line UL4, the fifth upper conductive line UL5, and the sixth upper conductive line UL6 can include a conductive material. In some embodiments, the upper bit line connection line UBO, the upper data connection line UDO, the first upper conductive line UL1, the second upper conductive line UL2, the third upper conductive line UL3, the fourth upper conductive line UL4, the fifth upper conductive line UL5, and the sixth upper conductive line UL6 can be arranged at the same level.

[0074] The upper bit line contact UBC can be connected to the upper bit line UBL. The upper bit line connection line UBO can be connected to the upper bit line contact UBC. The upper data contact UDC can be connected to the upper data storage structure UDS. The upper data connection line UDO can be connected to the lower data contact UDC.

[0075] A first through contact CON1 connecting a first upper conductive line UL1 and a first connecting conductive line CL1, a second through contact CON2 connecting a second upper conductive line UL2 and a second connecting conductive line CL2, a third through contact CON3 connecting a third upper conductive line UL3 and a third connecting conductive line CL3, a first upper connecting contact UCO1 connecting a fourth upper conductive line UL4 and a second upper electrode portion UEP2 of a first upper word line UWL1, a second upper connecting contact UCO2 connecting a fifth upper conductive line UL5 and a second upper electrode portion UEP2 of a second upper word line UWL2, and a third upper connecting contact UCO3 connecting a sixth upper conductive line UL6 and a second upper electrode portion UEP2 of a third upper word line UWL3 can be provided.

[0076] The first to third upper connecting contacts UCO1, UCO2, UCO3 and the first to third through contacts CON1, CON2, CON3 can extend in a third direction. The first to third upper connecting contacts UCO1, UCO2, UCO3 can extend through an upper insulating film 150 and a second cover insulating film 140. The first to third through contacts CON1, CON2, CON3 can penetrate an upper stacked structure USS. The first to third through contacts CON1, CON2, CON3 can extend through an upper insulating film 150, a second cover insulating film 140, and an interlayer insulating film 130. The first to third upper connecting contacts UCO1, UCO2, UCO3 and the first to third through contacts CON1, CON2, CON3 can include a conductive material.

[0077] The first lower word line LWL1 can be electrically connected to the first upper conductive line UL1 through the first lower connection contact LCO1, the first connection conductive line CL1, and the first through contact CON1. The second lower word line LWL2 can be electrically connected to the second upper conductive line UL2 through the second lower connection contact LCO2, the second connection conductive line CL2, and the second through contact CON2. The third lower word line LWL3 can be electrically connected to the third upper conductive line UL3 through the third lower connection contact LCO3, the third connection conductive line CL3, and the third through contact CON3.

[0078] The first upper word line UWL1 can be electrically connected to the fourth upper conductive line UL4 through the first upper connection contact UCO1. The second upper word line UWL2 can be electrically connected to the fifth upper conductive line UL5 through the second upper connection contact UCO2. The third upper word line UWL3 can be electrically connected to the sixth upper conductive line UL6 through the third upper connection contact UCO3.

[0079] The first to third lower connection contacts LCO1, LCO2, LCO3, the first to third through contacts CON1, CON2, CON3, and the first to third upper connection contacts UCO1, UCO2, UCO3 can be arranged in the connection region OR.

[0080] Referring to FIGS. 3B, 3C, and 3E, each of the first to third connection conductive lines CL1, CL2, CL3 can include a first portion P1 extending in the first direction D1 and a second portion P2, and a third portion P3 extending in the second direction D2. The third portion P3 can connect the first portion P1 and the second portion P2.

[0081] The lower surface of the first portion P1 of the first connecting conductive line CL1 can be in contact with the upper surface of the first lower connecting contact LCO1. The lower surface of the first portion P1 of the second connecting conductive line CL2 can be in contact with the upper surface of the second lower connecting contact LCO2. The lower surface of the first portion P1 of the third connecting conductive line CL3 can be in contact with the upper surface of the third lower connecting contact LCO3. The upper surface of the second portion P2 of the first connecting conductive line CL1 can be in contact with the lower surface of the first through contact CON1. The upper surface of the second portion P2 of the second connecting conductive line CL2 can be in contact with the lower surface of the second through contact CON2. The upper surface of the second portion P2 of the third connecting conductive line CL3 can be in contact with the lower surface of the third through contact CON3.

[0082] The first portions P1 of the first to third connecting conductive lines CL1, CL2, and CL3 can be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the first upper word line UWL1 and the second lower electrode portion LEP2 of the first lower word line LWL1.

[0083] The first portions P1 of the second and third connecting conductive lines CL2 and CL3 can be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the second upper word line UWL2 and the second lower electrode portion LEP2 of the second lower word line LWL2. The first portion P1 of the first connecting conductive line CL1 does not have to be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the second upper word line UWL2 and the second lower electrode portion LEP2 of the second lower word line LWL2.

[0084] The first portion P1 of the third connecting conductive line CL3 can be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the third upper word line UWL3 and the second lower electrode portion LEP2 of the third lower word line LWL3. The first portions P1 of the first and second connecting conductive lines CL1 and CL2 do not have to be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the third upper word line UWL3 and the second lower electrode portion LEP2 of the third lower word line LWL3.

[0085] The first connecting conductive line CL1 can be disposed between the first and second portions P1, P2 of the second connecting conductive line CL2. The first and second connecting conductive lines CL1, CL2 can be disposed between the first and second portions P1, P2 of the third connecting conductive line CL3.

[0086] The first to third lower connecting contacts LCO1, LCO2, LCO3, and the first to third upper connecting contacts UCO1, UCO2, UCO3 can be superimposed along a third direction D3 on the second upper electrode portion UEP2 of the first upper word line UWL1 and the second lower electrode portion LEP2 of the first lower word line LWL1.

[0087] The second and third lower connecting contacts LCO2, LCO3, and the second and third upper connecting contacts UCO2, UCO3 can be superimposed along a third direction D3 on the second upper electrode portion UEP2 of the second upper word line UWL2 and the second lower electrode portion LEP2 of the second lower word line LWL2. The first lower connecting contact LCO1 and the first upper connecting contact UCO1 may not be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the second upper word line UWL2 and the second lower electrode portion LEP2 of the second lower word line LWL2.

[0088] The third lower connecting contact LCO3 and the third upper connecting contact UCO3 can be superimposed along a third direction D3 on the second upper electrode portion UEP2 of the third upper word line UWL3 and the second lower electrode portion LEP2 of the third lower word line LWL3. The first and second lower connecting contacts LCO1, LCO2, and the first and second upper connecting contacts UCO1, UCO2 may not be superimposed along the third direction D3 on the second upper electrode portion UEP2 of the third upper word line UWL3 and the second lower electrode portion LEP2 of the third lower word line LWL3.

[0089] The first to third through contacts CON1, CON2, and CON3 do not necessarily need to overlap with the upper word line UWL and the lower word line LWL along the third direction D3. The second portions P2 of the first to third connecting conductive lines CL1, CL2, and CL3 do not necessarily need to overlap with the upper word line UWL and the lower word line LWL along the third direction D3.

[0090] In some embodiments, the first lower connecting contact LCO1 and the first upper connecting contact UCO1 can be overlapped in the third direction D3.

[0091] The length of the second connecting conductive line CL2 may be greater than the length of the first connecting conductive line CL1. The length of the third connecting conductive line CL3 may be greater than the length of the second connecting conductive line CL2.

[0092] The lengths of the first and second portions P1 and P2 of the first connecting conductive line CL1 in the first direction D1 may be smaller than the lengths of the first and second portions P1 and P2 of the second connecting conductive line CL2 in the first direction D1. The lengths of the first and second portions P1 and P2 of the second connecting conductive line CL2 in the first direction D1 may be smaller than the lengths of the first and second portions P1 and P2 of the third connecting conductive line CL3 in the first direction D1.

[0093] The length of the third portion P3 of the first connecting conductive line CL1 in the second direction D2 may be smaller than the length of the third portion P3 of the second connecting conductive line CL2 in the second direction D2. The length of the third portion P3 of the second connecting conductive line CL2 in the second direction D2 may be smaller than the length of the third portion P3 of the third connecting conductive line CL3 in the second direction D2.

[0094] The third portions P3 of the first to third connecting conductive lines CL1, CL2, and CL3 can be arranged in the cell region CR. The first and second portions P1 and P2 of the first to third connecting conductive lines CL1, CL2, and CL3 can extend to the connection region OR in the cell region CR.

[0095] In some embodiments, the first connecting conductive line CL1 can have a line shape extending in the second direction D2.

[0096] The length of the first lower connecting contact LCO1 in the third direction D3 may be greater than the length of the second lower connecting contact LCO2 in the third direction D3. The length of the second lower connecting contact LCO2 in the third direction D3 may be greater than the length of the third lower connecting contact LCO3 in the third direction D3. The length of the first upper connecting contact UCO1 in the third direction D3 may be greater than the length of the second upper connecting contact UCO2 in the third direction D3. The length of the second upper connecting contact UCO2 in the third direction D3 may be greater than the length of the third upper connecting contact UCO3 in the third direction D3. The lengths of the first to third through contacts CON1, CON2, CON3 in the third direction D3 may be greater than the lengths of the first to third lower connecting contacts LCO1, LCO2, LCO3 and the first to third upper connecting contacts UCO1, UCO2, UCO3 in the third direction D3. In some embodiments, the lengths of the first to third through contacts CON1, CON2, CON3 in the third direction D3 can be the same.

[0097] In some embodiments, the first to third connecting conductive lines CL1, CL2, CL3 can be superimposed along the third direction D3 on at least one of the upper channel film UCL, the lower channel film LCL, the upper data storage structure UDS, or the lower data storage structure LDS.

[0098] The distance in the second direction D2 between the first lower connecting contact LCO1 and the first through contact CON1 may be smaller than the distance in the second direction D2 between the second lower connecting contact LCO2 and the first through contact CON1. The distance in the second direction D2 between the first through contact CON1 and the second upper electrode portion UEP2 of the first upper word line UWL1 may be smaller than the distance in the second direction D2 between the first through contact CON1 and the first upper connecting contact UCO1 and the distance in the second direction D2 between the first through contact CON1 and the first lower connecting contact LCO1.

[0099] According to some embodiments, a semiconductor device includes an interlayer insulating film and a connecting conductive line, so that a lower word line superimposed on an upper word line can be electrically connected to an upper conductive line. Accordingly, the area occupied by the connection region can be minimized, and the size of the semiconductor device can be minimized. In addition, the wiring freedom degree of the semiconductor device can be improved, and the difficulty level of the manufacturing process of the semiconductor device can be improved.

[0100] FIG. 4 is a plan view showing a connecting conductive line of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 4 may be similar to the semiconductor device according to FIGS. 3A to 3E except as described below.

[0101] Referring to FIG. 4, the first connecting conductive line CL1a can have a line or bar shape extending in the second direction D2. The first connecting conductive line CL1a can be disposed in the connection region OR. The first portion P1a, the second portion P2a, and the third portion P3a of the second connecting conductive line CL2a can be disposed in the connection region OR. The third portion P3a of the third connecting conductive line CL3a can be disposed in the cell region CR. The first portion P1a and the second portion P2a of the third connecting conductive line CL3a can extend to the connection region OR in the cell region CR.

[0102] The first connecting conductive line CL1a can be disposed between the third portion P3a of the second connecting conductive line CL2a and the third portion P3a of the third connecting conductive line CL3a. The first and second portions P1a, P2a of the second connecting conductive line CL2a and the first and second portions P1a, P2a of the third connecting conductive line CL3a can be disposed between the third portion P3a of the second connecting conductive line CL2a and the third portion P3a of the third connecting conductive line CL3a.

[0103] FIGS. 5A and 5B are cross-sectional views of a semiconductor device according to some embodiments. The semiconductor device according to FIGS. 5A and 5B may be similar to the semiconductor device according to FIGS. 3A to 3E except as described below.

[0104] Referring to FIGS. 5A and 5B, a peripheral transistor PTR can be provided between a substrate SUB and a lower insulating film 110. The peripheral transistor PTR can include an impurity region 211, a peripheral gate insulating film 212, and a peripheral gate electrode 213. The impurity region 211 can be formed by doping impurities into the substrate SUB. The peripheral gate insulating film 212 can include an insulating material. The peripheral gate electrode 213 can include a conductive material.

[0105] A first bonding insulating film BI1 can be provided on the lower insulating film 110. A second bonding insulating film BI2 can be provided on the first bonding insulating film BI1. A first cover insulating film 215 can be provided on the second bonding insulating film BI2. A second cover insulating film 240 can be provided on the first cover insulating film 215. The second cover insulating film 240 can surround a bit line BLb, a channel film CLb, a word line WLb, and a data storage structure DSb. The data storage structure DSb can include a first electrode EL1b, a capacitor insulating film CIb, and a second electrode EL2b. The first bonding insulating film BI1, the second bonding insulating film BI2, the first cover insulating film 215, and the second cover insulating film 240 can include an insulating material.

[0106] A first contact 214 can be provided in the lower insulating film 110. A first bonding pad BP1 can be provided in the first bonding insulating film BI1. A second bonding pad BP2 can be provided in the second bonding insulating film BI2. A second contact 216 can be provided in the first cover insulating film 215. The first contact 214, the second contact 216, the first bonding pad BP1, and the second bonding pad BP2 can include a conductive material.

[0107] The first bonding insulating film BI1 and the first bonding pad BP1 can be hybrid bonded to the second bonding insulating film BI2 and the second bonding pad BP2. The first bonding insulating film BI1 can be bonded to the second bonding insulating film BI2 through a wafer bonding process. The first bonding pad BP1 can be bonded to the second bonding pad BP2 through a wafer bonding process.

[0108] A bit line contact BCb, a bit line connection line BOb, a data contact DCb, a data connection line DOb, and an upper conductive line UL can be provided in the upper insulating film 150.

[0109] The word line WLb can include a first electrode portion EP1b and a second electrode portion EP2b. A through-insulating pattern 230 penetrating the second electrode portion EP2b can be provided. The through-insulating pattern 230 can have a ring shape. The through-insulating pattern 230 can include an insulating material.

[0110] A connection contact 220 can be provided. The connection contact 220 can connect the upper conductive line UL and the second bonding pad BP2. The connection contact 220 can extend through the upper insulating film 150, the second cover insulating film 240, and the first cover insulating film 215. The connection contact 220 can extend in a third direction D3. The connection contact 220 can include a conductive material.

[0111] The connection contact 220 can include a connection part 221, a lower part 222, and an upper part 223. A connection part 221 can be provided between the lower part 222 and the upper part 223 of the connection contact 220. The connection part 221 of the connection contact 220 can be in contact with the second electrode part EP2b. The lower part 222 of the connection contact 220 can be in contact with the second bonding pad BP2. The upper part 223 of the connection contact 220 can be in contact with the upper conductive line UL. At least one of the upper part 223 or the lower part 222 of the connection contact 220 can penetrate through the through-insulation pattern 230 and the word line WLb.

[0112] The width of the connection part 221 of the connection contact 220 may be larger than the widths of the lower part 222 and the upper part 223 of the connection contact 220. As an example, the width of the connection part 221 of the connection contact 220 in the second direction D2 may be larger than the widths of the lower part 222 and the upper part 223 of the connection contact 220 in the second direction D2.

[0113] The bit line BLb can be electrically connected to the peripheral transistor PTR through the second contact 216, the second bonding pad BP2, the first bonding pad BP1, and the first contact 214. The bit line BLb can be electrically connected to the bit line connection line BOb through the bit line contact BCb.

[0114] The data storage structure DSb can be electrically connected to the peripheral transistor PTR through the second contact 216, the second bonding pad BP2, the first bonding pad BP1, and the first contact 214. The data storage structure DSb can be electrically connected to the data connection line DOb through the data contact DCb.

[0115] The word line WLb can be electrically connected to the upper conductive line UL through the connection contact 220. The word line WLb can be electrically connected to the peripheral transistor PTR through the connection contact 220, the second bonding pad BP2, the first bonding pad BP1, and the first contact 214.

[0116] The word line WLb can include a first word line WL1b, a second word line WL2b on the first word line WL1b, and a third word line WL3b on the second word line WL2b. The channel film CLb can include a first channel film CL1b that penetrates the first electrode portion EP1b of the first word line WL1b, and a second channel film CL2b that penetrates the first electrode portion EP1b of the second word line WL2b. The through-insulating pattern 230 can include a first through-insulating pattern 230a that penetrates the second electrode portion EP2b of the first word line WL1b, a second through-insulating pattern 230b that penetrates the second electrode portion EP2b of the second word line WL2b, and a third through-insulating pattern 230c that penetrates the second electrode portion EP2b of the third word line WL3b.

[0117] The connection contact 220 can include a first connection contact 220a that is electrically connected to the first word line WL1b and a second connection contact 220b that is electrically connected to the second word line WL2b.

[0118] The upper portion 223 of the first connection contact 220a can penetrate through the second electrode portion EP2b of the second word line WL2b, the second through-insulating pattern 230b, the second electrode portion EP2b of the third word line WL3b, and the third through-insulating pattern 230c. The lower portion 222 of the second connection contact 220b can penetrate through the second electrode portion EP2b of the first word line WL1b and the first through-insulating pattern 230a. The upper portion 223 of the second connection contact 220b can penetrate through the second electrode portion EP2b of the third word line WL3b and the third through-insulating pattern 230c. The thickness of the connection portion 221 of the first connection contact 220a in the third direction D3 can be the same as the thickness of the second electrode portion EP2b of the first word line WL1b in the third direction D3. The thickness of the first through-insulating pattern 230a in the third direction D3 can be the same as the thickness of the second electrode portion EP2b of the first word line WL1b in the third direction D3.

[0119] FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 6 may be similar to the semiconductor device according to FIGS. 3A to 3E, except as described below.

[0120] Referring to FIG. 6, the semiconductor device can include a cover insulating film 340 on the lower insulating film 110. The first word line WL1c, the second word line WL2c, and the third word line WL3c surrounded by the cover insulating film 340 can be provided. The second word line WL2c can be disposed on the first word line WL1c. The third word line WL3c can be disposed on the second word line WL2c.

[0121] The first connection contact 310 and the second connection contact 320 can be provided. Each of the third word line WL3c and the second word line WL2c can be electrically connected to the upper conductive line UL through the first connection contact 310.

[0122] The second connection contact 320 can include a lower contact 321, a conductive pattern 322, and an upper contact 323. The heights of the upper contacts 323 can be the same. The heights of the lower contacts 321 can be different from each other. The conductive pattern 322 can be disposed at the same level as the second word line WL2b. The thickness of the conductive pattern 322 in the third direction D3 can be the same as the thickness of the second word line WL2c in the third direction D3. The width of the conductive pattern 322 may be larger than the widths of the upper contact 323 and the lower contact 321.

[0123] FIG. 7 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 7 can be similar to the semiconductor device according to FIGS. 3A to 3E, except as described below.

[0124] Referring to FIG. 7, the semiconductor device can include a cover insulating film 440 on the lower insulating film 110. A word line WLd surrounded by the cover insulating film 440 can be provided. A through insulating pattern 430 penetrating the word line WLd can be provided.

[0125] A first connection contact 410 and a second connection contact 420 can be provided. The first connection contact 410 can penetrate at least one through insulating pattern 430 and at least one word line WLd. The first connection contact 410 can be electrically connected to the word line WLd. The second connection contact 420 can be electrically connected to the word line WLd disposed at the uppermost part among the word lines WLd. The second connection contact 420 may not penetrate the through insulating pattern 430 and the word line WLd.

[0126] FIG. 8 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 8 can be similar to the semiconductor device according to FIGS. 3A to 3E, except as described below.

[0127] Referring to FIG. 8, the semiconductor device may include a cover insulating film 540 on the lower insulating film 110. A word line WLe surrounded by the cover insulating film 540 may be provided.

[0128] The word line WLe may include a first portion 511 and a second portion 512. The first portion 511 of the word line WLe may extend in the second direction D2. The second portion 512 of the word line WLe may extend in the fourth direction D4. The fourth direction D4 may intersect the first direction D1, the second direction D2, and the third direction D3. The fourth direction D4 may intersect the vertical direction and the horizontal direction. The fourth direction D4 may be a direction inclined with respect to the upper surface of the substrate SUB.

[0129] The word line WLe may be electrically connected to the upper conductive line UL through the connection contact 520. The connection contact 520 may be in contact with the second portion 512 of the word line WLe.

[0130] FIG. 9 is a plan view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 9 may be similar to the semiconductor device according to FIGS. 3A to 3E, except as described below.

[0131] Referring to FIG. 9, the semiconductor device can include a first stacked structure SS1f and a second stacked structure SS2f. The first stacked structure SS1f and the second stacked structure SS2f can be spaced apart from each other in the second direction D2. Each of the first and second stacked structures SS1f, SS2f can include a bit line BLf, a channel film CLf, a data storage structure DSf, and a word line WLf. The first and second stacked structures SS1f, SS2f can have a structure that is symmetric with respect to each other based on their centers. The bit line BLf, the channel film CLf, and the data storage structure DSf of the first stacked structure SS1f can be sequentially arranged along the second direction D2. The bit line BLf, the channel film CLf, and the data storage structure DSf of the second stacked structure SS2f can be sequentially arranged along the direction opposite to the second direction D2. The distance in the second direction D2 between the data storage structures DSf of the first and second stacked structures SS1f, SS2f may be smaller than the distance in the second direction D2 between the data storage structure DSf of the first stacked structure SS1f and the bit line BLf of the second stacked structure SS2f.

[0132] FIG. 10 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 10 can be similar to the semiconductor device according to FIGS. 3A to 3E, except as described below.

[0133] Referring to FIG. 10, the semiconductor device can include a first stacked structure SS1g and a second stacked structure SS2g. The first stacked structure SS1g and the second stacked structure SS2g can be spaced apart from each other in the second direction D2. Each of the first and second stacked structures SS1g, SS2g can include a bit line BLg, a channel film CLg, a data storage structure DSg, and a word line WLg. The bit lines BLg, channel films CLg, and data storage structures DSg of each of the first and second stacked structures SS1g, SS2g can be sequentially arranged along the second direction D2. The distance in the second direction D2 between the data storage structures DSg of the first and second stacked structures SS1g, SS2g may be greater than the distance in the second direction D2 between the data storage structure DSg of the first stacked structure SS1g and the bit line BLg of the second stacked structure SS2g.

[0134] As described above, embodiments of the present invention have been described with reference to the accompanying drawings. Those having ordinary knowledge in the technical field to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. Also, the embodiments of the present invention can be combined with each other.

Explanation of Reference Numerals

[0135] 110 Lower insulating film 120 First cover insulating film 130 Interlayer insulating film 140 Second cover insulating film 150 Upper insulating film EL1, EL2 Electrodes CI Capacitor insulating film CR Cell region GI Gate insulating film IIP Intervening insulating pattern CP1 First capping pattern CP2 Second capping pattern LBC Lower bit line contact LBL Lower Bit Line LBO Lower Data Link Line LCL Lower Channel Film LDC Lower Data Contact LDO Lower Data Link Line LBL Lower Bit Line LDS Lower Data Storage Structure LSS Lower Stacked Structure LWL Lower Word Line OR Connection Region UBC Upper Bit Line Contact UBL Upper Bit Line UBO Upper Data Link Line UCL Upper Channel Film UDC Upper Data Contact UDO Upper Data Link Line UBL Upper Bit Line UDS Upper Data Storage Structure USS Upper Stacked Structure UWL Upper Word Line

Claims

1. a lower stack structure including a first lower word line, a first lower channel layer passing through the first lower word line, and a lower data storage structure connected to the first lower channel layer; an interlayer insulating film on the lower laminate structure; an upper stack structure disposed on the interlayer insulating film, the upper stack structure including upper word lines, an upper channel film passing through the upper word lines, and an upper data storage structure connected to the upper channel film; a lower connection contact on the first lower word line; a connecting conductive line on the lower connecting contact; a through contact on the connecting conductive line, the lower connection contact overlaps the upper word line; The through contact does not overlap the upper word line.

2. The connecting conductive line is a first portion contacting an upper surface of the lower connecting contact; a second portion contacting a lower surface of the via contact; The semiconductor device according to claim 1 , further comprising: a third portion connecting said first portion and said second portion.

3. the first portion of the connecting conductive line overlaps the upper word line; The semiconductor device of claim 2 , wherein the second portion of the connecting conductive line does not overlap the upper word line.

4. the third portion of the connecting conductive line, the first lower channel film, and the upper channel film extend in a first direction; The semiconductor device of claim 2 , wherein the first and second portions of the connecting conductive line extend in a second direction intersecting the first direction.

5. The semiconductor device of claim 1 , wherein the lower connecting contact and the through contact are spaced apart in a horizontal direction.

6. The lower laminate structure includes: a second lower word line disposed at a level higher than the first lower word line; a second lower channel film passing through the second lower word line, The first lower word line is a first lower electrode portion surrounding the first lower channel film; a second lower electrode portion in contact with the lower connecting contact, The second lower word line is a first bottom electrode portion overlapping the first bottom electrode portion of the first bottom word line; a second bottom electrode portion overlapping the second bottom electrode portion of the first bottom word line, 2 . The semiconductor device of claim 1 , wherein a length of the second bottom electrode portion of the first bottom word line is greater than a length of the second bottom electrode portion of the second bottom word line.

7. The upper word line is a first upper electrode portion overlapping the first lower electrode portion of the first lower word line; a second upper electrode portion overlapping the second lower electrode portion of the first lower word line, The semiconductor device of claim 6 , wherein a length of the second upper electrode portion of the upper word line is greater than a length of the second lower electrode portion of the second lower word line.

8. The semiconductor device according to claim 1 , wherein the connecting conductive line is disposed in the interlayer insulating film.

9. a first lower word line; a first lower channel film passing through the first lower word line; a first lower connection contact contacting the first lower word line; a second lower word line disposed at a level higher than the first lower word line; a second lower channel film passing through the second lower word line; a second lower connection contact contacting the second lower word line; a first upper word line disposed at a level higher than the second lower word line; a first upper channel film passing through the first upper word line; a first upper connecting contact contacting the first upper word line; The first lower word line is a first lower electrode portion surrounding the first lower channel film; a second lower electrode portion in contact with the first lower connecting contact, The second lower word line is a first lower electrode portion surrounding the second lower channel film; a second lower electrode portion in contact with the second lower connecting contact, The first upper word line is a first upper electrode portion surrounding the first upper channel film; a second upper electrode portion in contact with the first upper connecting contact, a length of the second bottom electrode portion of the second bottom word line is smaller than a length of the second bottom electrode portion of the first bottom word line and a length of the second top electrode portion of the first top word line.

10. the first lower channel film, the second lower channel film, and the first upper channel film extend in a first direction; 10. The semiconductor device of claim 9, wherein a length of the second lower electrode portion of the second lower word line in the first direction is smaller than a length of the second lower electrode portion of the first lower word line in the first direction and a length of the second upper electrode portion of the first upper word line in the first direction.

11. a second upper word line disposed at a level higher than the first upper word line; a second upper channel film passing through the second upper word line; a second upper connecting contact contacting the second upper word line, The second upper word line is a first upper electrode portion surrounding the second upper channel film; a second upper electrode portion in contact with the second upper connecting contact, The semiconductor device of claim 9 , wherein a length of the second upper electrode portion of the second upper word line is smaller than a length of the second upper electrode portion of the first upper word line.

12. 10. The semiconductor device of claim 9, further comprising a lower bit line connected to the first and second lower channel layers.

13. a lower bit line contact on the lower bit line; a lower bit line connecting line on the lower bit line contact; a first connecting conductive line on the first lower connecting contact; a second connecting conductive line on the second lower connecting contact, 13. The semiconductor device of claim 12, wherein the lower bit line connecting line, the first connecting conductive line, and the second connecting conductive line are disposed at the same level.

14. an interlayer insulating layer surrounding the lower bit line connecting line, the first connecting conductive line, and the second connecting conductive line, The semiconductor device of claim 13 , wherein the interlayer insulating film is disposed between the first upper word line and the second lower word line.

15. 10. The semiconductor device of claim 9, wherein the first lower connection contact and the second lower connection contact overlap the second upper electrode portion of the first upper word line.

16. A lower laminate structure; an interlayer insulating film on the lower laminate structure; an upper laminate structure on the interlayer insulating film; an upper insulating film on the upper laminate structure; a first connecting conductive line and a second connecting conductive line in the interlayer insulating film; a first upper conductive line, a second upper conductive line, and a third upper conductive line in the upper insulating film; a first lower connection contact contacting a lower surface of the first connection conductive line; a second lower connection contact contacting a lower surface of the second connection conductive line; an upper connection contact electrically connecting the first upper conductive line and the upper stack structure; a first through contact contacting a lower surface of the second upper conductive line and an upper surface of the first connecting conductive line; a second through contact contacting a lower surface of the third upper conductive line and an upper surface of the second connecting conductive line, The lower laminate structure includes: a first lower word line contacting a lower surface of the first lower connection contact; a second lower word line contacting a lower surface of the second lower connection contact, The second connecting conductive line is a first portion in contact with an upper surface of the second lower connecting contact; a second portion in contact with a lower surface of the second via contact; The first connecting conductive line is disposed between the first and second portions of the second connecting conductive line.

17. The semiconductor device of claim 16 , wherein a length of the second connecting conductive line is greater than a length of the first connecting conductive line.

18. The semiconductor device of claim 16 , wherein a distance between the first bottom connection contact and the first via contact is smaller than a distance between the second bottom connection contact and the first via contact.

19. the upper stack structure includes an upper word line contacting a lower surface of the upper connection contact, 17. The semiconductor device of claim 16, wherein a distance between the first lower interconnect contact and the first via contact is greater than a distance between the first via contact and the upper word line.

20. The semiconductor device of claim 16 , wherein the upper interconnection contact and the first lower interconnection contact overlap.

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