Semiconductor device, semiconductor package including the same and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of contributing to chip size reduction and ensuring process stability, a semiconductor package including the semiconductor device, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device according to the present invention includes a first semiconductor chip of a first type and a second semiconductor chip of a second type which have rectangular shapes with the substantially same size. The first semiconductor chip and the second semiconductor chip are included in a plurality of semiconductor chips corresponding to 1-shot in an exposure process, the 1-shot meaning an area of a pattern transferred on a wafer through one exposure process using a mask. When the first semiconductor chip and the second semiconductor chip are arranged adjacent to each other in a first direction, the first semiconductor chip and the second semiconductor chip are mirror-symmetrical with respect to an axis in a second direction perpendicular to the first direction.SELECTED DRAWING: Figure 4B

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to two types of semiconductor devices, a semiconductor package including the semiconductor devices, and a method for manufacturing the semiconductor devices.

Background Art

[0002] As miniaturization, multifunctionality, and high performance of electronic products are required, high-capacity semiconductor memory devices are required. To provide high-capacity semiconductor memory devices, increased integration density is required, which has been a problem. Since the integration density of conventional two-dimensional (2D) semiconductor memory devices is mainly determined by the area occupied by a unit memory cell, the integration density of 2D semiconductor memory devices, although increasing, is still limited. Therefore, three-dimensional (3D) semiconductor memory devices have been developed in which a plurality of memory cells are stacked vertically on a substrate to increase the memory capacity. For example, in the case of VNAND (vertical NAND), it is already in commercial use.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention has been made in view of the problems in the above-described conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device that contributes to chip size reduction and ensures process stability, a semiconductor package including the semiconductor device, and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0004] The semiconductor device according to the present invention made to achieve the above object has a first semiconductor chip of a first type and a second semiconductor chip of a second type having a substantially identical rectangular shape, and the first semiconductor chip and the second semiconductor chip are included in a plurality of semiconductor chips corresponding to one shot in an exposure process, where the one shot means a region of a pattern transferred onto a wafer through one said exposure process using a mask, and when the first semiconductor chip and the second semiconductor chip are arranged adjacent to each other in a first direction, the first semiconductor chip and the second semiconductor chip are mirror-symmetric to each other with respect to an axis in a second direction orthogonal to the first direction.

[0005] The semiconductor package according to the present invention made to achieve the above object has a package substrate, a first semiconductor chip of a first type mounted on the package substrate, and a second semiconductor chip of a second type stacked on the first semiconductor chip, and the first semiconductor chip and the second semiconductor chip have a substantially identical rectangular shape, and the first semiconductor chip and the second semiconductor chip are mirror-symmetric to each other with respect to a reference line.

[0006] Further, the semiconductor package according to the present invention made to achieve the above object has a package substrate, at least one first semiconductor chip of a first type mounted on the package substrate, and at least one second semiconductor chip of a second type mounted on the package substrate, and the first semiconductor chip and the second semiconductor chip have a substantially identical rectangular shape, and the first semiconductor chip and the second semiconductor chip are mirror-symmetric to each other with respect to a reference line, and on the package substrate, the semiconductor chips of the first type and the semiconductor chips of the second type are alternately stacked.

[0007] A method for manufacturing a semiconductor device according to the present invention, which is made to achieve the above object, includes a step of preparing a mask, a step of forming a pattern on a wafer through an exposure process using the mask, a step of determining whether the semiconductor device is completed, and a step of singulating the wafer into a plurality of semiconductor chips when the semiconductor device is completed. When the semiconductor device is not completed, the method returns to the step of preparing the mask and further includes a step of preparing a mask corresponding to the next pattern. In the step of forming a pattern on the wafer, when the area of the pattern transferred through one exposure process is defined as one shot, the one shot has a structure including a plurality of mirror-symmetric semiconductor chips or a structure including a plurality of origin-symmetric semiconductor chips.

Advantages of the Invention

[0008] According to the semiconductor device, semiconductor package including the same, and method for manufacturing a semiconductor device according to the present invention, the semiconductor device includes first and second semiconductor chips of different types, the first and second semiconductor chips are manufactured by the same wafer, and when the first and second semiconductor chips are arranged side by side in the x direction, they have a mirror-symmetric structure about the axis in the y direction. Such a semiconductor device according to the present invention can improve process stability and ensure mass productivity by maintaining symmetry between chips within one shot during the process of manufacturing the semiconductor device. For reference, when there is asymmetry between semiconductor chips within one shot, when forming a structure with a high aspect ratio (aspect ratio: A / R), defects such as mold leaning, landslip, and 3D effects may occur. However, in the semiconductor device according to the present invention, by arranging an extended region on one side surface of the cell region, generally, an effect of chip size reduction (CSR) of 3% or more is expected compared to a structure in which extended regions are arranged on both side surfaces of the cell region.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Next, specific examples of embodiments for implementing a semiconductor element according to the present invention, a semiconductor package including the same, and a method for manufacturing the semiconductor element will be described with reference to the drawings. For the same components in the drawings, the same reference numerals are used, and redundant descriptions related thereto are omitted.

[0011] FIGS. 1A and 1B are a plan view and a cross-sectional view showing a schematic configuration of a semiconductor element according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line I-I' of FIG. 1A. Referring to FIGS. 1A and 1B, the semiconductor element 100 of the present embodiment includes two types of semiconductor chips. For example, the semiconductor element 100 of the present embodiment includes a first semiconductor chip 100L and a second semiconductor chip 100R. The first semiconductor chip 100L and the second semiconductor chip 100R have a mirror-symmetric structure with respect to the axis in the y direction. More specifically, the first semiconductor chip 100L includes a first cell region 110L (CA), a first extended region 120L (EXA), and a first peripheral region 130L (PA), and the second semiconductor chip 100R includes a second cell region 110R (CA), a second extended region 120R (EXA), and a second peripheral region 130R (PA).

[0012] The first semiconductor chip 100L and the second semiconductor chip 100R are arranged adjacent to each other in the x direction. When the long sides of the first semiconductor chip 100L and the second semiconductor chip 100R are arranged along the x direction, the first extended region 120L of the first semiconductor chip 100L is arranged on the left side of the first cell region 110L in the x direction, and the first peripheral region 130L of the first semiconductor chip 100L is arranged below the first cell region 110L and the first extended region 120L in the y direction. Also, the second extended region 120R of the second semiconductor chip 100R is arranged on the right side of the second cell region 110R in the x direction, and the second peripheral region 130R of the second semiconductor chip 100R is arranged below the second cell region 110R and the second extended region 120R in the y direction.

[0013] When a dashed-dotted line extending in the y direction between the first semiconductor chip 100L and the second semiconductor chip 100R is taken as the reference line RL, the first semiconductor chip 100L and the second semiconductor chip 100R are mirror-symmetrical with respect to the reference line RL. In addition, if the reference line RL is an axis in the y direction, it can also be said that the first semiconductor chip 100L and the second semiconductor chip 100R are mirror-symmetrical with respect to the axis in the y direction. Here, the meaning of the mirror symmetry between the first semiconductor chip 100L and the second semiconductor chip 100R is not limited to the mirror symmetry between the regions seen in the plane of FIG. 1A, and the components included in the first cell region 110L and the second cell region 110R can also be mirror-symmetrical to each other. Also, the components included in the first extended region 120L and the second extended region 120R are mirror-symmetrical to each other, and the components included in the first peripheral region 130L and the second peripheral region 130R can also be mirror-symmetrical to each other.

[0014] Regarding the vertical non-volatile memory element VNAND (vertical NAND), more specifically, generally, VNAND includes a vertical channel structure arranged in a two-dimensional array structure on a substrate of a cell region, and a stacked structure including a gate electrode layer and an interlayer insulating layer laminated with each other by sidewalls of the vertical channel structure on the substrate. In the cell region, the stacked structure extends in the x direction, and in the extended region, the gate electrode layer constitutes an electrode pad. In some embodiments, the electrode pad is also referred to as a word line pad. In the extended region, the electrode pad has a stepped structure. For example, the electrode pad extends shorter from the cell region as it gets farther from the substrate in the vertical direction, and extends longer from the cell region as it gets closer to the substrate.

[0015] Note that the peripheral region is disposed outside the cell region and the extended region, and a peripheral circuit is disposed in the peripheral region. The peripheral circuit includes a high-voltage transistor and / or a low-voltage transistor, and passive elements such as resistors and capacitors. In addition, the peripheral circuit includes wirings connected to the transistors and the passive elements. The wiring of the peripheral circuit is connected to the bit line in the cell region. In addition, the wiring of the peripheral circuit is connected to the electrode pad in the extended region.

[0016] In the case of the first semiconductor chip 100L which is a VNAND, in the first cell region 110L, the stacked structure extends leftward in the x direction, and in the first extended region 120L disposed on the left side of the first cell region 110L, an electrode pad having a stepped structure is formed. In the case of the second semiconductor chip 100R which is a VNAND, in the second cell region 110R, the stacked structure extends rightward in the x direction, and in the second extended region 120R disposed on the right side of the second cell region 110R, an electrode pad having a stepped structure is formed. In FIG. 1B, the stepped structures of the first extended region 120L and the second extended region 120R are simplified as inclined planes and shown in the figure for convenience.

[0017] The arrangement position of the vertical channel structure on the plane of the first cell region 110L is mirror-symmetrical with respect to the axis in the y direction to the arrangement position of the vertical channel structure on the plane of the second cell region 110R. In addition, the direction and length of the stacked structure extending from the first cell region 110L to the first extended region 120L are also mirror-symmetric with respect to the axis in the y direction to the direction and length of the stacked structure extending from the second cell region 110R to the second extended region 120R. Furthermore, since they are mirror-symmetric with respect to the axis in the y direction, the stepped structures of the first extended region 120L and the second extended region 120R have opposite inclinations to each other. Note that the first peripheral region 130L is disposed below the first cell region 110L and the first extended region 120L in the y direction. Also, since they are mirror-symmetric with respect to the axis in the y direction, the second peripheral region 130R is also disposed below the second cell region 110R and the second extended region 120R in the y direction. Furthermore, the positions and directions of the elements and wirings in the first peripheral region 130L are mirror-symmetric with respect to the axis in the y direction to the positions and directions of the elements and wirings in the second peripheral region 130R.

[0018] The first semiconductor chip 100L and the second semiconductor chip 100R of the semiconductor device 100 of the present embodiment are manufactured together on the same wafer. The principle that two types of mirror-symmetric first semiconductor chips 100L and second semiconductor chips 100R are manufactured from the same wafer is that when forming a pattern on the wafer through an exposure process, a plurality of semiconductor chips are arranged to be mirror-symmetric or arranged to be centrosymmetric with respect to one shot corresponding to the plurality of semiconductor chips. The mirror symmetry and centrosymmetry of the plurality of semiconductor chips within one shot will be described in detail in the description parts of FIGS. 4A to 10B.

[0019] For reference, one shot means the region of the pattern transferred onto the wafer through one exposure process using a mask. Note that in the final structure, it can be said that a plurality of semiconductor chips are mirror-symmetric or centrosymmetric within one shot. However, in the process of manufacturing a semiconductor device, on a certain layer where the exposure process is carried out, it can be said that the pattern corresponding to the semiconductor chip is mirror-symmetric or origin-symmetric within one shot.

[0020] The semiconductor device 100 of the present embodiment includes a first semiconductor chip 100L and a second semiconductor chip 100R of different types from each other. In addition, the first semiconductor chip 100L and the second semiconductor chip 100R are manufactured by the same wafer, and when the first semiconductor chip 100L and the second semiconductor chip 100R are arranged side by side in the x direction, they have a mirror-symmetric structure with respect to the axis in the y direction. Such a semiconductor device 100 of the present embodiment can improve process stability and ensure mass productivity by maintaining inter-chip symmetry within one shot in the process of manufacturing the semiconductor device.

[0021] For reference, when there is asymmetry between semiconductor chips within one shot, when forming a structure with a high aspect ratio A / R (aspect ratio: A / R), defects such as mold leaning, landslip, and 3D effects may occur. Here, the 3D effect refers to the effect that the staircase line is deformed during deep etching. In addition, in the semiconductor device 100 of the present embodiment, by arranging the extended region on one side surface of the cell region, generally, an effect of reducing the chip size (chip size reduction: CSR) by 3% or more can be expected compared to the structure in which the extended regions are arranged on both side surfaces of the cell region.

[0022] Incidentally, although a general VNAND has been described as an example above, the semiconductor device 100 of the present embodiment is not limited to a general VNAND. For example, the semiconductor device 100 of the present embodiment can be applied to all types of VNANDs including stepped electrode pads such as on / op mold VNAND, SEG (selective epitaxial growth)-oriented VNAND, COP (chip on peri) structure VNAND, BVNAND, or word line pads. For reference, in on / op mold, on mold means an oxide / nitride mold, and op mold means an oxide / polysilicon mold. Also, BVNAND is bonding VNAND, which means a structure in which two VNANDs are joined. Further, the semiconductor device 100 of the present embodiment is not limited to VNAND, and can be applied to all 3D semiconductor chips having stepped electrode pads.

[0023] Figs. 2A to 2E are plan views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. The contents already described in the description portions of Figs. 1A and 1B will be briefly described or omitted. Referring to Fig. 2A, the semiconductor device 100a of the present embodiment includes a first semiconductor chip 100La and a second semiconductor chip 100Ra. The first semiconductor chip 100La and the second semiconductor chip 100Ra are substantially the same as the first semiconductor chip 100L and the second semiconductor chip 100R in Fig. 1A. However, the first semiconductor chip 100La includes a first chip pad 140L on the front side of the chip, and the second semiconductor chip 100Ra includes a second chip pad 140R on the front side of the chip. Here, the front side of the chip means the upper surface side where the multilayer wiring layer is disposed when the substrate, integrated circuit, and multilayer wiring layer are sequentially disposed along the vertical direction, i.e., the z direction, and corresponds to the active surface. Also, the chip pad means an input / output terminal for connecting the multilayer wiring layer to the outside, and is connected to a wire, a bump, etc. when the semiconductor chip is mounted on a package substrate or the like.

[0024] In the semiconductor device 100a of the present embodiment, the first semiconductor chip 100La and the second semiconductor chip 100Ra are mirror-symmetrical with respect to the axis in the y direction, and the first chip pad 140L and the second chip pad 140R are also mirror-symmetrical with respect to the axis in the y direction. Specifically, when the first semiconductor chip 100La and the second semiconductor chip 100Ra are arranged adjacent to each other in the x direction and the long sides of the first semiconductor chip 100La and the second semiconductor chip 100Ra are arranged along the x direction, the first chip pad 140L is arranged along the x direction on the front surface of the chip corresponding to the first peripheral region 130L, and the second chip pad 140R is arranged along the x direction on the front surface of the chip corresponding to the second peripheral region 130R. The arrangement position and the arranged direction of the first chip pad 140L are mirror-symmetrical with respect to the axis in the y direction to the arrangement position and the arranged direction of the second chip pad 140R. In FIG. 2A, although the first chip pad 140L and the second chip pad 140R are each arranged in one row, the first chip pad 140L and the second chip pad 140R are not limited thereto and may be arranged in two or more rows.

[0025] Referring to FIG. 2B, the semiconductor device 100b of the present embodiment is different from the semiconductor device 100a of FIG. 2A in the arrangement position and the arranged direction of the chip pads (140La, 140Ra) of the first semiconductor chip 100Lb and the second semiconductor chip 100Rb, respectively. Specifically, the semiconductor device 100b of the present embodiment includes a first semiconductor chip 100Lb and a second semiconductor chip 100Rb. Further, when the first semiconductor chip 100Lb and the second semiconductor chip 100Rb are arranged adjacent to each other in the x direction and their respective long sides are arranged along the x direction, the first chip pad 140La of the first semiconductor chip 100Lb is arranged along the y direction on the front surfaces of the chips of the outer peripheral portions on both sides in the x direction, and the second chip pad 140Ra of the second semiconductor chip 100Rb is arranged along the y direction on the front surfaces of the chips of the outer peripheral portions on both sides in the x direction. The arrangement position and the arranged direction of the first chip pad 140La are mirror-symmetrical with respect to the axis in the y direction to the arrangement position and the arranged direction of the second chip pad 140Ra. In addition, in FIG. 2B, although each of the first chip pad 140La and the second chip pad 140Ra is arranged in one column in the x direction at both side outer portions, the first chip pad 140La and the second chip pad 140Ra are not limited thereto, and may be arranged in two or more columns in the x direction at both side outer portions. In addition, in some embodiments, the first chip pad 140La and the second chip pad 140Ra may be arranged along the y direction on the front surface of one of the outer portion chips in the x direction.

[0026] Referring to FIG. 2C, the semiconductor element 100c of the present embodiment is different from the semiconductor element 100a of FIG. 2A in the arrangement position and the arranged direction of the chip pads (140Lb, 140Rb) of the first semiconductor chip 100Lc and the second semiconductor chip 100Rc, respectively. Specifically, the semiconductor element 100c of the present embodiment includes a first semiconductor chip 100Lc and a second semiconductor chip 100Rc. In addition, when the first semiconductor chip 100Lc and the second semiconductor chip 100Rc are arranged adjacent to each other in the x direction and their long sides are arranged along the x direction, the first chip pad 140Lb of the first semiconductor chip 100Lc is arranged along the y direction on the front surface of the central portion chip in the x direction, and the second chip pad 140Rb of the second semiconductor chip 100Rc is arranged along the y direction on the front surface of the central portion chip in the x direction. The arrangement position and the arranged direction of the first chip pad 140Lb are mirror-symmetrical with respect to the axis in the y direction to the arrangement position and the arranged direction of the second chip pad 140Rb. In addition, in FIG. 2C, although the first chip pads 140Lb and the second chip pads 140Rb are each arranged in two columns in the central portion in the x direction, the first chip pads 140Lb and the second chip pads 140Rb are not limited thereto, and may be arranged in one column or three or more columns in the central portion in the x direction.

[0027] Referring to FIG. 2D, the semiconductor element 100d of the present embodiment is different from the semiconductor elements (100a to 100c) of FIGS. 2A to 2C in the arrangement positions of the chip pads (140L, 140Rc) of the first semiconductor chip 100L and the second semiconductor chip 100Rd, respectively. Specifically, in the semiconductor element 100d of the present embodiment, the arrangement structures of the cell regions (110L, 110R), the extension regions (120L, 120R), and the peripheral regions (130L, 130R) of the first semiconductor chip 100L and the second semiconductor chip 100Rd are substantially the same as the arrangement structures of the cell regions (110L, 110R), the extension regions (120L, 120R), and the peripheral regions (130L, 130R) of the first semiconductor chip 100L and the second semiconductor chip 100R in the semiconductor element 100 of FIG. 1A. However, the arrangement positions of the first chip pad 140L of the first semiconductor chip 100L and the second chip pad 140Rc of the second semiconductor chip 100Rd are different from each other and are not mirror-symmetric with respect to the axis in the y direction.

[0028] For example, in the semiconductor element 100d of the present embodiment, when the first semiconductor chip 100L and the second semiconductor chip 100Rd are arranged adjacent to each other in the x direction and their long sides are arranged along the x direction, the first chip pad 140L is arranged along the x direction on the front surface of the chip corresponding to the first peripheral region 130L, and the second chip pad 140Rc is arranged along the x direction on the front surface of the chip corresponding to the opposite side of the second peripheral region 130R in the y direction. Therefore, the arrangement position of the first chip pad 140L is not mirror-symmetric with the arrangement position of the second chip pad 140Rc with respect to the axis in the y direction. In FIG. 2D, although the first chip pads 140L and the second chip pads 140Rc are arranged in a single row, the first chip pads 140L and the second chip pads 140Ra are not limited thereto and may be arranged in two or more rows.

[0029] In the semiconductor device 100d of the present embodiment, the mirror-asymmetric structure between the first chip pad 140L of the first semiconductor chip 100L and the second chip pad 140Rc of the second semiconductor chip 100Rd is realized by configuring the patterns of the semiconductor chips within one shot corresponding thereto not to be mirror-symmetric when forming the chip pads of the semiconductor chips on the wafer and the wirings connected thereto through the exposure process. In other words, until the chip pads and the wirings are formed, all the corresponding patterns of the semiconductor chips within one shot are configured to be mirror-symmetric, but the patterns of the semiconductor chips within one shot corresponding to the chip pads and the wirings are configured not to be mirror-symmetric. In this way, the semiconductor device 100d of the present embodiment forms the first chip pad 140L of the first semiconductor chip 100L and the second chip pad 140Rc of the second semiconductor chip 100Rd not to be mirror-symmetric with respect to the axis in the y direction, so that when mounting the first semiconductor chip 100L and the second semiconductor chip 100Rd on the package substrate, the connection structure with wires or bumps can be configured more freely and diversely. As a result, in the semiconductor package, the degrees of freedom of the mounting structure of the semiconductor chips on the package substrate and the wiring structure within the package substrate can be greatly improved.

[0030] Referring to FIG. 2E, the semiconductor device 100e of the present embodiment is different from the semiconductor device 100d of FIG. 2D in the arrangement positions of the chip pads (140La, 140Rb) of the first semiconductor chip 100Lb and the second semiconductor chip 100Rc, respectively. Specifically, the semiconductor device 100e of the present embodiment includes the first semiconductor chip 100Lb and the second semiconductor chip 100Rc. Further, when the first semiconductor chip 100L and the second semiconductor chip 100Rc are arranged adjacent to each other in the x direction with their respective long sides arranged along the x direction, the first chip pad 140La of the first semiconductor chip 100Lb is arranged along the y direction on the front surfaces of the outer peripheral portion chips on both sides in the x direction, and the second chip pad 140Rb of the second semiconductor chip 100Rc is arranged along the y direction on the front surface of the central portion chip in the x direction. Thereby, the arrangement position of the first chip pad 140La is not mirror-symmetrical with the arrangement position of the second chip pad 140Rb with respect to the axis in the y direction. In addition, in FIG. 2E, the first chip pads 140L are arranged in one row in the outer peripheral portions on both sides in the x direction, and the second chip pads 140Rb are arranged in two rows in the central portion in the x direction. However, the number of rows of the first chip pads 140La and the second chip pads 140Rb is not limited thereto.

[0031] In the semiconductor elements (100d, 100e) of FIGS. 2D and 2E, the chip pads have been described for two types of structures that are not mirror-symmetrical with respect to the axis in the y direction. However, the structure of the chip pads of the semiconductor element of the present embodiment is not limited thereto. For example, in the semiconductor element of the present embodiment, the chip pads can be arranged in various other structures that are not mirror-symmetrical with respect to the axis in the y direction in addition to the two types of structures described above.

[0032] FIG. 3 is a flowchart for explaining a method of manufacturing a semiconductor element according to an embodiment of the present invention, and FIGS. 4A to 4C are a plan view and a cross-sectional view for explaining the concept of one-shot mirror symmetry in the method of manufacturing the semiconductor element of FIG. 3, and FIG. 4C is a cross-sectional view taken along the line II-II' of FIG. 4B. Referring to both FIGS. 1A and 1B for explanation, the content already explained in the description portions of FIGS. 1A to 2E will be briefly explained or omitted.

[0033] Referring to FIG. 3 and FIGS. 4A to 4C, the method of manufacturing the semiconductor element of the present embodiment first prepares a mask (step S110). In semiconductor manufacturing, an exposure process using a mask is performed to form a pattern on a semiconductor chip of a wafer. Simply defined, a mask can be said to be a pattern transfer body in which a pattern shape of an opaque material is formed on a transparent base material. The mask preparation process or mask manufacturing process includes layout design related to patterns, OPC (optical proximity correction), MTO (mask tape-out), MDP (mask data preparation), E-beam exposure, etc.

[0034] After mask preparation, a pattern is formed on the wafer through an exposure process using the mask (step S120). That is, through the exposure process using the mask, the same pattern is formed on a large number of semiconductor chips in the wafer. Generally, through one exposure process using a mask, the pattern transferred onto the wafer or the area of the pattern is called one shot, and within one shot, patterns corresponding to a plurality of semiconductor chips are included. Also, multiple exposure processes corresponding to multiple shots are carried out along the x-direction and the y-direction, and a pattern is formed over the entire wafer.

[0035] FIG. 4A is a plan view corresponding to one shot (1S), and an actual pattern is formed in the hatched portion at the center. For reference, the peripheral portion is an overlapping portion with an adjacent shot, and in some embodiments, alignment marks or the like are arranged. FIG. 4B shows the pattern included in one shot in a diagram with the concept of a semiconductor chip. In other words, within one shot, a plurality of patterns corresponding to a plurality of semiconductor chips are included. Hereinafter, for the sake of convenience of explanation, one pattern will be described with the concept of one semiconductor chip.

[0036] In the method for manufacturing a semiconductor device according to the present embodiment, a plurality of semiconductor chips are included within one shot. Also, within one shot, two semiconductor chips are arranged adjacent to each other in the x direction, and two or more, for example, four semiconductor chips are arranged in the y direction. In FIG. 4B, the semiconductor chip represented by the circled number 1 corresponds to the first semiconductor chip 100L, and the semiconductor chip represented by the circled number 2 corresponds to the second semiconductor chip 100R. Thereby, each of the semiconductor chips represented by the circled number 1 has, as described for the first semiconductor chip 100L, the first extension region 120L arranged on the left side of the first cell region 110L in the x direction, and the first peripheral region 130L arranged below the first cell region 110L in the y direction. Also, each of the semiconductor chips represented by the circled number 2 has, as described for the second semiconductor chip 100R, the second extension region 120R arranged on the right side of the second cell region 110R in the x direction, and the second peripheral region 130R arranged below the second cell region 110R in the y direction.

[0037] In the method for manufacturing a semiconductor device according to the present embodiment, the semiconductor chips represented by the circled number 1 and the semiconductor chips represented by the circled number 2 included within one shot are mirror-symmetrical with respect to the reference line RL, that is, the axis in the y direction. More precisely, the patterns corresponding to the semiconductor chips, which are formed in the exposure process of the layer, are mirror-symmetrical with respect to the reference line RL. The mirror symmetry is as described in the description part of FIGS. 1A and 1B. Furthermore, since the extended region having a stepped structure is not formed in the initial semiconductor device, the cross-sectional view of FIG. 4C corresponds to the cross-sectional view of the semiconductor device after the extended region having a stepped structure is formed. Note that in some embodiments, in the step of forming a pattern on the wafer (step S120), the structure in which the semiconductor chips within one shot are mirror-symmetrical with respect to the reference line RL does not hold for the chip pads and the wirings connected to the chip pads. For example, as described with the semiconductor elements (100d, 100e) in FIGS. 2D and 2E, the pattern within one shot corresponding to the first chip pads (140L, 140La) of the first semiconductor chip (100L, 100Lb) is not mirror-symmetric with the pattern within one shot corresponding to the second chip pads (140Rc, 140Rb) of the second semiconductor chip (100Rd, 100Rc).

[0038] After forming a pattern on the wafer, it is determined whether the semiconductor element is completed (step S130). Generally, in order to complete a semiconductor element, patterns must be formed in several tens to several hundreds of layers, and the pattern of each layer is formed using a corresponding mask. Also, since at least one mask is required to form the pattern of one layer, a larger number of masks than the number of layers is required to form the patterns of all layers. If the semiconductor element is not completed (No), the process proceeds to the step of preparing a mask (step S110), a mask corresponding to the next pattern is prepared, and the subsequent steps are further executed. If the semiconductor element is completed (Yes), the wafer is individualized into a plurality of semiconductor chips (step S140). The individualization of the wafer is executed through a sawing process. In FIG. 4B, the narrow region between adjacent semiconductor chips corresponds to the scribe lane region. The sawing process is advanced by executing a cutting process using a blade, a laser, or the like on the scribe lane region.

[0039] Through the individualization into semiconductor chips, the semiconductor element 100 in FIG. 1A is completed. The semiconductor element 100 includes a first semiconductor chip 100L corresponding to the circled number 1 and a second semiconductor chip 100R corresponding to the circled number 2. When the semiconductor chips on the wafer corresponding to all the shots are completed into semiconductor elements, the semiconductor chips manufactured by one wafer include the same number of first semiconductor chips 100L and second semiconductor chips 100R.

[0040] FIGS. 5A and 5B are plan views showing other forms of a mirror-symmetric one-shot. Referring to FIG. 5A, in the method of manufacturing a semiconductor element of the present embodiment, although the semiconductor chips within one shot are mirror-symmetric with respect to the reference line RL, they are mirror-symmetric in a different manner from FIG. 4B. Specifically, within one shot, the first semiconductor chip 100L represented by the circled number 1 is arranged on the right side in the x direction, and the second semiconductor chip 100R represented by the circled number 2 is arranged on the left side in the x direction. As described previously, in the first semiconductor chip 100L, the first extended region 120L is arranged on the left side of the first cell region 110L in the x direction, and the first peripheral region 130L is arranged below the first cell region 110L in the y direction. Also, in the second semiconductor chip 100R, the second extended region 120R is arranged on the right side of the second cell region 110R in the x direction, and the second peripheral region 130R is arranged below the second cell region 110R in the y direction.

[0041] In the method of manufacturing a semiconductor element of the present embodiment, within one shot, the first semiconductor chip 100L and the second semiconductor chip 100R are mirror-symmetric with respect to the reference line RL. However, within one shot in FIG. 4B, the first cell region 110L and the second cell region 110R are adjacent to each other in the x direction. In the method of manufacturing a semiconductor element of the present embodiment, due to the change in the positions of the first semiconductor chip 100L and the second semiconductor chip 100R within one shot, in one shot of FIG. 5A, the first extended region 120L and the second extended region 120R are adjacent to each other in the x direction.

[0042] Referring to FIG. 5B, in the method for manufacturing a semiconductor device according to the present embodiment, the number of semiconductor chips within one shot is different from the number of semiconductor chips within one shot in FIG. 4B. Specifically, within one shot, five first semiconductor chips 100L and five second semiconductor chips 100R are arranged in the y direction, respectively. However, the number of semiconductor chips arranged within one shot is not limited thereto. For example, within one shot, various numbers of two or more semiconductor chips are arranged in the y direction, and there is no limitation to even or odd numbers. However, based on the mirror symmetry with respect to the reference line RL, two first semiconductor chips 100L and two second semiconductor chips 100R are arranged in the x direction within one shot. However, in some embodiments, in the x direction within one shot, the first semiconductor chip 100L and the second semiconductor chip 100R may be paired and arranged in an even number of four or more.

[0043] FIGS. 6A to 6D are a plan view and a cross-sectional view showing the form of one shot according to a comparative example. Referring to FIGS. 6A and 6B, in the case of the first comparative example (Com1.), within one shot, all semiconductor chips have the same structure. In each semiconductor chip, the cell region is divided into two cell regions (CA1, CA2), and extension regions (Ex1, Ex2) are arranged on both sides of the cell region in the x direction. In such one shot of the first comparative example (Com1.), since two extension regions (Ex1, Ex2) are arranged within one semiconductor chip, it is disadvantageous in terms of realizing chip size reduction (CSR) of the chip.

[0044] Referring to FIGS. 6C and 6D, in the case of the second comparative example (Com2.), within one shot, all semiconductor chips have the same structure. In each semiconductor chip, one extension region (Ex) is arranged on the left side of the cell region (CA). However, since it has an asymmetric structure on the side of the entire one shot, problems occur in the process progress. For example, in the case of VNAND, defects such as the inclination, collapse, and 3D effect of the previous mold due to mold asymmetry may occur, and a warpage problem may also occur. In contrast, in the method for manufacturing a semiconductor device according to the present embodiment, within one shot, two types of semiconductor chips are arranged symmetrically with respect to a mirror, thereby solving the problems caused by the asymmetric structure of the second comparative example (Com2.). In addition, since one extension region is arranged in one semiconductor chip, it is much more advantageous in terms of chip size reduction (CSR) compared to the first comparative example (Com1.).

[0045] FIGS. 7A to 7C are a plan view and a cross-sectional view for explaining the concept of one shot that is symmetric with respect to the origin in the method for manufacturing a semiconductor device of FIG. 3, and FIGS. 7B and 7C are cross-sectional views taken along line III-III' and line IV-IV' of FIG. 7A. The content already described in the description part of FIGS. 1A to 6D will be briefly described or omitted. Referring to FIGS. 7A to 7C, in the method for manufacturing a semiconductor device according to the present embodiment, within one shot, a plurality of semiconductor chips are included. In addition, within one shot, in the x direction, two semiconductor chips are arranged adjacent to each other, and in the y direction, two or more, for example, four semiconductor chips are arranged.

[0046] In FIG. 7A, the semiconductor chip represented by the circled number 1 corresponds to the first semiconductor chip 100L, and the semiconductor chip represented by the circled number 2 corresponds to the second semiconductor chip 100R. In FIG. 7A, each of the first semiconductor chips 100L represented by the circled number 1 and arranged on the left side in the x direction has a first extension region 120L arranged on the left side of the first cell region 110L in the x direction, and a first peripheral region 130L arranged below the first cell region 110L in the y direction.

[0047] In addition, each of the first semiconductor chips 100L represented by the circled number 1 and arranged on the right side in the x direction has a first extended region 120L arranged on the right side of the first cell region 110L in the x direction, and a first peripheral region 130L arranged above the first cell region 110L in the y direction. Therefore, the first semiconductor chips 100L arranged on the left side and the first semiconductor chips 100L arranged on the right side in the x direction have a 180° rotation relationship. In addition, each of the second semiconductor chips 100R represented by the circled number 2 and arranged on the right side in the x direction has a second extended region 120R arranged on the right side of the second cell region 110R in the x direction, and a second peripheral region 130R arranged below the second cell region 110R in the y direction. In addition, each of the second semiconductor chips 100R represented by the circled number 2 and arranged on the left side in the x direction has a second extended region 120R arranged on the left side of the first cell region 110R in the x direction, and a second peripheral region 130R arranged above the second cell region 110R in the y direction. Therefore, the second semiconductor chips 100R arranged on the left side and the second semiconductor chips 100R arranged on the right side in the x direction have a 180° rotation relationship.

[0048] In the method for manufacturing a semiconductor device according to the present embodiment, the first semiconductor chips 100L and the second semiconductor chips 100R included within one shot are mirror-symmetrical with respect to the reference line RL, that is, the axis in the y direction. In addition, within one shot, the first semiconductor chips 100L and the second semiconductor chips 100R are alternately arranged along the y direction. In this way, since the first semiconductor chips 100L and the second semiconductor chips 100R are mirror-symmetrical with respect to the reference line RL in the x direction and are alternately arranged along the y direction, four semiconductor chips (100L, 100R) adjacent to each other in the x direction and the y direction are origin-symmetrical with respect to the reference point RP, that is, the origin.

[0049] More specifically, as shown in FIG. 7A, when four semiconductor chips are arranged on the quadrants within one shot, two first semiconductor chips 100L are arranged on the first quadrant and the third quadrant, and two second semiconductor chips 100R are arranged on the second quadrant and the fourth quadrant. Therefore, the two first semiconductor chips 100L are symmetric with respect to the origin with respect to the reference point RP, and the two second semiconductor chips 100R are symmetric with respect to the origin with respect to the reference point RP. Also, in the x direction, the second semiconductor chip 100R and the first semiconductor chip 100L arranged on the left side are symmetric with respect to the reference line RL in the x direction and are symmetric with respect to the origin with respect to the reference point RP while being mirror-symmetric with the first semiconductor chip 100L and the second semiconductor chip 100R arranged on the right side.

[0050] As shown in FIG. 7A, eight semiconductor chips are included within one shot, and thus, the four semiconductor chips on the upper side are symmetric with respect to the origin with respect to the reference point RP, and the four semiconductor chips on the lower side are symmetric with respect to the origin with respect to the reference point RP. In the method for manufacturing a semiconductor device of the present embodiment, within one shot, the first semiconductor chip 100L and the second semiconductor chip 100R are alternately arranged in the y direction and an even number of them are arranged. In other words, in order to form symmetry with respect to the origin, the first semiconductor chip 100L and the second semiconductor chip 100R are not arranged in an odd number in the y direction. Based on mirror symmetry with respect to the reference line RL, two first semiconductor chips 100L and two second semiconductor chips 100R are arranged in the x direction within one shot. However, in some embodiments, within one shot, the first semiconductor chip 100L and the second semiconductor chip 100R may be paired and arranged in an even number of four or more in the x direction.

[0051] Furthermore, since an extended region of the staircase structure is not formed in the initial semiconductor device, the cross-sectional views of FIGS. 7B and 7C correspond to the cross-sectional views of the semiconductor device after the extended region of the staircase structure is formed. In some embodiments, in the step of forming a pattern on a wafer (S120), the structure in which the semiconductor chips within one shot are symmetric with respect to the reference line RL and symmetric with respect to the reference point RP does not hold for the chip pads and the wirings connected to the chip pads.

[0052] FIGS. 8A and 8B are plan views showing other forms of one shot that is symmetric with respect to the origin. Referring to FIG. 8A, in the method for manufacturing a semiconductor device according to the present embodiment, although the four semiconductor chips within one shot are symmetric with respect to the reference point RP, they are symmetric with respect to the origin in a different manner from FIG. 7A. Specifically, as shown in FIG. 8A, when the four semiconductor chips are arranged on the quadrants within one shot, two first semiconductor chips 100L are arranged on the second quadrant and the fourth quadrant, and two second semiconductor chips 100R are arranged on the first quadrant and the third quadrant. Therefore, the two first semiconductor chips 100L are symmetric with respect to the reference point RP, and the two second semiconductor chips 100R are symmetric with respect to the reference point RP. Also, in the x direction, the first semiconductor chip 100L and the second semiconductor chip 100R arranged on the left side are symmetric with respect to the reference line RL in the x direction, and are symmetric with respect to the reference point RP while being symmetric with the second semiconductor chip 100R and the first semiconductor chip 100L arranged on the right side.

[0053] Note that, compared with FIG. 7A, the positions of the first semiconductor chip 100L and the second semiconductor chip 100R within one shot change in the x direction. Thereby, within one shot of FIG. 7A, the first cell region 110L and the second cell region 110R are adjacent to each other in the x direction, but within one shot of FIG. 8A, the first extended region 120L and the second extended region 120R are adjacent to each other in the x direction. Furthermore, in the x direction, the first semiconductor chip 100L arranged on the left side and the first semiconductor chip 100L arranged on the right side have a 180° rotation relationship. In the x direction, the second semiconductor chip 100R arranged on the left side and the second semiconductor chip 100R arranged on the right side have a 180° rotational relationship.

[0054] Referring to FIG. 8B, in the method for manufacturing a semiconductor device according to the present embodiment, although the four semiconductor chips within one shot are symmetric about the origin with respect to the reference point RP, they are symmetric about the origin in a different manner from that in FIG. 8A. Specifically, as shown in FIG. 8B, when the four semiconductor chips are arranged on the quadrants within one shot, two first semiconductor chips 100L are arranged on the second quadrant and the fourth quadrant, and two second semiconductor chips 100R are arranged on the first quadrant and the third quadrant. Therefore, the two first semiconductor chips 100L are symmetric about the origin with respect to each other with respect to the reference point RP, and the two second semiconductor chips 100R are symmetric about the origin with respect to each other with respect to the reference point RP. In the x direction, the first semiconductor chip 100L and the second semiconductor chip 100R arranged on the left side are symmetric about the reference line RL in the x direction with the second semiconductor chip 100R and the first semiconductor chip 100L arranged on the right side, and are symmetric about the origin with respect to the reference point RP.

[0055] Note that, compared with the structure of one shot in FIG. 8A, in the structure of one shot in FIG. 8B, the positions of the first semiconductor chips 100L on the second quadrant and the fourth quadrant are interchanged with each other. Also, compared with the structure of one shot in FIG. 8A, in the structure of one shot in FIG. 8B, the positions of the second semiconductor chips 100R on the first quadrant and the third quadrant are interchanged with each other. Specifically, in one shot of FIG. 8A, the first semiconductor chip 100L on the second quadrant has a structure in which the first extended region 120L is arranged on the right side of the first cell region 110L in the x direction, and the first peripheral region 130L is arranged above the first cell region 110L in the y direction. In contrast, in one shot of FIG. 8B, the first semiconductor chip 100L in the second quadrant has a structure in which the first extended region 120L is arranged on the left side of the first cell region 110L in the x direction, and the first peripheral region 130L is arranged below the first cell region 110L in the y direction. In each of one shot of FIGS. 8A and 8B, the 180° rotational relationship between the first semiconductor chip 100L in the second quadrant and the first semiconductor chip 100L in the fourth quadrant is maintained as it is.

[0056] In one shot of FIG. 8A, the second semiconductor chip 100R in the first quadrant has a structure in which the second extended region 120R is arranged on the left side of the second cell region 110R in the x direction, and the second peripheral region 130R is arranged above the second cell region 11OR in the y direction. In contrast, in one shot of FIG. 8B, the second semiconductor chip 100R in the first quadrant has a structure in which the second extended region 120R is arranged on the right side of the second cell region 110R in the x direction, and the second peripheral region 130R is arranged below the second cell region 110R in the y direction. In each of one shot of FIGS. 8A and 8B, the 180° rotational relationship between the second semiconductor chip 100R in the first quadrant and the second semiconductor chip 100R in the third quadrant is maintained as it is. Although not shown in the figure, for the one-shot structure of FIG. 7A, a one-shot structure in which the positions of the first semiconductor chips 100L in the first quadrant and the third quadrant are interchanged with each other, and the positions of the second semiconductor chips 100R in the second quadrant and the fourth quadrant are interchanged with each other is also symmetric about the origin with respect to the reference point RP.

[0057] Furthermore, in the method of manufacturing a semiconductor device of the present embodiment, even if it is not possible to achieve symmetry about the origin, various one-shot structures that are mirror-symmetric with respect to the reference line RL are applied to the exposure process for patterning on the wafer. For example, a unit couple chip composed of the first semiconductor chip 100L and the second semiconductor chip 100R that are mirror-symmetric with respect to the reference line RL can be arranged in various combinations in the y direction to embody a one-shot structure. Here, the unit couple chip includes four types of structures, for example, the structure of FIG. 4B, the structure of FIG. 5A, and the 180° rotation structures related to each of them.

[0058] FIGS. 9A and 9B are plan views showing two adjacent mirror-symmetric one-shot patterns. Referring to FIGS. 9A and 9B, a structure in which two shots are arranged adjacent to each other in the x direction is shown. In other words, FIG. 9A shows a structure in which two one-shot patterns of FIG. 4B are arranged adjacent to each other along the x direction, and FIG. 9B shows a structure in which two one-shot patterns of FIG. 5A are arranged adjacent to each other along the x direction. Note that, as described above, since one shot is the area of the pattern transferred in one exposure process using a mask, the structure of the two shots shown in FIGS. 9A and 9B does not correspond to a structure in which two shots are transferred onto the wafer at once, but rather corresponds to a structure in which one shot is repeatedly transferred while moving in the x direction.

[0059] FIGS. 10A and 10B are plan views showing two adjacent origin-symmetric one-shot patterns. Referring to FIGS. 10A and 10B, again, a structure in which two shots are arranged adjacent to each other in the x direction is shown. In other words, FIG. 10A shows a structure in which two one-shot patterns of FIG. 7A are arranged adjacent to each other along the x direction, and FIG. 10B shows a structure in which two one-shot patterns of FIG. 8A are arranged adjacent to each other along the x direction. Also, the structure of the two shots shown in FIGS. 10A and 10B does not correspond to a structure in which two shots are transferred onto the wafer at once, but rather corresponds to a structure in which one shot is repeatedly transferred while moving in the x direction.

[0060] FIGS. 11A and 11B are a plan view and a cross-sectional view related to a semiconductor package including a semiconductor element according to an embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along the line V-V' of FIG. 11A. With reference to both FIGS. 1A and 1B, the content already described in the description parts of FIGS. 1A to 10B will be briefly described or omitted. Referring to FIGS. 11A and 11B, the semiconductor package 1000 of the present embodiment includes a package substrate 200, semiconductor chips (100-1, 100-2), and a sealing material 300.

[0061] The package substrate 200 is, for example, a PCB (printed circuit board). External connection terminals 250 are arranged on the lower surface of the package substrate 200. The package substrate 200 includes a body layer, a multilayer wiring layer, and a protective layer. The body layer includes, for example, glass fiber such as FR4 and resin. However, the material of the body layer is not limited thereto. For example, the body layer may include BT (bismaleimide-triazine) resin, PC (polycarbonate) resin, reinforcing films such as ABF (Ajinomoto Build-up Film), or other laminate resins.

[0062] The multilayer wiring layer is arranged within the body layer. For example, the multilayer wiring layer may include 8 to 20 layers of wiring. However, the number of layers of the multilayer wiring layer is not limited to the aforementioned range. Note that the wirings of other layers are connected to each other via vertical vias. The wiring and the vertical vias include, for example, copper (Cu). However, the materials of the wiring and the vertical vias are not limited to Cu. The protective layer is a layer that protects the body layer and the multilayer wiring layer from external physical and chemical damage. The protective layer includes an upper protective layer and a lower protective layer. The protective layer includes, for example, SR (solder resist). However, the material of the protective layer is not limited to SR.

[0063] The lower semiconductor chip (100-1) is stacked on the package substrate 200 via the adhesive layer 105, and the upper semiconductor chip (100-2) is stacked on the lower semiconductor chip (100-1) via the adhesive layer 105. Also, the two semiconductor chips (100-1, 100-2) are electrically connected to the package substrate 200 via the wire 150. For example, the chip pads 140 of the two semiconductor chips (100-1, 100-2) and the substrate pads 210 of the package substrate 200 are connected to each other via the wire 150. In the semiconductor package 1000 of the present embodiment, the two semiconductor chips (100-1, 100-2) are, for example, the first semiconductor chip 100La of the semiconductor element 100a in FIG. 2A. However, it is not limited thereto, and it may also be the second semiconductor chip 100Ra of the semiconductor element 100a in FIG. 2A.

[0064] On the upper surface of each of the two semiconductor chips (100-1, 100-2), chip pads 140 are arranged corresponding to the peripheral region 130. Also, in the semiconductor package 1000 of the present embodiment, the two semiconductor chips (100-1, 100-2) are arranged on the package substrate 200 such that the long sides face in the y direction. Thereby, the chip pads 140 of each of the two semiconductor chips (100-1, 100-2) are arranged along the y direction. As shown in FIGS. 11A and 11B, the two semiconductor chips (100-1, 100-2) are stacked in a staircase structure in the x direction, whereby the chip pads 140 of the lower semiconductor chip (100-1) are exposed.

[0065] The encapsulant 300 covers and seals the semiconductor chips (100-1, 100-2) and the wire 150 on the package substrate 200. The encapsulant 300 encapsulates the semiconductor chips (100-1, 100-2) and protects the semiconductor chips (100-1, 100-2) from external physical and chemical damage. The encapsulant 300 is formed of, for example, EMC. However, the encapsulant 300 is not limited to EMC and can be formed of various substances, such as epoxy-based substances, thermosetting substances, thermoplastic substances, UV curable substances, and the like. Also, the encapsulant 300 can be formed of resin and may contain a filler.

[0066] Furthermore, the semiconductor package 1000 of the present embodiment is classified into two types according to the types of the stacked semiconductor chips (100-1, 100-2). For example, it is classified into a first type of semiconductor package including the first semiconductor chip 100La of the semiconductor element 100a in FIG. 2A and a second type of semiconductor package including the second semiconductor chip 100Ra. Although a structure in which two semiconductor chips are stacked on the package substrate 200 is illustrated, the number of semiconductor chips stacked on the package substrate 200 is not limited to two. For example, in the semiconductor package 1000 of the present embodiment, three or more semiconductor chips can be stacked on the package substrate 200.

[0067] FIGS. 12A and 12B are a plan view and a cross-sectional view related to a semiconductor package including a semiconductor element according to an embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along line VI-VI' of FIG. 12A. With reference to FIGS. 1A and 1B, the content already described in the description part of FIGS. 11A and 11B will be briefly described or omitted. Referring to FIGS. 12A and 12B, the semiconductor package 1000a of the present embodiment is different from the semiconductor package 1000 in FIG. 11A in that two types of semiconductor chips (100L, 100R) are stacked on the package substrate 200.

[0068] Specifically, in the semiconductor package 1000a of the present embodiment, on the package substrate 200, the first semiconductor chip 100L is laminated via the adhesive layer 105, and on the first semiconductor chip 100L, the second semiconductor chip 100R is laminated via the adhesive layer 105. In the semiconductor package 1000a of the present embodiment, the first semiconductor chip 100L and the second semiconductor chip 100R are the first semiconductor chip 100La and the second semiconductor chip 100Ra of the semiconductor element 100a in FIG. 2A. Further, the first semiconductor chip 100L and the second semiconductor chip 100R are arranged on the package substrate 200 such that the long sides face in the y direction. Thereby, the first chip pad 140L of the first semiconductor chip 100L is arranged along the y direction on the upper surface of the chip corresponding to the left first peripheral region 130L in the x direction. Also, the second chip pad 140R of the second semiconductor chip 100R is arranged along the y direction on the upper surface of the chip corresponding to the right second peripheral region 130R in the x direction.

[0069] Note that the first semiconductor chip 100L is connected via the wire 150 in the x direction to the substrate pad 210 arranged on the left side of the package substrate 200, and the second semiconductor chip 100R is connected via the wire 150 in the x direction to the substrate pad 210 arranged on the right side of the package substrate 200. Further, based on the mirror-symmetric structure of the first semiconductor chip 100La and the second semiconductor chip 100Ra, the substrate pads 210 on the package substrate 200 are arranged in a symmetric structure. Due to such a symmetric structure of the substrate pads 210, the wiring structure inside the package substrate 200 is further simplified, and the wiring freedom is improved. Note that also in the semiconductor package 1000a of the present embodiment, the first semiconductor chip 100L and the second semiconductor chip 100R are laminated in a stepped structure in the x direction on the package substrate 200, whereby the first chip pad 140L of the first semiconductor chip 100L is exposed to the outside.

[0070] FIG. 13A and FIG. 13B are a plan view and a cross-sectional view related to a semiconductor package including a semiconductor element according to an embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along line VII-VII' of FIG. 13A. The description will be made with reference to both FIG. 1A and FIG. 1B, and the content already described in the description part of FIGS. 11A to 12B will be briefly described or omitted. Referring to FIGS. 13A and 13B, the semiconductor package 1000b of the present embodiment is different from the semiconductor package 1000a of FIG. 12A in that four semiconductor chips of two types (100L-1, 100L-2, 100R-1, 100R-2) are stacked on the package substrate 200.

[0071] Specifically, in the semiconductor package 1000b of the present embodiment, a lower first semiconductor chip (100L-1) is stacked on the package substrate 200, a lower second semiconductor chip (100R-1) is stacked on the lower first semiconductor chip (100L-1), an upper first semiconductor chip (100L-2) is stacked on the lower second semiconductor chip (100R-1), and an upper second semiconductor chip (100R-2) is stacked on the upper first semiconductor chip (100L-2). In the semiconductor package 1000b of the present embodiment, the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2) are the first semiconductor chip 100La of the semiconductor element 100a in FIG. 2A, and the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are the second semiconductor chip 100Ra of the semiconductor element 100a in FIG. 2A.

[0072] Further, the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2), and the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are arranged on the package substrate 200 such that the long sides face in the y direction. Accordingly, the first chip pads 140L of the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100R-2) are arranged along the y direction on the upper surface of the chip corresponding to the left first peripheral region 130L in the x direction. Also, the second chip pads 140R of the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are arranged along the y direction on the upper surface of the chip corresponding to the right second peripheral region 130R in the x direction.

[0073] Note that the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2) are connected to the substrate pads 210 arranged on the left side of the package substrate 200 in the x direction via the wires 150, and the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are connected to the substrate pads 210 arranged on the right side of the package substrate 200 in the x direction via the wires 150. Also, based on the mirror-symmetric structure between the first semiconductor chip 100La and the second semiconductor chip 100Ra, the substrate pads 210 on the package substrate 200 are arranged in a symmetric structure. Due to such a symmetric structure of the substrate pads 210, the wiring structure inside the package substrate 200 is further simplified, and the wiring freedom is improved. Note that in the semiconductor package 1000b of the present embodiment, the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2), and the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are stacked in a zigzag structure in the x direction on the package substrate 200, whereby the first chip pads 140L of the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2) and the second chip pads 140R of the lower second semiconductor chip (100R-1) are exposed to the outside.

[0074] FIGS. 14A to 14C are a plan view and cross-sectional views related to a semiconductor package including a semiconductor element according to an embodiment of the present invention, and FIGS. 14B and 14C are cross-sectional views taken along the line VIII-VIII' of FIG. 14A. Referring to both FIGS. 1A and 1B, the content already described in the description parts of FIGS. 11A to 13B will be briefly described or omitted. Referring to FIGS. 14A and 14B, the semiconductor package 1000c of this embodiment is different from the semiconductor package 1000 in FIG. 11A in that two types of semiconductor chips are stacked on the package substrate 200 and are stacked so that the directions in which the long sides face are different.

[0075] Specifically, in the semiconductor package 1000c of this embodiment, a first semiconductor chip 100L is stacked on the package substrate 200 via an adhesive layer 105, and a second semiconductor chip 100R is stacked on the first semiconductor chip 100L via the adhesive layer 105. In the semiconductor package 1000c of this embodiment, the first semiconductor chip 100L and the second semiconductor chip 100R are the first semiconductor chip 100Lb and the second semiconductor chip 100Rb of the semiconductor element 100b in FIG. 2B. Also, the first semiconductor chip 100L is arranged on the package substrate 200 such that its long side faces the x direction, and the second semiconductor chip 100R is arranged on the package substrate 200 such that its long side faces the y direction. Thereby, the first chip pads 140L of the first semiconductor chip 100L are arranged along the y direction on the upper surfaces of the chips on both sides in the x direction.

[0076] Also, the second chip pads 140R of the second semiconductor chip 100R are arranged along the x direction on the upper surfaces of the chips on both sides in the y direction. Note that since the long sides of the first semiconductor chip 100L and the second semiconductor chip 100R face in different directions from each other, the first semiconductor chip 100L and the second semiconductor chip 100R form a cross shape. Note that the first semiconductor chip 100L is connected via wires 150 in the x direction to the substrate pads 210 arranged on both sides of the package substrate 200, and the second semiconductor chip 100R is connected via wires 150 in the y direction to the substrate pads 210 arranged on both sides of the package substrate 200. In addition, the substrate pads 210 on the package substrate 200 are arranged in a symmetric structure. Due to such a symmetric structure of the substrate pads 210, the wiring structure inside the package substrate 200 is further simplified, and the wiring freedom is improved.

[0077] Referring to FIG. 14C, the semiconductor package 1000d of the present embodiment is different from the semiconductor package 1000c of FIG. 14B in that four semiconductor chips (100L-1, 100L-2, 100R-1, 100R-2) of two types are stacked on the package substrate 200. Specifically, in the semiconductor package 1000d of the present embodiment, a lower first semiconductor chip (100L-1) is stacked on the package substrate 200, a lower second semiconductor chip (100R-1) is stacked on the lower first semiconductor chip (100L-1), an upper first semiconductor chip (100L-2) is stacked on the lower second semiconductor chip (100R-1), and an upper second semiconductor chip (100R-2) is stacked on the upper first semiconductor chip (100L-2).

[0078] In the semiconductor package 1000d of the present embodiment, the lower first semiconductor chip (100L-1) and the upper first semiconductor chip (100L-2) are the first semiconductor chips 100Lb of the semiconductor element 100b in FIG. 2B, and the lower second semiconductor chip (100R-1) and the upper second semiconductor chip (100R-2) are the second semiconductor chips 100Rb of the semiconductor element 100b in FIG. 2B. The semiconductor package 1000d of the present embodiment is similar to the structure of the semiconductor package 1000c of FIG. 14B except that the upper first semiconductor chip (100L-2) and the upper second semiconductor chip (100R-2) are further stacked.

[0079] FIGS. 15A and 15B are a plan view and a cross-sectional view related to a semiconductor package including a semiconductor element according to an embodiment of the present invention. FIG. 15B is a cross-sectional view taken along line IX-IX' of FIG. 15A. Referring to both FIGS. 1A and 1B, the content already described in the description parts of FIGS. 11A to 14B will be briefly described or omitted. Referring to FIGS. 15A and 15B, the semiconductor package 1000e of this embodiment is similar to the semiconductor package 1000d in FIG. 14C in that two types of four semiconductor chips (100La-1, 100La-2, 100Ra-1, 100Ra-2) are stacked. However, the structures of the chip pads (140Le, 140Re) of the respective semiconductor chips (100La-1, 100La-2, 100Ra-1, 100Ra-2) are different from those of the semiconductor package 1000d in FIG. 14C.

[0080] Specifically, in the semiconductor package 1000e of this embodiment, a lower first semiconductor chip (100La-1) is stacked on the package substrate 200, a lower second semiconductor chip (100Ra-1) is stacked on the lower first semiconductor chip (100La-1), an upper first semiconductor chip (100La-2) is stacked on the lower second semiconductor chip (100Ra-1), and an upper second semiconductor chip (100Ra-2) is stacked on the upper first semiconductor chip (100La-2). Also, the first chip pad 140Le of the lower first semiconductor chip (100La-1) is arranged along the y direction on the upper surface of the left chip in the x direction, and the first chip pad 140Le of the upper first semiconductor chip (100La-2) is arranged along the y direction on the upper surface of the right chip in the x direction. Note that the second chip pad 140Re of the lower second semiconductor chip (100Ra-1) is arranged along the x direction on the upper surface of the upper chip in the y direction, and the second chip pad 140Re of the upper second semiconductor chip (100Ra-2) is arranged along the x direction on the upper surface of the lower chip in the y direction.

[0081] In the semiconductor package 1000e of the present embodiment, the lower first semiconductor chip (100La-1) and the upper first semiconductor chip (100La-2) are arranged on the package substrate 200 such that the long sides face in the x direction, and the lower second semiconductor chip (100Ra-1) and the upper second semiconductor chip (100Ra-2) are arranged on the package substrate 200 such that the long sides face in the y direction. Thereby, the first chip pad 140Le of the lower first semiconductor chip (100La-1) is connected in the x direction to the substrate pad 210 arranged on the left side of the package substrate 200, and the second chip pad 140Re of the lower second semiconductor chip (100Ra-1) is connected in the y direction to the substrate pad 210 arranged above the package substrate 200. The first chip pad 140Le of the upper first semiconductor chip (100La-2) is connected in the x direction to the substrate pad 210 arranged on the right side of the package substrate 200, and the second chip pad 140Re of the upper second semiconductor chip (100Ra-2) is connected in the y direction to the substrate pad 210 arranged below the package substrate 200.

[0082] Therefore, the chip pads (140Le, 140Re) of the four semiconductor chips (100La-1, 100La-2, 100Ra-1, 100Ra-2) are connected to the substrate pads 210 on the four surfaces of the corresponding package substrate 200. Note that the first semiconductor chips (100La-1, 100La-2) are mirror-symmetric with the second semiconductor chips (100Ra-1, 100Ra-2). Thereby, the substrate pads 210 on the package substrate 200 are also arranged in a symmetric structure. Due to such a symmetric structure of the substrate pads 210, the wiring structure inside the package substrate 200 is further simplified, and the wiring freedom is improved.

[0083] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.

Description of Reference Numerals

[0084] 100, 100a to 100e semiconductor elements 100-1, 100-2 semiconductor chips 100L, 100La to 100Lc first semiconductor chips 100R, 100Ra to 100Rd second semiconductor chips 105 adhesive layer 110L first cell region 110R second cell region 120L first expansion region 120R second expansion region 130 peripheral region 130L first peripheral region 130R second peripheral region 140 chip pad 140L, 140La, 140Lb first chip pads 140R, 140Ra to 140Rc second chip pads 150 wire 200 package substrate 210 substrate pad 250 external connection terminal 300 encapsulant 1000, 1000a to 1000e semiconductor packages

Claims

1. a first semiconductor chip of a first type and a second semiconductor chip of a second type having a rectangular shape of substantially the same size; the first semiconductor chip and the second semiconductor chip are included in a plurality of semiconductor chips corresponding to one shot in an exposure process; Here, the one shot refers to an area of ​​a pattern transferred onto a wafer through one exposure process using a mask, A semiconductor element characterized in that when the first semiconductor chip and the second semiconductor chip are arranged adjacent to each other in a first direction, the first semiconductor chip and the second semiconductor chip are mirror-symmetric to each other with respect to an axis in a second direction perpendicular to the first direction.

2. In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed on the left side of a cell region in the first direction, an extension region of the second semiconductor chip is disposed on the right side of the cell region in the first direction; In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed to the right of the cell region in the first direction, an extension region of the second semiconductor chip is disposed to the left of the cell region in the first direction; The semiconductor device according to claim 1 , wherein in the mirror symmetric state, peripheral regions of the first semiconductor chip and the second semiconductor chip are disposed below the cell region in the second direction.

3. 3. The semiconductor device of claim 2, wherein the first chip pads of the first semiconductor chip and the second chip pads of the second semiconductor chip are disposed at different positions on a front surface of the chips.

4. A package substrate; a first semiconductor chip of a first type mounted on the package substrate; a second semiconductor chip of a second type stacked on the first semiconductor chip; the first semiconductor chip and the second semiconductor chip have a rectangular shape of substantially the same size; 2. A semiconductor package, wherein the first semiconductor chip and the second semiconductor chip are mirror images of each other with respect to a reference line.

5. the reference line is a line extending in a second direction perpendicular to the first direction when the first semiconductor chip and the second semiconductor chip are disposed adjacent to each other in a first direction, In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed on the left side of a cell region in the first direction, an extension region of the second semiconductor chip is disposed on the right side of the cell region in the first direction; In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed to the right of the cell region in the first direction, an extension region of the second semiconductor chip is disposed to the left of the cell region in the first direction; 5. The semiconductor package according to claim 4, wherein in the mirror symmetric state, peripheral regions of the first semiconductor chip and the second semiconductor chip are disposed below the cell region in the second direction.

6. On the package substrate, long sides of the first semiconductor chip and the second semiconductor chip are disposed in the second direction, a first chip pad of the first semiconductor chip is disposed along the second direction on a front surface of the chip at a left outer portion in the first direction; 6. The semiconductor package of claim 5, wherein the second chip pads of the second semiconductor chip are disposed along the second direction on a front surface of a chip at a right outer portion in the first direction.

7. the first chip pads are disposed on the front surface corresponding to a peripheral region of the first semiconductor chip; The semiconductor package of claim 6 , wherein the second chip pads are disposed on the front surface corresponding to a peripheral region of the second semiconductor chip.

8. 7. The semiconductor package of claim 6, wherein the second semiconductor chip is stacked on the first semiconductor chip in a staircase structure in the first direction such that the first chip pads are exposed.

9. When a long side of the first semiconductor chip is disposed on the package substrate in a first direction, a long side of the second semiconductor chip is disposed on the package substrate in the second direction to form a cross shape with the first semiconductor chip, a first chip pad of the first semiconductor chip is disposed on a front surface of the chip at both outer portions in the first direction along the second direction; 6. The semiconductor package of claim 5, wherein the second chip pads of the second semiconductor chip are disposed along the first direction on a front surface of the chip at both outer periphery portions in the second direction.

10. at least one third semiconductor chip disposed on the second semiconductor chip; the third semiconductor chip is the first type or the second type, 6. The semiconductor package according to claim 5, wherein when three or more semiconductor chips are stacked on the package substrate, the first type semiconductor chips and the second type semiconductor chips are stacked alternately.

11. the three or more semiconductor chips are stacked in a staircase structure or a zigzag structure in the first direction; or 11. The semiconductor package of claim 10, wherein an upper semiconductor chip is stacked in a cross shape on a lower semiconductor chip.

12. A package substrate; at least one first semiconductor chip of a first type mounted on the package substrate; at least one second semiconductor chip of a second type mounted on the package substrate; the first semiconductor chip and the second semiconductor chip have a rectangular shape of substantially the same size; the first semiconductor chip and the second semiconductor chip are mirror symmetrical with respect to a reference line; a first type semiconductor chip and a second type semiconductor chip are alternately stacked on the package substrate, the first type semiconductor chip and the second type semiconductor chip being stacked alternately on the package substrate;

13. the reference line is a line extending in a second direction perpendicular to the first direction when the first semiconductor chip and the second semiconductor chip are disposed adjacent to each other in a first direction, In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed on the left side of a cell region in the first direction, an extension region of the second semiconductor chip is disposed on the right side of the cell region in the first direction; In the mirror symmetric state, when an extension region of the first semiconductor chip is disposed to the right of the cell region in the first direction, an extension region of the second semiconductor chip is disposed to the left of the cell region in the first direction; 13. The semiconductor package of claim 12, wherein in the mirror symmetric state, peripheral regions of the first semiconductor chip and the second semiconductor chip are disposed below the cell region in the second direction.

14. On the package substrate, long sides of the first semiconductor chip and the second semiconductor chip are disposed in the second direction, a first chip pad of the first semiconductor chip is disposed along the second direction on a front surface of the chip at a left outer portion in the first direction; 14. The semiconductor package of claim 13, wherein the second chip pads of the second semiconductor chip are disposed along the second direction on a front surface of a chip at a right outer portion in the first direction.

15. when a long side of the first semiconductor chip is disposed on the package substrate in a first direction, a long side of the second semiconductor chip is disposed on the package substrate in the second direction; a first chip pad of the first semiconductor chip is disposed on a front surface of the chip at both outer portions in the first direction along the second direction; 14. The semiconductor package of claim 13, wherein second chip pads of the second semiconductor chip are disposed along the first direction on a front surface of the chip at both outer periphery portions in the second direction.

16. Preparing a mask; forming a pattern on a wafer through an exposure process using the mask; determining whether the semiconductor device is complete; and when the semiconductor device is completed, singulating the wafer into a plurality of semiconductor chips; If the semiconductor device is not completed, the method further includes returning to the step of preparing a mask and preparing a mask corresponding to a next pattern; A method for manufacturing a semiconductor device, characterized in that, in the step of forming a pattern on the wafer, when an area of ​​a pattern transferred through one exposure process is defined as one shot, the one shot has a structure including a plurality of semiconductor chips that are mirror symmetrical, or a structure including a plurality of semiconductor chips that are symmetrical about an origin.

17. The one shot has a structure including a plurality of mirror-symmetric semiconductor chips, In the one shot, a first semiconductor chip of a first type and a second semiconductor chip of a second type are disposed adjacent to each other in a first direction; 17. The method of claim 16, wherein the first semiconductor chip and the second semiconductor chip are mirror-symmetric with respect to an axis of a second direction perpendicular to the first direction.

18. In the one shot, when an extension region of the first semiconductor chip is disposed on the left side of a cell region in the first direction, an extension region of the second semiconductor chip adjacent to the first semiconductor chip in the first direction is disposed on the right side of the cell region in the first direction; In the one shot, when an extension region of the first semiconductor chip is disposed on the right side of the cell region in the first direction, an extension region of the second semiconductor chip adjacent to the first semiconductor chip in the first direction is disposed on the left side of the cell region in the first direction; 20. The method of claim 17, wherein in the one shot, peripheral regions of the first semiconductor chip and the second semiconductor chip adjacent to each other in the first direction are disposed below the cell region in the second direction.

19. The one shot has a structure including a plurality of semiconductor chips symmetrical with respect to an origin, When the four semiconductor chips are arranged on the quadrants in one shot, a first semiconductor chip is arranged on the first and third quadrants, and a second semiconductor chip is arranged on the second and fourth quadrants, or the second semiconductor chip is arranged on the first and third quadrants, and the first semiconductor chip is arranged on the second and fourth quadrants, the two first semiconductor chips are symmetrical with respect to the origin of the quadrant, 17. The method of claim 16, wherein the two second semiconductor chips are symmetrical to each other with respect to an origin of the quadrant.

20. In the one shot, when an extension region of the first semiconductor chip is disposed on a left side of a cell region in a first direction, an extension region of the second semiconductor chip adjacent to the first semiconductor chip in the first direction is disposed on a right side of the cell region in the first direction; In the one shot, when an extension region of the first semiconductor chip is disposed on the right side of the cell region in the first direction, an extension region of the second semiconductor chip adjacent to the first semiconductor chip in the first direction is disposed on the left side of the cell region in the first direction; 20. The method of claim 19, wherein in one shot, peripheral regions of the first semiconductor chip and the second semiconductor chip adjacent to each other in the first direction are disposed below or above the cell region in a second direction perpendicular to the first direction.

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