Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A memory circuit includes a first transistor and a second transistor. The first transistor is provided on a silicon substrate. The second transistor is provided in an upper layer of a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode provided with a first channel formation region therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is configured using a region where an impurity element that provides conductivity in the silicon substrate is selectively introduced. The second transistor includes a second channel formation region. The second channel formation region contains metal oxide.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods.

Background Art

[0003] Metal oxides have attracted attention as semiconductors applicable to transistors. Indium-gallium-zinc oxide, called "IGZO", "Igzo", etc., is a typical multi-component metal oxide. In the research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystals nor amorphous, have been found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an "oxide semiconductor transistor" or an "OS transistor") has been reported to have an extremely small off-current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] In addition, a memory that utilizes the extremely small off-current of an OS transistor (sometimes referred to as an OS memory) has been proposed. For example, Patent Document 1 discloses the circuit configuration of NOSRAM. Note that "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell, and the access transistor is an OS transistor. The OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, a leakage current. NOSRAM can be used as a non-volatile memory by holding charges corresponding to data in the memory circuit using the characteristic of extremely small leakage current.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0008] In NOSRAM, data reading is performed by applying the potential held with the OS transistor in the off state to the gate of a transistor (Si transistor) having silicon in the channel formation region. In NOSRAM, in order to reduce the power consumption for data reading, it is effective to lower the voltage of the signal applied to each wiring. However, since the threshold voltage of the Si transistor varies greatly with the miniaturization of the transistor size, it is difficult to lower the voltage of the signal applied to each wiring.

[0009] When the Si transistor is in the on state, the current flowing (on-current) is much larger than the on-current of the OS transistor. However, when performing intermittent operations such as in the peripheral circuits for driving the OS memory, there is a risk that the current flowing (leakage current) when the Si transistor is turned off increases, or that the standby power increases with the integration of the transistors.

[0010] One aspect of the present invention is to provide a semiconductor device excellent in low power consumption. Or, one aspect of the present invention is to provide a semiconductor device in which a leakage current is reduced and which is excellent in reduction of standby power. Or, one aspect of the present invention is to provide a semiconductor device having a novel configuration.

[0011] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it suffices if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. Other problems will be naturally apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0012] One aspect of the present invention is a semiconductor device having a memory circuit including a first transistor and a second transistor, the first transistor being provided on a silicon substrate, the second transistor being provided on an upper layer of the layer where the first transistor is provided, the first transistor having a first gate electrode and a first back gate electrode provided with the first channel formation region therebetween, the first gate electrode being electrically connected to one of the source or drain of the second transistor, and the first back gate electrode being configured using a region in which an impurity element for imparting conductivity is selectively introduced in the silicon substrate.

[0013] One aspect of the present invention includes a memory circuit having a first transistor and a second transistor, and a peripheral circuit of the memory circuit having a third transistor and a fourth transistor. The first transistor, the third transistor, and the fourth transistor are each provided on a silicon substrate, and the second transistor is provided on an upper layer of the layer where the first transistor, the third transistor, and the fourth transistor are provided. The first transistor has a first gate electrode and a first back gate electrode provided with the first channel formation region therebetween. The first gate electrode is electrically connected to one of the source or drain of the second transistor, and the first back gate electrode is configured using a region where an impurity element that imparts conductivity is selectively introduced in the silicon substrate. It is a semiconductor device.

[0014] In one aspect of the present invention, it is preferable that the first transistor has an insulating layer between the first back gate electrode and the channel formation region, and the insulating layer is an insulating layer formed by buried oxidation.

[0015] In one aspect of the present invention, it is preferable that the second transistor has a second channel formation region, and the second channel formation region has a metal oxide.

[0016] In one aspect of the present invention, it is preferable that the semiconductor device includes In, Ga, and Zn in the metal oxide.

[0017] In one aspect of the present invention, it is preferable that the second transistor has a second back gate electrode.

[0018] In one aspect of the present invention, the third transistor includes a third gate electrode and a third back gate electrode provided with the third channel formation region therebetween, and the fourth transistor includes a fourth gate electrode and a fourth back gate electrode provided with the fourth channel formation region therebetween. The third back gate electrode is formed using a region in which a first impurity element that imparts n-type conductivity in the silicon substrate is selectively introduced, and the fourth back gate electrode is formed using a region in which a second impurity element that imparts p-type conductivity in the silicon substrate is selectively introduced. A semiconductor device is preferred.

[0019] Other aspects of the present invention are described in the following embodiments and the drawings.

Advantages of the Invention

[0020] One aspect of the present invention can provide a semiconductor device excellent in power consumption reduction. Or, one aspect of the present invention can provide a semiconductor device in which the leakage current is reduced and excellent in standby power reduction. Or, a semiconductor device having a novel configuration can be provided.

[0021] The description of a plurality of effects does not prevent the existence of other effects. Also, one embodiment of the present invention does not necessarily have to have all of the illustrated effects. Also, regarding one embodiment of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0022]

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[0023] Hereinafter, embodiments of the present invention will be described. However, one embodiment of the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as limited to the description of the embodiments shown below.

[0024] In this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, the component referred to as "first" in one of the embodiments of this specification and the like may be the component referred to as "second" in other embodiments or the claims. Also, for example, the component referred to as "first" in one of the embodiments of this specification and the like may be omitted in other embodiments or the claims.

[0025] In the drawings, the same reference numerals may be assigned to the same elements, elements having similar functions, elements of the same material, or elements formed simultaneously, and repeated explanations thereof may be omitted.

[0026] In this specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0027] Also, when the same reference numeral is used for a plurality of elements, particularly when it is necessary to distinguish them, identification symbols such as "_1", "_2", "[n]", "[m,n]" may be appended to the reference numeral for description. For example, the second wiring GL is described as wiring GL[2].

[0028] (Embodiment 1) The configuration and the like of a semiconductor device which is one aspect of the present invention will be described.

[0029] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, logic circuits, arithmetic units, and memory devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc. may be said to have a semiconductor device.

[0030] FIG. 1A is a diagram for explaining a semiconductor device 10 which is one aspect of the present invention.

[0031] The semiconductor device 10 shown in FIG. 1A functions as a memory circuit having a function of holding data. The semiconductor device 10 includes at least a transistor 103A and a transistor 104A each having a gate electrode and a back gate electrode. The transistor 103A is illustrated as a p-channel type transistor, and the transistor 104A is illustrated as an n-channel type transistor.

[0032] In FIG. 1A, in addition to transistors 103A and 104A, a capacitive element 113 for holding the gate potential (node FN) of transistor 103A is illustrated. Also in FIG. 1A, a wiring wwl for controlling the on or off of transistor 104A that functions as a switch is illustrated. Also in FIG. 1A, a wiring wbl for writing a potential corresponding to data to node FN is illustrated. As the potential corresponding to data, binary or multi-valued data of three values or more can be used.

[0033] Also in FIG. 1A, a wiring rbl for reading out a potential corresponding to data is illustrated. Also in FIG. 1A, a wiring rwl for performing control to read out a potential corresponding to data to wiring rbl is illustrated. Wiring rwl is set to, for example, the H level during the period of reading out data. In transistor 104A, a current flows according to the potential of node FN and the threshold voltage of transistor 104A. Wiring rbl changes to a potential corresponding to the current, and the potential of wiring rbl can be output to a peripheral circuit.

[0034] In the semiconductor device 10 shown in FIG. 1A, writing of data is performed by applying a high-level potential to wiring wwl to turn transistor 104A on and electrically connecting node FN and wiring wbl. Specifically, when transistor 104A is in the conducting state, a potential corresponding to the data to be written is applied to wiring wbl, and the potential is written to node FN. Thereafter, a low-level potential is applied to wiring wwl to turn transistor 104A off, thereby holding the potential of node FN.

[0035] Reading of data is performed by applying a predetermined potential to wiring rbl, then setting wiring rbl to an electrically floating state, and applying a high-level potential to wiring rwl. Hereinafter, applying a predetermined potential to wiring rbl and then setting wiring rbl to the floating state is expressed as precharging wiring rbl.

[0036] For example, by precharging the wiring rbl with the potential Vss, the transistor 103A has a potential difference between the source and the drain, and the current flowing between the source and the drain of the transistor 103A is determined by the potential held at the node FN. Therefore, the potential held at the node FN can be read by reading the potential change of the wiring rbl when the wiring rbl is in a floating state.

[0037] The row in which the semiconductor device 10 for writing data is arranged is selected by applying a high-level potential to the wiring wwl, and the row in which the semiconductor device 10 for reading data is arranged is selected by applying a high-level potential to the wiring rwl. Conversely, for the row in which the semiconductor device 10 that does not write data is arranged, a low-level potential is applied to the wiring wwl, and for the row in which the semiconductor device 10 that does not read data is arranged, the same potential as the potential for precharging the wiring rbl is applied to the wiring rwl, so that it can be made non-selective.

[0038] In one aspect of the present invention, the transistor constituting the semiconductor device 10 includes, in addition to the gate electrode, a back gate electrode for controlling the threshold voltage.

[0039] The transistor 103A has a gate electrode and a back gate electrode. The transistor 104A has a gate electrode and a back gate electrode. The threshold voltage of each transistor is controlled by the height of the potential of the back gate electrode, more specifically, by the potential difference between the source and the back gate electrode.

[0040] The semiconductor layer of transistor 103A is silicon. That is, transistor 103A is a Si transistor. Transistor 103A is formed using a SOI (Silicon On Insulator) substrate having an insulating layer (also referred to as a BOX (Buried oxide) layer) formed by embedded oxidation in a silicon substrate and a thin-film single-crystalline silicon on the insulating layer, and is a fully-depleted SOI (FD-SOI: Fully-Depleted Silicon On Insulator) transistor. As the SOI substrate, an SOI substrate fabricated by the SIMOX (Separated by Implanted Oxygen) method or the smart cut method can be used. Transistor 103A can be an n-channel type or p-channel type transistor according to the impurity element added to the impurity region.

[0041] In the silicon substrate in the region where transistor 103A is provided, a region (well region) to which an impurity element for imparting conductivity is added can be provided in an overlapping manner. The well region can function as a back gate electrode by independently changing the potential of the well region. Therefore, the threshold voltage of the Si transistor can be controlled. In particular, when the Si transistor is a p-channel type transistor, by applying a positive potential to the well region, the threshold voltage of the Si transistor can be made larger and the off-current can be reduced. Therefore, by applying a positive potential to the well region, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be made smaller. Also, since the addition of an impurity element to the channel formation region for the purpose of controlling the threshold voltage becomes unnecessary, the variation in the threshold voltage can be reduced, and the power supply voltage and the amplitude voltage of the signal to each wiring can be lowered.

[0042] Also, the semiconductor layer of transistor 104A is an oxide semiconductor (metal oxide). That is, transistor 104A is an OS transistor.

[0043] Since the bandgap of the metal oxide is 2.5 eV or more, the OS transistor has an extremely small off-current. As an example, when the voltage between the source and drain is 3.5 V at room temperature (25 °C), the off-current per 1 μm channel width is less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A. That is, the on / off current ratio of the drain current can be 20 digits or more and 150 digits or less.

[0044] In a highly integrated semiconductor device, heat may be generated due to the driving of the circuit. Due to this heat generation, the temperature of the transistor rises, which may change the characteristics of the transistor, such as a change in the field-effect mobility or a decrease in the operating frequency. Since the OS transistor has higher heat resistance than the Si transistor, a change in the field-effect mobility due to a temperature change is less likely to occur, and a decrease in the operating frequency is also less likely to occur. Furthermore, the OS transistor is likely to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage even when the temperature rises. Therefore, by using the OS transistor, stable operation in a high-temperature environment can be achieved.

[0045] The semiconductor device 10 having the transistor 104A composed of the OS transistor can be stacked and provided on the Si transistor, so that an n-channel transistor and a p-channel transistor can be arranged without increasing the circuit area. In one aspect of the present invention, the p-channel transistor, which is a Si transistor, is provided on a well region that functions as a back gate, so that the threshold voltage can be controlled and the power supply voltage and the amplitude voltage of the signal to each wiring can be switched. As a result, the standby power in the semiconductor device can be reduced.

[0046] When the absolute value of the threshold voltage of transistor 103A is such that transistor 103A is of the p-channel type, the absolute value of the threshold voltage tends to increase as the potential Vctl_1 applied to the back gate electrode increases. Conversely, the absolute value of the threshold voltage of transistor 103A tends to decrease as the potential Vctl_1 applied to the back gate electrode decreases. Therefore, in one aspect of the present invention, standby power can be suppressed low by configuring to switch the potential Vctl_1 according to the operating state according to the conductivity type of the transistor.

[0047] When the absolute value of the threshold voltage of transistor 103A is such that transistor 103A is of the n-channel type, the absolute value of the threshold voltage tends to increase as the potential Vctl_1 applied to the back gate electrode decreases. Conversely, the absolute value of the threshold voltage of transistor 103A tends to decrease as the potential Vctl_1 applied to the back gate electrode increases. Therefore, in one aspect of the present invention, standby power can be suppressed low by configuring to switch the potential Vctl_1 according to the operating state according to the conductivity type of the transistor.

[0048] Also, when the absolute value of the threshold voltage of transistor 104A is such that transistor 104A is of the n-channel type, the absolute value of the threshold voltage tends to increase as the potential Vctl_2 applied to the back gate electrode decreases. Conversely, the absolute value of the threshold voltage of transistor 104A tends to decrease as the potential Vctl_2 applied to the back gate electrode increases. Therefore, in one aspect of the present invention, standby power is suppressed low by configuring to switch the potential Vctl_2 according to the operating state.

[0049] Next, the structures of transistors 103A and 104A used in semiconductor device 10 will be described. FIG. 1B shows an example of the cross-sectional structures of transistors 103A and 104A.

[0050] In FIG. 1B, transistors 103A and 104A are formed on a silicon substrate 300. Transistor 103A is a transistor provided with a well region that functions as a back gate electrode in fully-depleted silicon-on-insulator (FD-SOI).

[0051] An insulating layer 302 and a well region 306 are formed in the silicon substrate 300.

[0052] The silicon substrate 300 is preferably a substrate made of p-type or n-type single-crystalline silicon.

[0053] The insulating layer 302 functions as an element isolation layer. The element isolation layer can be formed by forming an opening reaching into the silicon substrate 300 and then embedding the opening with a single layer or a stacked insulating layer of silicon oxide and silicon nitride. An island-shaped insulating layer 302 can be formed by selectively removing the insulating layer other than the opened one by a method such as chemical mechanical polishing (CMP).

[0054] The well region 306, which is a region where impurity elements for imparting conductivity are selectively introduced in the silicon substrate, functions as a back gate electrode. The well region 306 can be formed into an n-type or p-type well region 306 by ion-implanting an n-type impurity such as phosphorus (P) or arsenic (As), or an impurity for imparting a p-type such as boron (B) to the silicon substrate 300.

[0055] On the well region 306, an impurity region 310A, an impurity region 310B, and a channel formation region 310C, which are semiconductor layers, are provided via an insulating layer 308 that is a BOX layer. Also, on the well region 306, an impurity region 312 and a conductive layer 322C for applying a potential Vctl_1 to the well region 306 are formed. On the channel formation region 310C, an insulating layer 314, a conductive layer 316, and a conductive layer 322D are formed. The conductive layer 316 and the conductive layer 322D function as gate electrodes to which a potential Vin1 is applied. The insulating layer 314 functions as a gate insulating film. On the impurity regions 310A and 310B, an insulating layer 318, a conductive layer 322A, and a conductive layer 322B are formed.

[0056] The insulating layer 308 is, for example, a silicon oxide layer having a film thickness of 10 nm to 50 nm. The insulating layer 308 is an insulating layer formed by buried oxidation.

[0057] The semiconductor layers in which the impurity regions 310A, 310B, and the channel formation region 310C are provided are single crystal silicon provided by a method such as SIMOX (Separated by Implanted Oxygen) method or Smart Cut method. The impurity regions 310A, 310B, and the impurity region 312 can be formed into n-type or p-type impurity regions 310A, 310B, and 312 by ion implanting an n-type impurity such as phosphorus (P) or arsenic (As), or an impurity that imparts a p-type such as boron (B). The semiconductor layer directly under the insulating layer 314 and the conductive layer 316 has no impurities introduced and becomes the channel formation region 310C.

[0058] The insulating layer 314 functions as a gate insulating film. The insulating layer 314 is, for example, a silicon oxide layer having a film thickness of 1 nm to 10 nm. The conductive layer 316 and the conductive layer 322D function as the gate electrode of the transistor 103A to which a potential Vin1 is applied. The conductive layer 316 is, for example, polycrystalline silicon of 40 nm to 200 nm.

[0059] The insulating layer 318 functions as a sidewall insulating layer (sidewall spacer). The insulating layer 318 can be formed by anisotropic dry etching or the like on the insulating film that becomes the insulating layer 318 after the formation of the insulating film. As the insulating layer 318, silicon oxide, silicon nitride, or a laminate of silicon oxide and silicon nitride can be used.

[0060] The conductive layers 322A to 322D are, for example, metal silicide layers such as cobalt silicide, nickel silicide, or nickel platinum silicide. The conductive layers 322A to 322D can enhance the conductivity of each terminal such as the source, drain, and gate in the transistor 103A.

[0061] On the transistor 103A, an insulating layer 324 that functions as an interlayer insulating film and a conductive layer 326 that functions as an electrode for applying a potential Vctl_1 to the transistor 103A and the well region are provided. An insulating layer 328, a conductive layer 330, an insulating layer 332, and a conductive layer 334 are provided on the insulating layer 324 and the conductive layer 326. An insulating layer 336 and a conductive layer 338 are formed on the insulating layer 332 and the conductive layer 334. The conductive layer 338 functions as a back gate electrode of an n-channel transistor to which a potential Vctl_2 is applied.

[0062] As the insulating layer 324, the insulating layer 328, the insulating layer 332, and the insulating layer 336, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0063] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0064] Further, for the insulating layer 332, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse into the region where the transistor 104A is provided from the silicon substrate 300 or the transistor 103A or the like.

[0065] As an example of the film having a barrier property against hydrogen, for example, silicon nitride formed by CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 104A, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 103A and the transistor 104A. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0066] Also, as the materials of the conductive layer 326, the conductive layer 330, the conductive layer 334, and the conductive layer 338, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used alone or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum that have both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0067] An insulating layer 340 is provided on the insulating layer 336 and the conductive layer 338. A semiconductor layer 342 and conductive layers 344A and 344B are provided on the insulating layer 340. Further, an insulating layer 346 and an insulating layer 348 are provided on the semiconductor layer 342 and the conductive layers 344A and 344B. The conductive layers 344A and 344B function as the source electrode or the drain electrode of the transistor 104A.

[0068] The insulating layer 340 is preferably made of an insulator containing more oxygen than the stoichiometric composition. Such oxygen is likely to be released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulating layer 340. By providing such an insulator containing excess oxygen in contact with the semiconductor layer 342, oxygen vacancies (V O : also referred to as oxygen vacancy) in the semiconductor layer 342 can be reduced, and the reliability of the transistor 104A can be improved. When hydrogen enters the oxygen vacancies in the semiconductor layer 342, such defects (hereinafter sometimes referred to as V O H) may function as donors and generate electrons as carriers. Also, a part of the hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the semiconductor layer 342 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and supply oxygen to the oxide semiconductor to fill oxygen vacancies (also referred to as "oxygen addition treatment"). By using an oxide semiconductor in which impurities such as V O H are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0069] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which some oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more. The oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0070] Further, the insulator having the excess oxygen region and the semiconductor layer 342 may be subjected to any one or more of heat treatment, microwave treatment, or RF treatment in contact with each other. By performing the treatment, water or hydrogen in the semiconductor layer 342 can be removed. For example, in the semiconductor layer 342, a reaction in which the bond of VoH is broken occurs, in other words, a reaction of "V O H→Vo+H" occurs, and dehydrogenation can be performed. A part of the hydrogen generated at this time may be combined with oxygen to form H2O and removed from the semiconductor layer 342 or the insulator near the semiconductor layer 342. Also, a part of the hydrogen may be gettered by the conductive layers 344A and 344B.

[0071] In addition, for the above microwave treatment, it is preferable to use, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor layer 342 or the insulator near the semiconductor layer 342. Further, for the above microwave treatment, the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. As the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0072] The semiconductor layer 342 can be made into a semiconductor device with excellent reliability by adopting a structure in which two or more layers of oxides with different atomic number ratios of each metal atom are laminated. The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method.

[0073] Metal oxides applied to OS transistors include ZnO, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is any one or more selected from Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), etc. In particular, when a metal oxide using Ga as M is adopted for an OS transistor, it is preferable because a transistor with excellent electrical characteristics such as field-effect mobility can be obtained by adjusting the ratio of elements. Further, the oxide containing indium and zinc may contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0074] For improving the reliability and electrical characteristics of the OS transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having crystal parts such as CAAC-OS, CAC-OS, and nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0075] CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction, resulting in a crystal structure with strain. Note that the strain refers to a location where the lattice arrangement direction changes between a region with an aligned lattice arrangement and another region with an aligned lattice arrangement in the region where a plurality of nanocrystals are connected.

[0076] CAC-OS has a function of flowing carriers (electrons or holes) and a function of not flowing carriers that are electrons. By separating the function of flowing electrons and the function of not flowing electrons, both functions can be maximally enhanced. That is, by using CAC-OS in the channel formation region of the OS transistor, both a high on-current and an extremely low off-current can be realized.

[0077] Due to the large bandgap of the metal oxide and the difficulty of exciting electrons, and the large effective mass of holes, etc., the OS transistor may be less likely to cause avalanche breakdown, etc. compared to a general Si transistor. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. By being able to suppress hot carrier degradation, the OS transistor can be driven at a high drain voltage.

[0078] As the conductive layers 344A and 344B, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0079] The conductive layers 344A and 344B are shown in a single-layer configuration, but may also have a laminated configuration of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer configuration in which an aluminum film is laminated on a tungsten film, a two-layer configuration in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer configuration in which a copper film is laminated on a titanium film, and a two-layer configuration in which a copper film is laminated on a tungsten film may be used.

[0080] In addition, there are three-layer structures such as a titanium film or a titanium nitride film, on which an aluminum film or a copper film is laminated, and then a titanium film or a titanium nitride film is formed thereon; a molybdenum film or a molybdenum nitride film, on which an aluminum film or a copper film is laminated, and then a molybdenum film or a molybdenum nitride film is formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0081] The insulating layer 346 is provided so as to cover the conductive layers 344A and 344B and the semiconductor layer 342, and suppresses oxidation of the conductive layers 344A and 344B.

[0082] As the insulating layer 346, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. In addition, silicon oxynitride or silicon nitride can also be used as the insulating layer 346.

[0083] In particular, as the insulating layer 346, it is preferable to use an insulator containing one or both of aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), which contains oxides of aluminum or hafnium or both. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize during heat treatment in subsequent processes.

[0084] As the insulating layer 348, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0085] Openings are provided in the insulating layer 346 and the insulating layer 348 so that a part of the semiconductor layer 342 is exposed, and an insulating layer 350 and a conductive layer 352 are provided in the openings. The insulating layer 350 functions as a gate insulating film of the transistor 104A. The conductive layer 352 functions as a gate electrode of the transistor 104A.

[0086] Similar to the above-described insulating layer 340, the insulating layer 350 is preferably formed using an insulator that contains excessive oxygen and releases oxygen upon heating.

[0087] In addition, in order to efficiently supply the excessive oxygen possessed by the insulating layer 350 to the semiconductor layer 342, a metal oxide may be provided between the insulating layer 350 and the conductive layer 352. By providing the metal oxide, the diffusion of excessive oxygen from the insulating layer 350 to the conductive layer 352 is suppressed. That is, it is possible to suppress a decrease in the amount of excessive oxygen supplied to the semiconductor layer 342.

[0088] Note that the insulating layer 350 may have a stacked structure. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming the insulator that functions as the gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0089] The conductive layer 352 that functions as a gate electrode may have a single-layer structure or a stacked structure of two or more layers.

[0090] The conductive layer 352 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductive layer 352 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductive layer 352 may have a laminated structure, for example, a laminated structure with a conductive material having a function of suppressing diffusion of impurities such as tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0091] An insulating layer 354 and an insulating layer 356 are provided on the transistor 104A. A conductive layer 358 is provided on the insulating layer 336, the insulating layer 340, the insulating layer 346, the insulating layer 348, the insulating layer 354, and the insulating layer 356. The conductive layer 358 functions as an electrode for applying a signal to each wiring (rbl, wbl, rwl) of the semiconductor device 10 and an electrode of a node (FN). An insulating layer 360 and a conductive layer 362 are provided on the insulating layer 356 and the conductive layer 358.

[0092] It is preferable to use a material having barrier properties against oxygen and hydrogen for the insulating layer 354. For example, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide can be used for the insulating layer 354.

[0093] By applying a material with a relatively low dielectric constant to the insulating layer 356, the parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 356.

[0094] The conductive layer 358 can be provided using the same material as the conductive layer 326 or the like. The conductive layer 362 can be provided using the same material as the conductive layer 330 or the like. The conductive layer 362 is electrically connected to an electrode for applying a signal to each wiring (rbl, wbl, rwl) of the semiconductor device 10 and a node (FN).

[0095] As described above, one aspect of the present invention can provide a semiconductor device excellent in low power consumption. Or, one aspect of the present invention can provide a semiconductor device in which a leakage current is reduced and which is excellent in reduction of standby power. Or, a semiconductor device having a novel configuration can be provided.

[0096] FIG. 2A is a block diagram showing a configuration example of a memory cell array having the memory circuit shown as the semiconductor device 10 in FIG. 1A. The memory cell array 20 has a total of m×n semiconductor devices 10, where m (m is an integer of 2 or more) are arranged in a column and n (n is an integer of 2 or more) are arranged in a row. The semiconductor devices 10 are arranged in a matrix.

[0097] In FIG. 2A, [1,1], [i,1], [m,1], [1,j], [i,j], [m,j], [1,n], [i,n], [m,n] (where i is an integer from 1 to m and j is an integer from 1 to n) are addresses of the semiconductor device 10. For example, the semiconductor device 10 denoted as [i,j] is the semiconductor device 10 at the i-th row and j-th column.

[0098] The memory cell array 20 also has n wirings wbl (wbl(1) to wbl(n)) that function as write bit lines, n wirings rbl (rbl(1) to rbl(n)) that function as read bit lines, m wirings wwl (wwl(1) to wwl(m)) that function as write word lines, and m wirings rwl (rwl(1) to rwl(m)) that function as read word lines.

[0099] Each semiconductor device 10 is electrically connected to the wiring wbl, the wiring rbl, the wiring wwl, and the wiring rwl. For example, the semiconductor device 10 with the address [i,j] is electrically connected to the word line driver circuit 132 via the wiring wwl(i) and the wiring rwl(i), and is electrically connected to the bit line driver circuit 142 via the wiring wbl(j) and the wiring rbl(j).

[0100] FIG. 2B is a circuit diagram showing a configuration example applicable to the semiconductor device 10 shown in FIG. 1A.

[0101] The semiconductor device 10A includes a transistor 103A, a transistor 104A, and a capacitor element 113. One of the source or drain of the transistor 104A is electrically connected to the gate of the transistor 103A, the other of the source or drain of the transistor 104A is electrically connected to the wiring wbl, and the gate of the transistor 104A is electrically connected to the wiring wwl. Also, one of the source or drain of the transistor 103A is electrically connected to the wiring rbl, and the other of the source or drain of the transistor 103A is electrically connected to the wiring sl to which a fixed potential is applied. Here, a connection portion where one of the source or drain of the transistor 104A and the gate of the transistor 103A are electrically connected is defined as a node FN. One of the capacitor element 113 is electrically connected to the node FN. The other of the capacitor element 113 is electrically connected to the wiring rwl. A potential Vctl_1 for controlling the threshold voltage is applied to the back gate electrode of the transistor 103A. A potential Vctl_2 for controlling the threshold voltage is applied to the back gate electrode of the transistor 104A.

[0102] FIG. 2C is a circuit diagram showing a configuration example applicable to the semiconductor device 10 shown in FIG. 1A, which is different from FIG. 2B.

[0103] The semiconductor device 10B includes a transistor 103A, a transistor 103B, a transistor 104A, and a capacitor element 113. One of the source or drain of the transistor 104A is electrically connected to the gate of the transistor 103A, the other of the source or drain of the transistor 104A is electrically connected to the wiring wbl, and the gate of the transistor 104A is electrically connected to the wiring wwl. Also, one of the source or drain of the transistor 103A is electrically connected to one of the source or drain of the transistor 103B, and the other of the source or drain of the transistor 103A is electrically connected to the wiring sl to which a fixed potential is applied. The gate of the transistor 103B is electrically connected to the wiring rwl. The other of the source or drain of the transistor 103B is electrically connected to the wiring rbl. Here, the connection portion where one of the source or drain of the transistor 104A is electrically connected to the gate of the transistor 103A is defined as the node FN. One of the capacitor element 113 is electrically connected to the node FN. The other of the capacitor element 113 is applied with a fixed potential. A potential Vctl_1 for controlling the threshold voltage is applied to the back gate electrodes of the transistors 103A and 103B. A potential Vctl_2 for controlling the threshold voltage is applied to the back gate electrode of the transistor 104A.

[0104] In the circuit diagrams of the semiconductor devices illustrated in FIGS. 1A, 2B, and 2C, the transistors 103A and 103B are illustrated as p-channel types, but other configurations may be used. For example, as illustrated in FIGS. 3A, 3B, and 3C for the semiconductor devices 10C, 10D, and 10E, the transistors 113A and 113B may be n-channel type transistors. Since the configurations other than the transistors 113A and 113B are the same as those shown in FIGS. 1A, 2B, and 2C, the description thereof is omitted.

[0105] The semiconductor devices 10, and 10A to 10E that function as the above-described memory circuits are gain cell type memory cells composed of 2 transistors and 1 capacitor element (2T1C) or 3 transistors and 1 capacitor element (3T1C). The gain cell type memory cell can operate as a memory by amplifying the stored charge with the nearest transistor even when the capacitance for storing charge is small. The semiconductor devices 10, and 10A to 10E are the above-described NOSRAM. Since NOSRAM can read the stored data without destroying it (non-destructive readout), it is suitable for the multiplication and accumulation operations of neural networks that repeat a large number of data read operations.

[0106] FIG. 4 is a block diagram showing a configuration example of a peripheral circuit of a memory cell array 20 including the semiconductor device 10.

[0107] The memory system 99 has a peripheral circuit 30 and a memory cell array 20. The peripheral circuit 30 has a row decoder 41, a word line driver circuit 42, a control logic circuit 31, a column decoder 32, an output driver 33, and a bit line driver circuit 34. The memory cell array 20 has the semiconductor device 10, wiring wwl, wiring rwl, wiring wbl, and wiring rbl.

[0108] Potentials VSS, VDD, VDHR, VDHW, VBP, and VBN are input to the memory system 99. The potential VDHW is the high power supply potential of the wiring wwl. The potential VDHR is the high power supply potential of the wiring rwl. The potential VBP is the potential applied to the back gate electrode of the p-channel type transistor 103A in the peripheral circuit 30. The potential VBN is the potential applied to the back gate electrode of the n-channel type transistor 103A in the peripheral circuit 30. The potentials VBP and VBN are potentials (signals) that can be switched according to the operation mode and the like.

[0109] The memory system 99 receives a clock signal CLK, a chip enable signal CE, a global write enable signal GW, a byte write enable signal BW, an address signal ADDR, and a data signal WDATA. The memory system 99 outputs a data signal RDATA. Note that these signals are digital signals represented by a high level or a low level (which may be represented as High or Low, H or L, 1 or 0, etc.). The byte write enable signal BW, the address signal ADDR, the data signal WDATA, and the data signal RDATA are signals having a plurality of bits.

[0110] In this specification and the like, for a signal having a plurality of bits, for example, when the byte write enable signal BW has 4 bits, it is denoted as the byte write enable signal BW[3:0]. This means that the byte write enable signal has BW[0] to BW[3], and when it is necessary to specify one bit, for example, it is denoted as the byte write enable signal BW[0]. Also, when denoted as the byte write enable signal BW, it refers to any bit.

[0111] For example, the byte write enable signal BW can be 4 bits, and the data signals WDATA and RDATA can be 32 bits. That is, the byte write enable signal BW, the data signal WDATA, and the data signal RDATA are denoted as the byte write enable signal BW[3:0], the data signal WDATA[31:0], and the data signal RDATA[31:0], respectively.

[0112] Note that in the memory system 99, each of the above-described circuits, each potential, and each signal can be selected as necessary. Alternatively, other circuits, other potentials, or other signals may be added.

[0113] The control logic circuit 31 processes the chip enable signal CE and the global write enable signal GW to generate control signals for the row decoder 41 and the column decoder 32. For example, when the chip enable signal CE is at a high level and the global write enable signal GW is at a low level, the row decoder 41 and the column decoder 32 perform a read operation. When the chip enable signal CE is at a high level and the global write enable signal GW is at a high level, the row decoder 41 and the column decoder 32 perform a write operation. When the chip enable signal CE is at a low level, regardless of whether the global write enable signal GW is at a high level or a low level, the row decoder 41 and the column decoder 32 can be in a standby operation. The signals processed by the control logic circuit 31 are not limited to this, and other signals may be input as necessary.

[0114] Also, the control logic circuit 31 processes the byte write enable signals BW[3:0] to control the write operation. Specifically, when the byte write enable signal BW[0] is at a high level, the row decoder 41 and the column decoder 32 perform a write operation on the data signal WDATA[7:0]. Similarly, when the byte write enable signal BW[1] is at a high level, a write operation on the data signal WDATA[15:8], when the byte write enable signal BW[2] is at a high level, a write operation on the data signal WDATA[23:16], and when the byte write enable signal BW[3] is at a high level, a write operation on the data signal WDATA[31:24] are performed.

[0115] In addition to the control signals generated by the control logic circuit 31 described above, an address signal ADDR is input to the row decoder 41 and the column decoder 32.

[0116] The row decoder 41 decodes the address signal ADDR and generates a control signal for the word line driver circuit 42. The word line driver circuit 42 has a function of driving the wiring wwl and the wiring rwl. The word line driver circuit 42 selects the wiring wwl or the wiring rwl of the access target row based on the control signal of the row decoder 41. Further, when the memory cell array 20 is divided into a plurality of blocks, a pre-decoder 43 may be provided. The pre-decoder 43 has a function of decoding the address signal ADDR and determining the accessed block.

[0117] The column decoder 32 and the bit line driver circuit 34 have functions of writing the data input by the data signal WDATA into the memory cell array 20, reading data from the memory cell array 20, and amplifying the read data and outputting it to the output driver 33.

[0118] The output driver 33 has a function of outputting the data read from the memory cell array 20 from the memory system 99 as the data signal RDATA.

[0119] Further, the bit line driver circuit 34 includes a precharge circuit 51, a sense amplifier circuit 52, an output MUX (multiplexer) circuit 53, and a write driver circuit 54.

[0120] FIG. 5 is a circuit diagram showing a configuration example of a circuit 50 applicable to the bit line driver circuit 34. In the present embodiment, it is assumed that the memory cell array 20 has 128 semiconductor devices 10 in one row (n = 128).

[0121] The circuit 50 includes transistors M21 to M26, a sense amplifier 61, an AND circuit 62, an analog switch 63, and an analog switch 64.

[0122] Circuit 50 operates according to signals SEN[3:0], SEP[3:0], PRE, RSEL[3:0], WSEL, GRSEL[3:0], and GWSEL[15:0]. Note that among the 4-bit signal SEN[3:0], any one-bit signal is input to one circuit 50. The same applies to other signals (such as SEP[3:0]) having multiple bits.

[0123] Data DIN[31:0] is written into memory cell array 20 by bit line driver circuit 34, and data DOUT[31:0] is read from memory cell array 20. One circuit 50 has the function of writing any one-bit data out of the 32-bit data DIN[31:0] into memory cell array 20 and reading any one-bit data out of the 32-bit data DOUT[31:0] from memory cell array 20. Note that data DIN[31:0] and data DOUT[31:0] are internal signals and correspond to data signal WDATA and data signal RDATA, respectively.

[0124] Transistor M21 constitutes precharge circuit 51. By transistor M21, wiring rbl is precharged to the potential VSS. Signal PRE is a precharge signal, and the conduction state of transistor M21 is controlled by signal PRE.

[0125] Sense amplifier 61 constitutes sense amplifier circuit 52. Sense amplifier 61 determines the high level or low level of the data input to wiring rbl during the read operation. Also, sense amplifier 61 functions as a latch circuit that temporarily holds data DIN input from write driver circuit 54 during the write operation.

[0126] The sense amplifier 61 shown in FIG. 5 is a latch-type sense amplifier. The sense amplifier 61 has two inverter circuits, and the input node of one inverter circuit is connected to the output node of the other inverter circuit. If the input node of one inverter circuit is node SA and the output node is node SAb, complementary data is held at node SA and node SAb.

[0127] The signal SEN and the signal SEP are sense amplifier enable signals for activating the sense amplifier 61, and the reference potential Vref is a read determination potential. The sense amplifier 61 determines whether the potential of node SAb at the time of activation is at a high level or a low level based on the reference potential Vref.

[0128] The AND circuit 62 controls the conduction state between node SA and the wiring wbl. Also, the analog switch 63 controls the conduction state between node SAb and the wiring rbl, and the analog switch 64 controls the conduction state between node SA and the wiring that supplies the reference potential Vref.

[0129] The signal WSEL is a write selection signal and controls the AND circuit 62. The signal RSEL is a read selection signal and controls the analog switch 63 and the analog switch 64.

[0130] The transistors M22 and M23 constitute the output MUX circuit 53. The signal GRSEL[3:0] is a global read selection signal and controls the output MUX circuit 53. The output MUX circuit 53 has a function of selecting 32 wiring rbl for reading data from 128 wiring rbl. The output MUX circuit 53 functions as a 128-input, 32-output multiplexer. The output MUX circuit 53 reads the data DOUT[31:0] from the sense amplifier circuit 52 and outputs it to the output driver 33.

[0131] Note that the number of wirings rbl from which the output MUX circuit 53 reads data is not limited to 32. For example, it may be 16 or may be 64. Further, the bit line driver circuit 34 may be configured not to have the output MUX circuit 53. In that case, data read from 128 wirings rbl is output from the sense amplifier circuit 52 to the output driver 33. The number of wirings rbl from which the output MUX circuit 53 reads data, or the presence or absence of the output MUX circuit 53 can be adjusted according to the configuration of the output driver 33 or the like.

[0132] Transistors M24 to M26 constitute the write driver circuit 54. The signal GWSEL[15:0] is a global write selection signal and controls the write driver circuit 54. The write driver circuit 54 has a function of writing data DIN[31:0] to the sense amplifier circuit 52.

[0133] The write driver circuit 54 has a function of selecting a column to which data DIN[31:0] is written. The write driver circuit 54 performs data writing in units of bytes, half words, or one word according to the signal GWSEL[15:0].

[0134] The circuit 50 is electrically connected to a wiring to which data DIN[k] (k is an integer from 0 to 31) is supplied every four columns. Further, the circuit 50 is electrically connected to a wiring to which data DOUT[k] is supplied every four columns.

[0135] FIG. 6 is a diagram for explaining a cross-sectional structure of a transistor applicable to the peripheral circuit 30 illustrated in FIG. 4. The peripheral circuit 30 preferably has a configuration including a complementary logic circuit of a p-channel type transistor and an n-channel type transistor. By adopting such a configuration, power consumption can be reduced and the operation speed can be increased.

[0136] As shown in FIG. 6, the Si transistor in one aspect of the present invention is a transistor provided with a well region that functions as a back gate electrode in FD-SOI (Fully-Depleted Silicon-ON-Insulator). As shown in FIG. 6, on a silicon substrate 300, for example, an n-channel transistor 103A and a p-channel transistor 103B can be separately fabricated. Note that a transistor 104A, which is an OS transistor, can be provided on the layer where the transistors 103A and 103B are provided.

[0137] In the silicon substrate 300, a well region 305 containing an n-type impurity is provided in a region where the n-channel transistor 103A and the p-channel transistor 103B are provided. In the well region 305, a well region 306A having n-type conductivity imparted thereto is provided in a region where the p-channel transistor 103A is provided, and a well region 306B having p-type conductivity imparted thereto is provided in a region where the n-channel transistor 103B is provided. The well region 306A provided opposite to the gate electrode of the transistor 103A across the channel formation region functions as the back gate electrode of the transistor 103A. The well region 306B provided opposite to the gate electrode of the transistor 103B across the channel formation region functions as the back gate electrode of the transistor 103B.

[0138] In the semiconductor layer on the n-type well region 306A where the p-channel transistor 103A is provided, impurity regions 310A and 310B are formed by selectively imparting a p-type impurity element. In the semiconductor layer on the p-type well region 306B where the n-channel transistor 103B is provided, impurity regions 310D and 310E are formed by selectively imparting an n-type impurity element.

[0139] An impurity region 312A is formed in a region where the insulating layer, which is the BOX layer, is removed to apply a potential to the well region 306A. An impurity region 312B is formed in a region where the insulating layer, which is the BOX layer, is removed to apply a potential to the well region 306B.

[0140] In addition to the transistors 103A and 103B, in the silicon substrate 300, the insulating layer which is the BOX layer and the semiconductor layer may be removed, and n-channel and p-channel transistors (bulk transistors) may be provided on the silicon substrate 300. Alternatively, a transistor having a charge storage layer may be provided on the silicon substrate 300. Although complementary transistors are illustrated as the transistors applicable to the peripheral circuit 30, a logic circuit may be configured by only one of n-channel type or p-channel type. In particular, by configuring an Si transistor with only p-channel type, a complementary logic circuit with the n-channel type composed of OS transistors can be configured, so that the manufacturing process can be simplified.

[0141] One aspect of the present invention can be configured such that the potential applied to the back gate electrode can be switched in an Si transistor. The potential applied to the back gate electrode can be switched according to the operating state of the memory circuit.

[0142] For example, the memory circuit can be operated by switching it to four modes. As one of the four modes, there is a high-speed mode in which the power supply voltage to the memory circuit is increased and writing and reading to the memory circuit are performed in a short time. As one of the four modes, there is a normal mode in which writing and reading to the memory circuit are performed at a lower speed than in the high-speed mode. As one of the four modes, there is a low-power mode in which the power supply voltage to the memory circuit is decreased and writing and reading to the memory circuit are performed at a lower speed than in the normal mode. As one of the four modes, there is a sleep mode in which the power supply voltage to the memory circuit is extremely decreased and the leakage current in the memory circuit is reduced.

[0143] In the above four modes, the changes in the potentials VDD, VBP, and VBN, and the direction of the body bias representing the magnitude relationship of the potential between the silicon substrate 300 and the Si transistor are summarized and illustrated in Table 1. In Table 1, the high-speed mode is illustrated as "High Speed". In Table 1, the normal mode is illustrated as "Normal". In Table 1, the low-power mode is illustrated as "Low Power". In Table 1, the sleep mode is illustrated as "Sleep".

[0144]

Table 1

[0145] In Table 1, the potential VDD1 is greater than the potential VDD2. Also, the potential VDD2 is greater than the potential VDD3. Also, the potential VDD3 is greater than the potential VDD4. Also, the potential VBP1 is greater than 0V. Also, the potential VDD2 is greater than the potential VBP1. Also, the potential VBP3 is greater than the potential VDD2. Also, the potential VBP4 is greater than the potential VBP3. Also, the potential VBN1 is greater than 0V. Also, the potential VBN3 is less than 0V. Also, the potential VBN4 is less than the potential VBN3. The body bias has a forward direction, 0, and a reverse direction. Assume that the magnitude of the potential VBP1, i.e., the absolute value of the potential, is equal to the magnitude of the potential VBN1, i.e., the absolute value of the potential.

[0146] Figure 7 is a diagram for explaining the magnitude relationship of the potentials shown in Table 1. In Figure 7, the high-speed mode is illustrated as period T1, the normal mode as period T2, the low-power mode as period T3, and the sleep mode as period T4.

[0147] During period T1, the power supply voltages VDD1 - VSS (illustrated by thick solid and thick dashed lines) are large, and voltages VBN and VBP (illustrated by thin solid and thin dashed lines) are applied to the back gate electrode to reduce the threshold voltage. Therefore, the on / off switching of each transistor can be performed at high speed. During period T2, the power supply voltage VDD2 - VSS is made smaller compared to period T1, and voltages VBN and VBP are applied to the back gate electrode to increase the threshold voltage compared to period T1. Since the threshold voltage of each transistor can be increased, the through - current can be reduced. During period T3, the power supply voltage VDD3 - VSS is made even smaller compared to period T2, and voltages VBN and VBP are applied to the back gate electrode to further increase the threshold voltage compared to period T2. Since the threshold voltage of each transistor can be increased, the through - current can be further reduced. During period T4, the power supply voltage VDD4 - VSS is made even smaller compared to period T3, and voltages VBN and VBP are applied to the back gate electrode to further increase the threshold voltage compared to period T3. Since the threshold voltage of each transistor can be further increased, the leakage current can be extremely reduced.

[0148] As described above, one aspect of the present invention can provide a semiconductor device miniaturized by laminating an Si transistor and an OS transistor. Or, one aspect of the present invention can provide a semiconductor device that functions as a low - power - consumption memory circuit by having a back gate electrode for controlling the threshold voltage in both the Si transistor and the OS transistor. Or, one aspect of the present invention can provide a semiconductor device with a novel configuration.

[0149] (Embodiment 2) In the present embodiment, the configuration of an integrated circuit including the configuration of the semiconductor device 10 described in the above embodiment will be described with reference to FIGS. 8 and 9.

[0150] FIG. 8 is an example of a block diagram for explaining a configuration example of an integrated circuit including the configuration of the semiconductor device 10.

[0151] The integrated circuit 390 shown in FIG. 8 includes a CPU 410, an accelerator 420, on-chip memories 431A and 431B, a system controller 432, a power management circuit 433, a memory interface circuit 434, a GPIO (General Purpose Input / Output) 435, an input / output unit 441, a power circuit 442, a bus bridge circuit 450, a timer circuit 451, a watchdog circuit 452, a transceiver circuit 453, an interface circuit 454, and an interface circuit 455.

[0152] The CPU 410 marked with "M" in the figure controls devices (marked with "S" in the figure) connected to the high-speed bus 440A. The CPU 410 can transmit and receive signals such as data and addresses via the high-speed bus 440A. The accelerator 420 may have a circuit configuration for performing repetitive arithmetic operations such as multiply-accumulate operations.

[0153] The high-speed bus 440A is a bus for transmitting and receiving various signals between the CPU 410 and other circuits at high speed. As an example, AMBA (Advanced Microcontroller Bus Architecture)-AHB (Advanced High-performance Bus) can be used as the bus.

[0154] The on-chip memories 431A and 431B have a circuit configuration for storing data or programs input / output to circuits included in the integrated circuit 390, such as the CPU 410 or the accelerator 420. For the on-chip memory 431A, for example, NOSRAM which is an OS memory can be used. For the on-chip memory 431B, for example, a non-volatile memory using Si transistors can be used.

[0155] The system controller 432 has a circuit configuration for performing reset control of each circuit within the integrated circuit 390 and monitoring system lock-up.

[0156] The power management circuit 433 has a circuit configuration for controlling clock gating or power gating of circuits such as CPU cores included in the integrated circuit 390.

[0157] The memory interface circuit 434 has a circuit configuration for transmitting and receiving data with a memory device external to the integrated circuit 390.

[0158] The GPIO 435 has a circuit configuration for transmitting and receiving signals to and from external general-purpose devices.

[0159] The input / output unit 441 has a circuit configuration for converting signals input and output to and from the outside into a predetermined format. Also, the input / output unit 441 supplies a clock signal (Clock) supplied from the outside to each circuit of the integrated circuit 390.

[0160] The power supply circuit 442 is a circuit for generating voltages used within the integrated circuit 390. For example, it is a circuit for generating potentials VDD, VBP, VBN, etc. applied to transistors.

[0161] The low-speed bus 440B is a bus for transmitting and receiving various signals between the timer circuit 451, watchdog circuit 452, transceiver circuit 453, interface circuit 454, and interface circuit 455 at a low speed. As an example, AMBA-APB (Advanced Peripheral Bus) can be used as the bus. Transmission and reception of various signals between the high-speed bus 440A and the low-speed bus 440B are performed via the bus bridge circuit 450. The bus bridge circuit 450 marked with "M" in the figure controls devices (marked with "S" in the figure) connected to the low-speed bus 440B.

[0162] The timer circuit 451 and watchdog circuit 452 have a circuit configuration for performing interrupt processing in response to requests received from peripheral devices.

[0163] The transmission / reception circuit 453, the interface circuit 454, and the interface circuit 455 have a circuit configuration for functioning interfaces such as UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface).

[0164] FIGS. 9A and 9B are diagrams showing an example of the arrangement of circuit blocks when integrated into an SoC. Each configuration illustrated in the block diagram of FIG. 8, such as the integrated circuit 390 illustrated in FIG. 9A, can be arranged by dividing regions on the chip.

[0165] Note that the on-chip memory 431A described in FIG. 8 can be configured by a storage circuit composed of OS transistors, for example, NOSRAM or the like. That is, the on-chip memory 431A can be provided by being stacked on a transistor having Si transistors. Therefore, when integrated into an SoC, it is also possible to integrate the on-chip memory 431A and the on-chip memory 431B and arrange them in the same region, as in the integrated circuit 390E illustrated in FIG. 9B.

[0166] According to one aspect of the present invention described above, a novel semiconductor device and an electronic device can be provided. Or, according to one aspect of the present invention, a semiconductor device and an electronic device with low power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device and an electronic device capable of suppressing heat generation can be provided.

[0167] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0168] (Embodiment 3) In this embodiment, an electronic device, a moving body, and an arithmetic system to which the integrated circuit 390 described in the above embodiment can be applied will be described with reference to FIGS. 10 to 12.

[0169] FIG. 10A illustrates an external view of an automobile as an example of a moving body. FIG. 10B is a diagram simplifying the data exchange inside the automobile. The automobile 590 has a plurality of cameras 591 and the like. Further, the automobile 590 is provided with various sensors (not shown) such as an infrared radar, a millimeter-wave radar, and a lidar.

[0170] In the automobile 590, the above integrated circuit 390 can be used for the cameras 591 and the like. The automobile 590 processes a plurality of images obtained by the cameras 591 in a plurality of imaging directions 592 with the integrated circuit 390 described in the above embodiment, and collectively analyzes the plurality of images by a host controller 594 and the like via a bus 593 and the like, thereby determining the surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, and performing autonomous driving. Further, it can be used in a system for performing road guidance, danger prediction, and the like.

[0171] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (widening the dynamic range), restoring the image of a lensless image sensor, positioning, character recognition, and reducing reflection specular highlights can be performed.

[0172] Note that, in the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. An artificial intelligence-based system can be provided by applying the computer according to one aspect of the present invention to these moving bodies.

[0173] FIG. 11A is an external view showing an example of a portable electronic device. FIG. 11B is a diagram simplifying the data exchange inside the portable electronic device. The portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0174] In the portable electronic device 595, the integrated circuit 390 can be provided on the printed wiring board 596. The portable electronic device 595 can improve the convenience of the user by processing and analyzing a plurality of data obtained from a speaker 597, a camera 598, a microphone 599, etc. using the integrated circuit 390 described in the above embodiment. Further, it can be used in a system for performing voice guidance, image search, etc.

[0175] In the integrated circuit 390, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (widening the dynamic range), restoring the image of a lensless image sensor, positioning, character recognition, and reducing specular reflections can be performed.

[0176] The portable game machine 1100 shown in FIG. 12A has a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, etc. The housing 1101, the housing 1102, and the housing 1103 can be removed. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housing 1102 and the housing 1103 to the housing 1109, the housing 1102 and the housing 1103 are integrated and function as an operation unit. The integrated circuit 390 shown in the previous embodiment can be incorporated into chips etc. provided on the substrates of the housing 1102 and the housing 1103.

[0177] FIG. 12B shows a USB connection type stick-shaped electronic device 1120. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the substrate 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 etc. of the substrate 1124.

[0178] Figure 12C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0179] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0180] (Supplementary Note Regarding the Descriptions in this Specification, etc.) Regarding the above embodiments and the descriptions of each configuration in the embodiments, the following supplementary notes are provided.

[0181] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form an aspect of the present invention. Also, when multiple configuration examples are shown in one embodiment, it is possible to appropriately combine the configuration examples.

[0182] Note that the content described in one embodiment (even part of the content) can be applied, combined, or replaced with respect to the content described in another part (even part of the content) of the same embodiment and / or the content described in one or more other embodiments (even part of the content).

[0183] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text written in the specification.

[0184] Note that the figure (even part of it) described in one embodiment can be combined with another part of the figure, another figure (even part of it) described in the same embodiment, and / or the figure (even part of it) described in one or more other embodiments to form even more figures.

[0185] In this specification and the like, in a block diagram, components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate components by function, and there may be cases where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0186] Also, in the drawings, the size, layer thickness, or area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing shifts.

[0187] Also, the positional relationship of the components illustrated in the drawings and the like is relative. Therefore, when explaining the components with reference to the drawings, terms such as "above" and "below" indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description in this specification and can be appropriately rephrased according to the situation.

[0188] In this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source or drain" (or the second electrode, or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of the transistor can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode.

[0189] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0190] Also, in this specification and the like, voltage and potential can be appropriately interchanged. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground voltage (earthing voltage), the voltage can be interchanged with the potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to a wiring or the like may be changed.

[0191] Also, in this specification and the like, a node can be interchanged with a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., according to the circuit configuration, device structure, etc. Also, it is possible to interchange a terminal, wiring, etc. with a node.

[0192] In this specification and the like, when it is stated that A and B are connected, it means that A and B are electrically connected. Here, when A and B are electrically connected, it means a connection where an object (such as an element like a switch, transistor element, or diode, or a circuit including the element and wiring) exists between A and B and electrical signal transmission between A and B is possible. Note that when A and B are electrically connected, it includes the case where A and B are directly connected. Here, when A and B are directly connected, it means a connection where electrical signal transmission between A and B is possible through a wiring (or electrode) etc. between A and B without passing through the above object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0193] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to allow current to flow. Alternatively, a switch refers to a device that has a function of selecting and switching a path for current to flow.

[0194] In this specification and the like, the channel length refers to, for example, in a top view of a transistor, the distance between the source and the drain in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate overlap, or in a region where the channel is formed.

[0195] In this specification and the like, the channel width refers to, for example, in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in a region where the channel is formed, the length of the portion where the source and the drain face each other.

[0196] Note that in this specification and the like, terms such as "film" and "layer" can be interchanged with each other depending on the case or the situation. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Alternatively, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer".

Description of Reference Numerals

[0197] M21: Transistor, M22: Transistor, M23: Transistor, M24: Transistor, M26: Transistor, T1: Period, T2: Period, T3: Period, T4: Period, VBN1: Potential, VBN3: Potential, VBN4: Potential, VBP1: Potential, VBP3: Potential, VBP4: Potential, Vctl_1: Potential, Vctl_2: Potential, VDD1: Potential, VDD2: Potential, VDD3: Potential, VDD4: Potential, Vin1: Potential, 10: Semiconductor device, 10A: Semiconductor device, 10B: Semiconductor device, 10C: Semiconductor device, 10D: Semiconductor device, 10E: Semiconductor device, 20: Memory cell array, 30: Peripheral circuit, 31: Control logic circuit, 32: Column decoder, 33: Output driver, 34: Bit line driver circuit, 41: Row decoder, 42: Word line driver circuit, 43: Predecoder, 45: Watchdog circuit, 50: Circuit, 51: Precharge circuit, 52: Sense amplifier circuit, 53: Output MUX circuit, 54: Driver circuit, 61: Sense amplifier, 62: AND circuit, 63: Analog switch, 64: Analog switch, 99: Memory system, 103A: Transistor, 103B: Transistor, 104A: Transistor, 113: Capacitor element, 113A: Transistor, 113B: Transistor, 132: Word line driver circuit, 142: Bit line driver circuit, 147: Circuit, 300: Silicon substrate, 302: Insulating layer, 305: Well region, 306: Well region, 306A: Well region, 306B: Well region, 308: Insulating layer, 310A: Impurity region, 310B: Impurity region, 310C: Channel formation region, 310D: Impurity region, 310E: Impurity region, 312: Impurity region, 312A: Impurity region, 312B: Impurity region, 314: Insulating layer, 316: Conductive layer, 318: Insulating layer, 322A: Conductive layer, 322B: Conductive layer, 322C: Conductive layer, 322D: Conductive layer, 324: Insulating layer, 326: Conductive layer, 328: Insulating layer, 330: Conductive layer, 332: Insulating layer, 334: Conductive layer, 336: Insulating layer, 338: Conductive layer, 340: Insulating layer, 342: Semiconductor layer, 344A: Conductive layer, 344B: Conductive layer, 346: Insulating layer, 348: Insulating layer, 350: Insulating layer, 352: Conductive layer, 354: Insulating layer, 356: Insulating layer, 358: Conductive layer, 360: Insulating layer, 362: Conductive layer, 390: Integrated circuit, 390E: Integrated circuit, 410: CPU420: Accelerator, 431A: On-chip Memory, 431B: On-chip Memory, 432: System Controller, 433: Power Management Circuit, 434: Memory Interface Circuit, 440: High-speed Bus, 440A: High-speed Bus, 440B: Low-speed Bus, 441: Input / Output Unit, 442: Power Circuit, 450: Bus Bridge Circuit, 451: Timer Circuit, 452: Watchdog Circuit, 453: Transceiver Circuit, 454: Interface Circuit, 455: Interface Circuit, 590: Automobile, 591: Camera, 592: Imaging Direction, 593: Bus, 594: Host Controller, 595: Portable Electronic Device, 596: Printed Wiring Board, 597: Speaker, 598: Camera, 599: Microphone, 1100: Portable Game Machine, 1101: Housing, 1102: Housing, 1103: Housing, 1104: Display Unit, 1105: Connection Unit, 1107: Operation Key, 1108: Housing, 1109: Housing, 1120: Electronic Device, 1121: Housing, 1122: Cap, 1123: USB Connector, 1124: Substrate, 1125: Memory Chip, 1126: Controller Chip, 1130: Robot, 2101: Sensor, 2106: Sensor, 2110: Control Circuit,

Claims

[Claim 1] a first transistor and a second transistor, and a capacitance element; the first transistor has a first gate and a second gate; a first gate of the first transistor is electrically connected to one of a source and a drain of the second transistor; a first gate of the first transistor is electrically connected to a first terminal of the capacitive element; a second gate of the first transistor formed in a silicon substrate; The first transistor and the second transistor are formed in different layers.

Images