Semiconductor device and communication system

Abstract

To provide a semiconductor device that can realize data writing to a target device with an effective configuration.SOLUTION: A semiconductor device (1) comprises a communication unit (2) configured to perform data communication using a clock (SCL) and communication data (SDA), a register (21), an input terminal (Ti), and an output terminal (To). When an enable input signal that is input to the input terminal is at a first level, the communication unit is capable of rewriting data in the register based on a command via the data communication, and an enable output signal that is output from the output terminal is a signal that can take the first level or a second level.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, communication conforms to a serial communication standard called I2C (Inter-Integrated Circuit). A semiconductor device that performs reception is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-97489

[0004] [overview] In I2C, multiple slave devices can be connected to a master device via the I2C bus. It is possible to connect.

[0005] An object of the present disclosure is to provide a semiconductor device that can realize data writing to a target device with an effective configuration.

[0006] A semiconductor device according to an embodiment of the present disclosure includes: A communication unit configured to perform data communication using a clock and communication data; A register; An input terminal; An output terminal; Equipped with the communication unit is capable of rewriting data in the register based on a command through the data communication when an enable input signal input to the input terminal is at a first level; The enable output signal output from the output terminal is a signal that can take the first level or the second level. [Brief description of the drawings]

[0007]

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[0008] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Comparative Example> Here, before describing the embodiments of the present disclosure, a comparative example for comparison will be described. FIG. 18 is a diagram showing the configuration of a communication system 200 according to a comparative example. The communication system 200 is a system that performs I2C communication. The communication system 200 includes a control device (not shown), a plurality of semiconductor devices 100A to 100C, and a bus 300. The control device and the semiconductor devices 100A to 100C communicate via the bus 300. Note that the number of semiconductor devices is not limited to three as shown in FIG. 18, and may be a plurality.

[0010] The control device is configured by, for example, a microcomputer and functions as a master device. The semiconductor devices 100A to 100C are each configured as an IC (integrated circuit) that functions as a slave device. The semiconductor devices 100A to 100C are the same product.

[0011] The bus 300 has a signal line 301 for SCL (serial clock) and a signal line 302 for SDA (serial data). The control device and the semiconductor devices 100A to 100C are connected to the signal line 301 and the signal line 302. The signal line 301 and the signal line 302 are each pulled up by a pull-up resistor (not shown).

[0012] The semiconductor devices 100A to 100C each need to set an address (device address) for communication. In the configuration of FIG. 18, external resistors RA to RC for setting are connected to the semiconductor devices 100A to 100C respectively for address setting. The external resistors RA to RC are configured as pull-down resistors. Note that the external resistors RA to RC may be pull-up resistors. The semiconductor devices 100A to 100C need to be set to different addresses, and it is necessary to make the resistance values of the external resistors RA to RC different. Also, when the semiconductor devices 100A to 100C and the substrates on which they are mounted are configured as modules, it is necessary to fabricate and manage different types of modules.

[0013] Also, conventionally, even when trying to set addresses for a plurality of semiconductor devices without using the above external resistors, since the bus 300 is a common bus for a plurality of semiconductor devices, an address cannot be set for an arbitrary semiconductor device (target device).

[0014] <First Embodiment> In view of the above problems, an embodiment of the present disclosure as described below is implemented. FIG. 1 is a diagram showing the configuration of a communication system 20 according to the first embodiment of the present disclosure. The communication system 20 includes a control device 10 and semiconductor devices 1A to 1C. The communication system 20 is a system that performs I2C communication. However, in the present disclosure, the communication format is not limited to I2C.

[0015] The control device 10 functions as a master device. The semiconductor devices 1A to 1C are each an IC (IC chip) that functions as a slave device. Note that the number of semiconductor devices is not limited to three, and may be a plurality. The control device 10 and the semiconductor devices 1A to 1C are connected by a bus 300 for I2C communication. The bus 300 has a signal line 301 for SCL and a signal line 302 for SDA. The bus 300 is a common bus for the semiconductor devices 1A to 1C.

[0016] The semiconductor devices 1A to 1C are the same product. However, the semiconductor devices 1A to 1C may have the configurations according to the present disclosure in common even if they are different products. The semiconductor devices 1A to 1C each have a clock terminal T1 and a data terminal T2 as external terminals for establishing electrical connection with the outside. A signal line 301 is connected to each clock terminal T1 of the semiconductor devices 1A to 1C. A signal line 302 is connected to each data terminal T2 of the semiconductor devices 1A to 1C.

[0017] The semiconductor devices 1A to 1C each further include an input terminal Ti and an output terminal To as external terminals. Between the control device 10 and the input terminal Ti of the semiconductor device 1A, they are connected by a signal line 41. Between the output terminal To of the semiconductor device 1A and the input terminal Ti of the semiconductor device 1B, they are connected by a signal line 42. Between the output terminal To of the semiconductor device 1B and the input terminal Ti of the semiconductor device 1C, they are connected by a signal line 43. Thereby, the semiconductor devices 1A to 1C are daisy-chain connected to the control device 10. The semiconductor device 1A is the first device, and the semiconductor device 1C is the last (final stage) device.

[0018] From the control device 10 to the input terminal Ti of the semiconductor device 1A, a chip enable input signal (hereinafter, enable input signal) CE_I(1) is transmitted via the signal line 41. From the output terminal To of the semiconductor device 1A to the input terminal Ti of the semiconductor device 1B, a chip enable output signal (hereinafter, enable output signal) CE_O(1) is transmitted via the signal line 42. From the output terminal To of the semiconductor device 1B to the input terminal Ti of the semiconductor device 1C, an enable output signal CE_O(2) is transmitted via the signal line 43. The enable output signals CE_O(1) and CE_O(2) respectively correspond to the enable input signals for the semiconductor devices 1B and 1C. The enable input signal and the enable output signal are signals that can each take a high level or a low level. When the enable input signal indicates enable, the register can be rewritten by the command of I2C communication in the input device, and when it indicates disable, the rewrite is impossible.

[0019] Note that the output terminal To of the semiconductor device 1C and the control device 10 are connected by a signal line 44. An enable output signal CE_O(3) is transmitted from the semiconductor device 1C to the control device 10 via the signal line 44.

[0020] FIG. 2 is a diagram showing the internal configurations of the semiconductor devices 1A to 1C. Hereinafter, when each of the semiconductor devices 1A to 1C is shown alone, it may be represented as the semiconductor device 1. As shown in FIG. 2, the semiconductor device 1 includes a communication unit 2 and an output circuit 3. The communication unit 2 is configured to perform I2C communication with the control device 10. A clock (serial clock) SCL sent from the control device 10 via a signal line 301 is input to the communication unit 2 via a clock terminal T1. Communication data (serial data) SDA is transmitted and received between the communication unit 2 and the control device 10 via a signal line 302 and a data terminal T2.

[0021] Here, an example of transmitting one byte of data from the master (control device 10) to the slave (semiconductor device 1) will be described with reference to FIG. 3. FIG. 3 is a timing chart showing an example of communication data SDA and a clock SCL. A slave address SA indicating a communication target address and data DT are transferred in synchronization with the clock SCL.

[0022] A start condition S is formed by the fall of SDA when SCL is at a high level, and the start of communication is notified to the slave side. Thereafter, the slave address SA is transferred to the slave side. When the address of the slave itself matches the transferred address, the slave enters the standby state and can communicate with the master. After the transfer of the slave address SA, an acknowledgment A1 indicating reception completion is returned from the slave to the master. Thereafter, data DT is transferred from the master to the slave. After the transfer of the data DT, an acknowledgment A2 indicating reception completion is returned from the slave to the master. Thereafter, a stop condition P is formed by the rise of SDA when SCL is at a high level, and the end of communication is notified to the slave side.

[0023] Returning to the description of FIG. 2, the communication unit 2 has a register 21. For example, if data DT as shown in FIG. 3 indicates a command from the master to the slave, and a series of communications from the start condition S to the stop condition P is defined as command communication, then the data in the register 21 can be rewritten by the command communication.

[0024] The output circuit 3 outputs an enable output signal CE_O via an output terminal To in response to an output signal OUT output from the communication unit 2. The output signal OUT can be a high-level or low-level signal.

[0025] FIG. 4 is a diagram showing a first example of the output circuit 3. The output circuit 3 shown in FIG. 4 has a driver 31 and an NMOS 32. The NMOS 32 is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET). The source of the NMOS 32 is connected to the ground potential application terminal. The drain of the NMOS 32 is connected to one end of a pull-up resistor Rp via the output terminal To. The pull-up resistor Rp is externally connected to the output terminal To. That is, the output circuit 3 has an open-drain configuration. The driver 31 controls the gate of the NMOS 32 according to the level of the output signal OUT. When the NMOS 32 is turned on by the driver 31, the enable output signal CE_O becomes low level, and when the NMOS 32 is turned off, the enable output signal CE_O becomes high level.

[0026] FIG. 5 is a diagram showing a second example of the output circuit 3. The output circuit 3 shown in FIG. 5 includes a driver 33 and an inverter 34. The inverter 34 includes a PMOS 341 and an NMOS 342. The PMOS 341 is a P-channel type MOSFET. The PMOS 341 and the NMOS 342 constitute a CMOS structure. Gates of the PMOS 341 and the NMOS 342 are connected to an output terminal of the driver 33. The driver 33 controls the gates of the PMOS 341 and the NMOS 342 according to the level of the output signal OUT. A node N3 to which the PMOS 341 and the NMOS 342 are connected is connected to the output terminal To. Thereby, the output of the driver 33 is inverted by the inverter 34 to obtain an enable output signal CE_O.

[0027] Next, an example of the slave address setting operation in the communication system 20 configured as described above will be described with reference to the timing chart of FIG. 6. In FIG. 6, from the top row, in order, the clock SCL, the data SDA, the enable input signal CE_I(1), the enable output signals CE_O(1), CE_O(2), CE_O(3), and the respective addresses AD1 to AD3 of the semiconductor devices 1A to 1C are shown.

[0028] The enable input signal CE_I(1) input to the first semiconductor device 1A by the control device 10 is maintained at a high level. Hereinafter, it is assumed that a high level indicates enable and a low level indicates disable. Also, initially, the enable output signals CE_O(1), CE_O(2), CE_O(3) are all at a low level. Also, initially, the addresses AD1 to AD3 are all “0” as an example.

[0029] First, command communication CM_A1 for address writing by SCL and SDA is performed. Here, the slave address SA of the communication target to be specified is "0". In semiconductor devices 1A to 1C, when the enable input signal input to each of them is enabled (high level), the communication unit 2 can rewrite the register 21 with the address set by the command. Therefore, here, since only the enable input signal CE_I(1) input to the semiconductor device 1A is at the high level, the address AD1 is rewritten from "0" to "1" set by the command.

[0030] In the semiconductor device 1 in which the address has been rewritten, an enable (high level) enable output signal is output from the output circuit 3 by the output signal OUT output from the communication unit 2. Therefore, here, a high level enable output signal CE_O(1) is output from the semiconductor device 1A.

[0031] Next, command communication CM_A2 is performed, and the slave address SA specified here is "0". Here, in the semiconductor device 1B in which the address is "0" and the enable output signal CE_O(1) (i.e., the enable input signal) input to itself is at the high level, the address AD2 is rewritten from "0" to "2" set by the command communication CM_A2. Then, a high level enable output signal CE_O(2) is output from the semiconductor device 1B.

[0032] Next, command communication CM_A3 is performed, and the slave address SA specified here is "0". Here, in the semiconductor device 1C in which the address is "0" and the enable output signal CE_O(2) (i.e., the enable input signal) input to itself is at the high level, the address AD3 is rewritten from "0" to "3" set by the command communication CM_A3. Then, a high level enable output signal CE_O(3) is output from the semiconductor device 1C.

[0033] Thus, according to this embodiment, in a state where the semiconductor devices 1A to 1C, which are the same product, are daisy-chain connected, the respective addresses of the semiconductor devices 1A to 1C can be set using command communication via the common bus 300. Therefore, it is not necessary to set in advance using an external resistor for address setting as in the above-described comparative example. Further, when the semiconductor device is modularized, it is not necessary to fabricate different modules. Note that by sending the enable output signal CE_O(3) from the terminal semiconductor device 1C to the control device 10, it is possible to notify the control device 10 that the address setting has been completed for all of the semiconductor devices 1A to 1C.

[0034] Further, in the present disclosure, the rewriting in the register 21 is not limited to the address, and other data may be used.

[0035] <Modification example of communication system> FIG. 7 is a diagram showing the configuration of a communication system 20 according to a modification example of the first embodiment. In this modification example, as a difference from the configuration of FIG. 1 described above, a pull-up resistor Rp2 is connected to the input terminal Ti of the head semiconductor device 1A. Thereby, the enable input signal CE_I(1) input to the input terminal Ti of the semiconductor device 1A can be maintained at a high level.

[0036] <Modification example of address setting operation> FIG. 8 is a timing chart showing an example of a slave address setting operation according to a modification example of the first embodiment.

[0037] As a difference from the above-described operation (Fig. 6), after each of the command communications CM_A1 to CM_A3 for address writing, command communications CM_O1 to CM_O3 for switching the enable output signal are performed. In the command communication for switching the enable output signal, the address set in the immediately preceding command communication for address writing is specified as the slave address SA. After the addresses are rewritten in the respective registers 21 of the semiconductor devices 1A to 1C by the command communications CM_A1 to CM_A3, in each of the semiconductor devices 1A to 1C by the command communications CM_O1 to CM_O3, the communication unit 2 outputs the output signal OUT so as to switch the enable output signal output from the output circuit 3 from the low level to the high level. Even by such an operation, the addresses AD1 to AD3 can be rewritten in order respectively.

[0038] Note that, as yet another modification, the communication unit 2 may count the number of times the address writing command is sent, and when the number of times reaches a predetermined number, switch the enable output signal to the high level via the output circuit 3. In this case, the predetermined number is set to 1, 2, and 3 for each of the semiconductor devices 1A, 1B, and 1C, respectively.

[0039] <Second Embodiment> Next, a second embodiment of the present disclosure will be described. The configuration of the communication system 20 according to the second embodiment is the same as the configuration of Fig. 1 described above. However, the internal configuration of each of the semiconductor devices 1A to 1C is different from that of the first embodiment. Fig. 9 is a diagram showing the internal configuration of the semiconductor device 1 according to the second embodiment.

[0040] In the configuration shown in Fig. 9, the semiconductor device 1 has a flip-flop 4 in addition to the communication unit 2 and the output circuit 3, as a difference from the first embodiment. A clock terminal T1 is connected to the clock terminal of the flip-flop 4. An input terminal Ti is connected to the D terminal of the flip-flop 4. An output signal OUT is output from the Q output terminal of the flip-flop 4. The output signal OUT is input to the output circuit 3. The output circuit 3 is the same as that of the first embodiment.

[0041] An example of the slave address setting operation in the communication system 20 according to the second embodiment will be described with reference to FIG. 10. The types of signals in the timing chart shown in FIG. 10 (and FIGS. 11 and 12 described later) are the same as those in FIG. 6. Initially, the enable input signal CE_I(1) and the enable output signals CE_O(1) to CE_O(3) are all at a low level. Note that the method of initializing the enable output signals CE_O(1) to CE_O(3) to a low level will be described later.

[0042] Then, the enable input signal CE_I(1) is switched from a low level to a high level by the control device 10. Thereafter, a dummy clock DM1 is sent from the control device 10 using SCL. As a result, the output signal OUT is switched to a high level by the flip-flop 4 in the semiconductor device 1A, and the enable output signal CE_O(1) is switched to a high level.

[0043] Thereafter, a dummy clock DM2 is sent from the control device 10 using SCL. As a result, the output signal OUT is switched to a high level by the flip-flop 4 in the semiconductor device 1B, and the enable output signal CE_O(2) is switched to a high level.

[0044] Thereafter, a command communication CM_A for address writing is performed using SCL and SDA. Here, the slave address of the specified communication target is "0". At this time, when SCL rises for the first time, the output signal OUT is switched to a high level by the flip-flop 4 in the semiconductor device 1C, and the enable output signal CE_O(3) is switched to a high level. In this way, the shift register is configured by the flip-flops 4 in the semiconductor devices 1A to 1C, and the enable input signal CE_I(1) is shifted.

[0045] Then, when the second last SCL rising edge in the command communication CM_A occurs, the enable input signal CE_I(1) is switched from high level to low level by the control device 10. Then, when the next SCL rising edge occurs, the enable output signal CE_O(1) is switched to low level.

[0046] Here, as shown in FIG. 11, the communication unit 2 in the semiconductor device 1 rewrites the register 21 to the address set by the command when the enable input signal (enable output signal from the previous stage) input to itself maintains a high level between the start condition S and the stop condition P in the command communication. Therefore, in the example of FIG. 10, since only the enable output signal CE_O(2) among the enable input signal CE_I(1) and the enable output signals CE_O(1), CE_O(2) maintains a high level with respect to the command communication CM_A, the address AD3 is rewritten from "0" to "3".

[0047] FIG. 12 is a timing chart showing another example of the address setting operation in the communication system 20 according to the second embodiment. Here, after the enable input signal CE_I(1) is switched to high level, the enable output signal CE_O(1) is switched to high level by the dummy clock DM1. Then, the command communication CM_A is performed. When the first SCL rising edge in the command communication CM_A occurs, the enable output signal CE_O(2) is switched to high level. Then, when the last SCL rising edge of the command communication CMA occurs, the enable input signal CE_I(1) is switched to low level by the control device 10.

[0048] Therefore, since only the enable output signal CE_O(1) among the enable input signal CE_I(1) and the enable output signals CE_O(1), CE_O(2) maintains a high level with respect to the command communication CM_A, the address AD2 is rewritten from "0" to "2".

[0049] FIG. 13 is a timing chart showing still another example of the address setting operation in the communication system 20 according to the second embodiment. Here, after the enable input signal CE_I(1) is switched to the high level, the command communication CM_A is performed. That is, the dummy clock is not transmitted. The enable output signal CE_O(1) is switched to the high level when the first SCL rises in the command communication CM_A. Thereafter, when SCL rises, the enable input signal CE_O(2) is switched to the high level.

[0050] Therefore, since only the enable input signal CE_I(1) among the enable input signal CE_I(1) and the enable output signals CE_O(1), CE_O(2) maintains the high level with respect to the command communication CM_A, the address AD1 is rewritten from "0" to "1".

[0051] As described above, according to this embodiment, the address can be set in any of the semiconductor devices 1A to 1C specified by the pattern of the dummy clock by SCL and the pattern of the enable input signal CE_I(1).

[0052] FIG. 14 is a timing chart showing an example of the data writing operation in the communication system 20 according to the second embodiment. However, in FIG. 14, data examples at the same predetermined addresses RG1 to RG3 in the registers 21 in each of the semiconductor devices 1A to 1C are shown in the lower row. Here, the enable input signal CE_I(1) is maintained at the high level. Note that the enable input signal CE_I(1) may be maintained at the high level by the control device 10 in the configuration shown in FIG. 1, or may be performed by a configuration using a pull-up resistor Rp2 as shown in FIG. 7.

[0053] In FIG. 14, first, a dummy clock DM1 by SCL is sent. As a result, the enable output signal CE_O(1) is switched to the high level. Thereafter, command communication CM_A is performed. When SCL rises for the first time in the command communication CM_A, the enable output signal CE_O(2) is switched to the high level.

[0054] Therefore, since only the enable input signal CE_I(1) and the enable output signals CE_O(1) and CE_O(1) among the enable input signal CE_I(1) and the enable output signals CE_O(1) and CE_O(2) maintain the high level with respect to the command communication CM_A, the data of the same addresses RG11 and RG22 in the semiconductor devices 1A and 1B are rewritten from “DATA1” and “DATA2” to the same “DATA10” respectively.

[0055] In this way, it becomes possible to write the same data to a plurality of specified devices among the semiconductor devices 1A to 1C.

[0056] <Initialization of Flip-Flop Output> As shown in FIGS. 11 to 14, initially, it is necessary to set the enable output signals CE_O(1) to CE_O(3) to the low level. That is, it is necessary to initialize the output signal OUT of the flip-flop 4 in each of the semiconductor devices 1A to 1C to the low level.

[0057] As one method of initialization, the enable input signal CE_I(1) set to the low level by the control device 10 can be sequentially shifted by a shift register using SCL, and the output signal OUT in the semiconductor devices 1A to 1C can be set to the low level. However, in the case of the configuration of FIG. 7 (the case of FIG. 14), since the control device 10 is not used, the above method cannot be applied.

[0058] Therefore, various other initialization methods will be described below. FIG. 15 is a diagram showing a first example of the configuration related to the reset of the flip-flop 4. Here, a reset terminal Trs is provided as an external terminal in the semiconductor device 1, and the reset terminal Trs is connected to the reset terminal of the flip-flop 4. Thereby, when a reset signal RST is input to the reset terminal Trs, the flip-flop 4 can be reset and the output signal OUT can be forced to a low level.

[0059] FIG. 16 is a diagram showing a second example of the configuration related to the reset of the flip-flop 4. Here, a power supply terminal Tvcc is provided as an external terminal in the semiconductor device 1, and a POR (power-on reset) unit 5 is provided in the semiconductor device 1. The POR unit 5 monitors the power supply voltage VCC applied to the power supply terminal Tvcc, and when the power supply voltage VCC rises and exceeds a predetermined voltage, it outputs a reset signal Rs to the reset terminal of the flip-flop 4 to reset the flip-flop 4. Thereby, the output signal OUT can be forced to a low level.

[0060] FIG. 17 is a diagram showing a third example of the configuration related to the reset of the flip-flop 4. Here, it is possible to output a reset signal Rs from the communication unit 2 to the reset terminal of the flip-flop 4. When the communication unit 2 performs reset command communication via SCK and SDA, it outputs the reset signal Rs to the reset terminal of the flip-flop 4 to reset the flip-flop 4. Thereby, the output signal OUT can be forced to a low level.

[0061] <Others> In the embodiments of the present disclosure, various changes can be made as appropriate within the scope of the technical idea shown in the claims. The various embodiments described so far may be implemented in appropriate combination within a non-contradictory range. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each constituent element are not limited to those described in the above embodiments.

[0062] <Supplementary Note> As described above, the semiconductor device (1) according to one aspect of the present disclosure includes a communication unit (2) configured to perform data communication using a clock (SCL) and communication data (SDA), a register (21), an input terminal (Ti), an output terminal (To), and is configured such that when an enable input signal input to the input terminal is at a first level (for example, a high level), data in the register can be rewritten based on a command by the data communication, and an enable output signal output from the output terminal is a signal that can take the first level or a second level (for example, a low level) (first configuration).

[0063] According to such a configuration, when semiconductor devices are daisy-chain connected, data can be rewritten for any target device.

[0064] Further, in the first configuration, the communication unit may be configured to switch the enable output signal from the second level to the first level when the data in the register is rewritten (second configuration).

[0065] Further, in the first configuration, the communication unit may be configured to switch the enable output signal from the second level to the first level when receiving a command for switching an output signal sent after a command for data rewriting by the data communication (third configuration).

[0066] Further, in the first configuration, the communication unit may be configured to count the number of times a command for data rewriting is sent by the data communication, and switch the enable output signal from the second level to the first level when the counted number of times reaches a predetermined number of times (fourth configuration).

[0067] Also, in the above first configuration, a flip-flop (4) including a clock terminal configured to be able to input the clock, a D terminal connected to the input terminal, and a Q output terminal configured to be able to output an output signal (OUT) may be provided, and the enable output signal may be output based on the output signal (fifth configuration).

[0068] Also, in the above fifth configuration, a reset terminal (Trs) as an external terminal may be provided. The flip-flop may be configured to be reset by a signal input to the reset terminal (sixth configuration).

[0069] Also, in the above fifth configuration, a power-on reset unit (5) configured to monitor a power supply voltage (VCC) may be provided. The flip-flop may be configured to be reset by the power-on reset unit (seventh configuration).

[0070] Also, in the above fifth configuration, the flip-flop may be configured to be reset by the communication unit based on the data communication (eighth configuration).

[0071] Also, in any of the above first to eighth configurations, a configuration including an output circuit (3) configured to output the enable output signal may be provided (ninth configuration).

[0072] Also, in the above ninth configuration, the output circuit may have an open-drain configuration of an N-channel MOSFET or a CMOS structure (tenth configuration).

[0073] Also, a communication system (20) according to an aspect of the present disclosure includes a plurality of semiconductor devices (1) configured in any of the above first to tenth configurations. The semiconductor devices are daisy-chain connected by connecting the output terminal of the previous stage and the input terminal of the subsequent stage. The data communication is performed via a bus (300) common to the semiconductor device (11th configuration).

[0074] Also, in the 11th configuration, it may be configured to include a control device (10) connected to the input terminal of the first semiconductor device (1A) (12th configuration).

[0075] Also, in the 12th configuration, the output terminal of the last semiconductor device (1C) may be configured to be connected to the control device (13th configuration).

[0076] Also, in the 11th configuration, a pull-up resistor (Rp2) may be connected to the input terminal of the first semiconductor device (14th configuration).

Industrial Applicability

[0077] The present disclosure can be used in communication systems for various applications.

Explanation of Reference Numerals

[0078] 2 Communication unit 3 Output circuit 4 Flip-flop 5 POR unit 10 Control device 20 Communication system 21 Register 31 Driver 32 NMOS 33 Driver 34 Inverter 341 PMOS 342 NMOS 41~44 Signal lines 100A~100C Semiconductor devices 200 Communication system 300 Bus 301 Signal line 302 Signal line RA~RC External resistors Rp Pull-up resistor Rp2 Pull-up resistor T1 Clock terminal T2 Data terminal Ti Input terminal To Output terminal Trs Reset terminal Tvcc Power supply terminal

Claims

1. A communication unit configured to perform data communication using a clock and communication data, a register, an input terminal, an output terminal, comprising: when the enable input signal input to the input terminal is at a first level, the communication unit is capable of rewriting data in the register based on a command by the data communication, a semiconductor device, wherein the enable output signal output from the output terminal is a signal that can take the first level or a second level.

2. The semiconductor device according to claim 1, wherein the communication unit switches the enable output signal from the second level to the first level when the data in the register is rewritten.

3. The semiconductor device according to claim 1, wherein the communication unit switches the enable output signal from the second level to the first level when receiving a command for output signal switching sent after a command for data rewriting by the data communication.

4. The semiconductor device according to claim 1, wherein the communication unit counts the number of times a command for data rewriting is sent by the data communication, and when the counted number reaches a predetermined number, switches the enable output signal from the second level to the first level.

5. comprising a flip-flop including a clock terminal configured to be capable of inputting the clock, a D terminal connected to the input terminal, and a Q output terminal configured to be capable of outputting an output signal, The semiconductor device according to claim 1, wherein the enable output signal is output based on the output signal.

6. comprising a reset terminal as an external terminal, The semiconductor device according to claim 5, wherein the flip-flop is configured to be reset by a signal input to the reset terminal.

7. comprising a power-on reset unit configured to monitor a power supply voltage, The semiconductor device according to claim 5, wherein the flip-flop is configured to be reset by the power-on reset unit.

8. The semiconductor device according to claim 5, wherein the flip-flop is configured to be reset by the communication unit based on the data communication.

9. The semiconductor device according to claim 1, comprising an output circuit configured to output the enable output signal.

10. The semiconductor device according to claim 9, wherein the output circuit has an open-drain configuration of an N-channel MOSFET or a CMOS structure.

11. A plurality of semiconductor devices according to any one of claims 1 to 10 are provided, The semiconductor devices are daisy-chain connected by connecting the output terminal of the previous stage and the input terminal of the next stage, The data communication is performed via a common bus for the semiconductor devices, and the communication system.

12. The communication system according to claim 11, further comprising a control device connected to the input terminal of the first semiconductor device.

13. The output terminal of the terminal semiconductor device is connected to the control device, and the communication system according to claim 12.

14. A pull-up resistor is connected to the input terminal of the first semiconductor device, and the communication system according to claim 11.

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