Recording element substrate, recording head and recording device

Abstract

To provide a technique capable of improving area efficiency of a circuit in a recording element substrate stabilizing discharge operation of a recording head by a delay circuit.SOLUTION: A recording element substrate includes: a plurality of recording elements for discharging liquid; a plurality of first driving elements for driving the plurality of recording elements; a first control circuit for outputting a first control signal for controlling the plurality of first driving elements; a plurality of inverter circuits for delaying the input of the first control signal, so that timings of the input of the first control signal between the plurality of first driving elements become different; a plurality of heat generating elements for heating the element substrate; a plurality of second driving elements for driving the plurality of heat generating elements; a second control circuit for outputting a second control signal for controlling the plurality of second driving elements; and a plurality of flip-flop circuits for delaying the input of the second control signal, so that timings of the input of the second control signal between the plurality of second driving elements become different.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an element substrate, a recording head, and a recording apparatus.

Background Art

[0002] Types of recording heads (liquid ejection heads) used in liquid ejection type recording apparatuses typified by inkjet printers include thermal ejection types and piezoelectric element types. In a thermal ejection type recording head, on one recording element substrate (liquid ejection element substrate), a plurality of recording elements (liquid ejection elements) that generate ejection energy of ink as a recording liquid, heating elements that heat the recording element substrate, and nozzles are generally formed. In a thermal ejection type recording head, in order to eject ink from a plurality of ejection ports using the energy generated by the recording elements, it is necessary to apply a stable voltage to each of the plurality of recording elements. Further, in order to require stable ejection characteristics for each recording element, it is important to suppress temperature unevenness depending on the position on the recording element substrate. Therefore, it is important to apply a stable voltage to each heating element arranged in a specific area within the recording element substrate to make the temperature distribution of the recording element substrate uniform and heat it.

[0003] A plurality of drive elements corresponding to the plurality of recording elements and heating elements are also arranged. The drive elements are composed of field effect transistors and drive the recording elements and heating elements respectively by switching. When the plurality of recording elements and heating elements are driven simultaneously, a large current on the order of A (ampere) flows through the drive power supply wiring and the ground wiring particularly at the rise and fall of power supply.

[0004] In addition, the wiring lengths of the drive power supply wiring and the ground wiring from the power supply circuit arranged in the recording apparatus main body to the recording element substrate are long, and the parasitic inductance component is large. When a large current flows through this parasitic inductance component during driving, ringing occurs. Due to this ringing, a potential difference temporarily occurs between the ground wiring and the ground wiring for the recording element substrate. Due to this potential difference, the parasitic transistor of the field effect transistor, which is the drive element, turns on, and as a result, a large current on the order of A (ampere) flows through the parasitic transistor, causing a problem that the drive element malfunctions.

[0005] Patent Document 1 discloses a technique of introducing a delay circuit into a circuit configuration that drives a heating element by inputting a sub-heat data signal to a plurality of drive elements based on reception of a latch signal, thereby delaying the latch signal or the sub-heat data signal.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In Patent Document 1, the latch signal or the sub-heat data signal is delayed to shift the timing of the power supply rise and fall of a plurality of heating elements, thereby suppressing the current value flowing therethrough.

[0008] In recent years, since a large number of recording elements are required for high-density recording for high image quality, it is necessary to arrange delay circuits at a narrow interval at a large number of locations to introduce delays. On the other hand, if the heating elements are arranged finely, the control data and the circuit scale become large. Therefore, in order to avoid this, the number of systems is reduced with high power. This is common. Therefore, the delay circuit for the heating element has fewer placement locations compared to the delay circuit of the recording element, but it is necessary to take a large delay time with a single delay circuit. If we attempt to realize such a required delay configuration by sharing, for example, the delay circuit of the heating element and the delay circuit of the recording element, there is a concern that the circuit area within the recording element substrate will increase.

[0009] An object of the present invention is to provide a technology capable of improving the area efficiency of a circuit in a recording element substrate that stabilizes the ejection operation of a recording head by a delay circuit.

Means for Solving the Problem

[0010] To achieve the above object, the element substrate of the present invention is an element substrate, a plurality of recording elements for ejecting liquid, a plurality of first drive elements provided corresponding to the plurality of recording elements and driving the plurality of recording elements, a first control circuit that outputs a first control signal for controlling the plurality of first drive elements, a plurality of inverter circuits that delay the input of the first control signal so that the input of the first control signal has different timings among the plurality of first drive elements, a plurality of heating elements for heating the element substrate, a plurality of second drive elements provided corresponding to the plurality of heating elements and driving the plurality of heating elements, a second control circuit that outputs a second control signal for controlling the plurality of second drive elements, and a plurality of flip-flop circuits that delay the input of the second control signal so that the input of the second control signal has different timings among the plurality of second drive elements, and is characterized by comprising these.

Effect of the Invention

[0011] According to the present invention, it is possible to improve the area efficiency of a circuit in a recording element substrate that stabilizes the ejection operation of a recording head by a delay circuit.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0013] Hereinafter, with reference to the drawings, embodiments for carrying out this invention will be exemplarily and specifically described based on examples. However, dimensions, materials, shapes, relative arrangements, etc. of the components described in this embodiment should be appropriately changed according to the configuration and various conditions of the apparatus to which the invention is applied. That is, it is not intended to limit the scope of this invention to the following embodiments.

[0014] Also, although a plurality of features are described in each of the embodiments described below, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations among the embodiments are given the same reference numerals, and duplicate explanations are omitted.

[0015] In this specification, "recording" (sometimes referred to as "printing") refers not only to the formation of significant information such as characters and figures, but also regardless of whether it is significant or not. Furthermore, it includes not only whether it is manifested so that humans can perceive it visually, but also widely includes the formation of images, patterns, patterns, etc. on a recording medium or the processing of the medium. Also, "recording medium" refers not only to paper used in general recording devices, but also widely includes cloth, plastic film, metal plate, glass, ceramics, wood, leather, etc., which can receive ink.

[0016] Furthermore, "ink" (sometimes referred to as "liquid") should be interpreted widely in the same way as the above definition of "recording (printing)". Therefore, it refers to a liquid that can be used for the formation of images, patterns, patterns, etc., the processing of the recording medium, or the treatment of the ink (for example, the coagulation or insolubilization of the coloring agent in the ink applied to the recording medium) by being applied on the recording medium. Additionally, "recording element" generally refers to a discharge port or a liquid path communicating therewith and an element that generates energy used for ink discharge, unless otherwise specified. Additionally, "nozzle" generally refers to a discharge port or a liquid path communicating therewith and an element that generates energy used for ink discharge, unless otherwise specified.

[0017] The element substrate (head substrate) for the recording head used hereinafter does not refer simply to a substrate made of silicon semiconductor, but refers to a configuration provided with various elements, wirings, etc. Furthermore, "on the substrate" refers not only to simply above the element substrate, but also to the surface of the element substrate and the inner side of the element substrate near the surface.

[0018] The inkjet recording head (hereinafter referred to as the recording head), which is the most important feature of the present invention, has a plurality of recording elements and a drive circuit for driving these recording elements mounted on the same substrate on the element substrate of the recording head. As will be understood from the following description, the recording head incorporates a plurality of element substrates and has a structure in which these element substrates are cascade-connected. Therefore, this recording head can achieve a relatively long recording width. Therefore, the recording head is used not only in a generally seen serial type recording apparatus but also in a recording apparatus equipped with a full-line recording head whose recording width corresponds to the width of the recording medium. Further, among serial type recording apparatuses, the recording head is used in a large-format printer that uses a large-sized recording medium such as A0 or B0.

[0019] [First Embodiment] FIG. 1 is an external perspective view showing an outline of the configuration of an inkjet recording apparatus (hereinafter referred to as the recording apparatus) that performs recording using an inkjet recording head (hereinafter referred to as the recording head), which is an example of a typical embodiment of the present invention.

[0020] As shown in FIG. 1, the recording apparatus 1 mounts a recording head 100 that discharges ink according to the inkjet method on a carriage 2, and reciprocates the carriage 2 in the direction of arrow A to perform recording. A recording medium P such as recording paper is fed through a paper feeding mechanism 5, conveyed to the recording position, and recording is performed by discharging ink from the recording head 100 onto the recording medium P at the recording position. The recording medium P on which recording has been performed is discharged onto a paper discharge tray 7.

[0021] The carriage 2 of the recording apparatus 1 not only mounts the recording head 100 but also mounts an ink tank 6 that stores ink supplied to the recording head 100. The ink tank 6 is detachable from the carriage 2. The recording apparatus 1 shown in FIG. 1 is capable of color recording, and for this purpose, the carriage 2 mounts four ink cartridges that respectively store magenta (M), cyan (C), yellow (Y), and black (K) inks. These The four ink cartridges are each independently detachable.

[0022] The recording head 100 according to the present invention employs an inkjet method that discharges ink using thermal energy. For this reason, it is provided with an electrothermal converter. This electrothermal converter is provided corresponding to each ejection port, and by applying a pulse voltage to the corresponding electrothermal converter according to a recording signal, ink is ejected from the corresponding ejection port. Note that the recording apparatus is not limited to the serial type recording apparatus described above, and can also be applied to a so-called full line type recording apparatus in which a recording head (line head) having ejection ports arranged in the width direction of the recording medium is arranged in the conveyance direction of the recording medium.

[0023] FIG. 2 is a block diagram showing the control configuration of the recording apparatus shown in FIG. 1.

[0024] As shown in FIG. 2, the controller 10 includes an MPU 11, a ROM 12, an application specific integrated circuit (ASIC) 13, a RAM 14, a system bus 15, an A / D converter 16, and the like. The ROM 12 stores programs corresponding to various control sequences, required tables, and other fixed data. The ASIC 13 generates control signals for controlling the carriage motor M1, the conveyance motor M2, and the recording head 100. The RAM 14 is used as a development area for image data, a work area for program execution, and the like. The system bus 15 connects the MPU 11, the ASIC 13, and the RAM 14 to each other to perform data transfer. The A / D converter 16 inputs an analog signal from a sensor group described below, performs A / D conversion, and supplies a digital signal to the MPU 11.

[0025] Also, in FIG. 2, the host device 41 is an external information processing device such as a PC that is a supply source of image data. Between the host device 41 and the recording device 1, image data, commands, statuses, etc. are transmitted and received by packet communication via an interface (I / F) 42. Note that the interface 42 may further include a USB interface separately from the network interface so that bit data and raster data serially transferred from the host can be received.

[0026] The switch group 20 is composed of a power switch 21, a print switch 22, a recovery switch 23, and the like.

[0027] The sensor group 30 is a sensor group for detecting the state of the apparatus, and is composed of a position sensor 31, a temperature sensor 32, and the like. In addition, a photosensor for detecting the remaining ink amount is provided.

[0028] The carriage motor driver 43 is a carriage motor driver that drives a carriage motor M1 for reciprocatingly scanning the carriage 2 in the direction of arrow A. The conveyance motor driver 44 is a conveyance motor driver that drives a conveyance motor M2 for conveying the recording medium P.

[0029] When the recording head 100 performs recording scanning, the ASIC 13 transfers data for driving a heating element (a heater for ink ejection) to the recording head 100 while directly accessing the storage area of the RAM 14. In addition, this recording apparatus 1 is provided with a display unit composed of an LCD or an LED as a user interface.

[0030] FIG. 3 shows a configuration example of the recording head 100 in the recording apparatus 1 according to the first embodiment of the present invention.

[0031] The recording head 100 includes a recording element substrate 101, a flexible substrate 106, and a printed wiring board 107. The recording element substrate 101 is electrically connected to the printed wiring board 107 via the flexible substrate 106. The printed wiring board 107 is electrically connected to a head control board 109 disposed on the main body side of the recording apparatus 1 via a cable 108.

[0032] The recording element substrate 101 will be described in detail. The recording element substrate 101 includes a plurality of recording elements 102, a plurality of driving elements 103, a control gate 104, a logic circuit 105, a heating element 115, and a driving element 116. In the present embodiment, the recording element substrate 101 is composed of a semiconductor layer, a wiring layer, and an insulating layer.

[0033] The recording element 102 is a group of recording elements for heating and ejecting ink. The driving element 103 is a group of driving elements (first driving element group) for driving the recording element 102. The plurality of recording elements 102 and the plurality of driving elements 103 are divided into a plurality of blocks (a plurality of systems). As the driving element 103, a field effect transistor (FET: Field Effect Transistor) is mainly used. The control gate 104 is a group of control gates for controlling the driving element 103.

[0034] The logic circuit 105 is a logic circuit (first control circuit) that sends a control signal (first control signal) to the control gate 104. The logic circuit 105 mainly includes a latch circuit for holding recording data, a shift register circuit, and a HE generation circuit for generating a heat enable signal (HE) that determines the conduction time of the driving element. Details of these circuits will be described later. The logic circuit 105 receives various signals transmitted from the head control IC 120. The various signals here include a data signal (DATA), a clock signal (CLK), and a latch signal (LT). Note that the head control IC 120 is arranged on the head control substrate 109.

[0035] The heating element 115 is an element that heats a specific area of the recording element substrate 101, and by heating the element substrate 101, it heats to such an extent that ink is not ejected by the heating (sub-heater). The driving element 116 is a driving element (second driving element) for driving the heating element 115. The heating element 115 and the driving element 116 are arranged for each of the above-mentioned plurality of blocks.

[0036] In this embodiment, it is assumed that the drive element 103 for the recording element and the drive element 116 for the heating element are provided in the same semiconductor layer. Also, in this embodiment, both the drive element 103 and the drive element 116 use N-type field effect transistors.

[0037] One end of the recording element 102 is connected to a power supply (VH) for supplying a drive power supply. The other end of the recording element 102 is connected to the drain terminal of the FET which is the drive element 103. Similarly to the recording element 102, one end of the heating element 115 is connected to the power supply (VH), and the other end is connected to the drain terminal of the FET which is the drive element 116. Also, the source terminals of the drive element 103 and the drive element 116 are connected to the recording element ground wiring (GNDH), and the substrate terminal (back gate) is connected to the substrate ground wiring (VSS). The power supply of the control gate 104 is connected to the control gate power supply wiring (VHT), and the power supply of the logic circuit 105 is connected to the logic circuit power supply wiring (VDD). The ground terminals of the control gate 104 and the logic circuit 105 are connected to the substrate ground wiring (VSS).

[0038] The recording element power supply (VH) and the recording element ground (GNDH) for driving the recording element 102 and the heating element 115 are connected to the power supply circuit 110 on the head control board 109. These power supplies are generated by the power supply circuit 110 and supplied to the recording element substrate 101 via the cable 108, the printed wiring board 107, and the flexible substrate 106. The recording element ground wiring (GNDH) and the substrate ground wiring (VSS) are separated within the recording head 100 and short-circuited on the head control board 109. This prevents the electromagnetic noise generated when driving a plurality of recording elements 102 and heating elements 115 from propagating to the substrate ground wiring (VSS), and prevents the logic circuit from malfunctioning.

[0039] Due to the layout constraints within the recording apparatus 1 of the head control board 109 and the recording head 100, the wiring length of the cable 108 may be 1 m or more, which increases the value of the parasitic inductance. Specifically, the value of the cable 108 alone is on the order of several hundred nH to 1 μH. In order to reduce the ringing between VH - GNDH caused by the large parasitic inductance of this cable 108, a capacitor 114 is provided on the printed wiring board 107 between VH - GNDH. As the capacitor 114, for example, an electrolytic capacitor of about several hundred μF is used.

[0040] FIG. 4 is a diagram showing a detailed circuit configuration example of the recording element substrate 101 according to the first embodiment. In FIG. 4, when there are a plurality of identical components, a further subscript is added to the reference numeral for indication.

[0041] The logic circuit 207 is a logic circuit that receives various signals transmitted from the head control IC 120 and allocates data to respective predetermined locations. The logic circuit 201 for recording element group selection is a shift register - latch circuit for recording data that holds the recording data, and holds the recording data by a latch signal (lt). The logic circuit 203 for recording element block selection is a logic circuit that activates the control gate 104 in time - divided block units and holds a block selection signal.

[0042] The HE generation circuit 204 is a circuit that generates a heat enable signal (HE) that determines the conduction time of the drive element 103. The heat enable pulse delay circuit 202 is composed of at least one or more inverter circuits, and is a heat enable pulse delay circuit (first delay circuit) that delays the heat enable signal (HE) by several ns to several tens of ns.

[0043] The arrangement of the plurality of heat enable pulse delay circuits 202 shown in this embodiment is merely an example. For example, the number of arrangements of the heat enable pulse delay circuits 202 may be different for each of the plurality of groups composed of the plurality of recording elements 102.

[0044] To the plurality of control gates 104, delayed heat enable pulses (HE-1, HE-2, ···, HE-n) delayed by the heat enable pulse delay circuit 202 are respectively input. The control gate 104 outputs a heat data signal which is the result of the logical product of the recorded data, the block selection signal, and the heat enable signal (HE). Therefore, the timing at which the heat enable signal (HE) is input to each of the plurality of control gates 104 is delayed by several ns to several tens of ns each. Then, by inputting the heat data signal to the gate of the drive element 103, the on / off is controlled, and it becomes conductive or non-conductive simultaneously when it is turned on. Therefore, the timing at which each of the plurality of recording elements 102 is driven is delayed by several ns to several tens of ns each. That is, by delaying the input of the heat enable signal (HE) to the control gate 104 by the heat enable pulse delay circuit 202, the input of the heat data signal from the control gate 104 to the drive element 103 is delayed. As a result, the input of the heat data signal becomes different timings among the plurality of blocks of the drive element 103.

[0045] The latch circuit 209 for the heating element is a latch circuit for the sub-heat data signal that holds the sub-heat data signal which is a signal defining whether or not to drive the heating element 115 belonging to the corresponding block. The shift register circuit 206 for the heating element is a shift register circuit for the sub-heat data signal that transfers the sub-heat data signal. The latch signal delay circuit 208 is composed of at least one or more flip-flop circuits, and is a latch signal delay circuit (second delay circuit) that delays the latch signal by several ns to several hundreds of ns according to the number of stages of the flip-flop circuit. Also, in the present embodiment, it is assumed that the latch signal delay circuit 208 uses a D flip-flop circuit. However, the latch signal delay circuit 208 may be an RS type, JK type, or T type flip-flop circuit.

[0046] ​The arrangement of the plurality of latch signal delay circuits 208 shown in this embodiment is merely an example. That is, the number of arranged latch signal delay circuits 208 may be different for each of the plurality of groups composed of the plurality of recording elements 102. Alternatively, the present invention is not limited to the configuration in which the latch signal delay circuit 208 is arranged for each heat generating element latch circuit 209, and there may be one for every plurality of heat generating element latch circuits 209. That is, the heat enable pulse delay circuit 202 is arranged for each of the plurality of groups of the plurality of recording elements 102, while the latch signal delay circuit 208 may be arranged as a common delay circuit in some of the plurality of groups. Therefore, the circuit configuration can be such that the number of flip-flop circuits constituting the latch signal delay circuit 208 is less than the number of inverter circuits constituting the heat enable pulse delay circuit 202.

[0047] The plurality of heat generating element latch circuits 209 provided output sub-heat data signals as a second control circuit based on the delayed latch signals (lt-1, lt-2, ···, lt-m) delayed by the latch signal delay circuit 208. Therefore, the timings at which the plurality of heat generating element latch circuits 209 output their respective sub-heat data signals are delayed by several ns to several tens of ns each. Then, when the sub-heat data signal is input to the gate of the drive element 116, the on / off is controlled, and it becomes conductive or non-conductive simultaneously with being turned on. Therefore, the timings at which the plurality of heat generating elements 115 are each driven are delayed by several ns to several tens of ns each. That is, the input of the latch signal to the heat generating element latch circuit 209 is delayed by the latch signal delay circuit 208, so that the input of the sub-heat data signal from the heat generating element latch circuit 209 to the drive element 116 is delayed. As a result, the input of the sub-heat data signal becomes different timings among the plurality of drive elements 116 arranged in each block.

[0048] With the above configuration, since a large number of delay circuits need to be arranged at narrow intervals at multiple locations in the plurality of recording elements 102 to introduce delays, an inverter circuit with a small size and small delay per unit is suitable. On the other hand, since the number of systems of the heating elements 115 is reduced compared to the plurality of recording elements 102, there are fewer locations for introducing delays, but it is necessary to increase the delay interval due to power considerations. Therefore, a flip-flop circuit that can introduce a large delay with a small number is suitable.

[0049] From the above, it is expected that the area efficiency can be improved by adopting different delay methods for the plurality of recording elements 102 and the heating elements 115.

[0050] FIG. 5 is a diagram showing an example of the circuit layout of the recording element substrate 101 according to the embodiment.

[0051] The recording element substrate 101 includes an input / output unit 301, an end circuit 302, and a nozzle row circuit 303. The input / output unit 301 is a pad unit that inputs and outputs power, signals, and information between the main body of the recording apparatus 1 to which the recording head 100 is attached and the head control substrate 109 via the cable 108, the printed wiring board 107, and the flexible substrate 106. The end circuit 302 is a circuit unit disposed in the vicinity of the input / output unit 301. The nozzle row circuit 303 is a circuit unit disposed in the nozzle row of the recording head 100 to which the recording element substrate 101 is attached. The nozzle row itself may be not a single row but a plurality of rows.

[0052] The end circuit 302 is composed of a HE generation circuit 204, a shift register circuit 206 for heating elements, a logic circuit 207, a latch signal delay circuit 208, and a latch circuit 209 for heating elements. 。The nozzle array circuit 303 is composed of a heat enable pulse delay circuit 202, a logic circuit 311 for recording elements, a driver array for recording elements + a driver array for heating elements 312, an ink supply port 313, and a recording element array + a heating element array 314. The logic circuit 311 for recording elements is composed of a control gate 104, a logic circuit 201 for selecting a recording element group, and a logic circuit 203 for selecting a recording element block. The driver array for recording elements + the driver array for heating elements 312 is composed of a driving element 103 and a driving element 116. The recording element array + the heating element array 314 is composed of a recording element 102 and a heating element 115.

[0053] Due to the above configuration, the flip-flop circuit of the latch signal delay circuit 208 has a large area per unit and the width between columns becomes wide when placed in the nozzle array circuit 303, so it is arranged in the end circuit 302. The inverter circuit of the heat enable pulse delay circuit 202 has a small area per unit, but since it needs to be placed in many locations, the area will become large if it is put together in the end circuit 302. Therefore, the heat enable pulse delay circuit 202 is arranged separately for each column group of a plurality of recording elements 102 in the nozzle array circuit 303. From the above, arranging them in an appropriate arrangement for each leads to an improvement in area efficiency.

[0054] FIG. 6 is a timing chart of the latch signal delay circuit 208 in FIG. 4.

[0055] In this embodiment, the recording element substrate 101 performs time-division driving by dividing the recording of one line into a predetermined number of blocks and sequentially driving the heating elements 115. Here, the line time indicates the time for recording an image (line) for one column or one row on the recording medium. The block time indicates the time required for recording per block based on the block, and one line time corresponds to the time required for recording the above-mentioned predetermined number of blocks (predetermined number of block times). Also, the latch signal (LT) is a signal for identifying one block.

[0056] To heat and eject a very small amount of ink (for example, 1 picoliter) in one nozzle, the drive time of the printing element 102 can be as short as several hundred n (nano) seconds. Therefore, the printing element 102 is driven by a high-frequency heat enable signal (HE). On the other hand, the heating element 115 needs to heat and keep warm a specific area of ​​the element substrate, which has a large thermal capacity, so the drive time needs to be long, from several tens of μ (micro) seconds to several hundred m (milli) seconds. Therefore, the heating element 115 needs to be driven by a signal with a relatively low frequency.

[0057] The latch signal delay circuit 208 receives the latch signal (lt) from the logic circuit 207, and sequentially outputs delayed latch signals (lt-1, lt-2, . . . , lt-m) by delaying the latch signal at each rising edge of clk. The delay interval depends on the frequency of clk and is approximately several ns to several tens of ns.

[0058] FIG. 7 is a timing chart of the heat enable pulse delay circuit 202 of FIG.

[0059] The HE generation circuit 204 generates a heat enable signal (HE) set using the rising and falling edges of the clk signal. The heat enable pulse delay circuit 202 receives the heat enable signal (HE) from the HE generation circuit 204 and sequentially outputs delayed heat enable pulses (HE-1, HE-2, ..., HE-n). The delay interval is shorter than that of the latch signal delay circuit 208 (several ns to several tens of ns) and does not depend on the clk frequency. The heat enable signal (HE) shown here is just an example, and the width can be freely changed depending on the setting value.

[0060] 7 is larger than the delay amount of the heat enable pulse delay circuit 202. Therefore, the flip-flop circuit of the latch signal delay circuit 208 has a delay interval of the clk period. Since the delay depends on the period, it is possible to apply a delay with a larger interval than that of the heat enable pulse delay circuit 202.

[0061] The delay times of the latch signal delay circuit 208 and the heat enable pulse delay circuit 202 shown in FIGS. 6 and 7 are shown as an example and may be less than several ns or several hundreds of ns or more. Also, the delay times may vary depending on the location.

[0062] Also, the difference between the clk period and the delay amount of the heat enable pulse delay circuit 202 is shown as an example, and the delay amounts may be the same, or the clk period may be smaller than that of the heat enable pulse delay circuit 202.

[0063] (Second Embodiment) FIG. 8 is a diagram showing a detailed configuration example of the recording element substrate 101 according to the second embodiment of the present invention. It is different from the first embodiment in that a plurality of sub-heat data signal delay circuits 501 are provided. Since the other configurations are the same as those in the first embodiment, the description thereof will be omitted.

[0064] In the present embodiment, the sub-heat data signal delay circuit 501 receives the sub-heat data signal output from the latch circuit 209 for the heating element as an input, and outputs it as a delayed sub-heat data signal (SHE-1, SHE-2, ···, SHE-m) delayed by a predetermined delay time. Then, by inputting the delayed sub-heat data signal to the gate of the drive element 116, the on / off is controlled, and it becomes conductive or non-conductive simultaneously with being turned on. Therefore, the timings at which the plurality of heating elements 115 are driven are each delayed by several ns to several tens of ns. That is, the input of the sub-heat data signal from the latch circuit 209 for the heating element to the drive element 116 is delayed by the sub-heat data signal delay circuit 501. As a result, the inputs of the sub-heat data signals among the plurality of drive elements 116 arranged in each block have different timings from each other.

[0065] Similar to the latch signal delay circuit 208 of the first embodiment, the sub-heat data signal delay circuit 501 is composed of a flip-flop circuit and is arranged in the end circuit 302. By doing so, it leads to an improvement in area efficiency.

[0066] The arrangement of the plurality of sub-heat data signal delay circuits 501 shown in this embodiment is merely an example. For example, the number of arranged sub-heat data signal delay circuits 501 may be different for each of the plurality of groups composed of the plurality of recording elements 102. That is, while the heat enable pulse delay circuit 202 is arranged for each of the plurality of groups of the plurality of recording elements 102, the sub-heat data signal delay circuit 501 may be arranged as a common delay circuit in some of the plurality of groups. Therefore, a circuit configuration can be adopted in which the number of flip-flop circuits constituting the sub-heat data signal delay circuit 501 is smaller than the number of inverter circuits constituting the heat enable pulse delay circuit 202.

[0067] (Others) As described above, the forms and numbers of the various components shown in each embodiment, and the various numerical values are not limited to those described above, but are appropriately changed according to the configuration of the recording element substrate and the like.

[0068] For example, up to four recording elements 102 in one group of the recording elements 102 are illustrated, and illustration of more recording elements 102 is omitted. The number of nozzles included in the nozzle row corresponding to one group may be, for example, 512. Also, the number of nozzle rows may be one row or multiple rows.

[0069] The above embodiments can be combined with each other in terms of their respective configurations.

[0070] The disclosure of the embodiments of the present invention includes the following configurations. (Configuration 1) An element substrate, A plurality of recording elements for discharging a liquid, A plurality of first driving elements provided corresponding to the plurality of recording elements and driving the plurality of recording elements, A first control circuit that outputs a first control signal for controlling the plurality of first driving elements, A plurality of inverter circuits that delay the input of the first control signal so that the input of the first control signal has different timings among the plurality of first drive elements; A plurality of heating elements for heating the element substrate; A plurality of second drive elements provided corresponding to the plurality of heating elements and driving the plurality of heating elements; A second control circuit that outputs a second control signal for controlling the plurality of second drive elements; A plurality of flip-flop circuits that delay the input of the second control signal so that the input of the second control signal has different timings among the plurality of second drive elements, wherein the element substrate is characterized by comprising the same. (Configuration 2) The element substrate according to Configuration 1, wherein the number of the plurality of flip-flop circuits is smaller than the number of the plurality of inverter circuits. (Configuration 3) The plurality of recording elements and the plurality of first drive elements are divided into a plurality of blocks, The inverter circuit is arranged for each of the plurality of blocks, and delays the input of the first control signal so that the input of the first control signal has different timings among the plurality of blocks. The element substrate according to Configuration 1 or 2. (Configuration 4) The heating element, the second drive element, and the flip-flop circuit are arranged for each of the plurality of blocks. The element substrate according to any one of Configurations 1 to 3. (Configuration 5) The first control circuit receives a heat enable signal that determines the conduction time of the first drive element, and outputs, as the first control signal, a heat data signal that is a logical product of recording data, a block selection signal, and the heat enable signal. The inverter circuit delays the reception of the heat enable signal by the first control circuit. The element substrate according to any one of Configurations 1 to 4. (Configuration 6) The second control signal is a sub-heat data signal output to the plurality of second drive elements according to sub-heat data that defines whether to drive the heating element for each of the plurality of blocks. The second control circuit outputs the sub-heat data signal based on reception of a latch signal. The flip-flop circuit is the element substrate according to any one of Configurations 1 to 5 that delays the latch signal or the sub-heat data signal. (Configuration 7) The element substrate according to any one of Configurations 1 to 6, wherein a delay time of input of the first control signal by the inverter circuit is shorter than a delay time of input of the second control signal by the flip-flop circuit. (Configuration 8) The flip-flop circuit is a D flip-flop circuit according to any one of Configurations 1 to 7 of the element substrate according to the configuration. (Configuration 9) The element substrate according to any one of Configurations 1 to 8, wherein the plurality of inverter circuits are arranged in a nozzle row circuit corresponding to a nozzle row of a recording head on which the element substrate is mounted. (Configuration 10) The element substrate according to any one of Configurations 1 to 9, wherein the plurality of flip-flop circuits are arranged in an end circuit between an input / output unit that performs input / output with a recording apparatus on which the recording head is mounted and the nozzle row circuit. (Configuration 11) The element substrate according to any one of Configurations 1 to 10, wherein the plurality of recording elements and the plurality of heating elements are connected to a common power supply wiring. (Configuration 12) The element substrate according to any one of Configurations 1 to 11, wherein a ground wiring of the plurality of recording elements and a ground wiring of the plurality of heating elements are common. (Configuration 13) A recording head, comprising the element substrate according to any one of Configurations 1 to 12. (Configuration 14) A recording apparatus that performs recording by ejecting ink from the recording head according to Configuration 13 onto a recording medium.

Explanation of Signs

[0071] 101…Recording element substrate, 102…Recording element, 115…Heating element, 202…Heat enable pulse delay circuit, 208…Latch signal delay circuit, 111~112…Power supply circuit

Claims

1. An element substrate, comprising: a plurality of recording elements for discharging a liquid; a plurality of first driving elements provided corresponding to the plurality of recording elements and driving the plurality of recording elements; a first control circuit that outputs a first control signal for controlling the plurality of first driving elements; a plurality of inverter circuits that delay the input of the first control signal so that the input of the first control signal has different timings among the plurality of first driving elements; a plurality of heating elements for heating the element substrate; a plurality of second driving elements provided corresponding to the plurality of heating elements and driving the plurality of heating elements; a second control circuit that outputs a second control signal for controlling the plurality of second driving elements; a plurality of flip-flop circuits that delay the input of the second control signal so that the input of the second control signal has different timings among the plurality of second driving elements, wherein the element substrate is characterized by comprising the above components.

2. The element substrate according to claim 1, wherein the number of the plurality of flip-flop circuits is less than the number of the plurality of inverter circuits.

3. The plurality of recording elements and the plurality of first driving elements are divided into a plurality of blocks, wherein the inverter circuits are arranged for each of the plurality of blocks, and delay the input of the first control signal so that the input of the first control signal has different timings among the plurality of blocks. The element substrate according to claim 1.

4. The element substrate according to claim 3, wherein the heating elements, the second driving elements, and the flip-flop circuits are arranged for each of the plurality of blocks.

5. The first control circuit receives a heat enable signal that determines the conduction time of the first driving element, and outputs, as the first control signal, a heat data signal that is a logical product of recording data, a block selection signal, and the heat enable signal, wherein the inverter circuit delays the reception of the heat enable signal by the first control circuit. The element substrate according to claim 4.

6. The second control signal is a sub-heat data signal output to the plurality of second driving elements according to sub-heat data that defines whether to drive the heating elements for each of the plurality of blocks, wherein the second control circuit outputs the sub-heat data signal based on reception of a latch signal. The flip-flop circuit delays the latch signal or the sub-heat data signal, and the element substrate according to claim 5.

7. The delay time of the input of the first control signal by the inverter circuit is shorter than the delay time of the input of the second control signal by the flip-flop circuit, and the element substrate according to claim 6.

8. The flip-flop circuit is a D flip-flop circuit, and the element substrate according to claim 1.

9. The plurality of inverter circuits are arranged in a nozzle row circuit corresponding to a nozzle row of a recording head on which the element substrate is mounted. The element substrate according to claim 1.

10. The plurality of flip-flop circuits are arranged in an end circuit between an input / output unit that performs input / output with a recording apparatus on which the recording head is mounted and the nozzle row circuit, and the element substrate according to claim 9.

11. The plurality of recording elements and the plurality of heating elements are connected to a common power supply wiring, and the element substrate according to claim 1.

12. The ground wiring of the plurality of recording elements and the ground wiring of the plurality of heating elements are common, and the element substrate according to claim 1.

13. A recording head comprising the element substrate according to any one of claims 1 to 12.

14. A recording apparatus characterized by ejecting ink from the recording head according to claim 13 onto a recording medium to perform recording.

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