Semiconductor device

Abstract

To provide a semiconductor device capable of suitably laminating a plurality of semiconductor chips.SOLUTION: According to an embodiment, a semiconductor device includes one or more first substrate pads provided on a substrate, and one or more first chips provided on the substrate and arranged in a first direction with respect to the first substrate pads, each first chip including one or more first chip pads electrically connected to the first substrate pads. The device further includes one or more second substrate pads provided on the substrate, and one or more second chips provided on the first chips and arranged in a second direction intersecting the first direction with respect to the second substrate pads, each second chip including one or more second chip pads electrically connected to the second substrate pads. In addition, each second chip pad is arranged at a position overlapping the uppermost first chip among the first chips in a plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device.

Background Art

[0002] When manufacturing a semiconductor device by stacking a plurality of semiconductor chips, various problems may occur due to the stacking of the semiconductor chips. For example, wire bonding to the semiconductor chip may become difficult.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device capable of suitably stacking a plurality of semiconductor chips.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor device includes a substrate, one or more first substrate pads provided on the substrate, and one or more first chips provided on the substrate and arranged in a first direction with respect to the first substrate pads, each of the first chips having one or more first chip pads electrically connected to the first substrate pads. The device further includes one or more second substrate pads provided on the substrate, and one or more second chips provided on the first chips and arranged in a second direction intersecting the first direction with respect to the second substrate pads, each of the second chips having one or more second chip pads electrically connected to the second substrate pads. Further, each of the second chip pads is arranged at a position overlapping the topmost first chip among the first chips in a plan view.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 35, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

[0008] (First Embodiment) FIG. 1 and FIG. 2 are a cross-sectional view and a plan view showing the structure of a semiconductor device according to the first embodiment, respectively.

[0009] The semiconductor device of this embodiment includes a substrate 1, a resin layer 2, a plurality of metal pads P1, a plurality of metal pads P2, a plurality of metal pads P3, and a plurality of metal pads P4. The metal pad P1 is an example of one or more first substrate pads. The metal pad P2 is an example of one or more second substrate pads. The metal pad P3 is an example of one or more third substrate pads. The metal pad P4 is an example of one or more fourth substrate pads.

[0010] The semiconductor device of this embodiment further includes a plurality of semiconductor chips 11 to 12 electrically connected to the metal pad P1, a plurality of semiconductor chips 21 to 22 electrically connected to the metal pad P2, a plurality of semiconductor chips 31 to 32 electrically connected to the metal pad P3, and a plurality of semiconductor chips 41 to 42 electrically connected to the metal pad P4. These semiconductor chips 11 to 42 are, for example, semiconductor memory chips. The semiconductor chips 11 to 12 are examples of one or more first chips. The semiconductor chips 21 to 22 are examples of one or more second chips. The semiconductor chips 31 to 32 are examples of one or more third chips. The semiconductor chips 41 to 42 are examples of one or more fourth chips.

[0011] FIG. 1 and FIG. 2 show the X direction, Y direction, and Z direction that intersect each other. In FIGS. 1 and 2, the X direction and the Y direction are parallel to the surface of the substrate 1, and the Z direction is perpendicular to the surface of the substrate 1. Therefore, the X direction, the Y direction, and the Z direction are perpendicular to each other. In this specification, looking at the semiconductor device from the +Z direction position of the semiconductor device in the -Z direction as shown in FIG. 2 is treated as a plan view. The same applies to FIGS. 3 to 35. In this embodiment, the -Y direction is an example of the first direction, the +X direction is an example of the second direction, the +Y direction is an example of the third direction, and the -X direction is an example of the fourth direction.

[0012] The resin layer 2 is formed on the substrate 1 so as to cover the metal pads P1 to P4 and the semiconductor chips 11 to 42. FIG. 2 omits the illustration of the resin layer 2. Further details of the metal pads P1 to P4 and the semiconductor chips 11 to 42 will be described later.

[0013] FIGS. 3 to 5 are plan views showing a method of manufacturing the semiconductor device of the first embodiment.

[0014] The semiconductor device of this embodiment is manufactured by sequentially stacking semiconductor chips 11 to 42 on a substrate 1. First, metal pads P1 to P4 are formed on the upper surface of the substrate 1, and the semiconductor chips 11 to 12 are sequentially stacked on the substrate 1 (FIG. 3). Next, the semiconductor chips 21 to 22 are sequentially stacked on the semiconductor chip 12 (FIG. 4). Next, the semiconductor chips 31 to 32 are sequentially stacked on the semiconductor chip 22 (FIG. 5). Thereafter, the semiconductor chips 41 to 42 are sequentially stacked on the semiconductor chip 32, and a resin layer 2 is formed on the substrate 1 (FIGS. 1 and 2). For example, the substrate 1 and the semiconductor chip 11 are adhered to each other by an adhesive layer, and the semiconductor chips 11 to 42 are also adhered to each other by an adhesive layer.

[0015] Hereinafter, with reference to FIGS. 1 and 2, the structure of the semiconductor device of this embodiment will be described. In this description, FIGS. 3 to 5 will also be referred to as appropriate. The reason is that although some components of the semiconductor device of this embodiment are shown in FIGS. 3 to 5, they are hidden by other components and not shown in FIGS. 1 and 2.

[0016] [Metal pads P1 to P4] As shown in FIG. 2, the metal pads P1 to P4 are arranged around the semiconductor chips 11 to 42 on the substrate 1. Specifically, the metal pad P1 is arranged in the +Y direction of the semiconductor chips 11 to 42 and is arranged in a row along the X direction. The metal pad P2 is arranged in the -X direction of the semiconductor chips 11 to 42 and is arranged in a row along the Y direction. The metal pad P3 is arranged in the -Y direction of the semiconductor chips 11 to 42 and is arranged in a row along the X direction. The metal pad P4 is arranged in the +X direction of the semiconductor chips 11 to 42 and is arranged in a row along the Y direction.

[0017] In this embodiment, the semiconductor chips 11 to 42 have congruent shapes in plan view. Specifically, the shapes of the semiconductor chips 11 to 42 are congruent rectangles in plan view. Also, the semiconductor chips 11 to 42 of this embodiment have the same thickness except for the semiconductor chip 11 (FIG. 1). In this embodiment, the thickness of the lowermost semiconductor chip 11 among the semiconductor chips 11 to 42 is greater than the thicknesses of the other semiconductor chips 12 to 42. In this embodiment, the thicknesses of the semiconductor chips 12 to 42 are set to 50 μm or less (for example, 20 to 50 μm). Furthermore, in this embodiment, the thickness of the semiconductor chip 11 may also be set to 50 μm or less (for example, 20 to 50 μm). Note that the shapes and thicknesses of the semiconductor chips 11 to 42 may be different from those of this embodiment.

[0018] [Semiconductor chips 11 to 12] The semiconductor chips 11 to 12 are arranged in the -Y direction of the metal pad P1 and are electrically connected to the metal pad P1 (FIG. 3). The upper surfaces (rectangles) of the semiconductor chips 11 to 12 have short sides parallel to the X direction and long sides parallel to the Y direction. The semiconductor chip 12 is arranged on the semiconductor chip 11, but is not arranged at a position that completely overlaps the semiconductor chip 11 in plan view, but is arranged at a position that partially overlaps the semiconductor chip 11. Specifically, the center of gravity of the upper surface of the semiconductor chip 12 is located in the -Y direction of the center of gravity of the upper surface of the semiconductor chip 11. Therefore, the semiconductor chips 11 to 12 are stacked on the substrate 1 so as to form a staircase in the -Y direction.

[0019] The semiconductor chip 11 has a plurality of metal pads 11a provided on the upper surface of the semiconductor chip 11 (Fig. 3). The metal pads 11a are arranged in the stepped portion of the semiconductor chip 11, that is, near the short side in the +Y direction of the semiconductor chip 11, and are arranged in a row along the X direction. These metal pads 11a are electrically connected to the metal pad P1 by a plurality of bonding wires W11. Also, these metal pads 11a are arranged at positions that do not overlap with the semiconductor chip 12 in plan view. The metal pads 11a are examples of one or more first chip pads. For example, the bonding wires W11 are joined to the metal pads 11a by solder and are also joined to the metal pad P1 by solder (the same applies to other bonding pads).

[0020] The semiconductor chip 12 has a plurality of metal pads 12a provided on the upper surface of the semiconductor chip 12 (Fig. 3). The metal pads 12a are arranged in the stepped portion of the semiconductor chip 12, that is, near the short side in the +Y direction of the semiconductor chip 12, and are arranged in a row along the X direction. These metal pads 12a are electrically connected to the metal pads 11a by a plurality of bonding wires W12, and as a result, are electrically connected to the metal pad P1. Also, these metal pads 12a are arranged in the -Y direction of the plurality of metal pads 11a. The metal pads 12a are also examples of one or more first chip pads.

[0021] [Semiconductor chips 21 - 22] The semiconductor chips 21 - 22 are arranged in the +X direction of the metal pad P2 and are electrically connected to the metal pad P2 (Fig. 4). The upper surfaces (rectangles) of the semiconductor chips 21 - 22 have a short side parallel to the Y direction and a long side parallel to the X direction. The semiconductor chip 22 is arranged on the semiconductor chip 21, but is not arranged at a position that completely overlaps with the semiconductor chip 21 in plan view, but is arranged at a position that partially overlaps with the semiconductor chip 21. Specifically, the center of gravity of the upper surface of the semiconductor chip 22 is located in the +X direction of the center of gravity of the upper surface of the semiconductor chip 21. Therefore, the semiconductor chips 21 - 22 are stacked on the semiconductor chip 12 so as to form a step in the +X direction.

[0022] The semiconductor chip 21 has a plurality of metal pads 21a provided on the upper surface of the semiconductor chip 21 (Fig. 4). The metal pads 21a are arranged in the stepped portion of the semiconductor chip 21, that is, near the short side in the -X direction of the semiconductor chip 21, and are arranged in a line along the Y direction. These metal pads 21a are electrically connected to the metal pad P2 by a plurality of bonding wires W21. Further, these metal pads 21a are arranged at positions that do not overlap with the semiconductor chip 22 in a plan view. The metal pads 21a are examples of one or more second chip pads.

[0023] The semiconductor chip 22 has a plurality of metal pads 22a provided on the upper surface of the semiconductor chip 22 (Fig. 4). The metal pads 22a are arranged in the stepped portion of the semiconductor chip 22, that is, near the short side in the -X direction of the semiconductor chip 22, and are arranged in a line along the Y direction. These metal pads 22a are electrically connected to the metal pads 21a by a plurality of bonding wires W22, and as a result, are electrically connected to the metal pad P2. Further, these metal pads 22a are arranged in the +X direction of the plurality of metal pads 21a. The metal pads 22a are also examples of one or more second chip pads.

[0024] In the present embodiment, the semiconductor chips 11 to 12 are arranged such that the short sides are parallel to the X direction and the long sides are parallel to the Y direction, and form a step extending in the -Y direction. On the other hand, the semiconductor chips 21 to 22 are arranged such that the short sides are parallel to the Y direction and the long sides are parallel to the X direction, and form a step extending in the +X direction intersecting the -Y direction. Therefore, the overall shape of these four semiconductor chips 11 to 22 is L-shaped in a plan view. The semiconductor chip 21 of the present embodiment is arranged on the semiconductor chip 12 such that the lower left corner of the semiconductor chip 21 overlaps the lower left corner of the semiconductor chip 12 in a plan view (here, the term "lower left" means the lower left on the paper surface. The same applies hereinafter). Note that the lower left corner of the semiconductor chip 21 does not have to overlap the lower left corner of the semiconductor chip 12, and may be located in the -Y direction of the lower left corner of the semiconductor chip 12, for example.

[0025] In the present embodiment, the short side of the semiconductor chip 21 in the -X direction overlaps with the long side of the semiconductor chip 11 in the -X direction and also overlaps with the long side of the semiconductor chip 12 in the -X direction in a plan view. Further, in the present embodiment, the short side of the semiconductor chip 12 in the -Y direction overlaps with the long side of the semiconductor chip 21 in the -Y direction and also overlaps with the long side of the semiconductor chip 22 in the -Y direction in a plan view.

[0026] Each of the metal pads 21a to 22a of the present embodiment is disposed at a position overlapping with the uppermost semiconductor chip 12 among the semiconductor chips 11 to 12 in a plan view. That is, the metal pads 21a to 22a of the present embodiment are disposed at positions not protruding from the upper surface of the semiconductor chip 12 in a plan view. Therefore, in the present embodiment, the semiconductor chip 12 exists in the -Z direction of the metal pads 21a to 22a. According to the present embodiment, since the semiconductor chip 12 exists in the -Z direction of the metal pads 21a to 22a, even if the semiconductor chips 21 to 22 are thinned, it is possible to reduce the possibility that the semiconductor chips 21 to 22 are cracked. FIG. 1 shows the metal pads 21a to 22a disposed at positions overlapping with the semiconductor chip 12 in a plan view.

[0027] [Semiconductor chips 31 to 32] The semiconductor chips 31 to 32 are disposed in the +Y direction of the metal pad P3 and are electrically connected to the metal pad P3 (FIG. 5). The upper surfaces (rectangles) of the semiconductor chips 31 to 32 have a short side parallel to the X direction and a long side parallel to the Y direction. The semiconductor chip 32 is disposed on the semiconductor chip 31, but is not disposed at a position completely overlapping with the semiconductor chip 31 in a plan view, but is disposed at a position partially overlapping with the semiconductor chip 31. Specifically, the center of gravity of the upper surface of the semiconductor chip 32 is located in the +Y direction of the center of gravity of the upper surface of the semiconductor chip 31. Therefore, the semiconductor chips 31 to 32 are stacked on the semiconductor chip 22 so as to form a staircase in the +Y direction.

[0028] The semiconductor chip 31 has a plurality of metal pads 31a provided on the upper surface of the semiconductor chip 31 (Fig. 5). The metal pads 31a are arranged in the stepped portion of the semiconductor chip 31, that is, near the short side in the -Y direction of the semiconductor chip 31, and are arranged in a row along the X direction. These metal pads 31a are electrically connected to the metal pads P3 by a plurality of bonding wires W31. Also, these metal pads 31a are arranged at positions that do not overlap with the semiconductor chip 32 in plan view. The metal pads 31a are an example of one or more third chip pads.

[0029] The semiconductor chip 32 has a plurality of metal pads 32a provided on the upper surface of the semiconductor chip 32 (Fig. 5). The metal pads 32a are arranged in the stepped portion of the semiconductor chip 32, that is, near the short side in the -Y direction of the semiconductor chip 32, and are arranged in a row along the X direction. These metal pads 32a are electrically connected to the metal pads 31a by a plurality of bonding wires W32, and as a result, are electrically connected to the metal pads P3. Also, these metal pads 32a are arranged in the +Y direction of the plurality of metal pads 31a. The metal pads 32a are also an example of one or more third chip pads.

[0030] In the present embodiment, the semiconductor chips 21 to 22 are arranged such that the short sides are parallel to the Y direction and the long sides are parallel to the X direction, and form a step extending in the +X direction. On the other hand, the semiconductor chips 31 to 32 are arranged such that the short sides are parallel to the X direction and the long sides are parallel to the Y direction, and form a step extending in the +Y direction intersecting the +X direction. Therefore, the overall shape of these four semiconductor chips 21 to 32 is L-shaped in plan view. The semiconductor chip 31 of the present embodiment is arranged on the semiconductor chip 22 such that the lower right corner of the semiconductor chip 31 overlaps the lower right corner of the semiconductor chip 22 in plan view (here, the term "lower right" means the lower right on the paper surface. The same applies hereinafter). Note that the lower right corner of the semiconductor chip 31 does not have to overlap the lower right corner of the semiconductor chip 22, and may be located, for example, in the +X direction of the lower right corner of the semiconductor chip 22.

[0031] In this embodiment, the short side of the semiconductor chip 31 in the -Y direction overlaps with the long side of the semiconductor chip 21 in the -Y direction and also overlaps with the long side of the semiconductor chip 22 in the -Y direction in a plan view. Further, in this embodiment, the short side of the semiconductor chip 22 in the +X direction overlaps with the long side of the semiconductor chip 31 in the +X direction and also overlaps with the long side of the semiconductor chip 32 in the +X direction in a plan view.

[0032] Each of the metal pads 31a to 32a of this embodiment is disposed at a position overlapping with the uppermost semiconductor chip 22 among the semiconductor chips 21 to 22 in a plan view. That is, the metal pads 31a to 32a of this embodiment are disposed at positions not protruding from the upper surface of the semiconductor chip 22 in a plan view. Therefore, in this embodiment, the semiconductor chip 22 exists in the -Z direction of the metal pads 31a to 32a. According to this embodiment, since the semiconductor chip 22 exists in the -Z direction of the metal pads 31a to 32a, even if the semiconductor chips 31 to 32 are thinned, it is possible to reduce the possibility that the semiconductor chips 31 to 32 are cracked. FIG. 1 shows the metal pads 31a to 32a disposed at positions overlapping with the semiconductor chip 22 in a plan view.

[0033] [Semiconductor chips 41 to 42] The semiconductor chips 41 to 42 are disposed in the -X direction of the metal pad P4 and are electrically connected to the metal pad P4 (FIG. 2). The upper surfaces (rectangles) of the semiconductor chips 41 to 42 have a short side parallel to the Y direction and a long side parallel to the X direction. The semiconductor chip 42 is disposed on the semiconductor chip 41, but is not disposed at a position completely overlapping with the semiconductor chip 41 in a plan view, but is disposed at a position partially overlapping with the semiconductor chip 41. Specifically, the center of gravity of the upper surface of the semiconductor chip 42 is located in the -X direction of the center of gravity of the upper surface of the semiconductor chip 41. Therefore, the semiconductor chips 41 to 42 are stacked on the semiconductor chip 32 so as to form a staircase in the -X direction.

[0034] The semiconductor chip 41 has a plurality of metal pads 41a provided on the upper surface of the semiconductor chip 41 (Fig. 2). The metal pads 41a are arranged in the stepped portion of the semiconductor chip 41, that is, near the short side of the semiconductor chip 41 in the +X direction, and are arranged in a row along the Y direction. These metal pads 41a are electrically connected to the metal pad P4 by a plurality of bonding wires W41. Also, these metal pads 41a are arranged at positions that do not overlap with the semiconductor chip 42 in plan view. The metal pads 41a are examples of one or more fourth chip pads.

[0035] The semiconductor chip 42 has a plurality of metal pads 42a provided on the upper surface of the semiconductor chip 42 (Fig. 2). The metal pads 42a are arranged in the stepped portion of the semiconductor chip 42, that is, near the short side of the semiconductor chip 42 in the +X direction, and are arranged in a row along the Y direction. These metal pads 42a are electrically connected to the metal pads 41a by a plurality of bonding wires W42, and as a result, are electrically connected to the metal pad P4. Also, these metal pads 42a are arranged in the -X direction of the plurality of metal pads 41a. The metal pads 42a are also examples of one or more fourth chip pads.

[0036] In the present embodiment, the semiconductor chips 31 to 32 are arranged such that the short sides are parallel to the X direction and the long sides are parallel to the Y direction, forming a step extending in the +Y direction. On the other hand, the semiconductor chips 41 to 42 are arranged such that the short sides are parallel to the Y direction and the long sides are parallel to the X direction, forming a step extending in the -X direction intersecting the +Y direction. Therefore, the overall shape of these four semiconductor chips 31 to 42 is L-shaped in plan view. The semiconductor chip 41 of the present embodiment is arranged on the semiconductor chip 32 such that the upper right corner of the semiconductor chip 41 overlaps the upper right corner of the semiconductor chip 32 in plan view (here, the term "upper right" means the upper right on the paper surface. The same applies hereinafter). Note that the upper right corner of the semiconductor chip 41 does not have to overlap the upper right corner of the semiconductor chip 32, and for example, it may be located in the +Y direction of the upper right corner of the semiconductor chip 32.

[0037] In this embodiment, the short side of the semiconductor chip 41 in the +X direction in plan view overlaps with the long side of the semiconductor chip 31 in the +X direction and also overlaps with the long side of the semiconductor chip 32 in the +X direction. Further, in this embodiment, the short side of the semiconductor chip 32 in the +Y direction in plan view overlaps with the long side of the semiconductor chip 41 in the +Y direction and also overlaps with the long side of the semiconductor chip 42 in the +Y direction.

[0038] Each of the metal pads 41a to 42a of this embodiment is disposed at a position overlapping with the uppermost semiconductor chip 32 among the semiconductor chips 31 to 32 in plan view. That is, the metal pads 41a to 42a of this embodiment are disposed at positions not protruding from the upper surface of the semiconductor chip 32 in plan view. Therefore, in this embodiment, the semiconductor chip 32 exists in the -Z direction of the metal pads 41a to 42a. According to this embodiment, since the semiconductor chip 32 exists in the -Z direction of the metal pads 41a to 42a, even if the semiconductor chips 41 to 42 are thinned, it is possible to reduce the possibility that the semiconductor chips 41 to 42 are cracked. FIG. 1 shows the metal pads 41a to 42a disposed at positions overlapping with the semiconductor chip 32 in plan view.

[0039] As described above, the semiconductor chips 11 to 12 form steps extending in the -Y direction, and the semiconductor chips 21 to 22 form steps extending in the +X direction. Therefore, the direction in which the steps of the semiconductor chips 21 to 22 extend (+X direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the steps of the semiconductor chips 11 to 12 extend (-Y direction). Similarly, the direction in which the steps of the semiconductor chips 31 to 32 extend (+Y direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the steps of the semiconductor chips 21 to 22 extend (+X direction). Similarly, the direction in which the steps of the semiconductor chips 41 to 42 extend (-X direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the steps of the semiconductor chips 31 to 32 extend (+Y direction). Therefore, these semiconductor chips 11 to 42 are arranged in a spiral shape extending in the Z direction. Specifically, the positional relationship of these semiconductor chips 11 to 42 is such that, like a spiral staircase, they rise in the +Z direction while rotating. Counterclockwise is an example of a predetermined rotation direction.

[0040] Here, the spiral arrangement of the semiconductor chips 11 to 42 will be described. When the centers of gravity of the semiconductor chips 11 to 42 are connected by lines in the order of the semiconductor chips 11 to 42, this line becomes a spiral line extending in the +Z direction. Generally, a spiral line often refers to a line that is circular in plan view, but the term "spiral line" used in this specification includes not only a line that is circular in plan view but also a line that forms a non-circular shape in plan view. For example, when the centers of gravity of the semiconductor chips 11 to 42 are connected by lines in the order of the semiconductor chips 11 to 42, the shape of this line is generally square in plan view. The reason is that in plan view, the center of gravity of the semiconductor chip 12 is located in the -Y direction of the center of gravity of the semiconductor chip 11, the center of gravity of the semiconductor chip 22 is located in the +X direction of the center of gravity of the semiconductor chip 21, the center of gravity of the semiconductor chip 32 is located in the +Y direction of the center of gravity of the semiconductor chip 31, and the center of gravity of the semiconductor chip 42 is located in the -X direction of the center of gravity of the semiconductor chip 41.

[0041] However, semiconductor chips 11 to 42 have only rotated once (360 degrees) counterclockwise in plan view. In this case, if the center of gravity of semiconductor chip 42 coincides with the center of gravity of semiconductor chip 11 in plan view, the line connecting the centers of gravity of semiconductor chips 11 to 42 will form a quadrilateral, that is, a closed line, in plan view. However, in the present embodiment, since the center of gravity of semiconductor chip 42 does not coincide with the center of gravity of semiconductor chip 11 in plan view, the line connecting the centers of gravity of semiconductor chips 11 to 42 is not a closed line but an open line. Specifically, the line connecting the centers of gravity of semiconductor chips 11 to 42 in the present embodiment corresponds to a part of a quadrilateral.

[0042] If semiconductor chips 11 to 42 rotate two or more times in plan view, a large number of metal pads P1, a large number of metal pads P2, a large number of metal pads P3, and a large number of metal pads P4 must be arranged in the +Y direction, -X direction, -Y direction, and +X direction of semiconductor chips 11 to 42, respectively. This will cause the same problems as in the comparative examples (Figs. 6 to 10) described later. On the other hand, semiconductor chips 11 to 42 in the present embodiment have only rotated once in plan view. This makes it possible to improve the problems of the comparative example. This is the same for each of the embodiments described later.

[0043] Figs. 6 and 7 are a cross-sectional view and a plan view showing the structure of a semiconductor device of a comparative example of the first embodiment, respectively. Figs. 8 to 10 are plan views showing a manufacturing method of a semiconductor device of a comparative example of the first embodiment. Figs. 6 to 10 respectively correspond to Figs. 1 to 5.

[0044] The components (Figs. 6 to 10) of the semiconductor device of this comparative example are the same as those of the semiconductor device of the present embodiment (Figs. 1 to 5). However, in this comparative example, metal pads P1 to P2 are alternately arranged in the -X direction of semiconductor pads 11 to 42, and metal pads P3 to P4 are alternately arranged in the +X direction of semiconductor pads 11 to 42. Also, in this comparative example, semiconductor chips 11 to 22 form a staircase extending in the +X direction (Figs. 8 and 9), and semiconductor chips 31 to 42 form a staircase extending in the -X direction (Figs. 10 and 7).

[0045] Hereinafter, this embodiment and this comparative example are compared.

[0046] In this comparative example, metal pads P1 to P2 for two channels are arranged in a row in the -X direction of semiconductor pads 11 to 42 (FIG. 7). Therefore, the lengths of bonding wires W11 for metal pad P1 at the +Y-direction end of this row and bonding wires W21 for metal pad P2 at the -Y-direction end of this row are long. This is not preferable from the viewpoints of the resistance and impedance of bonding wires W11 and W21. The same applies to metal pads P3 to P4.

[0047] Also, in this comparative example, the metal pad 31a of semiconductor chip 31 is arranged near the row of metal pads P3 to P4 in a plan view (FIG. 7). The reason is that since the steps of semiconductor chips 11 to 42 extend only in the ±X directions, the dimensions of the overall shape of semiconductor chips 11 to 42 tend to be long in the X direction in a plan view. Therefore, in FIG. 6, the angle of bonding wire W31 with respect to the upper surface of substrate 1 is large. Specifically, since the angle depends on the ratio B / A of the distance A in the XY plane and the distance B in the Z direction between metal pad P3 electrically connected to this bonding wire W31 and metal pad 31a, when metal pad 31a is near metal pad P3 in a plan view, the ratio B / A becomes large and the angle becomes large. As a result, it becomes difficult to bond bonding wire W31 to metal pad 31a. The same applies to the other bonding wires W11, W21, and W41.

[0048] Also, in this comparative example, there is no semiconductor chip 22 in the -Z direction of the metal pad 31a (Fig. 6). The reason is that the semiconductor chip 31 protrudes in the +X direction of the semiconductor chip 22 in a plan view (overhang) so that the semiconductor chip 31 does not cover the metal pad 22a. In this case, when bonding the bonding wire W31 to the metal pad 31a, the possibility of the semiconductor chip 31 cracking increases. In this comparative example, in order to avoid cracking of the semiconductor chip 31, the thickness of the semiconductor chip 31 is thicker than that of other semiconductor chips.

[0049] On the other hand, the metal pads P1 to P4 of the present embodiment are arranged in a row at intervals of one channel in the ±X direction and the ±Y direction of the semiconductor pads 11 to 42 (Fig. 2). As a result, the lengths of the bonding wires W11, W21, W31, and W41 are shortened. Also, the position of each metal pad P1 in the X direction is within the region between the long side in the +X direction and the long side in the -X direction of the semiconductor chips 11 to 12, and the position of each metal pad P2 in the Y direction is within the region between the long side in the +Y direction and the long side in the -Y direction of the semiconductor chips 21 to 22. Similarly, the position of each metal pad P3 in the X direction is within the region between the long side in the +X direction and the long side in the -X direction of the semiconductor chips 31 to 32, and the position of each metal pad P4 in the Y direction is within the region between the long side in the +Y direction and the long side in the -Y direction of the semiconductor chips 41 to 42. In this case, it is desirable that the position of each metal pad P1 in the X direction is located as close as possible to the center line between the long side in the +X direction and the long side in the -X direction of the semiconductor chips 11 to 12, and the same applies to the metal pads P2 to P4.

[0050] Also, the steps of the semiconductor chips 11 to 42 of the present embodiment extend not only in the ±X direction but also in the ±Y direction (Fig. 2). As a result, the angles of the bonding wires W11, W21, W31, and W41 with respect to the upper surface of the substrate 1 are reduced.

[0051] In addition, in the present embodiment, the semiconductor chip 22 exists in the -Z direction of the metal pad 31a (FIG. 1). Thereby, even if the semiconductor chips 31 to 42 are made thin, when bonding the bonding wire W31 to the metal pad 31a, it is possible to reduce the possibility that the semiconductor chip 31 breaks.

[0052] As described above, in the present embodiment, the semiconductor chips 11 to 42 are stacked in a spiral shape, and the metal pads P1 to P4 are arranged in the ±X direction and the ±Y direction of the semiconductor chips 11 to 42. Further, in the present embodiment, the metal pads 21a to 22a are arranged at positions overlapping the semiconductor chip 12, the metal pads 31a to 32a are arranged at positions overlapping the semiconductor chip 22, and the metal pads 41a to 42a are arranged at positions overlapping the semiconductor chip 32. Therefore, according to the present embodiment, it is possible to suitably stack the semiconductor chips 11 to 42 so as to improve various problems of the present comparative example.

[0053] Note that the metal pads 21a to 22a may be arranged such that all of the metal pad 21a overlaps the semiconductor chip 12 and only a part of the metal pad 22a overlaps the semiconductor chip 12. The reason is that the possibility that the semiconductor chip 22 breaks when bonding the bonding wire W22 to the metal pad 22a is lower than the possibility that the semiconductor chip 21 breaks when bonding the bonding wire W21 to the metal pad 21a. Similarly, the metal pads 31a to 32a may be arranged such that all of the metal pad 31a overlaps the semiconductor chip 22 and only a part of the metal pad 32a overlaps the semiconductor chip 22. Similarly, the metal pads 41a to 42a may be arranged such that all of the metal pad 41a overlaps the semiconductor chip 32 and only a part of the metal pad 42a overlaps the semiconductor chip 32.

[0054] FIG. 11 is a cross-sectional view for explaining the structure of the semiconductor device of the first embodiment.

[0055] FIG. 11 shows semiconductor chips 11 to 42 arranged in a spiral shape extending in the Z direction, similar to FIG. 1. However, in FIG. 11, for clarity of various dashed lines and arrows, the illustration of bonding wires W11 to W42 is omitted.

[0056] FIG. 11 shows the length a [mm] of the short side of the upper surface of semiconductor chips 11 to 42 and the length b [mm] of the long side of the upper surface of semiconductor chips 11 to 42. FIG. 11 further shows the center line (center plane) A of semiconductor chips 31 to 32 and lines (planes) A1 and A2 passing through the outermost metal pads 31a to 32a among the metal pads 31a to 32a of semiconductor chips 31 to 32. Line A1 passes through the outermost part of the outermost metal pads 31a to 32a in the -X direction, and line A2 passes through the outermost part of the outermost metal pads 31a to 32a in the +X direction. FIG. 11 further shows the distance e [mm] between the center line A and lines A1 and A2.

[0057] Since the length a represents the short side and the length b represents the long side, the relationship a < b holds between the length a and the length b. In this embodiment, the shape of the upper surface of semiconductor chips 11 to 42 is, for example, a rectangle close to a square. In this case, the length a is a value close to the length b.

[0058] FIG. 12 is a plan view for explaining the structure of the semiconductor device of the first embodiment.

[0059] In FIG. 12, the above-mentioned center line A extends parallel to the Y direction. The center line A shown in FIG. 12 extends parallel to each long side of semiconductor chip 31 and passes through the center of each short side of semiconductor chip 31. In FIG. 12, the above-mentioned lines A1 and A2 also extend parallel to the Y direction. FIG. 12 further shows the above-mentioned length a, length b, and distance e.

[0060] In this embodiment, it is desirable that the metal pads 31a of the semiconductor chip 31 be arranged so as to satisfy the formula e ≦ b - a / 2 - 0.3. Thereby, even if there is a certain degree of error in the position or the like of the metal pad 31a, it is possible to avoid the metal pad 31a protruding from the upper surface of the semiconductor chip 22. The value 0.3 [mm] in the above formula corresponds to the offset amount.

[0061] Also, in this embodiment, it is desirable that the metal pads 11a to 42a of the semiconductor chips 11 to 42 other than the semiconductor chip 31 be arranged so as to satisfy the above formula. In this case, the distance e in each semiconductor chip is the distance between the center line A passing through the center of each short side of the semiconductor chip and the lines A1 and A2 passing through the outermost metal pads of the semiconductor chip. Note that the center line A in the semiconductor chips 11, 12, 31, and 32 is a straight line extending parallel to the Y direction, and the center line A in the semiconductor chips 21, 22, 41, and 42 is a straight line extending parallel to the X direction.

[0062] As described above, in this embodiment, the metal pads 21a to 22a are arranged at positions overlapping the semiconductor chip 12, the metal pads 31a to 32a are arranged at positions overlapping the semiconductor chip 22, and the metal pads 41a to 42a are arranged at positions overlapping the semiconductor chip 32. Therefore, according to this embodiment, when bonding the bonding wires W21 to W42 to the metal pads 21a to 42a, the possibility of the semiconductor chips 21 to 42 cracking can be reduced, and the semiconductor chips 11 to 42 can be suitably stacked.

[0063] (Second Embodiment) FIG. 13 and FIG. 14 are a cross-sectional view and a plan view showing the structure of the semiconductor device of the second embodiment, respectively. FIGS. 15 to 17 are plan views showing the manufacturing method of the semiconductor device of the second embodiment. FIGS. 13 to 17 respectively correspond to FIGS. 1 to 5.

[0064] In addition to the components of the semiconductor device of the first embodiment, the semiconductor device of this embodiment includes semiconductor chips 13 to 14 electrically connected to metal pad P1, semiconductor chips 23 to 24 electrically connected to metal pad P2, semiconductor chips 33 to 34 electrically connected to metal pad P3, and semiconductor chips 43 to 44 electrically connected to metal pad P4 (FIGS. 13 and 14). The semiconductor chips 13 to 14 are examples of one or more first chips, similar to the semiconductor chips 11 to 12. The semiconductor chips 23 to 24 are examples of one or more second chips, similar to the semiconductor chips 21 to 22. The semiconductor chips 33 to 34 are examples of one or more third chips, similar to the semiconductor chips 31 to 32. The semiconductor chips 43 to 44 are examples of one or more fourth chips, similar to the semiconductor chips 41 to 42. These 16 semiconductor chips 11 to 44 are, for example, semiconductor memory chips.

[0065] The semiconductor device of this embodiment is manufactured by sequentially stacking the semiconductor chips 11 to 44 on the substrate 1. First, metal pads P1 to P4 are formed on the upper surface of the substrate 1, and the semiconductor chips 11 to 14 are sequentially stacked on the substrate 1 (FIG. 15). Next, the semiconductor chips 21 to 24 are sequentially stacked on the semiconductor chip 14 (FIG. 16). Next, the semiconductor chips 31 to 34 are sequentially stacked on the semiconductor chip 24 (FIG. 17). Thereafter, the semiconductor chips 41 to 44 are sequentially stacked on the semiconductor chip 34, and a resin layer 2 is formed on the substrate 1 (FIGS. 13 and 14).

[0066] Hereinafter, with reference to FIGS. 13 to 17, the structure of the semiconductor device of this embodiment will be described.

[0067] [Metal pads P1 to P4] As shown in FIG. 14, the metal pads P1 to P4 are arranged around the semiconductor chips 11 to 44 on the substrate 1. The shapes and arrangements of the metal pads P1 to P4 of this embodiment are the same as those of the metal pads P1 to P4 of the first embodiment. Also, the shapes and thicknesses of the semiconductor chips 11 to 44 of this embodiment are the same as those of the semiconductor chips 11 to 42 of the first embodiment.

[0068] [Semiconductor Chips 11 - 14] Semiconductor chips 11 - 14 are arranged in the -Y direction of the metal pad P1 and are electrically connected to the metal pad P1 (Fig. 15). The upper surfaces (rectangles) of semiconductor chips 11 - 14 have short sides parallel to the X direction and long sides parallel to the Y direction. Similar to the semiconductor chips 11 - 12 of the first embodiment, the semiconductor chips 11 - 14 of this embodiment are stacked on the substrate 1 so as to form a staircase in the -Y direction.

[0069] The details of the semiconductor chips 13 - 14 of this embodiment are the same as those of the semiconductor chips 11 - 12 of the first embodiment. The semiconductor chip 13 has a plurality of metal pads 13a provided on the upper surface of the semiconductor chip 13 (Fig. 15). These metal pads 13a are electrically connected to the metal pad 12a by a plurality of bonding wires W13, and as a result, are electrically connected to the metal pad P1. The semiconductor chip 14 has a plurality of metal pads 14a provided on the upper surface of the semiconductor chip 14 (Fig. 15). These metal pads 14a are electrically connected to the metal pad 13a by a plurality of bonding wires W14, and as a result, are electrically connected to the metal pad P1. The metal pads 13a - 14a are examples of one or more first chip pads, similar to the metal pads 11a - 12a.

[0070] [Semiconductor Chips 21 - 24] Semiconductor chips 21 - 24 are arranged in the +X direction of the metal pad P2 and are electrically connected to the metal pad P2 (Fig. 16). The upper surfaces (rectangles) of semiconductor chips 21 - 24 have short sides parallel to the Y direction and long sides parallel to the X direction. Similar to the semiconductor chips 21 - 22 of the first embodiment, the semiconductor chips 21 - 24 of this embodiment are stacked on the semiconductor chip 14 so as to form a staircase in the +X direction.

[0071] The details of the semiconductor chips 23 to 24 in this embodiment are the same as those of the semiconductor chips 21 to 22 in the first embodiment. The semiconductor chip 23 has a plurality of metal pads 23a provided on the upper surface of the semiconductor chip 23 (FIG. 16). These metal pads 23a are electrically connected to the metal pads 22a by a plurality of bonding wires W23, and as a result, are electrically connected to the metal pad P2. The semiconductor chip 24 has a plurality of metal pads 22a provided on the upper surface of the semiconductor chip 23 (FIG. 16). These metal pads 24a are electrically connected to the metal pads 23a by a plurality of bonding wires W24, and as a result, are electrically connected to the metal pad P2. The metal pads 23a to 24a are examples of one or more second chip pads, similar to the metal pads 21a to 22a.

[0072] In this embodiment, the semiconductor chips 11 to 14 are arranged such that their short sides are parallel to the X direction and their long sides are parallel to the Y direction, forming a staircase extending in the -Y direction. On the other hand, the semiconductor chips 21 to 24 are arranged such that their short sides are parallel to the Y direction and their long sides are parallel to the X direction, forming a staircase extending in the +X direction intersecting the -Y direction. Therefore, the overall shape of these eight semiconductor chips 11 to 24 is L-shaped in plan view.

[0073] Each of the metal pads 21a to 24a in this embodiment is arranged at a position overlapping the uppermost semiconductor chip 14 among the semiconductor chips 11 to 14 in plan view. According to this embodiment, since the semiconductor chip 14 exists in the -Z direction of the metal pads 21a to 24a, even if the semiconductor chips 21 to 24 are thinned, it is possible to reduce the possibility of the semiconductor chips 21 to 24 cracking. FIG. 13 shows the metal pads 21a to 24a arranged at positions overlapping the semiconductor chip 14 in plan view.

[0074] [Semiconductor chips 31 to 34] Semiconductor chips 31 to 34 are arranged in the +Y direction of the metal pad P3 and are electrically connected to the metal pad P3 (FIG. 17). The upper surfaces (rectangles) of the semiconductor chips 31 to 34 have short sides parallel to the X direction and long sides parallel to the Y direction. Similar to the semiconductor chips 31 to 32 of the first embodiment, the semiconductor chips 31 to 34 of the present embodiment are stacked on the semiconductor chip 24 so as to form steps in the +Y direction.

[0075] Details of the semiconductor chips 33 to 34 of the present embodiment are the same as those of the semiconductor chips 31 to 32 of the first embodiment. The semiconductor chip 33 has a plurality of metal pads 33a provided on the upper surface of the semiconductor chip 33 (FIG. 17). These metal pads 33a are electrically connected to the metal pad 32a by a plurality of bonding wires W33, and as a result, are electrically connected to the metal pad P3. The semiconductor chip 34 has a plurality of metal pads 34a provided on the upper surface of the semiconductor chip 34 (FIG. 17). These metal pads 34a are electrically connected to the metal pad 33a by a plurality of bonding wires W34, and as a result, are electrically connected to the metal pad P3. The metal pads 33a to 34a are examples of one or more third chip pads, similar to the metal pads 31a to 32a.

[0076] In the present embodiment, the semiconductor chips 21 to 24 are arranged such that the short sides are parallel to the Y direction and the long sides are parallel to the X direction, forming steps extending in the +X direction. On the other hand, the semiconductor chips 31 to 34 are arranged such that the short sides are parallel to the X direction and the long sides are parallel to the Y direction, forming steps extending in the +Y direction intersecting the +X direction. Therefore, the overall shape of these eight semiconductor chips 21 to 34 is L-shaped in plan view.

[0077] Each of the metal pads 31a to 34a of the present embodiment is disposed at a position overlapping with the uppermost semiconductor chip 24 among the semiconductor chips 21 to 24 in a plan view. According to the present embodiment, since the semiconductor chip 24 exists in the -Z direction of the metal pads 31a to 34a, even if the semiconductor chips 31 to 34 are made thinner, it is possible to reduce the possibility that the semiconductor chips 31 to 34 are cracked. FIG. 13 shows the metal pads 31a to 34a disposed at positions overlapping with the semiconductor chip 24 in a plan view.

[0078] [Semiconductor chips 41 to 44] The semiconductor chips 41 to 44 are disposed in the -X direction of the metal pad P4 and are electrically connected to the metal pad P4 (FIG. 14). The upper surfaces (rectangles) of the semiconductor chips 41 to 44 have short sides parallel to the Y direction and long sides parallel to the X direction. The semiconductor chips 41 to 44 of the present embodiment are stacked on the semiconductor chip 32 so as to form a staircase in the -X direction, similarly to the semiconductor chips 41 to 42 of the first embodiment.

[0079] Details of the semiconductor chips 43 to 44 of the present embodiment are the same as those of the semiconductor chips 41 to 42 of the first embodiment. The semiconductor chip 43 has a plurality of metal pads 43a provided on the upper surface of the semiconductor chip 43 (FIG. 14). These metal pads 43a are electrically connected to the metal pad 42a by a plurality of bonding wires W43, and as a result, are electrically connected to the metal pad P4. The semiconductor chip 44 has a plurality of metal pads 44a provided on the upper surface of the semiconductor chip 44 (FIG. 14). These metal pads 44a are electrically connected to the metal pad 43a by a plurality of bonding wires W44, and as a result, are electrically connected to the metal pad P4. The metal pads 43a to 44a are examples of one or more fourth chip pads, similarly to the metal pads 41a to 42a.

[0080] In this embodiment, the semiconductor chips 31 to 34 are arranged such that their short sides are parallel to the X direction and their long sides are parallel to the Y direction, forming a staircase extending in the +Y direction. On the other hand, the semiconductor chips 41 to 44 are arranged such that their short sides are parallel to the Y direction and their long sides are parallel to the X direction, forming a staircase extending in the -X direction intersecting the +Y direction. Therefore, the overall shape of these eight semiconductor chips 31 to 44 is L-shaped in plan view.

[0081] Each of the metal pads 41a to 44a of this embodiment is arranged at a position overlapping the uppermost semiconductor chip 34 among the semiconductor chips 31 to 34 in plan view. According to this embodiment, since the semiconductor chip 34 exists in the -Z direction of the metal pads 41a to 44a, even if the semiconductor chips 41 to 44 are thinned, it is possible to reduce the possibility of the semiconductor chips 41 to 44 cracking. FIG. 13 shows the metal pads 41a to 44a arranged at positions overlapping the semiconductor chip 34 in plan view.

[0082] In this embodiment, the semiconductor chips 11 to 14 form a staircase extending in the -Y direction, and the semiconductor chips 21 to 24 form a staircase extending in the +X direction. As a result, the direction in which the staircase of the semiconductor chips 21 to 24 extends (+X direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the staircase of the semiconductor chips 11 to 14 extends (-Y direction). Similarly, the direction in which the staircase of the semiconductor chips 31 to 34 extends (+Y direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the staircase of the semiconductor chips 21 to 24 extends (+X direction). Similarly, the direction in which the staircase of the semiconductor chips 41 to 44 extends (-X direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the staircase of the semiconductor chips 31 to 34 extends (+Y direction). Therefore, these semiconductor chips 11 to 44 are arranged in a spiral shape extending in the Z direction.

[0083] As described above, in the present embodiment, the metal pads 21a to 24a are arranged at positions overlapping the semiconductor chip 14, the metal pads 31a to 34a are arranged at positions overlapping the semiconductor chip 24, and the metal pads 41a to 44a are arranged at positions overlapping the semiconductor chip 34. Therefore, according to the present embodiment, when bonding the bonding wires W21 to W44 to the metal pads 21a to 44a, it is possible to reduce the possibility of the semiconductor chips 21 to 44 cracking, etc., and it becomes possible to suitably stack the semiconductor chips 11 to 44.

[0084] Note that the metal pads 21a to 24a may be arranged such that all of the metal pad 21a overlaps the semiconductor chip 14, and only a part of the metal pads 22a to 24a overlaps the semiconductor chip 14. The reason is that the possibility of the semiconductor chips 22 to 24 cracking when bonding the bonding wires W22 to W24 to the metal pads 22a to 24a is lower than the possibility of the semiconductor chip 21 cracking when bonding the bonding wire W21 to the metal pad 21a. Similarly, the metal pads 31a to 34a may be arranged such that all of the metal pad 31a overlaps the semiconductor chip 24, and only a part of the metal pads 32a to 33a overlaps the semiconductor chip 24. Similarly, the metal pads 41a to 44a may be arranged such that all of the metal pad 41a overlaps the semiconductor chip 34, and only a part of the metal pads 42a to 44a overlaps the semiconductor chip 34.

[0085] (Third Embodiment) FIG. 18 and FIG. 19 are a cross-sectional view and a plan view showing the structure of the semiconductor device of the third embodiment, respectively. FIGS. 20 to 22 are plan views showing the manufacturing method of the semiconductor device of the third embodiment. FIGS. 18 to 22 respectively correspond to FIGS. 1 to 5.

[0086] As shown in FIGS. 18 and 19, the semiconductor device of the present embodiment includes the same components as the semiconductor device of the second embodiment.

[0087] However, semiconductor chips 21 to 24 of the present embodiment are stacked on semiconductor chip 14 so as to have an offset S from each other in the -Y direction (FIG. 21). As a result, semiconductor chips 21 to 24 of the present embodiment form a gentle staircase in the +X direction and a steep staircase in the -Y direction. The offset S of semiconductor chips 21 to 24 is also shown in FIG. 19. Semiconductor chips 21 to 24 of the present embodiment are arranged on semiconductor chip 14 such that the long side in the -Y direction of semiconductor chip 24 overlaps with the short side in the -Y direction of semiconductor chip 14 in plan view.

[0088] Similarly, semiconductor chips 31 to 34 of the present embodiment are stacked on semiconductor chip 14 so as to have an offset S from each other in the +X direction (FIG. 22). As a result, semiconductor chips 31 to 34 of the present embodiment form a gentle staircase in the +Y direction and a steep staircase in the +X direction. The offset S of semiconductor chips 31 to 34 is also shown in FIGS. 18 and 19. Semiconductor chips 31 to 34 of the present embodiment are arranged on semiconductor chip 24 such that the long side in the +X direction of semiconductor chip 34 overlaps with the short side in the +X direction of semiconductor chip 24 in plan view.

[0089] On the one hand, the semiconductor chips 11 to 14 of the present embodiment are stacked on the substrate 1 so as not to have an offset S from each other in the ±X direction (FIG. 20). Similarly, the semiconductor chips 41 to 44 of the present embodiment are stacked on the semiconductor chip 34 so as not to have an offset S from each other in the ±Y direction (FIG. 19). The offset S of the present embodiment is not provided in the semiconductor chips 11 to 14 belonging to the lowest semiconductor chip group and the semiconductor chips 41 to 44 belonging to the highest semiconductor chip group, and is provided in the semiconductor chips 21 to 34 belonging to the other semiconductor chip groups. Here, the semiconductor chip group including the semiconductor chips 11 to 14 means a group of semiconductor chips electrically connected to the metal pad P1, and the semiconductor chip group including the semiconductor chips 21 to 24 means a group of semiconductor chips electrically connected to the metal pad P2. Similarly, the semiconductor chip group including the semiconductor chips 31 to 34 means a group of semiconductor chips electrically connected to the metal pad P3, and the semiconductor chip group including the semiconductor chips 41 to 44 means a group of semiconductor chips electrically connected to the metal pad P4.

[0090] According to the present embodiment, by providing the offset S in the semiconductor chips 21 to 24, for example, it is possible to optimize the positional relationship between the metal pads 31a to 34a and the metal pad P3. Similarly, according to the present embodiment, by providing the offset S in the semiconductor chips 31 to 34, for example, it is possible to optimize the positional relationship between the metal pads 41a to 44a and the metal pad P4. The reason is that the bonding wires are shorter when there is no offset S in the lowest and highest semiconductor chip groups, but the bonding wires are shorter when there is an offset S in the other semiconductor chip groups. This is used, for example, when it is difficult to freely change the positions of the metal pads P1 to P4 in order to keep the size of the semiconductor package constant.

[0091] (Fourth Embodiment) FIG. 23 and FIG. 24 are a cross-sectional view and a plan view showing the structure of the semiconductor device according to the fourth embodiment, respectively. FIGS. 25 to 27 are plan views showing the manufacturing method of the semiconductor device according to the fourth embodiment. FIGS. 23 to 27 respectively correspond to FIGS. 1 to 5.

[0092] Similar to the semiconductor device of the first embodiment, the semiconductor device of the present embodiment includes a substrate 1, a resin layer 2, a plurality of metal pads P1, a plurality of metal pads P2, a plurality of semiconductor chips 11 to 12 electrically connected to the metal pad P1, and a plurality of semiconductor chips 21 to 22 electrically connected to the metal pad P2 (FIGS. 23 and 24).

[0093] However, these four semiconductor chips 11 to 22 are stacked on the substrate 1 in the order of semiconductor chip 11, semiconductor chip 21, semiconductor chip 12, and semiconductor chip 22. The semiconductor chip 11 of the present embodiment is an example of one or more first chips. The semiconductor chip 21 of the present embodiment is an example of one or more second chips. The semiconductor chip 12 of the present embodiment is an example of one or more third chips. The semiconductor chip 22 of the present embodiment is an example of one or more fourth chips.

[0094] Furthermore, the semiconductor chips 11 to 22 of the present embodiment are arranged in the -X direction of the metal pad P1 and in the +Y direction of the metal pad P2. The -X direction of the present embodiment is an example of the first direction, and the +Y direction of the present embodiment is an example of the second direction. Also, the metal pad P1 of the present embodiment is an example of one or more first substrate pads, similar to the metal pad P1 of the first embodiment, and the metal pad P2 of the present embodiment is an example of one or more second substrate pads, similar to the metal pad P2 of the first embodiment.

[0095] The semiconductor device of the present embodiment further includes a control chip 51 disposed on the substrate 1 for controlling the operations of the semiconductor chips 11 to 22. The control chip 51 of the present embodiment is disposed at a position partially overlapping the semiconductor chip 22 in plan view (FIGS. 23 and 24).

[0096] On the other hand, the semiconductor device of the present embodiment does not include a metal pad P3, a metal pad P4, a plurality of semiconductor chips 31 to 32 electrically connected to the metal pad P3, and a plurality of semiconductor chips 41 to 42 electrically connected to the metal pad P4.

[0097] The semiconductor device of the present embodiment is manufactured by arranging semiconductor chips 11 to 22 and a control chip 51 on a substrate 1. First, metal pads P1 to P2 are formed on the upper surface of the substrate 1, and the semiconductor chip 11 and the control chip 51 are arranged on the substrate 1 (FIG. 25). Next, the semiconductor chip 21 is arranged on the semiconductor chip 11 (FIG. 26). Next, the semiconductor chip 12 is arranged on the semiconductor chip 21 (FIG. 27). Thereafter, the semiconductor chip 22 is arranged on the semiconductor chip 12, and a resin layer 2 is formed on the substrate 1 (FIGS. 23 and 24). In FIGS. 23 and 24, the control chip 51 has a portion provided under the semiconductor chip 22 in plan view.

[0098] Hereinafter, with reference to FIGS. 23 to 27, the structure of the semiconductor device of the present embodiment will be described.

[0099] [Metal pads P1 to P2] As shown in FIG. 24, the metal pads P1 to P2 are arranged on the substrate 1 in the +X direction and -Y direction of the semiconductor chips 11 to 22. Specifically, the metal pad P1 is arranged in the +X direction of the semiconductor chips 11 to 22 and is arranged in a row along the Y direction. The metal pad P2 is arranged in the -Y direction of the semiconductor chips 11 to 22 and is arranged in a row along the X direction.

[0100] In the present embodiment, the semiconductor chips 11 to 22 have congruent shapes in plan view. Specifically, the shapes of the semiconductor chips 11 to 22 are congruent squares in plan view. Further, the semiconductor chips 11 to 22 of the present embodiment have the same thickness (FIG. 23). In the present embodiment, the thickness of the semiconductor chips 11 to 22 is set to 50 μm or less (for example, 20 to 50 μm). Note that the shapes and thicknesses of the semiconductor chips 11 to 22 may be different from those of the present embodiment.

[0101] [Semiconductor chip 11] The semiconductor chip 11 is arranged in the -X direction of the metal pad P1 and is electrically connected to the metal pad P1 (Fig. 25). The upper surface (square) of the semiconductor chip 11 has two sides parallel to the X direction and two sides parallel to the Y direction.

[0102] The semiconductor chip 11 has a plurality of metal pads 11a provided on the upper surface of the semiconductor chip 11 (Fig. 25). These metal pads 11a are electrically connected to the metal pad P1 by a plurality of bonding wires W11. The metal pads 11a of the present embodiment are examples of one or more first chip pads.

[0103] [Semiconductor chip 21] The semiconductor chip 21 is arranged in the +Y direction of the metal pad P2 and is electrically connected to the metal pad P2 (Fig. 26). The upper surface (square) of the semiconductor chip 21 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 21 is arranged on the semiconductor chip 11, but is not in a position that completely overlaps the semiconductor chip 11 in plan view, but is arranged in a position that partially overlaps the semiconductor chip 11. Specifically, the center of gravity of the upper surface of the semiconductor chip 21 is located in the -X direction of the center of gravity of the upper surface of the semiconductor chip 11. Therefore, the semiconductor chips 11 and 21 are stacked on the substrate 1 so as to form a staircase in the -X direction.

[0104] The semiconductor chip 21 has a plurality of metal pads 21a provided on the upper surface of the semiconductor chip 21 (Fig. 26). These metal pads 21a are electrically connected to the metal pad P2 by a plurality of bonding wires W21. The metal pads 21a of the present embodiment are examples of one or more second chip pads.

[0105] Each of the metal pads 21a of the present embodiment is arranged at a position overlapping the semiconductor chip 11 in plan view. According to the present embodiment, since the semiconductor chip 11 exists in the -Z direction of the metal pad 21a, even if the semiconductor chip 21 is thinned, it is possible to reduce the possibility of the semiconductor chip 21 cracking. FIG. 23 shows the metal pad 21a arranged at a position overlapping the semiconductor chip 11 in plan view.

[0106] [Semiconductor chip 12] The semiconductor chip 12 is arranged in the -X direction of the metal pad P1 and is electrically connected to the metal pad P1 (FIG. 27). The upper surface (square) of the semiconductor chip 12 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 12 is arranged on the semiconductor chip 21, but is not arranged at a position completely overlapping the semiconductor chip 21 in plan view, but is arranged at a position partially overlapping the semiconductor chip 21. Specifically, the center of gravity of the upper surface of the semiconductor chip 12 is located in the +Y direction of the center of gravity of the upper surface of the semiconductor chip 21. Therefore, the semiconductor chips 21 and 12 are stacked on the semiconductor chip 11 so as to form a step in the +Y direction.

[0107] The semiconductor chip 12 has a plurality of metal pads 12a provided on the upper surface of the semiconductor chip 12 (FIG. 27). These metal pads 12a are electrically connected to the metal pad 11a by a plurality of bonding wires W12, and as a result, are electrically connected to the metal pad P1. The metal pad 12a of the present embodiment is an example of one or more third chip pads.

[0108] Each of the metal pads 12a of the present embodiment is arranged at a position overlapping the semiconductor chip 21 in plan view. According to the present embodiment, since the semiconductor chip 21 exists in the -Z direction of the metal pad 12a, even if the semiconductor chip 12 is thinned, it is possible to reduce the possibility of the semiconductor chip 12 cracking. FIG. 23 shows the metal pad 12a arranged at a position overlapping the semiconductor chip 21 in plan view.

[0109] [Semiconductor chip 22] The semiconductor chip 22 is arranged in the +Y direction of the metal pad P2 and is electrically connected to the metal pad P2 (FIG. 24). The upper surface (square) of the semiconductor chip 22 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 22 is arranged on the semiconductor chip 12, but is not arranged at a position that completely overlaps the semiconductor chip 12 in plan view, but is arranged at a position that partially overlaps the semiconductor chip 12. Specifically, the center of gravity of the upper surface of the semiconductor chip 22 is located in the -X direction of the center of gravity of the upper surface of the semiconductor chip 12. Therefore, the semiconductor chips 12 and 22 are stacked on the semiconductor chip 21 so as to form a step in the -X direction.

[0110] The semiconductor chip 22 has a plurality of metal pads 22a provided on the upper surface of the semiconductor chip 22 (FIG. 24). These metal pads 22a are electrically connected to the metal pads 21a by a plurality of bonding wires W22, and as a result, are electrically connected to the metal pad P2. The metal pad 22a of the present embodiment is an example of one or more fourth chip pads.

[0111] Each of the metal pads 22a of the present embodiment is arranged at a position that overlaps the semiconductor chip 12 in plan view. According to the present embodiment, since the semiconductor chip 12 exists in the -Z direction of the metal pad 22a, even if the semiconductor chip 22 is thinned, it is possible to reduce the possibility that the semiconductor chip 22 breaks. FIG. 23 shows the metal pad 22a arranged at a position that overlaps the semiconductor chip 12 in plan view.

[0112] In this embodiment, the semiconductor chips 11 and 21 form steps extending in the -X direction, and the semiconductor chips 21 and 12 form steps extending in the +Y direction. As a result, the direction in which the steps of the semiconductor chips 21 and 12 extend (+Y direction) is rotated 90 degrees clockwise in plan view with respect to the direction in which the steps of the semiconductor chips 11 and 21 extend (-X direction). On the other hand, the direction in which the steps of the semiconductor chips 12 and 22 extend (-X direction) is rotated 90 degrees counterclockwise in plan view with respect to the direction in which the steps of the semiconductor chips 21 and 12 extend (+Y direction). Therefore, these semiconductor chips 11 to 22 form steps extending in the upper left direction in plan view (here, the term "upper left" means the upper left on the paper surface. The same applies hereinafter).

[0113] As a result, the semiconductor device of this embodiment has a space where the control chip 51 can be disposed under the semiconductor chip 22. Specifically, such a space is generated below the upper left corner of the semiconductor chip 22 in plan view. Therefore, the control chip 51 of this embodiment is disposed at a position partially overlapping the semiconductor chip 22 in plan view. Thereby, even if the area of the upper surface of the substrate 1 is small, it is possible to secure a space for disposing the control chip 51.

[0114] As described above, in this embodiment, the metal pad 21a is disposed at a position overlapping the semiconductor chip 11, the metal pad 12a is disposed at a position overlapping the semiconductor chip 21, and the metal pad 22a is disposed at a position overlapping the semiconductor chip 12. Therefore, according to this embodiment, it is possible to suitably stack the semiconductor chips 11 to 22, such as reducing the possibility that the semiconductor chips 21, 12, and 22 are cracked when bonding wires W21, W12, and W22 to the metal pads 21a, 12a, and 22a.

[0115] FIG. 28 and FIG. 29 are a cross-sectional view and a plan view, respectively, showing the structure of a semiconductor device according to a first modification of the fourth embodiment.

[0116] As shown in FIGS. 28 and 29, the semiconductor device of this modification includes the same components as the semiconductor device of the present embodiment. However, the thickness of the semiconductor chip 11 of this modification is thicker than the thicknesses of the other semiconductor chips 21, 12, and 22. As a result, the control chip 51 of this modification is arranged at a position that completely overlaps with the semiconductor chip 22 in plan view (FIG. 29), and the entire control chip 51 is located in the -Z direction of the semiconductor chip 22. Furthermore, the control chip 51 of this modification is arranged at a position that partially overlaps with the semiconductor chips 21 and 12 in plan view (FIG. 28), and has a portion located in the -Z direction of the semiconductor chips 21 and 12 and a portion not located in the -Z direction of the semiconductor chips 21 and 12. Thereby, even if the area of the upper surface of the substrate 1 is further reduced, it is possible to secure a space for arranging the control chip 51.

[0117] FIG. 30 is a plan view showing the structure of the semiconductor device according to the second modification of the fourth embodiment.

[0118] As shown in FIG. 30, the semiconductor device of this modification includes the same components as the semiconductor device of the present embodiment. However, the shapes of the semiconductor chips 11 to 22 of this modification are congruent rectangles in plan view. As a result, the control chip 51 of this modification is arranged at a position that does not overlap with the semiconductor chip 22 in plan view. However, according to this modification, since the shapes of the semiconductor chips 11 to 22 are rectangles, it is possible to secure a space for arranging the control chip 51 near the upper left corner of the semiconductor chip 22.

[0119] (Modification of the First Embodiment) FIGS. 31 and 32 are a cross-sectional view and a plan view, respectively, showing the structure of the semiconductor device according to the modification of the first embodiment. FIGS. 33 to 35 are plan views showing the manufacturing method of the semiconductor device according to the modification of the first embodiment. FIGS. 31 to 35 respectively correspond to FIGS. 1 to 5.

[0120] The semiconductor device of this modified example includes a substrate 1, a resin layer 2, a plurality of metal pads P1, a plurality of metal pads P2, a plurality of metal pads P3, and a plurality of metal pads P4, similar to the semiconductor device of the first embodiment (Figs. 31 and 32).

[0121] The semiconductor device of this modified example further includes a semiconductor chip 11 electrically connected to the metal pad P1, a semiconductor chip 21 electrically connected to the metal pad P2, a semiconductor chip 31 electrically connected to the metal pad P3, and a semiconductor chip 41 electrically connected to the metal pad P4, similar to the semiconductor device of the first embodiment (Figs. 31 and 32). However, these four semiconductor chips 11 to 41 are arranged in the -X direction of the metal pad P1, in the +Y direction of the metal pad P2, in the +X direction of the metal pad P3, and in the -Y direction of the metal pad P4. The -X direction of this modified example is an example of the first direction, and the +Y direction of this modified example is an example of the second direction. Also, the +X direction of this modified example is an example of the third direction, and the -Y direction of this modified example is an example of the fourth direction.

[0122] The semiconductor device of this modified example may further include a control chip 51, similar to the semiconductor device of the fourth embodiment.

[0123] The semiconductor device of this modified example is manufactured by arranging the semiconductor chips 11 to 41 on the substrate 1. First, the metal pads P1 to P4 are formed on the upper surface of the substrate 1, and the semiconductor chip 11 is arranged on the substrate 1 (Fig. 33). Next, the semiconductor chip 21 is arranged on the semiconductor chip 11 (Fig. 34). Next, the semiconductor chip 31 is arranged on the semiconductor chip 21 (Fig. 35). Thereafter, the semiconductor chip 41 is arranged on the semiconductor chip 31, and the resin layer 2 is formed on the substrate 1 (Figs. 31 and 32).

[0124] Hereinafter, with reference to Figs. 31 to 35, the structure of the semiconductor device of this modified example will be described.

[0125] [Metal pads P1 to P4] As shown in FIG. 32, the metal pads P1 to P4 are arranged around the semiconductor chips 11 to 41 on the substrate 1. Specifically, the metal pad P1 is arranged in the +X direction of the semiconductor chips 11 to 41 and is arranged in a row along the Y direction. The metal pad P2 is arranged in the -Y direction of the semiconductor chips 11 to 41 and is arranged in a row along the X direction. The metal pad P3 is arranged in the -X direction of the semiconductor chips 11 to 41 and is arranged in a row along the Y direction. The metal pad P4 is arranged in the +Y direction of the semiconductor chips 11 to 41 and is arranged in a row along the X direction.

[0126] In this modification, the semiconductor chips 11 to 41 have congruent shapes in plan view. Specifically, the shapes of the semiconductor chips 11 to 41 are congruent squares in plan view. Also, the semiconductor chips 11 to 41 of this modification have the same thickness (FIG. 31). In this modification, the thickness of the semiconductor chips 11 to 41 is set to 50 μm or less (for example, 20 to 50 μm). Note that the shapes and thicknesses of the semiconductor chips 11 to 41 may be different from those of this modification.

[0127] [Semiconductor chip 11] The semiconductor chip 11 is arranged in the -X direction of the metal pad P1 and is electrically connected to the metal pad P1 (FIG. 33). The upper surface (square) of the semiconductor chip 11 has two sides parallel to the X direction and two sides parallel to the Y direction.

[0128] The semiconductor chip 11 has a plurality of metal pads 11a provided on the upper surface of the semiconductor chip 11 (FIG. 33). These metal pads 11a are electrically connected to the metal pad P1 by a plurality of bonding wires W11. The metal pad 11a of this modification is an example of one or more first chip pads.

[0129] [Semiconductor chip 21] The semiconductor chip 21 is arranged in the +Y direction of the metal pad P2 and is electrically connected to the metal pad P2 (FIG. 34). The upper surface (square) of the semiconductor chip 21 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 21 is arranged on the semiconductor chip 11, but is not in a position that completely overlaps the semiconductor chip 11 in plan view, but is arranged in a position that partially overlaps the semiconductor chip 11. Specifically, the center of gravity of the upper surface of the semiconductor chip 21 is located in the -X direction of the center of gravity of the upper surface of the semiconductor chip 11. Therefore, the semiconductor chips 11 and 21 are stacked on the substrate 1 so as to form a step in the -X direction.

[0130] The semiconductor chip 21 has a plurality of metal pads 21a provided on the upper surface of the semiconductor chip 21 (FIG. 34). These metal pads 21a are electrically connected to the metal pad P2 by a plurality of bonding wires W21. The metal pad 21a of this modification is an example of one or more second chip pads.

[0131] Each of the metal pads 21a of this modification is arranged in a position that overlaps the semiconductor chip 11 in plan view. According to this modification, since the semiconductor chip 11 exists in the -Z direction of the metal pad 21a, even if the semiconductor chip 21 is thinned, it is possible to reduce the possibility that the semiconductor chip 21 breaks. FIG. 31 shows the metal pad 21a arranged in a position that overlaps the semiconductor chip 11 in plan view.

[0132] [Semiconductor chip 31] The semiconductor chip 31 is arranged in the +X direction of the metal pad P3 and is electrically connected to the metal pad P3 (Fig. 35). The upper surface (square) of the semiconductor chip 31 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 31 is arranged on the semiconductor chip 21, but is not arranged at a position that completely overlaps the semiconductor chip 21 in plan view, but is arranged at a position that partially overlaps the semiconductor chip 21. Specifically, the center of gravity of the upper surface of the semiconductor chip 31 is located in the +Y direction of the center of gravity of the upper surface of the semiconductor chip 21. Therefore, the semiconductor chips 21 and 31 are stacked on the semiconductor chip 11 so as to form a step in the +Y direction.

[0133] The semiconductor chip 31 has a plurality of metal pads 31a provided on the upper surface of the semiconductor chip 31 (Fig. 35). These metal pads 31a are electrically connected to the metal pad P3 by a plurality of bonding wires W31. The metal pad 31a of this modification example is an example of one or more third chip pads.

[0134] Each of the metal pads 31a of this modification example is arranged at a position that overlaps the semiconductor chip 21 in plan view. According to this modification example, since the semiconductor chip 21 exists in the -Z direction of the metal pad 31a, even if the semiconductor chip 31 is thinned, it is possible to reduce the possibility that the semiconductor chip 31 breaks. Fig. 31 shows the metal pad 31a arranged at a position that overlaps the semiconductor chip 21 in plan view.

[0135] [Semiconductor chip 41] The semiconductor chip 41 is disposed in the -Y direction of the metal pad P4 and is electrically connected to the metal pad P4 (FIG. 32). The upper surface (square) of the semiconductor chip 41 has two sides parallel to the X direction and two sides parallel to the Y direction. The semiconductor chip 41 is disposed on the semiconductor chip 31, but is not disposed at a position that completely overlaps the semiconductor chip 31 in plan view, but is disposed at a position that partially overlaps the semiconductor chip 31. Specifically, the center of gravity of the upper surface of the semiconductor chip 41 is located in the +X direction of the center of gravity of the upper surface of the semiconductor chip 31. Therefore, the semiconductor chips 31 and 41 are stacked on the semiconductor chip 21 so as to form a step in the +X direction.

[0136] The semiconductor chip 41 has a plurality of metal pads 41a provided on the upper surface of the semiconductor chip 41 (FIG. 32). These metal pads 41a are electrically connected to the metal pad P4 by a plurality of bonding wires W41. The metal pad 41a of this modification is an example of one or more fourth chip pads.

[0137] Each of the metal pads 41a of this modification is disposed at a position that overlaps the semiconductor chip 31 in plan view. According to this modification, since the semiconductor chip 31 exists in the -Z direction of the metal pad 41a, even if the semiconductor chip 31 is thinned, it is possible to reduce the possibility of the semiconductor chip 31 cracking. FIG. 31 shows the metal pad 41a disposed at a position that overlaps the semiconductor chip 31 in plan view.

[0138] In this modification, the semiconductor chips 11 and 21 form a step extending in the -X direction, and the semiconductor chips 21 and 31 form a step extending in the +Y direction. As a result, the direction in which the steps of the semiconductor chips 21 and 31 extend (+Y direction) is rotated 90 degrees clockwise in plan view with respect to the direction in which the steps of the semiconductor chips 11 and 21 extend (-X direction). Similarly, the direction in which the steps of the semiconductor chips 31 and 41 extend (+X direction) is rotated 90 degrees clockwise in plan view with respect to the direction in which the steps of the semiconductor chips 21 and 31 extend (+Y direction). Therefore, these semiconductor chips 11 to 41 are arranged in a spiral shape extending in the Z direction. Clockwise is an example of a predetermined rotation direction.

[0139] As described above, in this modified example, the metal pad 21a is disposed at a position overlapping the semiconductor chip 11, the metal pad 31a is disposed at a position overlapping the semiconductor chip 21, and the metal pad 41a is disposed at a position overlapping the semiconductor chip 31. Therefore, according to this modified example, when bonding the bonding wires W21 to W41 to the metal pads 21a to 41a, the possibility of cracking of the semiconductor chips 21 to 41 can be reduced, and the semiconductor chips 11 to 41 can be suitably stacked.

[0140] As described above, several embodiments have been described. However, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device described in this specification can be implemented in various other forms. Also, various omissions, substitutions, and changes can be made to the form of the device described in this specification without departing from the gist of the invention. The appended claims and the equivalents thereof are intended to include such forms and modifications included in the scope and gist of the invention.

Explanation of Reference Numerals

[0141] 1: Substrate, 2: Resin layer, 11 to 14: Semiconductor chips, 11a to 14a: Metal pads, 21 to 24: Semiconductor chips, 21a to 24a: Metal pads, 31 to 34: Semiconductor chips, 31a to 34a: Metal pads, 41 to 44: Semiconductor chips, 41a to 44a: Metal pads, 51: Control chip

Claims

1. A substrate, one or more first substrate pads provided on the substrate, one or more first chips provided on the substrate and arranged in a first direction with respect to the first substrate pads, each of the first chips having one or more first chip pads electrically connected to the first substrate pads, one or more second substrate pads provided on the substrate, one or more second chips provided on the first chip and arranged in a second direction intersecting the first direction with respect to the second substrate pads, each of the second chips having one or more second chip pads electrically connected to the second substrate pads, A semiconductor device, wherein each of the second chip pads is arranged at a position overlapping the uppermost first chip among the first chips in a plan view.

2. one or more third substrate pads provided on the substrate, one or more third chips provided on the second chip and arranged in a third direction intersecting the second direction with respect to the third substrate pads, each of the third chips having one or more third chip pads electrically connected to the third substrate pads, The semiconductor device according to claim 1, wherein each of the third chip pads is arranged at a position overlapping the uppermost second chip among the second chips in a plan view.

3. one or more fourth substrate pads provided on the substrate, one or more fourth chips provided on the third chip and arranged in a fourth direction intersecting the third direction with respect to the fourth substrate pads, each of the fourth chips having one or more fourth chip pads electrically connected to the fourth substrate pads, The semiconductor device according to claim 2, wherein each of the fourth chip pads is arranged at a position overlapping the uppermost third chip among the third chips in a plan view.

4. one or more third chips provided on the second chip and arranged in the first direction with respect to the first substrate pads, each of the third chips having one or more third chip pads electrically connected to the first substrate pads. The semiconductor device according to claim 1, wherein each of the third chip pads is disposed at a position overlapping with the uppermost second chip among the second chips in a plan view.

5. One or more fourth chips provided on the third chip and arranged in the second direction with respect to the second substrate pad, each of the fourth chips having one or more fourth chip pads electrically connected to the second substrate pad, further comprising one or more fourth chips, The semiconductor device according to claim 4, wherein each of the fourth chip pads is disposed at a position overlapping with the uppermost third chip among the third chips in a plan view.

6. The first chip includes a plurality of first chips stacked so as to form a staircase in the first direction, The second chip includes a plurality of second chips stacked so as to form a staircase in the second direction, The semiconductor device according to claim 1.

7. The plurality of first chips are stacked so as to form a staircase only in the first direction, The plurality of second chips are stacked so as to form a staircase in the second direction and the first direction, The semiconductor device according to claim 6.

8. The first chip includes a plurality of first chips stacked so as to form a staircase in the first direction, The second chip includes a plurality of second chips stacked so as to form a staircase in the second direction, The third chip includes a plurality of third chips stacked so as to form a staircase in the third direction, The semiconductor device according to claim 2.

9. The plurality of first chips are stacked so as to form a staircase only in the first direction, The plurality of second chips are stacked so as to form a staircase in the second direction and the first direction, The plurality of third chips are stacked so as to form a staircase in the third direction and the second direction, The semiconductor device according to claim 8.

10. The first chip includes a plurality of first chips stacked so as to form a staircase in the first direction, The second chip includes a plurality of second chips stacked so as to form a staircase in the second direction, The third chip includes a plurality of third chips stacked so as to form a staircase in the third direction, The fourth chip includes a plurality of fourth chips stacked so as to form a staircase in the fourth direction, The semiconductor device according to claim 3.

11. The second direction is rotated 90 degrees in a predetermined rotational direction with respect to the first direction, The third direction is rotated 90 degrees in the predetermined rotational direction with respect to the second direction, The fourth direction is rotated 90 degrees in the predetermined rotational direction with respect to the third direction, The semiconductor device according to claim 3.

12. The semiconductor device according to claim 3, wherein the first chip, the second chip, the third chip, and the fourth chip are arranged in a spiral shape.

13. When the length of the short side of the second chip is represented by a [mm], When the length of the long side of the second chip is represented by b [mm], When the distance between the center line parallel to the second direction of the second chip and the outermost second chip pad among the second chip pads is represented by e [mm], e ≦ b - a / 2 - 0.3 holds for the semiconductor device according to claim 1.

14. When the length of the short side of the third chip is represented by a [mm], When the length of the long side of the third chip is represented by b [mm], When the distance between the center line parallel to the third direction of the third chip and the outermost third chip pad among the third chip pads is represented by e [mm], e ≦ b - a / 2 - 0.3 holds for the semiconductor device according to claim 2.

15. When the length of the short side of the fourth chip is represented by a [mm], When the length of the long side of the fourth chip is represented by b [mm], When the distance between the center line parallel to the fourth direction of the fourth chip and the outermost fourth chip pad among the fourth chip pads is represented by e [mm], e ≦ b - a / 2 - 0.3 holds for the semiconductor device according to claim 3.

16. The semiconductor device according to claim 5, further comprising a control chip having a portion provided under the fourth chip in a plan view.

17. The thickness of the lowermost first chip among the first chips is thicker than the thickness of the other first chips among the first chips for the semiconductor device according to claim 1.

18. A substrate, A plurality of first substrate pads provided on the substrate, A plurality of first chips provided on the substrate, arranged in the first direction with respect to the first substrate pads, stacked so as to form steps in the first direction, and electrically connected to the first substrate pads, A plurality of second substrate pads provided on the substrate, A plurality of second chips provided on the first chip, arranged in a second direction intersecting the first direction with respect to the second substrate pad, stacked so as to form a staircase in the second direction, and electrically connected to the second substrate pad; A semiconductor device comprising the same. **Claim 19** A plurality of third substrate pads provided on the substrate; A plurality of third chips provided on the second chip, arranged in a third direction intersecting the second direction with respect to the third substrate pad, stacked so as to form a staircase in the third direction, and electrically connected to the third substrate pad; The semiconductor device according to claim 18, further comprising the same. **Claim 20** A plurality of fourth substrate pads provided on the substrate; A plurality of fourth chips provided on the third chip, arranged in a fourth direction intersecting the third direction with respect to the fourth substrate pad, stacked so as to form a staircase in the fourth direction, and electrically connected to the fourth substrate pad; The semiconductor device according to claim 19, further comprising the same.

Images