Broadband interstage matching

Abstract

To provide a system and a device for impedance matching.SOLUTION: A system can include a first amplification stage configured to amplify an input signal into an intermediate signal and a second amplification stage configured to amplify the intermediate signal into an output signal. The system can further include a matching network configured to match an output impedance of the first amplification stage to an input impedance of the second amplification stage. A configuration of the first amplification stage can define an impedance transformation ratio that minimizes impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage can specify at least one attribute of one or more transistors in the first amplification stage and at least one operating condition of the first amplification stage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to systems and apparatuses for impedance matching. More specifically, a particular configuration is defined for the stage preceding the inter-stage matching network.

Background Art

[0002] Multiple-input multiple-output (Massive MIMO) is a type of wireless communication technology that can double the capacity of a wireless link by using multiple transmit and receive antennas to utilize multipath propagation. A MIMO system can transmit and receive multiple data signals simultaneously on the same wireless channel by taking advantage of the differences in signal propagation between different antennas (such as due to multipath propagation). Another technology is Massive MIMO. In this case, the base station is equipped with a very large number of antenna elements to further improve spectral efficiency and energy efficiency. In Massive MIMO technology, the number of terminals can be made much less than the number of antennas at the base station. In a Massive MIMO system, relatively simple beamforming strategies such as maximum ratio transmission, maximum ratio combining, or zero forcing can be used.

Summary of the Invention

[0003] In one embodiment, generally, a system for impedance matching is provided. The system can include a first amplification stage configured to amplify an input signal to an intermediate signal. Further, the system can include a second amplification stage configured to amplify the intermediate signal to an output signal. Further, the system can include a matching network configured to match the output impedance of the first amplification stage to the input impedance of the second amplification stage. The configuration of the first amplification stage can define an impedance transformation ratio that minimizes the impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage can specify at least one of at least one attribute of one or more transistors of the first amplification stage, and at least one of at least one operating condition of the first amplification stage.

[0004] In one embodiment, generally, a system for impedance matching is provided. The system can include a first amplification stage configured to amplify an input signal to an intermediate signal. The first amplification stage can include a first main amplifier and a first peaking amplifier. Further, the system can include a second amplification stage configured to amplify the intermediate signal to an output signal. The second amplification stage can include a second main amplifier and a second peaking amplifier. Further, the system can include a first matching network configured to match the output impedance of the first main amplifier to the input impedance of the second main amplifier. Further, the system can include a second matching network configured to match the output impedance of the first peaking amplifier to the input impedance of the second peaking amplifier. The configuration of the first amplification stage can define an impedance transformation ratio that minimizes the impedance mismatch between the first amplification stage and the second amplification stage. The configuration of the first amplification stage specifies at least one of at least one attribute of one or more transistors of the first amplification stage, and at least one of at least one operating condition of the first amplification stage.

[0005] In one embodiment, generally, a system for impedance matching is provided. The system can include an antenna. Further, the system can include a first amplification stage configured to amplify an input signal to an intermediate signal. Further, the system can include a second amplification stage configured to amplify the intermediate signal to an output signal and supply the output signal to the antenna. Further, the system can include a matching network configured to match the output impedance of the first amplification stage to the input impedance of the second amplification stage. The configuration of the first amplification stage can define an impedance transformation ratio that minimizes the impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage can specify at least one attribute of one or more transistors of the first amplification stage and at least one operating condition of the first amplification stage.

Brief Description of the Drawings

[0006] Hereinafter, with reference to the accompanying drawings, further features, structures, and operations of various embodiments of the present invention will be described in detail. In these drawings, like reference numerals indicate the same or functionally similar elements.

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Mode for Carrying Out the Invention

[0007] In the following description, in order to facilitate the understanding of various embodiments of the present application, a number of specific details including specific structures, components, materials, dimensions, processing steps, and technologies are described. However, those skilled in the art will understand that the various embodiments of the present application can be realized without these specific details. In some cases, the description of the details of known structures or processing steps is omitted in order not to obscure the present application.

[0008] FIG. 1 is a diagram showing an exemplary system capable of implementing broadband inter-stage matching in one embodiment. System 100 may be part of a transmission chain implemented by one or more semiconductor devices within a radio frequency (RF) transmitter. System 100 may include at least a first amplification stage 110 (herein “driver stage 110”), a second amplification stage (herein “output stage 120”), and a matching network 130. The driver stage 110 may include at least one amplifier 112, and the output stage 120 may include at least one amplifier 122. The matching network 130 may be an inter-stage matching network configured to form a matching impedance between the driver stage 110 and the output stage 120. The matching network 130 may include matching elements that may be reactive circuit components such as capacitors and inductors. System 100 may be implemented using one or more semiconductor devices.

[0009] Input signal 102 may be provided to driver stage 110. Amplifier 112 within driver stage 110 may amplify input signal 102 to produce an intermediate signal 103 that is sent to output stage 120 via matching network 130. Amplifier 122 within output stage 120 may further amplify intermediate signal 103 to generate output signal 104. In one embodiment, if output stage 120 is an amplification stage preceding a load such as antenna 106, output signal 104 may be provided to the load. In one embodiment, input signal 102, intermediate signal 103, and output signal 104 may be radio frequency (RF) signals, and antenna 106 may be capable of radiating radio waves to transmit output signal 104 to other devices.

[0010] In one aspect, driver stage 110 may be a source having a source resistance R S and output stage 120 may be a load having a load resistance R L . Matching network 130 may be capable of varying load resistance R L to match source resistance R S . When R S >R L , m = R S / R L Using a power matching coefficient greater than 1, R L can be boosted or increased to match R S . When R S <R L , m = R S / R L Using a power matching coefficient less than 1, R L can be decreased to match R S . As the power matching coefficient approaches a value of 1 (e.g., as the difference between R L and R S decreases), the quality factor (the "Q value") can be expressed as

[0011]

Equation

[0012] In a massive MIMO system, the final stage of the transmit chain in front of the antenna can pose challenges in terms of gain, efficiency, and bandwidth. In one aspect, the MIMO density can determine the power capabilities of the final stage. The typical average power level for each stage ranges from 5 watts (W) to 10 W, and each stage is driven with a signal having a peak-to-average ratio of 8.5 decibels (dB) to 9 dB. There is a desire to build a MIMO system that can simultaneously achieve high output, high efficiency, and large bandwidth while keeping the system cost low.

[0013] In one aspect, some massive MIMO systems use conventional inter-stage network matching that cascades multiple gain blocks in the transmit chain to achieve a high line-up gain and match the high impedance of the input device to the low impedance of the output device. However, due to the large conversion ratio between stages, the inter-stage loss increases, the efficiency of subsequent stages decreases, and it may affect the overall transmitter line-up. Also, the bandwidth may become narrow and the number of matching elements may increase. An increase in the number of matching elements may lead to an increase in the occupied area (such as the on-chip area), the overall cost, the conduction loss, and the component sensitivity that affects the product yield.

[0014] As will be described in more detail below, system 100 can improve the line-up efficiency, bandwidth, compact footprint, and overall yield of the higher transmission chain by implementing driver stage 110 using a specific configuration 140. In one embodiment, configuration 140 can specify one or more specific operating conditions and settings of driver stage 110. For example, configuration 140 can specify one or more attributes of one or more devices or transistors within driver stage 110 and can specify one or more operating conditions of driver stage 110. The one or more attributes can include, but are not limited to, the type, size, technology, material, and / or substrate of one or more devices (e.g., transistors) used in the implementation of driver stage 110, or other attributes. Also, configuration 140 can specify the type of device, such as a cascode device, a common-source device, a Darlington configuration, or other types of devices that can perform amplification in the amplification stages described herein. Operating conditions can include, but are not limited to, the drain power supply voltage (VDD) being applied to driver stage 110, or other operating conditions. In one embodiment, the operating conditions set in configuration 140 can depend on one or more attributes. Also, in one embodiment, the topology of matching network 130 can be selected based on configuration 140. The combination of configuration 140 and the selected topology of matching network 130 can optimize and enhance the performance of the transmission chain using system 100. Further, the configuration 140 of driver stage 110 can bring the power matching coefficient (e.g., a ratio depending on R S / R L ) closer to a value of 1, thereby reducing the Q value, bringing the impedance transformation ratio closer to 1, and improving the bandwidth. The impedance transformation ratio based on configuration 140 can minimize the impedance mismatch between driver stage 110 and output stage 120. Also, the configuration 140 of driver stage 110 allows matching network 130 to be implemented using relatively simple components and can maintain the size of matching network 130 at a relatively compact size.

[0015] FIG. 2 is a diagram showing another exemplary system that can implement broadband inter-stage matching in one embodiment. The description of FIG. 2 can refer to the components shown in FIG. 1. In the embodiment shown in FIG. 2, the transmission chain including the system 100 of FIG. 1 can include an additional driver stage or amplification stage before the driver stage 110 (e.g., the input signal 102 can be provided by another driver or amplification stage within the transmission chain). To perform impedance matching, additional matching networks can be placed between different driver stages. In the embodiment shown in FIG. 2, another driver stage 202 precedes the driver stage 110, a matching network 201 precedes the driver stage 202, and a matching network 204 is placed between the driver stages 202 and 110 to perform impedance matching. Further, in the embodiment shown in FIG. 2, a load such as another output stage or antenna 106 follows the output stage 120 (and precedes the antenna 106 of FIG. 1), and a matching network 206 is placed between the output stage 120 and the next output stage or load to perform impedance matching. The driver stage 202, the driver stage 110, and the output stage 120 can be optimized based on various configurations such as configuration 140. In the embodiment shown in FIG. 2, the configuration 140 can specify different attributes and / or operating conditions for different stages, such as specifying power supply voltages V_supply1, V_supply2, and V_supply3 for the driver stage 202, the driver stage 110, and the output stage 120, respectively.

[0016] FIG. 3 is a diagram showing another exemplary system that can implement broadband inter-stage matching in one embodiment. The description of FIG. 3 can refer to the components shown in FIGS. 1 and 2. In the embodiment shown in FIG. 3, the driver stage 110 and the output stage 120 of the system 100 can be implemented by a Doherty amplifier including a main path and a peaking path. The driver stage 110 can include at least amplifier 312 and amplifier 314. Here, amplifier 312 can be the main amplifier in the main path, and amplifier 314 can be the peaking amplifier in the peaking path. The matching network 330 can be an inter-stage matching network configured to form a matching impedance between amplifier 312 in the driver stage 310 and amplifier 322 in the output stage 320. The output stage 120 can include at least amplifier 322 and amplifier 324. Here, amplifier 322 can be the main amplifier in the main path, and amplifier 324 can be the peaking amplifier in the peaking path. The matching network 332 can be an inter-stage matching network configured to form a matching impedance between amplifier 314 in the driver stage 310 and amplifier 324 in the output stage 320. The matching networks 330, 332 can include reactive circuit components such as capacitors and inductors. The description of the matching network 130 described herein is also applicable to the matching networks 330, 332.

[0017] The input signal 102 can be split (e.g., by a quadrature coupler) and distributed to the amplifiers 312, 314 in the driver stage 310. The amplifier 312 can amplify the input signal 102 to an intermediate signal 303 that can be passed through the matching network 330 to the amplifier 322 in the output stage 320. The amplifier 322 in the output stage 320 can further amplify the intermediate signal 303 to generate the output signal 307. The amplifier 314 can amplify the input signal 102 to an intermediate signal 305 that can be passed through the matching network 332 to the amplifier 324 in the output stage 320. The amplifier 324 in the output stage 320 can further amplify the intermediate signal 305 to generate the output signal 309. In a Doherty amplifier architecture, the amplifier 322 in the main path and the amplifier 324 in the peaking path can be biased differently. Thus, the signals 307, 309 may be out of phase by 90 degrees. The signals 307, 309 can be combined, for example, using a quarter-wave transmission line, and their phases can be added together. The combination of the signals 307, 309 can be output as the output signal 304. The output signal 304 can be provided to a load such as the antenna 306. In one embodiment, the input signal 302, the intermediate signals 303, 307, and the output signals 304, 307, 309 can be radio frequency (RF) signals, and the antenna 306 can radiate radio waves to transmit the output signal 304 to other devices.

[0018] In one embodiment, the configuration 140 can specify one or more of the size, technology, and / or substrate of the devices (e.g., transistors) used to implement the amplifiers 312, 314 in the driver stage 110, and the drain supply voltage applied to the amplifiers 312, 314 in the driver stage 110. The configuration 140 can specify the same or different sizes, technologies, substrates, and / or drain supply voltages for the amplifiers 312, 314.

[0019] FIG. 4 is a diagram showing additional details of an implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 4 can refer to the components shown in FIGS. 1-3. In the embodiment shown in FIG. 4, the driver stage 110 can include one or more devices such as device 402 that can implement the amplifier 112 of FIG. 1, the amplifier 312 of FIG. 2, and / or the amplifier 314 of FIG. 2. The output stage 120 can include one or more devices such as device 404 that can implement the amplifier 122 of FIG. 1, the amplifier 322 of FIG. 2, and / or the amplifier 324 of FIG. 2. In the example shown in FIG. 4, in order for the input impedance Zin of the output stage 120 to match the output impedance of the driver stage 110, the configuration 140 can specify various settings and parameters of the driver stage 110 such that the output impedance of the driver stage 110 becomes equivalent to the optimum impedance Zopt. Here, Zopt is substantially the same as Zin.

[0020] In one embodiment, to achieve Zopt at the output of the driver stage 110, the configuration 140 can specify settings and parameters such that the resistance across device 402 becomes equivalent to the optimum resistance Ropt. Here, Ropt is the resistance corresponding to Zopt (e.g., Ropt is the real part of Zopt). The optimum resistance Ropt can be expressed as follows:

[0021]

Equation

[0022] In one embodiment, the value of VDD specified by configuration 140 can depend on the size and / or technology, or materials used to implement device 402. The size and / or technology of device 402 can define the range of values for VDD. In one embodiment, the technology of device 402 in driver stage 110 can have a lower breakdown voltage than the technology of device 404 in output stage 120. In another embodiment, the technologies of device 402 and device 404 in driver stage 110 can be the same, but device 402 can have a smaller size and thus can have a lower breakdown voltage than device 404. The lower the breakdown voltage of driver stage 110, the lower the on-resistance (RDSon) of device 402 can be, and the losses can also be reduced. Based on the lower breakdown voltage of driver stage 110, configuration 140 can specify operating conditions such as a VDD for driver stage 110 that is lower than the VDD of output stage 120.

[0023] In one aspect, the voltage standing wave ratio (VSWR) of system 100 can be an indicator of how efficiently a signal is transmitted from driver stage 110 to output stage 120. The VSWR can vary according to the impedance transformation ratio Zopt / Zin. In an ideal scenario, the VSWR is equal to 1. This indicates that 100% of the energy is transmitted. The VSWR of system 100 shown in FIG. 4 can be expressed as follows:

[0024]

Equation

[0025]

Equation

[0026] FIG. 5 is a diagram showing an implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 5 can refer to the components shown in FIGS. 1 to 4. In the example shown in FIG. 5, the initial operating condition 502 (or initial state 502) of the driver stage 110 can include the VDD value of VDD1. When the driver stage 110 operates based on VDD1 and the Rg of the output stage 120 is 0.75 ohm, Ropt can be about 57 ohms and the Q value can be 8.66. For example, the configuration 140 can specify a new value of VDD, such as VDD2. When the driver stage 110 operates based on VDD2, the Rg of the output stage 120 remains 0.75 ohm, and the matching network 130 is not changed, Ropt can be about 2 ohms. The optimum impedance Zopt becomes (2 - j0.2) ohms, and the Q value can be reduced to about 1.29. Therefore, the configuration 140 can specify new operating conditions, such as a new value of VDD of the driver stage 110, to reduce the Q value and improve the overall performance of the system 100.

[0027] FIG. 6 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 6 can refer to the components shown in FIGS. 1 to 5. In the example shown in FIG. 6, the device 402 can be implemented by a technology operable at a relatively low breakdown voltage, such as a gallium nitride (GaN) device, a gallium arsenide (GaAs) device, or a silicon (Si) device. The device 404 can be implemented by a technology operable at a relatively high breakdown voltage, such as a GaN device or a silicon carbide (SiC) device. Corresponding to the device 402 being a GaN device, a GaAs device, or a silicon device, the configuration 140 can specify a value of VDD of the driver stage 110 that is lower than VDD used for the operation of the output stage 120. In the embodiment shown in FIG. 6, the output stage 120 can operate under a VDD of 50 volts (V), and the configuration 140 can specify the driver stage 110 to operate under a lower VDD, such as 5V. Therefore, the configuration 140 can specify operating conditions such as the value of VDD of the driver stage 110 according to the technology (e.g., GaN, GaAs, Si, or other technologies having a relatively low breakdown voltage) used for the implementation of the device 402 in the driver stage 110. In one embodiment, the lower the VDD of the driver stage 110, the more the matching network 130 can match the reduced output impedance of the driver stage 110 using relatively simple components. Thereby, the complexity and size of the matching network 130 can be reduced.

[0028] FIG. 7 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 7 can refer to the components shown in FIGS. 1 to 6. In the example shown in FIG. 7, device 402 can be one of a GaN device, a GaAs device, and a Si device, device 404 can be one of a GaN device and a SiC device, and device 402 can be made smaller than device 404. Since device 402 is smaller than device 404, device 402 can have a lower breakdown voltage than device 404, and the VDD used to operate device 402 is lower than the VDD for operating device 404. Corresponding to device 402 being smaller than device 404, configuration 140 can specify a value of VDD for driver stage 110 that is lower than the VDD used to operate output stage 120. In the embodiment shown in FIG. 7, output stage 120 can operate under a VDD of 50 volts (V), and configuration 140 can specify driver stage 110 to operate under a lower VDD, such as 5V. Therefore, configuration 140 can specify operating conditions, such as the value of VDD for driver stage 110, according to the size of device 402 in driver stage 110. In one embodiment, by lowering the VDD of driver stage 110, matching network 130 can match the reduced output impedance of driver stage 110 using relatively simple components. Thereby, the complexity and size of matching network 130 can be reduced.

[0029] FIG. 8 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 8 can refer to the components shown in FIGS. 1 to 7. In the example shown in FIG. 8, the driver stage 110 and the output stage 120 can implement a Doherty amplifier (similar to FIG. 3). In one embodiment, corresponding to the amplifier 312 being implemented by a GaN device, a GaAs device, or a silicon device, the configuration 140 can specify a value of VDD, such as VDD1A, for the amplifier 312. VDD1A can be lower than the VDD (e.g., VDD2) used for the operation of the amplifiers 322 and 324 in the output stage 120. In response to the amplifier 314 being implemented by a GaN device or a silicon device, the configuration 140 can specify a value of VDD, such as VDD1B, for the amplifier 314. VDD1B can be lower than the VDD (e.g., VDD2) used for the operation of the amplifiers 322 and 324 in the output stage 120. In one embodiment, VDD1A can be equivalent to VDD1B. In another embodiment, VDD1A can be different from VDD1B.

[0030] In one embodiment, corresponding to the amplifier 312 being implemented by a device smaller than the device implementing the amplifier 322, the configuration 140 can specify a value of VDD, such as VDD1A, for the amplifier 312, which is lower than the VDD2 used to operate the amplifier 322. In response to the amplifier 314 being implemented by a device smaller than the device implementing the amplifier 324, the configuration 140 can specify a value of VDD, such as VDD1B, for the amplifier 314, which is lower than the VDD2 used to operate the amplifier 324. In one embodiment, VDD1A can be equivalent to VDD1B. In another embodiment, VDD1A can be different from VDD1B. The configuration 140 can specify different operating conditions for different amplifiers or drivers in the Doherty amplifier to perform optimal impedance matching without increasing the complexity of the matching networks 330 and 332.

[0031] FIG. 9 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 9 can refer to the components shown in FIGS. 1 to 8. In the example shown in FIG. 9, the configuration 140 can specify operating conditions such as the output power from the device 402 of the driver stage 110 in order to control Zopt and to control the VSWR of the system 100 to approach 1. In the embodiment shown in FIG. 9, by reducing the output power from the device 402, the range of impedance values of Zopt that can be used for matching the output impedance of the driver stage 110 can be expanded. For example, when the output power decreases from 40.5 dBm to 40.25 dBm and then to 40.0 dBm, the range of Zopt that can be used for matching the output impedance of the driver stage 110 increases. By increasing the available range of Zopt, the number of different matching network topologies that can be used for implementing the matching network 130 can be increased.

[0032] FIG. 10 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 10 can refer to the components shown in FIGS. 1 to 9. In the example shown in FIG. 10, in addition to the configuration 140 that specifies various attributes and operating conditions of the driver stage 110, the operating conditions of the device 404 of the output stage 120 can also be configured to control Zin and to control the VSWR of the system 100 to approach 1. In the embodiment shown in FIG. 10, by reducing the gain from the device 404, the range of impedance values of Zin that can be used for matching the input impedance of the output stage 120 can be expanded. For example, when the gain decreases from 16 dB to 15.75 dB and then to 15.50 dB, the range of Zin that can be used for matching the input impedance of the output stage 120 increases. By increasing the available range of Zin, the number of different matching network topologies that can be used for implementing the matching network 130 can be increased.

[0033] FIG. 11 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 11 can refer to the components shown in FIGS. 1 to 10. In the embodiment shown in FIG. 11, the device manifolds of the driver stage 110 and / or the output stage 120 can be adjusted according to the configuration 140. In the embodiment shown in FIG. 11, each of the driver stage 110 and the output stage 120 can include more amplifiers than an amplifier, and the output stage 120 can include more amplifiers than the driver stage 110. For example, when the configuration 140 specifies a technology using a lower VDD, a smaller device size, and / or a lower VDD, the number of amplifiers in the driver stage 110 can be reduced to a number less than the number of amplifiers in the output stage 120. By reducing the number of devices in the driver stage 110, the number of components of the matching network 130 used for impedance matching of the output impedance of the driver stage 110 can be reduced.

[0034] By operating the device manifolds of the driver stage 110 and / or the output stage 120 based on the configuration 140, the impedance transformation ratio Zopt / Zin can be made closer to 1 (for example, reducing the difference between Zopt and Zin), and the decrease in the impedance transformation ratio leads to a decrease in the Q value. For example, when the driver stage 110 is divided into two amplifiers as shown in FIG. 11, the output impedance of each amplifier of the driver stage 110 is reduced to half of the total output impedance Zout of the driver stage 110. Instead of using large or complex components to match Zout, the matching network 130 can use two sets of relatively small and less complex components having a Zopt that matches Zout / 2. Also, even if the driver stage 110 is implemented using a plurality of amplifiers, it does not affect the VDD specified by the configuration 140, and the same VDD can be applied to the plurality of amplifiers.

[0035] Also, in the example shown in FIG. 11, the output stage 120 is divided into eight amplifiers. As a result, the matching network 130 includes two sets of 1:4 matching networks (e.g., four outputs for one input). The input impedance of each amplifier in the output stage 120 is reduced to 1 / 8 of the total input impedance Zin of the output stage 120. Instead of using large or complex components to match Zin, the matching network 130 can use two sets of relatively small and uncomplicated components having an impedance that matches Zin / 8.

[0036] FIG. 12 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 12 can refer to the components shown in FIGS. 1 to 11. In the embodiment shown in FIG. 12, the driver stage 110 can be implemented by a cascode device 1202. The cascode device 1202 can include two transistors or devices connected in a cascode arrangement. Exemplary technologies or materials for the cascode devices described herein can include GaN on SiC, GaN on Si, silicon-on-insulator (SOI), or other technologies and materials for forming different types of cascode devices. Configuration 140 can specify a relatively low VDD corresponding to the driver stage 110 implemented using the cascode device 1202. For example, the VDD specified by the configuration 140 can be supplied to the cascode device 1202, and each device in the cascode device 1202 can be operated using VDD / 2. By reducing the VDD of each device to VDD / 2 or the like, the effective resistance of each device in the cascode device 1202 can be reduced. Since one of the two devices in the cascode device 1202 is connected to the matching network 130, the matching network 130 can use relatively few components having Zopt that can be matched to VDD / 2.

[0037] In one embodiment, configuration 140 can specify a fixed and non-adjustable VDD. In response to configuration 140 specifying a fixed VDD, configuration 140 can further specify a configuration of an apparatus that can match Zopt to the output impedance of driver stage 110 so that the impedance conversion ratio Zopt / Zin can be made closer to 1 (for example, reducing the difference between Zopt and Zin). For example, if configuration 140 specifies a fixed VDD of 10V and can make Zopt / Zin approximately 1 with a VDD value of 5V, configuration 140 can further specify to use a configuration of an apparatus that can divide the fixed VDD in half, such as the cascode apparatus 1202 of FIG. 12.

[0038] FIG. 13 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 13 can refer to the components shown in FIGS. 1 to 12. In the embodiment shown in FIG. 13, driver stage 110 can be implemented by a multi-transistor structure 1302 having a relatively low output impedance, such as a Darlington structure. The Darlington structure can be a circuit including two transistors or devices (for example, bipolar transistors) in which the emitter of one transistor is connected to the base of the other transistor so that the current amplified by the first transistor is further amplified by the second transistor, as shown by the multi-transistor structure 1302. The Darlington structure can have a relatively high input impedance and a relatively low output impedance. Therefore, by using the Darlington structure to implement the multi-transistor structure 1302, matching network 130 can use relatively few components having a Zopt that can match the reduced output impedance of the multi-transistor structure 1302.

[0039] In one embodiment, configuration 140 can specify a fixed and non-adjustable VDD. In response to configuration 140 specifying a fixed VDD, configuration 140 can further specify a configuration of a device that can operate using a VDD lower than the fixed VDD so as to bring the impedance conversion ratio Zopt / Zin closer to 1 (for example, reduce the difference between Zopt and Zin). For example, if configuration 140 specifies a fixed VDD of 10V, configuration 140 can further specify to use a device configuration that can operate the driver stage 110 using a VDD lower than 10V, such as the multi-transistor structure 1302 of FIG. 13.

[0040] FIG. 14 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 14 can refer to the components shown in FIGS. 1 to 13. In the embodiment shown in FIG. 14, devices 402 and 404 can be interconnected with the matching network 130 using wire bonds 1402 and 1404, respectively. The wire shapes of wire bonds 1402 and 1404 can affect the total inductance of the driver stage 110 and the output stage 120, and thus can also affect Zopt and Zin. Configuration 140 can specify various wire shapes, such as the thickness, diameter, number of wires, width, radius, and total number of parallel wires of wire bonds 1402 and 1404. The specification of the wire bond shape by configuration 140 can control Zopt and Zin so as to bring the impedance conversion ratio Zopt / Zin closer to 1 (for example, reduce the difference between Zopt and Zin). By specifying the wire bond shape, Zopt and / or Zin can be adjusted without changing the matching network 130. Therefore, a matching network 130 with relatively simple components can be used, and the wire bond shape can be adjusted based on the matching network used.

[0041] FIG. 15 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 15 can refer to the components shown in FIGS. 1 to 14. In the embodiment shown in FIG. 15, an implementation example of the matching network 130 is shown. The matching network 130 in FIG. 15 is a single-section matching network including various matching elements such as capacitors C1, C2, C3, C_DC and inductors (e.g., wires or transmission lines) L1, L2, L3. In one embodiment, the matching network 130 can be selected based on the specifications of configuration 140. In one embodiment, the matching elements C1 and L1 can be reused as part of the first bias network on the input side of the matching network 130. By using the matching elements C1 and L1 as part of the first bias network, the matching elements C1 and L2 can also be reused as part of the second bias network on the output side of the matching network 130. Thereby, there is no need to separately construct the second bias network. Therefore, the space on the circuit board can be saved.

[0042] FIG. 16 is a diagram showing another implementation example of broadband inter-stage matching in one embodiment. The description of FIG. 16 can refer to the components shown in FIGS. 1 to 15. In the embodiment shown in FIG. 16, an implementation example of the matching network 130 is shown. The matching network 130 in FIG. 16 is a multi-section matching network including various matching elements such as capacitors C1, C2, C3, C4, C5, C6, C_DC and inductors (e.g., wires or transmission lines) L1, L2, L3, L4. In one embodiment, when the bandwidth of the system 100 is limited to a fixed value, a multi-section matching network as shown in the embodiment of FIG. 16 can be used for impedance matching between the driver stage 110 and the output stage 120. Similar to the embodiment shown in FIG. 15, matching elements such as C1, L1 and C2, L2 can be reused as bias networks. Note that although a single section as shown in the embodiment of FIG. 15 has less insertion loss compared to the multi-section matching network in FIG. 16, it should be noted that the multi-section matching network in FIG. 16 can be used in implementations where the bandwidth may be limited.

[0043] The terms used in this specification are used only for the purpose of describing particular embodiments and are not intended to limit the present invention. The singular terms used in this specification are also intended to include the plural unless specifically stated otherwise. It should also be noted that the term "comprising" used in this specification defines the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0044] All means or steps and corresponding structures, materials, operations, and equivalents of functional elements recited in the appended claims are intended to include any structure, material, or operation for realizing functions in combination with other specifically described elements. The description of the disclosed embodiments of the present invention is provided for purposes of illustration and explanation, but is not intended to be exhaustive or limited to the disclosed forms. It will be apparent to those skilled in the art that many modifications and variations can be made without departing from the scope and spirit of the present invention. The above-described embodiments have been selected and described in order to best explain the principles and practical applications of the present invention and to enable those skilled in the art to understand the present invention with various modifications suitable for the particular uses under consideration.

Claims

1. a first amplification stage configured to amplify an input signal to an intermediate signal; a second amplification stage configured to amplify the intermediate signal into an output signal; a matching network configured to match an output impedance of the first amplifier stage to an input impedance of the second amplifier stage; Including, a configuration of the first amplifier stage defines an impedance transformation ratio that minimizes an impedance mismatch between the output impedance of the first amplifier stage and the input impedance of the second amplifier stage; The configuration of the first amplification stage comprises: at least one attribute of one or more transistors in the first amplification stage; and At least one operating condition of the first amplifier stage Specify at least one of system.

2. The at least one attribute is: the type of the one or more transistors in the first amplification stage; a material of the one or more transistors in the first amplification stage; and The size of one or more transistors and the at least one operating condition includes at least a power supply voltage used to operate the first amplifier stage; The system of claim 1 .

3. The system of claim 2 , wherein the power supply voltage depends on the material of the one or more transistors in the first amplification stage.

4. 2. The system of claim 1, wherein the at least one operating condition of the first amplification stage includes a first power supply voltage used to operate the first amplification stage, the first power supply voltage being less than a second power supply voltage used to operate the second amplification stage.

5. 2. The system of claim 1 , wherein the at least one attribute includes a size of the one or more transistors in the first amplification stage, the size of the one or more transistors in the first amplification stage being smaller than a size of one or more transistors in the second amplification stage.

6. the at least one attribute includes a material of the one or more transistors in the first amplification stage, the material being one of gallium nitride (GaN) on silicon carbide (SiC), GaN on silicon (Si), gallium arsenide (GaAs), Si on insulator (SOI), and silicon (Si); the second amplification stage includes one or more transistors formed of GaN on SiC and GaN on Si; The system of claim 1 .

7. The system of claim 1 , wherein the first and second amplification stages are Doherty amplifiers.

8. 2. The system of claim 1, wherein the one or more transistors in the first amplification stage include at least one cascode device.

9. 2. The system of claim 1, wherein the one or more transistors in the first amplification stage include at least one Darlington structure.

10. The system of claim 1 , wherein the configuration specifies the at least one attribute and the at least one operating condition to cause an impedance transformation ratio to approach a value of one.

11. a first amplification stage configured to amplify an input signal to an intermediate signal, the first amplification stage including a first main amplifier and a first peaking amplifier; a second amplification stage configured to amplify the intermediate signal to an output signal, the second amplification stage including a second main amplifier and a second peaking amplifier; a first matching network configured to match an output impedance of the first main amplifier to an input impedance of the second main amplifier; a second matching network configured to match an output impedance of the first peaking amplifier to an input impedance of the second peaking amplifier; Including, a configuration of the first amplifier stage defines an impedance transformation ratio that minimizes impedance mismatch between the first amplifier stage and the second amplifier stage; The configuration of the first amplification stage comprises: at least one attribute of one or more transistors in the first amplification stage; and At least one operating condition of the first amplifier stage Specify at least one of system.

12. The at least one attribute is: the type of the one or more transistors in the first amplification stage; a material of the one or more transistors in the first amplification stage; and The size of the one or more transistors and the at least one operating condition includes at least a power supply voltage used to operate the first amplifier stage; The system of claim 11.

13. The system of claim 12 , wherein the power supply voltage depends on the material of the one or more transistors in the first amplification stage.

14. 12. The system of claim 11, wherein the at least one operating condition of the first amplification stage includes a first power supply voltage used to operate the first main amplifier and the first peaking amplifier, the first power supply voltage being less than a second power supply voltage used to operate the second main amplifier and the second peaking amplifier.

15. 12. The system of claim 11, wherein the at least one attribute includes a size of the one or more transistors in the first amplification stage, the size of the one or more transistors in the first amplification stage being smaller than a size of one or more transistors in the second amplification stage.

16. the at least one attribute includes a material of the one or more transistors in the first amplification stage, the material being one of gallium nitride (GaN) on silicon carbide (SiC), GaN on silicon (Si), gallium arsenide (GaAs), Si on insulator (SOI), and silicon (Si); the second amplification stage includes one or more transistors formed of GaN on SiC and GaN on Si; The system of claim 11.

17. The system of claim 11 , wherein the configuration specifies the at least one attribute and the at least one operating condition to cause an impedance transformation ratio to approach a value of unity.

18. The antenna, a first amplification stage configured to amplify an input signal to an intermediate signal; a second amplification stage configured to amplify the intermediate signal into an output signal and provide the output signal to the antenna; a matching network configured to match an output impedance of the first amplifier stage to an input impedance of the second amplifier stage; Including, a configuration of the first amplifier stage defines an impedance transformation ratio that minimizes an impedance mismatch between the output impedance of the first amplifier stage and the input impedance of the second amplifier stage; The configuration is at least one attribute of one or more transistors in the first amplification stage; and At least one operating condition of the first amplifier stage and the second amplifier stage Specify at least one of system.

19. The at least one attribute is: the type of the one or more transistors in the first amplification stage; a material of the one or more transistors in the first amplification stage; and The size of the one or more transistors and The at least one operating condition is: a power supply voltage used to operate the first amplifier stage; the output power from the first amplifier stage; and The gain of the second amplifier stage At least one of:

20. The system of claim 18.

20. 20. The system of claim 18, wherein the at least one operating condition of the first amplification stage includes a first power supply voltage used to operate the first amplification stage, the first power supply voltage being less than a second power supply voltage used to operate the second amplification stage.

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