Clock synchronous type dynamic semiconductor storage device

Abstract

To provide an optimum operation method of a memory cell, which stores data according to an amount of electricity accumulated on a floating body and satisfies current SDRAM operation specifications.SOLUTION: A clock synchronous type dynamic semiconductor storage device that uses a memory cell storing two logic values according to an amount of electricity accumulated on a floating body performs writing two logic values into the memory cell, which is performed not simultaneously but separately, triggered by different commands or at different times. The writing of one of the two logic values into the memory cell is performed, triggered by a command to release a memory cell selection state or at timing to perform the release.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a clock-synchronized dynamic semiconductor memory device (hereinafter referred to as SDRAM) that complies with the specifications of a double data rate (hereinafter referred to as DDR) clock-synchronized dynamic semiconductor memory device and a low-power double data rate (hereinafter referred to as LPDDR) clock-synchronized dynamic semiconductor memory device, accumulates charges in a floating body, and uses a memory cell that distinguishes stored data by their electrical amounts.

Background Art

[0002] A dynamic semiconductor memory device (hereinafter referred to as DRAM) is widely used as a memory device, and in recent years, it has become clock-synchronized in order to speed up data input / output.

[0003] The memory cell of a current DRAM is composed of one MOS field-effect transistor (hereinafter referred to as MOS transistor) and one capacitor. However, due to higher density and larger capacity, the occupied area of the memory cell has been decreasing. On the other hand, in order to satisfy the function as a memory cell, even though the occupied area is decreasing, it is necessary to keep the capacitance of the capacitor constant or make the rate of decrease in the capacitance of the capacitor smaller than the rate of decrease in the occupied area of the memory cell. Therefore, as the structure of the memory cell, it forms a three-dimensional structure, that is, the capacitor is arranged in a cylindrical structure above the MOS transistor on the silicon substrate surface with respect to the silicon substrate, and the aspect ratio of the capacitor is increasing. That is, the length of the cylinder of the cylindrical capacitor is becoming larger compared to the diameter, and the diameter of the cylinder is becoming smaller. Since the diameter of the cylinder of the capacitor is determined by the thicknesses of the electrodes of the two capacitors and the thickness of the insulating film between the electrodes, if one tries to reduce the diameter of the cylinder of the capacitor, the difficulty of manufacturing technologies such as capacitor processing and insulating film formation increases, and it is approaching a physical limit.

[0004] Therefore, a proposal has been made to increase the storage capacity by arranging a memory cell composed of one MOS transistor and one capacitor in parallel with the semiconductor substrate and further stacking them (Patent Documents 1 and 2). Although the manufacturing process is reduced compared to stacking memory cells with the current cylindrical capacitor structure that extends perpendicular to the semiconductor substrate, it is obvious that the manufacturing process becomes more complex.

[0005] For the above reasons, memory cells composed of one MOS transistor without a capacitor, which is a major factor in complicating the manufacturing process, have been continuously proposed (see Patent Documents 3 and 4 and Non-Patent Documents 1 to 5). In a memory cell composed of one MOS transistor and one capacitor, logical storage data "1" or "0" is stored by the charge stored in the capacitor. In contrast, in a memory cell composed of one MOS transistor, logical storage data "1" or "0" is stored by the charge stored in the floating body. For example, as shown in FIG. 90, by flowing a current between the source and drain of an N-channel MOS transistor, electron-hole pairs are generated in the channel by the impact ionization phenomenon, and among them, the hole pairs are retained in the floating body for data storage to write the logical storage data "1". As shown in FIG. 92(A), the hole pairs are removed from the floating body to write the logical storage data "0". As shown in the band diagram of FIG. 92(B), the PN junction formed by the floating body and the source or drain is forward-biased to remove the hole pairs from the floating body. In FIGS. 92(A) and 92(B), both PN junctions formed by the floating body and the source or drain are forward-biased, but only one of them may be sufficient. Incidentally, in the case of writing "0", the state may be such that an excessive number of electron-hole pairs are injected compared to the thermally stable state.

[0006] The potential of the floating body changes according to the amount of electricity of the floating body. That is, since the threshold value changes due to the change in the bias state of the back gate of the MOS transistor, as shown in FIG. 89, when an N-channel MOS transistor is used, there is a difference in the threshold value between the case of the "1" write state in which holes are accumulated in the floating body and the case of the "0" write state in which the hole group is removed from the floating body. Therefore, when the gate potential is constant, the current flowing from the drain to the source is different between the "1" write state and the "0" write state, and the data written in the memory cell is discriminated by the difference in the amount of current.

[0007] A writing method different from the impact ionization phenomenon has been proposed. In Non-Patent Document 5, a method is proposed in which the logical memory data "1" is written not by the impact ionization phenomenon but by the BTBT (Band to Band Tunneling) phenomenon (which may be called the GIDL (Gate Induced Drain Leakage) phenomenon), and a hole group is accumulated in a floating body for data storage. That is, as shown in FIG. 91(A), when an N-channel MOS transistor is used, a bias condition is set such that the majority carriers of the floating body are accumulated on the gate side, and a voltage is applied to the drain such that the PN junction formed by the drain and the floating body is reverse-biased. Then, as shown in FIGS. 91(B) and 91(C), due to the high electric field between the drain and the floating body, electrons in the valence band of the floating body flow into the conduction band of the drain, and a hole group is accumulated in the floating body. Also in Non-Patent Document 5, for the logical memory data "0" write, the PN junction formed by the floating body and the drain is set to a forward bias to discharge the hole group from the floating body.

[0008] Under the bias conditions shown in TABLE III of Non-Patent Document 5, not only the drain voltage applied to the bit line but also the gate voltage applied to the word line are different between the "0" write and the "1" write. That is, in the case of a "0" write, the PN junction formed by the floating body and the drain is in a forward bias state, while in the case of a "1" write, the PN junction is in a reverse bias state. An attempt is made to control the gate potential by utilizing the capacitive coupling between the floating body and the gate, and due to the breakdown voltage of the transistors in the peripheral circuit that drives the memory cell, the gate potential has to be changed. When an N-channel MOS transistor is used, the gate potential will be at a higher level for a "0" write than for a "1" write, and at a lower level for a "1" write than for a "0" write.

[0009] Generally, in a semiconductor memory device, in order to achieve high integration and high density, as shown in FIGS. 2 and 30, a plurality of memory cells are arranged on a plane (memory cell array), a drive circuit is provided at the end arranged on the plane, and a word line drive circuit that is selected and driven by a so-called low address and a memory cell at the intersection of bit lines that are selected and driven by a column address are selected for reading or writing. In current large-capacity semiconductor memory devices, reading and writing are performed simultaneously on a plurality of memory cells. Since the difference in time required for reading and writing between the CPU (Central Processing Unit) and the semiconductor memory device has been significantly widened, the number of memory cells for which reading and writing are performed simultaneously tends to increase. Since it is common to reflect data on the bit lines, a plurality of bit lines equal in number to the number of cells to be operated during operation are selected, while only one word line is selected. Also, generally, the data of cells that are written simultaneously do not all match. Therefore, the fact that both the voltages of the bit line and the word line differ according to the write data means that "0" writing and "1" writing cannot be performed simultaneously and need to be performed at different timings. Writing to the memory cells of a general semiconductor memory device is performed on a plurality of memory cells, and data of "0" and "1" are mixed. Therefore, when writing to a plurality of memory cells with respect to the same word line, after setting the word line potential for "0" writing and performing "0" writing, it is necessary to set the word line potential for "1" writing.

[0010] If only one memory cell can be selected for one memory cell array, the above problem will not occur. However, at the same time, it is necessary to operate the memory cell array by the number of memory cells to be written simultaneously, which leads to an increase in power consumption. Furthermore, bit line drive circuits and word line drive circuits need to be arranged at the ends of the memory cell array and the memory cell array by the number of memory cells to be written simultaneously, which leads to an increase in chip area and higher cost.

[0011] In the memory cells shown in Non-Patent Document 1 and Patent Document 3, the voltage of the word line is the same in the case of writing "1" and the case of writing "0", but the purge operation is actually removing the hole group from the floating body. The subsequent "0" writing only prevents holes from being accumulated in the floating body. Therefore, an operation called purge is required before the write operation, which is not defined as the specification of SDRAM using a memory cell composed of one MOS transistor and one capacitor currently.

[0012] In Non-Patent Document 4, the same word line potential is set for "1" writing and "0" writing. In "0" writing, the PN junction is forward-biased by the potential of the floating body and the bit line to discharge the hole group from the floating body to the bit line. When the potential of the word line is increased, the potential of the floating body where the hole group is accumulated increases due to capacitive coupling. However, if a channel is formed, the potential of the floating body does not increase following the potential of the word line. Therefore, increasing the word line potential according to the "1" writing condition only increases the current from the source line to the bit line, leading to an increase in power consumption and imposing an excessive burden on the negative voltage generation circuit for the bit line. That is, it is more useful from the chip size aspect to lower the potential of the word line during "0" writing than during "1" writing, suppress the drive current, and suppress the increase in the area of the negative voltage generation circuit for the bit line.

[0013] That is, in a memory cell that accumulates charges in a floating body and differentiates the data to be stored according to the amount of electricity, when there are "1" writes and "0" writes for a plurality of memory cells connected to the same word line in a memory cell array, the "1" write and the "0" write cannot be performed simultaneously with optimal potential settings.

[0014] In order to perform "1" writes and "0" writes with optimal potential settings respectively, it is also conceivable to perform "0" writes and "1" writes separately by setting the voltages of the word line and the bit line again in one write cycle by a write command input from a device external to the SDRAM to the SDRAM. However, the specification of the SDRAM using a memory cell composed of one MOS transistor and one capacitor is determined according to the operation when using a memory cell composed of one MOS transistor and one capacitor in some aspects, so it is not specified to perform "0" writes and "1" writes at different timings. This is because in the case of a memory cell composed of one MOS transistor and one capacitor, the MOS transistor connected to the word line only serves as a switch, and there is no necessity to change the voltage at all. Therefore, as the write time, since there is only enough margin to apply one voltage pulse to the word line, there is no time margin to pulse-drive the word line twice separately for "0" writes and "1" writes.

[0015] As described above, there is a problem that a method for satisfying the specifications of the current SDRAM with an optimal operation method for the memory cell that does not have a capacitor, accumulates charges in a floating body, and differentiates the data to be stored according to the amount of electricity has not been shown.

Prior Art Documents

Patent Documents

[0016]

Patent Document 1

[0017] [Non-Patent Document 1] Hsing-jen Wann and Chenming Hu: “A Capacitorless DRAM Cell on SOI Substrate,” IEEE International Electron Device Meeting Technical Digest, pp.635 - 638 (1993) [Non-Patent Document 2] P. C. Fazan, S. Okhonin, M. Nagoga and J. M. Sallese: “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs,” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp.99 - 102 (2002)

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Non-Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0018] There has been a problem that no optimal operation method has been proposed for a memory cell that accumulates charges in a floating body and distinguishes stored data by the amount of electricity thereof, corresponding to the operation specifications of current SDRAMs.

Means for Solving the Problems

[0019] To solve the above problems, a first invention of the present application is a clock-synchronous semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix in two orthogonal directions in a plan view on a semiconductor substrate, having a data register that temporarily stores data between the memory cell array and input / output terminals of the clock-synchronous semiconductor memory device, Furthermore, the clock-synchronous semiconductor memory device has an instruction set which is a collection of instructions (commands) for operating the clock-synchronous semiconductor memory device. The instruction set includes an active command for selecting the memory cell, a precharge command for releasing the selected state of the memory cell, a write command for inputting data from the input / output terminal, and a plurality of commands with auto-precharge for releasing the selected state of the memory cell without depending on the precharge command. When the write command is received, the data input from the input / output terminal of the clock-synchronous semiconductor memory device is written into the data register. After receiving either the precharge command or one of the plurality of commands with auto-precharge, while the selected state of the memory cell is being released, the data stored in the data register is written into the memory cell selected by the active command. It is characterized by this.

[0020] According to a second invention of the present application, in the first invention described above, the instruction set includes a read command for outputting data from the input / output terminal, a write command with auto-precharge for inputting data from the input / output terminal and releasing the selected state of the memory cell after completing the data input, and a read command with auto-precharge for outputting data from the input / output terminal and releasing the selected state of the memory cell after starting the data output. When the write command is received, the data input from the input / output terminal is written into the data register. After receiving the precharge command, or after the elapse of a first period of time after receiving the read command with auto precharge, or after the elapse of a second period of time different from the first period of time after receiving the write command with auto precharge, an operation of writing the data stored in the data register into the memory cell selected by the active command is started. It is characterized by this.

[0021] The third invention of the present application is the first invention described above, wherein the data register is disposed adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command.

[0022] The fourth invention of the present application is the first invention described above, wherein the data register is disposed adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command within the memory cell array disposed adjacent to the data register.

[0023] The fifth invention of the present application is the first invention described above, wherein the memory cell has a structure including a MOS type field effect transistor in which at least a part of a floating body serving as a memory node forms a current path.

[0024] The sixth invention of the present application is the first invention described above, wherein the data that can be stored in the memory cell is binary as a logic level, and after the data stored in the selected memory cell is written into the data register by the active command, a writing operation of data of one of the binary logics is performed on all the selected memory cells.

[0025] The seventh invention of the present application is, in the first invention described above, the data that can be stored in the memory cell is binary as a logical level, and the data of one of the two logics is stored in the data register by a signal different from the control signal for writing to all the selected memory cells. The data stored in the data register is written to the memory cells selected by the active command.

[0026] The eighth invention of the present application is, in the sixth invention described above, the operation of inputting data via the input / output terminal, or the operation of outputting data via the input / output terminal, and the operation of writing data of one of the two logics are performed independently and in parallel for all the selected memory cells.

[0027] The ninth invention of the present application is, in the sixth invention described above, by receiving the write command or the write command with auto precharge, the write operation of the data of one of the two logics is performed for all the selected memory cells.

[0028] The tenth invention of the present application is, in the ninth invention described above, only when the write command or the write command with auto precharge is received for the first time after receiving the active command, the write operation of the data of one of the two logics is performed for all the selected memory cells by the write command or the write command with auto precharge.

[0029] The eleventh invention of the present application is, in the ninth invention described above, even when the read command or the read command with auto precharge is received, the write operation of the data of one of the two logics is performed for all the selected memory cells.

[0030] The 12th invention of the present application is characterized in that, in the 11th invention described above, when any one of the write command, the write command with auto precharge, the read command, or the read command with auto precharge is received for the first time after receiving the active command, the writing operation of the data of one of the two logics is performed on all the selected memory cells.

[0031] In the 13th invention of the present application, in the 1st invention described above, one end of the memory cell is connected to a bit line, the other end is connected to a source line, and the data stored in the memory cell is determined by the amount of current flowing between the bit line and the source line, and the extension direction of the bit line and the extension direction of the source line are arranged in parallel.

[0032] In the 14th invention of the present application, in the 13th invention described above, the bit line connected to one end of one of the memory cells and the source line connected to the other end are different wiring layers, all the bit lines in the memory cell array are the same wiring, and all the source lines are the same wiring layer.

[0033] In the 15th invention of the present application, in the 13th invention described above, the bit line connected to one end of one of the memory cells and the source line connected to the other end are different wiring layers, and in the memory cell array, there are bit lines formed in different wiring layers.

[0034] In the 16th invention of the present application, in the 13th invention described above, the bit line connected to one end of one of the memory cells and the source line connected to the other end are different wiring layers, and in the memory cell array, there are source lines formed in different wiring layers.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0036] In order to solve the above problems, in the SDRAM according to the present invention, charges are accumulated in the floating body, and by their amounts of electricity, writing "0" and writing "1" to the memory cells that distinguish the data to be stored are not simultaneously performed by a write command according to the operation specification of DDR-SDRAM. Instead, the data of the memory cell(s) selected by receiving an active command according to the operation specification of DDR-SDRAM is first read into the data register(s), and then data of one logical value is written to the memory cell(s) of the selected bank, and writing data of the other logical value to the memory cell(s) is performed before the execution of the deselection of the selected memory cell(s) by a command according to the operation specification of DDR-SDRAM, and writing to the memory cell(s) is not performed for each write command. This is the characteristic.

[0037] The present invention relates to writing to memory cells and does not relate to the input / output of semiconductor memory devices. Therefore, it is applicable to DDR-SDRAM of each generation of DDR, DDR2, DDR3, DDR4, DDR5 or future generations of DDR-SDRAM and LPDDR of each generation of LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X or future generations of LPDDR-SDRAM and GDDR (Graphics Double Data Rate)-SDRAM of each generation of GDDR, GDDR3, GDDR4, GDDR5, GDDR5X, GDDR6, GDDR6X or future generations of GDDR-SDRAM, but it is not applicable to SDRAM with a single data rate (SDR) specification whose specifications related to writing to memory cells are different. In addition, for the gate insulating film of the MOS transistor, not only a silicon oxide film but also an insulating film other than the silicon oxide film may be used, or a laminated film of a silicon insulating film and an insulating film other than the silicon insulating film may be used. Therefore, neither the memory cell of the SDRAM according to the present invention nor the gate insulating film of the MOS transistor constituting the circuit is limited to only a silicon oxide film, and an insulating film other than the silicon oxide film may be used, or a laminated film of a silicon insulating film and an insulating film other than the silicon insulating film may be used.

[0038] (First Embodiment) Hereinafter, an SDRAM (an example of the "clock-synchronous semiconductor memory device" in the claims) according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an SDRAM compliant with the DDR4 specification. Therefore, although ACT_n exists, when there is no ACT_n as in DDR3 or DDR5, it is generated inside the SDRAM by a combination of command signals input from the address signal lines. That is, the address receiver shown as 112 in FIG. 1 and the address decoder shown in 117 etc. in FIG. 1 determine the logical value of the address signal input from the external device of the SDRAM, and further interpret and output it as a command by the command receiver and the command decoder shown as 111 in FIG. 1. Incidentally, a signal whose name ends with _n is a negative logic signal, and a relatively low potential including a negative potential logically represents "1", and a signal whose name ends with _t is a positive logic signal, and a relatively high potential logically represents "1".

[0039] FIG. 2 is a diagram showing an example of a cell array block shown as 101 in FIG. 1, where there are four in the SDRAM shown as 100 in FIG. 1. In the SDRAM using a memory cell (an example of the "memory cell" in the claims) that accumulates charges in a floating body according to the present embodiment and distinguishes the data to be stored by the amount of those charges, the cell array block can operate independently, similar to the SDRAM using a memory cell composed of one transistor and one capacitor in the current situation. Also, similar to the SDRAM using a memory cell composed of one transistor and one capacitor in the current situation, the memory cell group is divided into a plurality of banks across the cell array blocks.

[0040] As shown in FIG. 2, in the SDRAM using a memory cell that accumulates charges in a floating body according to the present embodiment and distinguishes the data to be stored by the amount of those charges, similar to the SDRAM using a memory cell composed of one transistor and one capacitor in the current situation, the cell array block is divided into a plurality of sub-cell arrays (shown as 103 in FIG. 2). Similar to the SDRAM using a memory cell composed of one transistor and one capacitor in the current situation, the SDRAM according to the present embodiment interprets an address signal input from an external device by a row decoder shown as 130 in FIG. 2 in synchronization with an active command (an example of the "active command" in the claims, hereinafter referred to as an ACT command), so that one global word line is selected from a plurality of global word lines (WL) (shown as 140 in FIG. 2) and is driven by a corresponding global word line (WL) driver existing in 130 of FIG. 2. Similar to the SDRAM using a memory cell composed of one transistor and one capacitor in the current situation, the global word line (WL) drives a local word line (WL) driver associated with each sub-cell array, and as shown in 134 of FIG. 2, each word line (WL) of the sub-cell array is arranged to be driven by the local word line (WL) driver.

[0041] As shown in 133 of FIG. 2, the same number of BL sense amplifiers (groups) as the bit lines (BLs) (groups) connectable to the bit lines (BLs) (groups) connected to the memory cell(s) connected to one word line (WL) to discriminate the data of the memory cell(s); the same number of data registers (groups, an example of the "data register" in the claims) as the BL sense amplifiers (groups) to store the data of the memory cell(s) discriminated by the BL sense amplifiers (groups); and the same number of BL driver circuits (groups) as the data registers (groups) connectable to the bit lines (BLs) (groups) connected to the memory cell(s) connected to one word line (WL) are attached to the sub-cell array. Further, a source line (SL) connected to the memory cell(s) connected to one word line (WL) and an SL driver circuit connectable to the source line (SL) are attached to the sub-cell array. In the fourth and fifth embodiments described later, the same number of SL driver circuits (groups) individually connectable to the source line(s) connected to the memory cell(s) connected to one word line (WL) are attached to the sub-cell array. In 133 of FIG. 2, the BL driver circuit and the SL driver circuit are collectively referred to as a BL / SL driver. The BL sense amplifiers (groups), the data registers (groups), and the BL / SL drivers (groups) are selectively used for the memory cell(s) of the two sub-cell arrays sandwiching the BL sense amplifiers (groups), the data registers (groups), and the BL / SL drivers (groups). That is, according to the input address, the BL sense amplifiers (groups), the data registers (groups), and the BL / SL drivers (groups) are connected to the bit lines (groups) and the source lines (groups) of the memory cell(s) of one of the sub-cell arrays.

[0042] In synchronization with a read command (hereinafter referred to as an RD command), a read command with auto precharge (an example of the "command with auto precharge" in the claims, hereinafter referred to as an RDA command), a write command (an example of the "write command" in the claims, hereinafter referred to as a WR command), or a write command with auto precharge (an example of the "command with auto precharge" in the claims, hereinafter referred to as a WRA command), a column decoder that interprets an address signal input from an external device and outputs a selection signal for selecting one or a plurality of data registers from a plurality of data registers, an IO driver circuit for writing data input from an external device to the selected data register, an IO sense amplifier circuit for sense amplifying a data signal from the selected data register for output to an external device, and an IO MUX for connecting the selected data register to the IO driver circuit or the IO sense amplifier circuit in accordance with the output of the column decoder is provided (131 in FIG. 2).

[0043] FIG. 3 is a diagram excerpting a portion related to the present embodiment from the state transition diagram of a current SDRAM. Although the details of the specifications of DDR-SDRAM differ between generations, the operations related to FIG. 3 are applicable to each generation of DDR, and the SDRAM according to the present invention also realizes the state transition shown in FIG. 3. What is shown in the circles is the state of the SDRAM. The solid arrows indicate that the state transitions by receiving the command denoted by the abbreviation attached to the arrow, and the dashed arrows indicate that the state transitions without depending on the command. The abbreviations of the commands are explained in the table in the figure.

[0044] From the idle state indicated as 030 in the state transition diagram of FIG. 3, by an active command (an example of the "active command" in the claims, hereinafter referred to as the ACT command), it enters the startup state indicated as 031 in the state transition diagram of FIG. 3, and the memory cell(s) specified by the address signal input in synchronization with the ACT command can be read from or written to, entering the active state indicated as 032 in the state transition diagram of FIG. 3. If the memory cell(s) is not put into the active state, no read or write operation can be performed on the memory cell(s). From the active state indicated as 032 in the state transition diagram of FIG. 3, when receiving a read command (hereinafter referred to as the RD command), a read command with auto - precharge (hereinafter referred to as the RDA command), a write command (hereinafter referred to as the WR command), a write command with auto - precharge (hereinafter referred to as the WRA command), or a precharge command (an example of the "precharge command" in the claims, hereinafter referred to as the PRE command), it transitions to the read state indicated as 033 in the state transition diagram of FIG. 3, the read state indicated as 035 in the state transition diagram of FIG. 3, the write state indicated as 034 in the state transition diagram of FIG. 3, the write state indicated as 036 in the state transition diagram of FIG. 3, and the precharge state indicated as 037 in the state transition diagram of FIG. 3, respectively.

[0045] When receiving the RD command and entering the read state indicated as 033 in the state transition diagram of FIG. 3, data is read from the memory cell(s) selected by the address signal input in synchronization with the RD command to an external device with respect to the SDRAM. From the read state indicated as 033 in the state transition diagram of FIG. 3, when receiving the RDA command, the WR command, the WRA command, or the PRE command, it transitions to the read state indicated as 035 in the state transition diagram of FIG. 3, the write state indicated as 034 in the state transition diagram of FIG. 3, the write state indicated as 036 in the state transition diagram of FIG. 3, and the precharge state indicated as 037 in the state transition diagram of FIG. 3, respectively. Also, from the read state indicated as 033 in the state transition diagram of FIG. 3, it is also possible to transition back to the read state indicated as 033 in the state transition diagram of FIG. 3 by accepting the RD command again. Also, if no command is input, it returns to the active state indicated as 032 in the state transition diagram of FIG. 3.

[0046] When the RDA command is accepted and the read state indicated as 035 in the state transition diagram of FIG. 3 is entered, reading is performed from the memory cell(s) selected by the address signal input in synchronization with the RDA command to an external device with respect to the SDRAM. After a predetermined time has elapsed since the RDA command was accepted, even if the PRE command is not input, it transitions to the precharge state indicated as 037 in the state transition diagram of FIG. 3. Since it is no longer in the active state, it is not possible to input the RD command or the WR command after the RDA command is input.

[0047] When the WR command is accepted and the write state indicated as 034 in the state transition diagram of FIG. 3 is entered, writing is performed from an external device to the memory cell(s) selected by the address signal input in synchronization with the WR command with respect to the SDRAM. When the RD command, RDA command, WRA command, or PRE command is accepted from the write state indicated as 034 in the state transition diagram of FIG. 3, it transitions to the read state indicated as 033 in the state transition diagram of FIG. 3, the read state indicated as 035 in the state transition diagram of FIG. 3, the write state indicated as 036 in the state transition diagram of FIG. 3, and the precharge state indicated as 037 in the state transition diagram of FIG. 3, respectively. Also, from the write state indicated as 034 in the state transition diagram of FIG. 3, it is also possible to transition back to the write state indicated as 034 in the state transition diagram of FIG. 3 by accepting the WR command again. Also, if no command is input, it returns to the active state indicated as 032 in the state transition diagram of FIG. 3.

[0048] When the WRA command is received and the write state shown as 036 in the state transition diagram of FIG. 3 is entered, writing is performed from an external device to the memory cell(s) selected by the address signal input in synchronization with the WRA command with respect to the SDRAM. After a predetermined time has elapsed since the reception of the WRA command, even if the PRE command is not input, a transition is made to the precharge state shown as 037 in the state transition diagram of FIG. 3. Since it is no longer in the active state, it is not possible to input the RD command or the WR command after the WRA command is input.

[0049] In the current SDRAM specification, when a predetermined time has elapsed since the reception of the RDA command or when a predetermined time has elapsed since the reception of the WRA command, a transition is made to the precharge state shown as 037 in the state transition diagram of FIG. 3. Alternatively, from the active state shown as 032 in the state transition diagram of FIG. 3, the read state shown as 033 in the state transition diagram of FIG. 3, and the write state shown as 034 in the state transition diagram of FIG. 3, when the PRE command is received, a transition is made to the precharge state shown as 037 in the state transition diagram of FIG. 3. After transitioning to the precharge state, after a predetermined time has elapsed, a transition is made to the idle state shown as 030 in the state transition diagram of FIG. 3.

[0050] There is also a low-power LPDDR-SDRAM for SDRAM, and there are differences such as the presence or absence of a DLL (Delay Locked Loop; a circuit that synchronizes the clock signal used inside the device by amplifying the clock signal input from outside the device inside the device using a delay circuit), but the operation of FIG. 3 related to this embodiment is also applicable to the LPDDR-SDRAM. Also, although the detailed operation specifications of the GDDR-SDRAM for graphics applications are different from those of the DDR-SDRAM and the LPDDR-SDRAM, it is applicable to the basic operation as a DRAM shown in FIG. 3.

[0051] As a comparison target for clarifying the difference from the gist of the present invention, FIG. 93 shows a state transition diagram of a unit of one memory cell (group) and a unit of one data register (group) that operate according to a certain address signal input in synchronization with an ACT command in a current SDRAM using a memory cell composed of one MOS transistor and one capacitor. What is shown in the circles are the states of the memory cell (group) and the data register (group) that operate according to the address signal input in synchronization with the ACT command, and are shown in tabular form. What is denoted as cell is the memory cell (group) specified by the address signal input in synchronization with the ACT command, and what is denoted as DR is the data register (group) specified by the address signal input in synchronization with the CT command. Hold is the state in which the held data is maintained, write is the write state, and read is the read state. Precharge indicates that the data held as the state of the data register is invalid. The solid-line arrow represents that the state transitions by receiving the command associated with the arrow, and the dashed-line arrow represents that the state transitions regardless of the command.

[0052] Since FIG. 93 is a state transition diagram of a certain memory cell (group) and data register (group) specified by an address signal input in synchronization with the ACT command, even if the SDRAM receives the ACT command and enters the active state, the memory cell (group) and data register (group) not specified by the address input in synchronization with the ACT command do not undergo state transitions. As a result of the previously received command, it stays in the idle state shown as 010 in the state transition diagram of FIG. 93 or the active state shown as 012 in the state transition diagram of FIG. 93.

[0053] It starts from the idle state. The memory cell(s) hold the previously written data, and the data register(s) maintain the pre-charge state due to the operation executed before entering the idle state. Therefore, in the idle state shown as 010 in the state transition diagram of FIG. 93, cell in the table is hold and DR in the table is also hold.

[0054] When a current SDRAM using a memory cell composed of one MOS transistor and one capacitor receives an ACT command, it enters the startup state, receives the address signal input simultaneously with the ACT command, reads data from the memory cell(s) selected by the received address signal, and stores the read data in the data register(s) specified by the received address signal. Therefore, in the startup state shown as 011 in the state transition diagram of FIG. 93, cell in the table is read and DR in the table is write.

[0055] When data is read from the memory cell(s) specified by the address signal and the storage of data into the data register(s) specified by the address signal is completed, the SDRAM transitions to the active state, and the memory cell(s) and data register(s) maintain the data they hold. Therefore, in the active state shown as 012 in the state transition diagram of FIG. 93, cell in the table is hold and DR in the table is also hold. When receiving an RD command, an RDA command, a WR command, a WRA command, or a PRE command from the active state shown as 012 in the state transition diagram of FIG. 93, it transitions to the read state shown as 013 in the state transition diagram of FIG. 93, the read state shown as 015 in the state transition diagram of FIG. 93, the write state shown as 014 in the state transition diagram of FIG. 93, the write state shown as 016 in the state transition diagram of FIG. 93, and the pre-charge state shown as 017 in the state transition diagram of FIG. 93, respectively.

[0056] When the SDRAM receives an RD command, it transitions to the read state indicated as 013 in the state transition diagram of FIG. 93. In the case of a current SDRAM using a memory cell composed of one MOS transistor and one capacitor, when an RD command is received, the memory cell(s) selected by the address signal received simultaneously with the ACT command does not operate at all and holds the data. Among the data register(s) specified by the address signal received simultaneously with the ACT command, data is read from the data register(s) specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RD command holds the data. Therefore, in the read state indicated as 013 in the state transition diagram of FIG. 93, cell in the table is hold, and DR in the table is read and hold.

[0057] Furthermore, it is possible for the SDRAM to receive an RD command again. Among the data register(s) specified by the address signal received simultaneously with the ACT command, data is read from the data register(s) specified by the newly received address signal simultaneously with the RD command to a device external to the SDRAM. In the state transition diagram of FIG. 93, it will stay in the read state indicated as 013. If no command is input from the read state indicated as 013 in the state transition diagram of FIG. 93, after a predetermined time elapses according to the specifications of the current SDRAM, it transitions to the active state indicated as 012 in the state transition diagram of FIG. 93. Also, when the RDA command, WR command, WRA command, or PRE command is received from the read state indicated as 013 in the state transition diagram of FIG. 93, the state transitions to the read state indicated as 015 in the state transition diagram of FIG. 93, the write state indicated as 014 in the state transition diagram of FIG. 93, the write state indicated as 016 in the state transition diagram of FIG. 93, and the precharge state indicated as 017 in the state transition diagram of FIG. 93, respectively.

[0058] When the SDRAM receives the RDA command, it transitions to the read state indicated as 015 in the state transition diagram of FIG. 93. The memory cell specified by the address signal received simultaneously with the ACT command does not operate at all and holds the data. Of the data register(s) specified by the address signal received simultaneously with the ACT command, data is read from the data register(s) specified by the address signal received simultaneously with the RDA command to a device external to the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RDA command holds the data. Therefore, in the read state indicated as 015 in the state transition diagram of FIG. 93, the cell in the table is hold, and the DR in the table is read and hold. After a predetermined time has elapsed, the state transitions to the precharge state indicated as 017 in the state transition diagram of FIG. 93.

[0059] When the SDRAM receives the WR command, it transitions to the write state indicated as 014 in the state transition diagram of FIG. 93. Data is written from a device external to the SDRAM to the memory cell(s) and data register(s) specified by the address signal received simultaneously with the WR command among the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command. On the one hand, the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WR command are in a state of holding data. Therefore, in the write state indicated as 014 in the state transition diagram of FIG. 93, the cells in the table are write and hold, and the DRs in the table are also write and hold.

[0060] Furthermore, it is possible for the SDRAM to receive the WR command again, and data is written from a device external to the SDRAM to the memory cell(s) and data register(s) newly specified by the address signal received simultaneously with the WR command among the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command. In terms of the state transition diagram of FIG. 93, it will remain in the write state indicated as 014. If no command is input from the write state indicated as 014 in the state transition diagram of FIG. 93, after a predetermined time elapses according to the current SDRAM specification, it will transition to the active state indicated as 012 in the state transition diagram of FIG. 93. When the SDRAM receives the RD command, RDA command, WRA command, or PRE command from the write state indicated as 014 in the state transition diagram of FIG. 93, it will transition to the read state indicated as 013, the read state indicated as 015, the write state indicated as 016, and the precharge state indicated as 017 in the state transition diagram of FIG. 93, respectively.

[0061] When the SDRAM receives the WRA command, it will transition to the write state indicated as 016 in the state transition diagram of FIG. 93. Data is written from a device external to the SDRAM to the memory cell(s) and data register(s) specified by the address signal received simultaneously with the WRA command among the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command. On the one hand, the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WRA command are in a state of holding data. Therefore, in the write state indicated as 016 in the state transition diagram of FIG. 93, the cells in the table are write and hold, and the DRs in the table are also write and hold. After a predetermined time has elapsed, it transitions to the precharge state indicated as 017 in the state transition diagram of FIG. 93.

[0062] In the current SDRAM specification, when a predetermined time elapses after receiving the RDA command or when a predetermined time elapses after receiving the WRA command, it transitions to the precharge state indicated as 017 in the state transition diagram of FIG. 93. Alternatively, from the active state indicated as 012 in the state transition diagram of FIG. 93, the read state indicated as 013 in the state transition diagram of FIG. 93, and the write state indicated as 014 in the state transition diagram of FIG. 93, by receiving the PRE command, it transitions to the precharge state indicated as 017 in the state transition diagram of FIG. 93. In the case of a current SDRAM using a memory cell composed of one MOS transistor and one capacitor, no operation is performed on the memory cell(s) specified by the address signal received simultaneously with the ACT command, and it is in a state of maintaining data, while the data register(s) also serving as the BL sense amplifier(s) is precharged. Therefore, in the precharge state indicated as 017 in the state transition diagram of FIG. 93, the cells in the table are hold, and the DRs in the table are precharge.

[0063] After a further predetermined period of time, the system transitions to the idle state indicated as 010 in the state transition diagram of FIG. 93. Neither the memory cell(s) nor the data register(s) specified by the address signal received simultaneously with the ACT command perform any operation. Therefore, in the idle state indicated as 010 in the state transition diagram of FIG. 93, both the cell in the table and the DR in the table are in the hold state.

[0064] Comparing the state transition diagram of FIG. 3 with the state transition diagram of FIG. 93, the only difference is that when receiving a read command, instead of actually reading from the memory cell, the data previously read from the data of the memory cell by a pre-start operation is read from the data register to perform the read operation.

[0065] The SDRAM according to the first embodiment of the present invention performs the same state transition as the current SDRAM shown in FIG. 3. However, it accumulates charge in the floating body and sets potentials suitable for writing "0" and writing "1" for the memory cell(s) composed of 1-transistor without a capacitor, which distinguish the data to be stored by their electric charges. Therefore, for the cells targeted for "0" writing and the cells targeted for "1" writing connected to the same word line, "0" writing and "1" writing are not performed simultaneously. The specific operation is described below.

[0066] Substantially, the writing of one of the binary data is performed for all the memory cell(s) connected to the word line selected by the address signal input in synchronization with the ACT command from an external device after receiving the WR command or the WRA command from the external device and then executed. What is executed here is, for the sake of convenience of the following explanation, described as a substantial "0" data writing, erasure. There is no problem even if it is a "1" writing instead of "0" as logical data.

[0067] From the perspective of power consumption, it is desirable not to execute the erasure operation every time a WR command is received, but rather to execute the erasure operation again only with a WRA command after a WR command has been input once. Furthermore, considering the subsequent operation sequence, it is desirable to perform it only once when the first WR command or WRA command is input. In the following operation description, it is assumed that the erasure operation is performed only when the first WR command or WRA command is input.

[0068] Writing to a memory cell (group) of other data different from the data written in the erasure operation is executed after receiving a PRE command after receiving a WR command from an external device (RD commands and WR commands can be received any number of times between the WR command and the PRE command). Alternatively, if a WR command is received even once before the RDA command is input (RD commands and WR commands can be received any number of times between the WR command and the RDA command), it is executed after receiving the RDA command and after a predetermined time has elapsed. Alternatively, it is executed after a predetermined time has elapsed after the completion of data input from an external device after receiving a WRA command from the external device. If the erasure operation performs a substantial "0" write as logical data, then what is executed here is a "1" data write. If the erasure operation performs a substantial "1" write as logical data, then the write at this point is a "0" write as logical data.

[0069] A voltage is applied so that a "1" write is executed for the memory cell (group) to be written with "1". However, since the memory cell (group) to be written with "0" has already been subjected to the erasure operation, the voltage applied at this point is only such that it does not destroy the "0" state of the memory cell (group) to be written with "0", and no voltage for "0" writing is applied to the memory cell to be written with "0".

[0070] Memory cells that are not to be written are erased when the WR command or the WRA command is received, and the data becomes "0". However, by receiving the ACT command that is always input before the WR command or the WRA command, the data of the memory cell(s) that would otherwise be erased is read out in advance, written into the data register(s), and stored. Therefore, as the data to be written, along with the data written into the data register(s) by the WR command or the WRA command, a "1" is stored in advance in the memory cells that were not to be written by the WR command or the WRA command, and a "1" is written based on the data stored in the data register(s). Thus, the data does not change.

[0071] The SDRAM according to the first embodiment does not perform a write operation on the memory cells specified by the address signal received simultaneously with the WR command when the WR command is received. However, since it has been written into the data register specified by the address signal received simultaneously with the WR command, there is no problem with the data read from the data register by a subsequent RD command for the data of the memory cells specified by the address signal received simultaneously with the WR command.

[0072] The SDRAM according to the first embodiment does not perform a write operation after a read operation if the WR command has not been received between receiving the ACT command and receiving the RDA command. The SDRAM according to the first embodiment does not perform a write operation by the PRE command if the WR command has not been received from receiving the ACT command until receiving the PRE command.

[0073] Based on the above, FIG. 4 shows a state transition diagram in a form focusing on the memory cells and data registers of the SDRAM according to the first embodiment of the present invention. Similar to the state transition diagram shown in FIG. 93, what is shown within the circles is the state of the SDRAM as a memory cell(s) and data register(s) transitioning in response to a command, specified by an address signal input in synchronization with an ACT command. What is shown in tabular form is the actual state of the memory cell(s) (denoted as cell) and data register(s) (denoted as DR) specified by the address signal input in synchronization with the ACT command. hold is the state in which the held data is maintained, write is the write state, erase is the erase state, and read is the read state. reset indicates that the data held as the state of the data register is invalid. Similar to the state transition diagram shown in FIG. 93, the solid arrows represent the transition of the state by receiving the command associated with the arrow, and the dashed arrows represent the transition of the state without depending on a command. Similar to the state transition diagram shown in FIG. 93, the state transition diagram shown in FIG. 4 is a state transition diagram of a certain memory cell(s) and data register(s) specified by an address signal input in synchronization with an ACT command. Therefore, even if the SDRAM receives an ACT command and enters the active state, the memory cell(s) and data register(s) not specified by the address input in synchronization with the ACT command do not undergo a state transition. As a result of the previously received command, the SDRAM maintains the idle state shown at 040 in the state transition diagram of FIG. 4, the active state shown at 042 in the state transition diagram of FIG. 4, or the active state shown at 047 in the state transition diagram of FIG. 4.

[0074] It starts from the idle state shown at 040 in the state transition diagram of FIG. 4. The memory cell(s) is in the state of holding the previously written data, and the data register(s) maintains the state of being in the precharge state or the reset state due to the operation executed before entering the idle state. cell in the table is hold, and DR in the table is hold. Even if the idle state is after power-on, in the case of a memory cell that uses the amount of electricity stored in the floating body related to the present embodiment as data, it is highly likely that the charge in the floating body has been discharged, and it can be said that the data in the state where the charge in the floating body has been discharged is being held. According to the sequence determined in the specification of the SDRAM after power-on, the data register(s) also maintains the state of being in the precharge state or the reset state.

[0075] When the SDRAM according to the first embodiment of the present invention receives an ACT command, it enters the startup state shown in 041 of the state transition diagram in FIG. 4, receives the address signal input simultaneously with the ACT command, and reads data from the memory cell(s) selected by the received address signal and stores it in the data register(s) specified by the received address signal. Therefore, in the startup state shown in 041 of the state transition diagram in FIG. 4, cell in the table is read, and DR in the table is write.

[0076] When data is read from the memory cell(s) specified by the address signal and the storage in the data register(s) specified by the address signal is completed, the SDRAM transitions to the active state shown in 042 of the state transition diagram in FIG. 4. Therefore, in the active state shown in 042 of the state transition diagram in FIG. 4, cell in the table is hold, and DR in the table is hold. When the RD command, RDA command, WR command, WRA command, or PRE command is received from the active state shown as 042 in the state transition diagram of FIG. 4, the SDRAM transitions to the read state shown as 043 in the state transition diagram of FIG. 4, the read state shown as 044 in the state transition diagram of FIG. 4, the write state shown as 046 in the state transition diagram of FIG. 4, the write state shown as 050 in the state transition diagram of FIG. 4, and the precharge state shown as 045 in the state transition diagram of FIG. 4, respectively.

[0077] When the SDRAM according to the first embodiment of the present invention receives an RD command from the active state shown as 042 in the state transition diagram of FIG. 4, it transitions to the read state shown as 043 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, the memory cell(s) selected by the address signal received simultaneously with the ACT command does not operate at all when receiving the RD command, and remains in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RD command remains in a state of holding data. Therefore, in the read state shown as 043 in the state transition diagram of FIG. 4, the cell in the table is hold, and the DR in the table is read and hold.

[0078] Furthermore, it is possible for the SDRAM according to the first embodiment of the present invention to receive an RD command again. Among the data register(s) specified by the address signal received simultaneously with the ACT command, data is read from the data register(s) specified by the address signal received simultaneously with the new RD command to a device external to the SDRAM according to the first embodiment. In the state transition diagram of FIG. 4, it will remain in the read state shown as 043. If no command is input from the read state shown as 043 in the state transition diagram of FIG. 4, after a predetermined time elapses according to the specifications of the current SDRAM, it transitions to the active state shown as 042 in the state transition diagram of FIG. 4. Also, when receiving an RDA command, a WR command, a WRA command, or a PRE command from the read state shown as 043 in the state transition diagram of FIG. 4, it transitions to the read state shown as 044, the write state shown as 046, the write state shown as 050, and the precharge state shown as 045 in the state transition diagram of FIG. 4, respectively.

[0079] When the SDRAM according to the first embodiment of the present invention receives an RDA command from the active state shown as 042 in the state transition diagram of FIG. 4 or the read state shown as 043 in the state transition diagram of FIG. 4, it transitions to the read state shown as 044 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, the memory cell(s) selected by the address signal received simultaneously with the ACT command does not operate at all when receiving the RDA command, and is in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RDA command to a device external to the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RDA command is in a state of holding data. Therefore, in the read state shown as 044 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is read and hold. After a predetermined time has elapsed, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4.

[0080] When the SDRAM according to the first embodiment of the present invention receives a PRE command from the active state shown as 042 in the state transition diagram of FIG. 4 or the read state shown as 043 in the state transition diagram of FIG. 4, or when a predetermined time has elapsed from the read state shown as 044 in the state transition diagram of FIG. 4, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment of the present invention, the memory cell(s) does not operate at all and is in a state of holding data. Assuming that the circuit shown in FIG. 42 is used as the data register, the data register(s) is reset. Therefore, in the precharge state shown as 045 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is reset.

[0081] When the SDRAM according to the first embodiment of the present invention receives a WR command from the active state indicated as 042 in the state transition diagram of FIG. 4 or the read state indicated as 043 in the state transition diagram of FIG. 4, it transitions to the write state indicated as 046 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, when receiving a WR command, the memory cell(s) selected by the address signal received simultaneously with the ACT command is erased. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WR command holds the data. Therefore, in the write state indicated as 046 in the state transition diagram of FIG. 4, cell in the table is erase, and DR in the table is write and hold. Although the memory cell(s) selected by the address signal received simultaneously with the ACT command is erased, if the writing of data from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command is not completed, it transitions to the write state indicated as 049 in the state transition diagram of FIG. 4. When the erasure of the memory cell(s) selected by the address signal received simultaneously with the ACT command is completed and the writing of data from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command is completed, it transitions to the active state indicated as 047 in the state transition diagram of FIG. 4.

[0082] After the memory cell(s) selected by the address signal received simultaneously with the ACT command is erased and data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command, it transitions to the active state indicated as 047 in the state transition diagram of FIG. 4. The data register(s) specified by the address signal received simultaneously with the WR command holds the written data after the data has been written. On the other hand, the memory cell(s) selected by the address signal received simultaneously with the ACT command and the data register(s) not specified by the address signal received simultaneously with the WR command do not perform any operation and hold the data. Therefore, in the active state indicated as 047 in the state transition diagram of FIG. 4, the cell in the table is hold and the DR in the table is also hold. When the RD command, RDA command, WR command, WRA command, or PRE command is received from the active state indicated as 047 in the state transition diagram of FIG. 4, the state transitions to the read state indicated as 048 in the state transition diagram of FIG. 4, the read state indicated as 051 in the state transition diagram of FIG. 4, the write state indicated as 049 in the state transition diagram of FIG. 4, the write state indicated as 052 in the state transition diagram of FIG. 4, and the precharge state indicated as 053 in the state transition diagram of FIG. 4, respectively.

[0083] When the SDRAM according to the first embodiment of the present invention receives the WRA command from the active state indicated as 042 in the state transition diagram of FIG. 4 or the read state indicated as 043 in the state transition diagram of FIG. 4, the state transitions to the write state indicated as 050 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, when the WRA command is received, the memory cell(s) selected by the address signal received simultaneously with the ACT command is erased and holds the data. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WRA command holds the data. Therefore, in the write state indicated as 050 in the state transition diagram of FIG. 4, the cell in the table is in the erase state, and the DR in the table is in the write and hold states. The memory cell(s) selected by the address signal received simultaneously with the ACT command is erased. However, if the writing of data from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command is not completed, the state transitions to the write state indicated as 052 in the state transition diagram of FIG. 4. If the erasure of the memory cell(s) selected by the address signal received simultaneously with the ACT command is completed and the writing of data from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command is completed, the state transitions to the precharge state indicated as 053 in the state transition diagram of FIG. 4.

[0084] When the SDRAM according to the first embodiment of the present invention receives an RD command from the active state indicated as 047 in the state transition diagram of FIG. 4 or from the write state indicated as 049 in the state transition diagram of FIG. 4, the state transitions to the read state shown as 048 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, the memory cell(s) selected by the address signal received simultaneously with the ACT command does not perform any operation upon receiving the RD command and remains in the state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RD command remains in the state of holding data. Therefore, in the read state shown as 048 in the state transition diagram of FIG. 4, the cell in the table is in the hold state, and the DR in the table is in the read and hold states.

[0085] Furthermore, the SDRAM according to the first embodiment of the present invention can receive the RD command again, and data is read from the data register(s) specified by the address signal received simultaneously with the RD command among the data register(s) specified by the address signal received simultaneously with the ACT command to an external device of the SDRAM according to the first embodiment. As the state transition diagram of FIG. 4, it stays in the read state shown as 048. When no command is input from the read state shown as 048 in the state transition diagram of FIG. 4, after a predetermined time elapses according to the specifications of the current SDRAM, it transitions to the active state shown as 047 in the state transition diagram of FIG. 4. Also, when the RDA command, WR command, WRA command, or PRE command is received from the read state shown as 048 in the state transition diagram of FIG. 4, it transitions to the read state shown as 051, the write state shown as 049, the write state shown as 052, and the precharge state shown as 053 in the state transition diagram of FIG. 4, respectively.

[0086] When the SDRAM according to the first embodiment of the present invention receives the RDA command from the active state shown as 047 or the read state shown as 048 in the state transition diagram of FIG. 4, it transitions to the read state shown as 051 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, the memory cell(s) selected by the address signal received simultaneously with the ACT command does not operate at all when the RDA command is received, and remains in the state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RDA command to an external device of the SDRAM. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the RDA command remains in the state of holding data. Therefore, in the read state shown at 051 in the state transition diagram of FIG. 4, the cell in the table is in hold, and the DR in the table is in read and hold. After a predetermined time has elapsed, it transitions to the precharge state shown as 053 in the state transition diagram of FIG. 4.

[0087] When the SDRAM according to the first embodiment of the present invention receives a WR command from the active state shown as 047 in the state transition diagram of FIG. 4 or the read state shown as 048 in the state transition diagram of FIG. 4, it transitions to the write state shown as 049 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, since the memory cell(s) selected by the address signal received simultaneously with the ACT command has already been erased, it does not operate at all and is in a state of holding data. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WR command is in a state of holding data. Therefore, in the write state shown as 049 in the state transition diagram of FIG. 4, the cell in the table is in hold, and the DR in the table is in write and hold.

[0088] It is possible for the SDRAM according to the first embodiment to receive a WR command again. Among the memory cell(s) and data register(s) specified by the address signal received simultaneously with the ACT command, data is written from a device external to the SDRAM to the data register(s) newly specified by the address signal received simultaneously with the WR command. As for the state transition diagram of FIG. 4, it will stay in the write state shown as 049. When no command is input from the write state shown as 049 in the state transition diagram of FIG. 4, after a predetermined time elapses according to the current SDRAM specification, it transitions to the active state shown as 047 in the state transition diagram of FIG. 4. When receiving an RD command, an RDA command, a WRA command, or a PRE command from the write state indicated as 049 in the state transition diagram of FIG. 4, the SDRAM transitions to the read state indicated as 048, the read state indicated as 051, the write state indicated as 052, and the precharge state indicated as 053 in the state transition diagram of FIG. 4, respectively.

[0089] When the SDRAM according to the first embodiment of the present invention receives a WRA command from the active state indicated as 047, the read state indicated as 048, or the write state indicated as 049 in the state transition diagram of FIG. 4, it becomes the write state indicated as 052 in the state transition diagram of FIG. 4. Alternatively, it may transition by an automatic sequence from the write state indicated as 050 in the state transition diagram of FIG. 4. In the case of the SDRAM according to the first embodiment, since the memory cell(s) selected by the address signal received simultaneously with the ACT command has already been erased, it does not perform any operation and holds the data. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command. On the other hand, the data register(s) specified by the address signal received simultaneously with the ACT command and not specified by the address signal received simultaneously with the WRA command holds the data. Therefore, in the write state indicated as 050 in the state transition diagram of FIG. 4, the cell in the table is hold, and the DR in the table is write and hold. When the writing of data from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command is completed, it transitions to the precharge state indicated as 053 in the state transition diagram of FIG. 4.

[0090] In the case of the SDRAM according to the first embodiment, when a predetermined time elapses after receiving an RDA command or when a predetermined time elapses after receiving a WRA command, the SDRAM transitions to the precharge state indicated by 053 in the state transition diagram of FIG. 4. Alternatively, from the active state indicated by 047 in the state transition diagram of FIG. 4, the read state indicated by 048 in the state transition diagram of FIG. 4, or the write state indicated by 049 in the state transition diagram of FIG. 4, by receiving a PRE command, the SDRAM transitions to the precharge state indicated by 053 in the state transition diagram of FIG. 4. Writing is performed on the memory cell(s) specified by the address signal received simultaneously with the ACT command according to the data in the data register(s) specified by the address signal received simultaneously with the ACT command. Therefore, in the precharge state indicated by 053 in the state transition diagram of FIG. 4, cell in the table is write and DR in the table is read.

[0091] The SDRAM according to the first embodiment of the present invention transitions from the precharge state indicated by 053 in the state transition diagram of FIG. 4 to the precharge state indicated by 045 in the state transition diagram of FIG. 4 by an automatic sequence. In the SDRAM according to the first embodiment of the present invention, the memory cell(s) do not operate at all and are in a state of holding data. Assuming that the circuit shown in FIG. 42 is used as the data register, the data register(s) is reset. Therefore, in the precharge state indicated by 045 in the state transition diagram of FIG. 4, cell in the table is hold and DR in the table is reset.

[0092] After further elapse of a predetermined time, the SDRAM transitions to the idle state indicated by 040 in the state transition diagram of FIG. 4. Neither the memory cell(s) specified by the address signal received simultaneously with the ACT command nor the data register(s) perform any operation. Therefore, in the idle state indicated by 040 in the state transition diagram of FIG. 4, both cell in the table and DR in the table are hold.

[0093] By the state transition shown in FIG. 4, without deviating from the specifications of the current SDRAM, charge is accumulated in the floating body, and for the memory cell(s) composed of a single transistor without a capacitor that distinguishes the data to be stored by their electrical amounts, appropriate potentials for "0" writing and "1" writing are set, so that "0" writing and "1" writing are not simultaneously performed on the cells to be "0" written and the cells to be "1" written connected to the same word line. Also, the erasure operation is performed only once when the first WR command or WRA command is input, thereby achieving low power consumption.

[0094] As an example of the state transition situation of the SDRAM according to the first embodiment of the present invention shown in FIG. 4, it is shown by waveform diagrams in FIGS. 5 to 17. The signals shown in FIGS. 5 to 17 are only the signal lines related to this embodiment. The command signal and the address signal input from outside the device to the clock-synchronous dynamic semiconductor memory device are represented as command and address, respectively, as a combined set of signals. The signal lines to which the command signal and the address signal are input are not completely independent. The signal input in one signal line may be an address signal depending on the timing, and may be a command signal at another timing. The input and output of data between the clock-synchronous dynamic semiconductor memory device and the outside of the device are represented as DQ.

[0095] As can be understood from the features of this embodiment, the waveforms of the selected word lines (WL) of the selected sub-cell array, the waveforms of the non-selected word lines (WL) of the selected sub-memory cell array, the waveforms of the word lines (WL) of the non-selected sub-cell array, the waveforms of the bit lines (BL) connected to the cells to be written with "1" in the selected sub-cell array, the waveforms of the bit lines (BL) connected to the cells to be written with "0" in the selected sub-cell array, and the waveforms of the source lines (SL) of the selected sub-cell array are shown by the address signals input in synchronization with the ACT command.

[0096] The SDRAM has the configuration shown in FIGS. 1 and 2, and the sub-cell array has, for example, the configuration shown in FIG. 29. The sub-cell array shown in FIG. 29 is related to the fourth embodiment described later. The memory cell is a memory cell composed of one transistor as a memory cell that accumulates charges in the floating body and distinguishes the data to be stored by the amount of those charges. A specific circuit diagram of the memory cell is shown in FIG. 29(A). As the symbol of the memory cell, the one shown in FIG. 29(B) is used and arranged as symbol 104 in FIG. 30. As an example of the physical structure of the memory cell, a schematic cross-sectional view in a direction orthogonal to the extending direction of the word line (WL) is shown in FIG. 29(C).

[0097] The meanings of the symbols representing the potentials of the word lines (WL), bit lines (BL), and source lines (SL) shown in FIGS. 5 to 17 and FIGS. 20 to 26 are summarized in the table of FIG. 27. Specific examples of the potentials are shown in the tables of FIGS. 28(A) and 28(B). FIG. 28(A) shows a method of performing a "1" write operation on a memory cell using an NMOS transistor by utilizing the impact ionization phenomenon, and FIG. 28(B) shows a case of performing a "1" write operation on a memory cell using an NMOS transistor by utilizing the BTBT (Band to Band Tunneling) phenomenon.

[0098] An explanation of the table in FIG. 27 will be given. "Write" indicates that the sub-cell array is in a write state, "Erase" indicates that the sub-cell array is in an erase state, "Read" indicates that the sub-cell array is in a read state, and "Idle" indicates that the sub-cell array is in an idle state. The idle state is a state in which none of the operations of "write", "erase", or "read" are performed on the memory cell(s) of the sub-cell array, but the data must be retained as a memory cell.

[0099] In the column of "As Sub-Cell Array", "Selected" indicates that the sub-cell array is in a selected state by the address signal input in synchronization with the ACT command, and "Deselected" indicates that the sub-cell array is not selected by the address signal input in synchronization with the ACT command. In the column of "Within Selected Sub-Cell Array", "Selected" represents that the sub-cell array is in a selected state by the address signal input in synchronization with the ACT command, and the word line (WL), bit line (BL), or source line (SL) is in a selected state by the address signal input in synchronization with the ACT command, and "Deselected" represents that the sub-cell array is in a selected state by the address signal input in synchronization with the ACT command, and the word line (WL) is in a non-selected state by the address signal input in synchronization with the ACT command. According to this embodiment, all the bit lines (BL) and source lines (SL) of the selected sub-cell array are in the "selected" state. Therefore, in FIG. 27, there is no item of "selected" as the sub-cell array of the bit line (BL) and source line (SL) and "deselected" within the cell array. The same applies to the source line (SL). If it is "unselected" in the column of "as a sub-cell array", the term "within the selected sub-cell array" loses its meaning. Therefore, when it is "unselected" in the column of "as a sub-cell array", the column in the "within the selected sub-cell array" is shown as "-".

[0100] When the sub-cell array is in the unselected state by the address signal input in synchronization with the ACT command, all of the word line (WL), bit line (BL), and source line (SL) of the unselected sub-cell array are unselected. Even if a read operation, write operation, or erase operation is being performed on the memory cells of the selected sub-cell array, the unselected sub-cell array is in an idle state.

[0101] The memory cell according to this embodiment, which accumulates charge in the floating body and distinguishes the data to be stored by the amount of the charge, will lose the data if it remains in the idle state for a certain period or longer after writing the data. Therefore, similar to the memory cell composed of one transistor and one capacitor, a refresh operation is required. The refresh operation for the memory cell is an operation of reading data from the memory cell and writing the same data back to the memory cell again. Since refresh can be said to be a combination of read and write, it is not particularly described as an item in FIG. 27.

[0102] VIWL is the potential of the word line (WL) in the idle state. VRWL is the potential of the selected word line (WL) of the selected sub-cell array during read. The potential of the unselected word line (WL) of the selected sub-cell array during read is the same as the idle state, which is VIWL. VWWLH is the potential of the selected word line (WL) of the selected sub-cell array during write. The potential of the unselected word line (WL) of the selected sub-cell array during write is VWWLL. VEWLH is the potential of the selected word line (WL) of the selected sub-cell array during erase. The potential of the unselected word line (WL) of the selected sub-cell array during erase is VEWLL. The word line (WL) potential of the non - selected sub - cell array is VIWL.

[0103] VRBL is the bit line (BL) potential of the selected sub - cell array during readout. Depending on the method of biasing the bit line during readout, the data of the memory cell may vary slightly depending on whether it is "0" or "1". Here, it is assumed that a readout method is adopted in which a constant voltage VRBL is applied to the bit line (BL), and whether it is "0" or "1" is determined by the current value of the memory cell. VEBL is the bit line (BL) potential of the selected sub - cell array during erasure. VWBL is the bit line (BL) potential of the selected sub - cell array during "1" writing. According to this embodiment, since "0" writing only needs to maintain the state of the memory cell after erasure, the bit line (BL) potential and the source line (SL) potential of the selected sub - cell array during "0" writing are made the same and set to 0V so that no current flows. The source line (SL) potential of the selected sub - cell array is 0V when the memory cell is writing and reading. During erasure, it is set to the same potential as the bit line to suppress unnecessary power consumption. When the sub - cell array is in the idle state, the bit line (BL) and the source line (SL) potentials are floating without the need for biasing.

[0104] Specific examples of the potentials corresponding to FIG. 27 are shown in FIGS. 28(A) and 28(B). The meanings of the items "selected", "non - selected", "writing", "erasure", "readout", and "idle" in the table are the same as those in FIG. 27. The numerical values indicate the voltage values and the unit is volts (V). FIG. 28(A) assumes that one transistor constituting the memory cell is an NMOS transistor, and assumes the following operation mode. Writing is performed by flowing a current from the bit line (BL) to the source line (SL) which is at 0V, generating an impact ionization phenomenon by the word line (WL) potential, accumulating the generated hole(s) in the floating body, and discharging the generated electron(s) to the bit line. Erasure is performed by setting a bias condition such that the PN junction formed in the diffusion layer joining the floating body and the bit line or the source line is forward-biased, thereby discharging the hole(s) accumulated in the floating body to the bit line or the source line.

[0105] Depending on the amount of holes accumulated in the floating body, the potential of the floating body varies, and even when the same potential is applied to the word line as a bias, the current flowing from the bit line to the source line is different. Based on the above, it is determined whether the data of the memory cell is "1" or "0". In the idle state, the word line is biased to a potential such that the PN junction formed in the diffusion layer joining the floating body and the bit line or the source line is not forward-biased and is slightly reverse-biased so that the hole(s) (if any) accumulated in the floating body are not discharged.

[0106] FIG. 28(B) shows an example of voltage conditions when using the BTBT (Band to Band Tunneling) phenomenon (sometimes called the GIDL (Gate Induced Drain Leakage) phenomenon) instead of the impact ionization phenomenon to accumulate a group of holes in the floating body which is the storage node, assuming that one transistor constituting the memory cell is an NMOS transistor.

[0107] Operation waveform diagrams showing the features of the first embodiment are shown in FIGS. 5 to 17. In the waveform diagrams from FIGS. 5 to 17, the burst length is set to 8 (BL8). Fig. 5 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate a memory cell (group) with a bank address and a row address specified by ADr, an RD command is input to read a memory cell (group) with a bank address and a column address specified by ADc, and a PRE command is input to shift the memory cell (group) with the bank address and the row address specified by ADr, which is in an active state, to an idle state.

[0108] When the operation waveform shown in Fig. 5 is compared with the state transition diagram shown in Fig. 3, the following results. In the state transition diagram shown in Fig. 3, starting from the idle state indicated by 030, by receiving the ACT command input from an external device of the SDRAM at time T01 shown in the operation waveform diagram of Fig. 5, it transitions to the startup state indicated by 031 in the state transition diagram shown in Fig. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in Fig. 3 by an automatic sequence without a command. By receiving the RD command input from an external device of the SDRAM at time T04 shown in the operation waveform diagram of Fig. 5, it transitions to the read state indicated by 033 in the state transition diagram shown in Fig. 3. Further, by receiving the PRE command input from an external device of the SDRAM at time T07 shown in the operation waveform diagram of Fig. 5, it transitions to the precharge state indicated by 037 in the state transition diagram shown in Fig. 3, and then transitions to the idle state indicated by 030 in the state transition diagram of Fig. 3 by an automatic sequence without a command. Then, it receives the ACT command input from an external device of the SDRAM at time T08 shown in the operation waveform diagram of Fig. 5. This is the sequence.

[0109] When the operation waveform shown in Fig. 5 is compared with the state transition diagram of the first embodiment shown in Fig. 4, the following results. In the state transition diagram shown in FIG. 4, starting from the idle state indicated by 040, upon receiving the ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 5 and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram of FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. Upon receiving the RD command input from a device external to the SDRAM at time T04 shown in the operation waveform diagram of FIG. 5, it transitions to the read state indicated by 043 in the state transition diagram shown in FIG. 4. Further, upon receiving the PRE command input from a device external to the SDRAM at time T07 shown in the operation waveform diagram of FIG. 5 and the address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 045 in the state transition diagram shown in FIG. 4, and then transition to the idle state indicated by 040 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. At time T08 shown in the operation waveform diagram of FIG. 5, it receives the ACT command input from a device external to the SDRAM. However, the address signal input from a device external to the SDRAM in synchronization with the ACT command at time T08 shown in the operation waveform diagram of FIG. 5 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, and this is the sequence.

[0110] Furthermore, the operation waveforms of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment shown in FIG. 5 will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When receiving an ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 5, in the state transition diagram of FIG. 3, it transitions from the idle state indicated by 030 to the activation state indicated by 031. In the state transition diagram of FIG. 4, it transitions from the idle state indicated by 040 to the activation state indicated by 041. Synchronously with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 5 is received. In the operation waveform diagram of FIG. 5, it is indicated by ADr. The address receiver and address decoder shown as 112 in FIG. 1 discriminate the address signal from a device external to the SDRAM, and the word lines (WL) of the specified bank address and row address are selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the global word line and local word line driver shown as 134 in FIG. 2, biased from the potential VIWL to the potential VRWL at time T02. The potential of the word lines (WL) (group) of the addresses not specified by the ADr, the word lines (WL) (group) of the sub-cell array (group) remains at VIWL, being driven in a non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2 to be global word lines, and further by the global word line and local word line driver shown in 134 of FIG. 2.

[0111] The source lines (SL) (group) of the sub-cell array specified by the ADr are biased from the floating state to 0V at time T02. The bit lines (BL) (group) of the sub-cell array specified by the ADr are biased from the floating state, once passing through 0V, to the potential VRBL at time T02. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after discriminating whether the data is "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written into each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0112] At time T03 shown in the operation waveform diagram of FIG. 5 when the data storage into the data register is completed, the potential of the word line (WL) specified by the ADr is driven to VIWL, and the bit line(s) (BL) specified by the ADr in the sub-cell array starts discharging to 0V at time T03. Thereafter, the bit line(s) (BL) becomes floating together with the source line(s) (SL) specified by the ADr. It is considered that a transition has occurred to the active state indicated by 032 in the state transition diagram of FIG. 3 and the active state indicated by 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T04 shown in the operation waveform diagram of FIG. 5. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained. On the other hand, the data register(s) specified by the ADr holds the same data as the data held in the memory cell(s) specified by the ADr.

[0113] When an RD command input from a device external to the SDRAM is received at time T04 shown in the operation waveform diagram of FIG. 5 after the elapse of tRCD (ACT Command to internal read or write delay time) from the input of the ACT command, the data of the memory cell(s) of the bank address and column address specified by the address signal input in synchronization with the RD command and the ADc is read out to the device external to the SDRAM. In the state transition diagram of FIG. 3, it is the read state indicated by 033, and it transitions to the read state indicated by 043 in the state transition diagram of FIG. 4. After the CL (Column Latency) has elapsed since the reception of the RD command at time T04 shown in the operation waveform diagram of FIG. 5, data output starts from time T05 shown in the operation waveform diagram of FIG. 5. Since it is the BL8 setting, data is output 8 times. Substantially, among the data registers (group) specified by the ADr that hold the same data as the memory cell (group) specified by the ADr, the data of the data registers (group) specified by ADc and BL8 is read out to a device external to the SDRAM. Among the data registers (group) specified by the ADr, the data registers (group) other than the data registers (group) specified by ADc and BL8 are in a data holding state. From time T04 to time T07 shown in the operation waveform diagram of FIG. 5, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0114] At time T07 after the elapse of tRTP (Internal READ Command to PRECHARGE Command delay) from the input of the RD command, the input of the PRE command becomes possible. When the SDRAM according to the first embodiment receives the PRE command input from a device external to the SDRAM at time T07 shown in the operation waveform diagram of FIG. 5, it receives the address signal ADr input from the device external to the SDRAM in synchronization with the PRE command, and the sub-cell array specified by the address signal ADr becomes an idle state. From time T07 to time T08 shown in the operation waveform diagram of FIG. 5, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. In the state transition diagram of FIG. 3, it is considered that the transition has occurred to the precharge state indicated by 037, and in the state transition diagram of FIG. 4, the transition has occurred to the precharge state indicated by 045. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is reset. After that, by an automatic sequence without a command, in the state transition diagram of FIG. 3, it transitions from the precharge state indicated by 037 to the idle state indicated by 030, and in the state transition diagram of FIG. 4, it transitions from the precharge state indicated by 045 to the idle state indicated by 040. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr maintains the reset state.

[0115] It receives the ACT command input from a device external to the SDRAM at time T08 shown in the operation waveform diagram of FIG. 5. However, since the address signal received at time T08 shown in the operation waveform diagram of FIG. 5 is ADp, which is different from ADr, the memory cell(s) and data register(s) designated by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the ACT command and the address signal synchronized with the ACT command, after time T08 shown in the operation waveform diagram of FIG. 5, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, as for the SDRAM, it transitions from the idle state of 030 shown in the state transition diagram of FIG. 3 to the activation state of 031.

[0116] FIG. 6 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate the memory cell(s) of the bank address and row address designated by ADr, an RDA command is input to read the memory cell(s) of the bank address and column address designated by ADc, and then, by an automatic sequence without a command, the memory cell(s) of the bank address and row address designated by ADr, which are in the active state, transition to the idle state.

[0117] When the operation waveform shown in FIG. 6 is compared with the state transition diagram shown in FIG. 3, the following results are obtained. In the state transition diagram shown in FIG. 3, from the idle state indicated by 030, by receiving the ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 6, it transitions to the startup state indicated by 031 in the state transition diagram of FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram of FIG. 3 by an automatic sequence without a command. By receiving the RDA command input from a device external to the SDRAM at time T04 shown in the operation waveform diagram of FIG. 6, it transitions to the read state indicated by 035 in the state transition diagram of FIG. 3. After a predetermined time has elapsed since receiving the RDA command, it transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3 by an automatic sequence without a command, and further transitions to the idle state indicated by 030 in the state transition diagram of FIG. 3 by an automatic sequence without a command, and then receives the ACT command input from a device external to the SDRAM at time T08 shown in the operation waveform diagram of FIG. 6. This is the sequence.

[0118] When the operation waveform shown in FIG. 6 is compared with the state transition diagram of the first embodiment shown in FIG. 4, the following results are obtained. In the state transition diagram shown in FIG. 4, from the idle state indicated by 040, upon receiving the ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 6 and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram of FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram of FIG. 4 by an automatic sequence without a command. Upon receiving the RDA command input from a device external to the SDRAM at time T04 shown in the operation waveform diagram of FIG. 6, it transitions to the read state indicated by 044 in the state transition diagram of FIG. 4. After a predetermined time has elapsed, by an automatic sequence without a command, the memory cell(s) and data register(s) specified by the ADr at time T04 shown in the operation waveform diagram of FIG. 6 transition to the precharge state indicated by 045 in the state transition diagram of FIG. 4, and then transition to the idle state indicated by 040 in the state transition diagram of FIG. 4 by an automatic sequence without a command. At time T08 shown in the operation waveform diagram of FIG. 6, it receives the ACT command input from a device external to the SDRAM. However, the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T08 shown in the operation waveform diagram of FIG. 6 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4, and this is the sequence.

[0119] Furthermore, the operation waveforms of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment shown in FIG. 6 will be described in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When receiving the ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 6, in the state transition diagram of FIG. 3, it transitions from the idle state indicated by 030 to the startup state indicated by 031. In the state transition diagram of FIG. 4, it transitions from the idle state indicated by 040 to the startup state indicated by 041. Synchronously with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time T01 shown in the operation waveform diagram of FIG. 6. In the operation waveform diagram of FIG. 6, it is indicated by ADr. The address receiver and address decoder shown as 112 in FIG. 1 discriminate the address signal from the device external to the SDRAM, and the word lines (WL) of the designated bank address and row address are selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the global word line and local word line driver shown as 134 in FIG. 2, they are biased from the potential VIWL to the potential VRWL at time T02. The potential of the word lines (WL) (group) of the addresses not designated by the ADr and the word lines (WL) (group) of the sub-cell array (group) are driven to a non-selective state by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the global word line and local word line driver shown as 134 in FIG. 2, the potential remains at VIWL.

[0120] The source lines (SL) (group) of the sub-cell array designated by the ADr are biased from a floating state to 0V at time T02 shown in the operation waveform diagram of FIG. 6. The bit lines (BL) (group) of the sub-cell array designated by the ADr are biased from a floating state, once passing through 0V, to the potential VRBL at time T02 shown in the operation waveform diagram of FIG. 6. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell (group) designated by the ADr is copied to the data register (group) designated by the ADr.

[0121] When the data storage to the data register is completed, at time T03 shown in the operation waveform diagram of FIG. 6, the potential of the word line (WL) designated by the ADr is driven to VIWL, and the bit line (BL) (group) of the sub-cell array designated by the ADr starts to discharge to 0V. Thereafter, the bit line (BL) (group) becomes floating together with the source line (SL) (group) designated by the ADr. It means that the state has shifted to the active state indicated by 032 in the state transition diagram of FIG. 3 and the active state indicated by 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T04 shown in the operation waveform diagram of FIG. 6. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register (group) designated by the ADr holds the same data as the data held by the memory cell (group) designated by the ADr.

[0122] When an RDA command is input from a device external to the SDRAM at time T04 shown in the operation waveform diagram of FIG. 6 after the elapse of tRCD (ACT Command to internal read or write delay time) from the input of the ACT command, the data of the memory cell (group) of the address signal, bank address, and column address input in synchronization with the RDA command and designated by the ADc is read out to the device external to the SDRAM. It means that the state has shifted to the read state indicated by 035 in the state transition diagram of FIG. 3 and the read state indicated by 044 in the state transition diagram of FIG. 4 in light of the state transition diagram of FIG. 4. After the elapse of CL (Column Latency) from the reception of the RDA command at time T04 shown in the operation waveform diagram of FIG. 6, data output starts from time T05 shown in the operation waveform diagram of FIG. 6. Since it is BL8 setting, data is output eight times. Substantially, among the data register(s) specified by the ADr that hold the same data as the memory cell(s) specified by the ADr, the data of the data register(s) specified by being ADc and BL8 is read out to a device external to the SDRAM. Among the data register(s) specified by the ADr, data registers(s) other than the data register(s) specified by being ADc and BL8 are in a data holding state. From time T04 to time T07 shown in the operation waveform diagram of FIG. 6, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0123] After receiving the RDA command, at time T07 shown in the operation waveform diagram of FIG. 6 after tRTP (Internal READ Command to PRECHARGE Command delay) has elapsed, the sub-cell array specified by the ADr becomes idle by the automatic sequence in the SDRAM. From time T07 to time T08 shown in the operation waveform diagram of FIG. 6, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. As the state transition diagram, it has transitioned to the precharge state of 037 in FIG. 3 and the precharge state of 045 in FIG. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Thereafter, by the automatic sequence without a command, it transitions from the precharge state indicated by 037 in the state transition diagram of FIG. 3 to the idle state indicated by 030, and from the precharge state indicated by 045 in the state transition diagram of FIG. 4 to the idle state indicated by 040. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr maintains a reset state.

[0124] It receives an ACT command input from an external device of the SDRAM at time T08 shown in the operation waveform diagram of FIG. 6. However, since the address signal received at time T08 shown in the operation waveform diagram of FIG. 6 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as an address signal synchronized with the ACT command, after time T08 shown in the operation waveform diagram of FIG. 6, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. However, as for the SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the startup state 031.

[0125] FIG. 7 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate the memory cell(s) of the bank address and row address specified by ADr, a WR command is input to write to the memory cell(s) of the bank address and column address specified by ADc, and a PRE command is input to transition the memory cell(s) of the bank address and row address specified by ADr, which are in the active state, to the idle state.

[0126] When the operation waveform shown in FIG. 7 is compared with the state transition diagram shown in FIG. 3, the following results. In the state transition diagram shown in FIG. 3, starting from the idle state indicated by 030, by receiving the ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 7, it transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. By receiving the WR command input from a device external to the SDRAM at time T14 shown in the operation waveform diagram of FIG. 7, it transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3. Further, by receiving the PRE command input from a device external to the SDRAM at time T19 shown in the operation waveform diagram of FIG. 7, it transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3, and then transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. Furthermore, it is a sequence of receiving the ACT command input from a device external to the SDRAM at time T22 shown in the operation waveform diagram of FIG. 7.

[0127] When the operation waveform shown in FIG. 7 is compared with the state transition diagram of the first embodiment shown in FIG. 4, it is as follows. In the state transition diagram shown in FIG. 4, starting from the idle state indicated by 040, upon receiving the ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 7 and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. Upon receiving the WR command input from a device external to the SDRAM at time T14 shown in the operation waveform diagram of FIG. 7, they transition to the write state indicated by 046 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 047 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. Upon receiving the PRE command input from a device external to the SDRAM at time T19 shown in the operation waveform diagram of FIG. 7 and the address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and further transition to the idle state indicated by 040 in the state transition diagram shown in FIG. 4 via the precharge state indicated by 045 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. At time T22 shown in the operation waveform diagram of FIG. 7, it receives the ACT command input from a device external to the SDRAM. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T22 shown in the operation waveform diagram of FIG. 7 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, which is the sequence described above.

[0128] Furthermore, the operation waveforms of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment are described in reference to the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When receiving an ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 7, in the state transition diagram of FIG. 3, it transitions from the idle state indicated by 030 to the startup state indicated by 031. In the state transition diagram of FIG. 4, it transitions from the idle state indicated by 040 to the startup state indicated by 041.

[0129] Synchronized with the timing of receiving the ACT command, at time T11 shown in the operation waveform diagram of FIG. 7, an address signal is received as an input signal from a device external to the SDRAM. In the operation waveform diagram of FIG. 7, it is indicated by ADr. The address receiver and address decoder shown as 112 in FIG. 1 discriminate the address signal from a device external to the SDRAM, and the word lines (WL) of the specified bank address and row address are selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, biased from the potential VIWL to the potential VRWL at time T12 shown in the operation waveform diagram of FIG. 7. The potential of the word lines (WL) (group) of the addresses not specified by the ADr and the word lines (WL) (group) of the sub-cell array (group) remains at VIWL, being driven to a non-select state by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line.

[0130] The source lines (SL) (group) of the sub-cell array specified by the ADr are biased from a floating state to 0V at time T12 shown in the operation waveform diagram of FIG. 7. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T12 shown in the operation waveform diagram of FIG. 7, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0131] At time T13 shown in the operation waveform diagram of FIG. 7 when the data storage in the data register is completed, the potential of the word line (WL) designated by the ADr is driven to the potential VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V, and then the bit line(s) (BL) becomes floating together with the source line(s) (SL) designated by the ADr. It means that the state transitions to the active state shown as 032 in the state transition diagram of FIG. 3 and the active state shown as 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T15 shown in the operation waveform diagram of FIG. 7. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0132] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), at time T14 shown in the operation waveform diagram of FIG. 7, when receiving the first WR command from a device external to the SDRAM after receiving the ACT command, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr that is input in synchronization with the ACT command. It means that the writing state shown as 034 in the state transition diagram of FIG. 3 and the writing state shown as 046 in the state transition diagram of FIG. 4 are entered.

[0133] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the global word line selected by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 from time T15 shown in the operation waveform diagram of FIG. 7, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the sub-cell array is in a selected state and the non-selected word line(s) are driven to a non-selected state by the row decoder global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 from time T15 shown in the operation waveform diagram of FIG. 7, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2, and remain at the potential VIWL.

[0134] The source line(s) and bit line(s) of the sub-cell array designated by the ADr are biased to the potential VEBL from the floating state starting from time T15 shown in the operation waveform diagram of FIG. 7 as well. On the other hand, the source line(s) and bit line(s) of the sub-cell array not designated by the ADr remain in the floating state.

[0135] With the above potential settings, depending on the potential relationships between the respective floating bodies of the memory cell(s) connected to the word lines of the bank address and row address designated by the ADr, the bit lines, and the source lines, if holes (group) were accumulated in the floating body, the holes (group) are released. Depending on the potential relationships, electrons (group) may also be injected. Including the memory cell(s) in which holes (group) were not originally accumulated in the floating body, the memory cell(s) connected to the word lines of the bank address and row address designated by the ADr become in a state where holes (group) are not accumulated in the floating body, and are thus erased. At this point, the data held by the memory cell(s) designated by the ADr is erased. However, in the SDRAM according to the first embodiment, after receiving the PRE command, the data remaining after being copied to the data register(s) designated by the ADr is rewritten to the memory cell(s), so data loss of the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word lines of the bank address and row address not designated by the ADr, the memory cell(s) belonging to the non-selected sub-cell array are in the idle state, and the potential relationships between the respective floating bodies of the memory cell(s) connected to the non-selected word line(s) where the sub-cell array is in the selected state, the bit lines, and the source lines are almost the same as in the idle state, so the charge of the floating body is maintained.

[0136] To end the erasure operation, the source line(s) and bit line(s) of the sub-cell array specified by the ADr start discharging to 0V at time T16 after the elapse of the time set inside the SDRAM device from time T15 shown in the operation waveform diagram of FIG. 7. Thereafter, the bit line(s) (BL) enter a floating state together with the source line(s) (SL) specified by the ADr. The potential of the word line of the sub-cell array specified by the ADr is biased from VEWLH or VEWLL to VIWL at time T16 shown in the operation waveform diagram of FIG. 7, and the sub-cell array specified by the ADr enters an idle state. The potential of each word line, the state of each bit line, and the state of each source line continue until time T20 shown in the operation waveform diagram of FIG. 7. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0137] After receiving the WR command, from time T17 after a predetermined time has elapsed (CWL; CAS Write Latency), since the burst length is 8 (BL8), as shown in the operation waveform diagram of FIG. 7, eight sets of data are sequentially input from the DQ signal line in FIG. 1. After the input data is sensed and amplified by the data input receiver shown in 118 of FIG. 1, it is stored in the data input register shown in 119 of FIG. 1. After storage, from the data input register shown in 119 of FIG. 1, the IO driver shown in 123 of FIG. 1 writes to the data register of the address specified by ADc that is input in synchronization with the WR command and exists in 133 of FIG. 2 associated with the sub-cell array of the address specified by ADr. The above operations for the WR command are the same as those of a clock-synchronous dynamic semiconductor memory device using a memory cell composed of one transistor and one capacitor. However, in a clock-synchronous dynamic semiconductor memory device using a memory cell composed of one transistor and one capacitor, the input data is written into the memory cell (group) of the address specified by ADr, ADc, and BL8, whereas in the clock-synchronous dynamic semiconductor memory device of the present embodiment, no writing is performed on the memory cell (group), and the input data is only written into the data register (group) that is specified by ADc and BL8 and exists in 133 of FIG. 2 among the data register (group) specified by ADr. Therefore, among the data register (group) specified by ADr, the data register not specified by ADc and further BL8 holds the same data as the memory cell that can be connected to the same bit line (BL) specified by ADr.

[0138] During data input, no writing is performed on the memory cells. Therefore, at time T16 shown in the operation waveform diagram of FIG. 7, the potential of the selected word line has started to be biased to VIWL, and the potentials of the selected bit lines and source lines have been discharged to 0V and then are in a floating state. Each non-selected word line is in a state biased to VIWL, and the non-selected bit lines and non-selected source lines have also been discharged to 0V at some previous stage and then are in a floating state. The potentials of the word lines, the states of the bit lines and source lines continue until time T20 shown in the operation waveform diagram of FIG. 7.

[0139] Data is input from an external device of the SDRAM via the DQ signal line. After the input signal is sensed and amplified by the data input receiver shown in 118 of FIG. 1, it is stored in the data input register shown in 119 of FIG. 1. After storage, from the data input register shown in 119 of FIG. 1, by the IO driver shown in 123 of FIG. 1, writing is performed on the data register existing in 133 of FIG. 2, which is specified by ADc and further BL8 among the data register(s) specified by ADr. The process of performing an erase operation on the memory cell(s) connected to the word lines of the bank address and row address specified by ADr is performed in parallel, and the operations of each other are independent. Therefore, depending on the set value of CWL (CAS Write Latency) and the period of the clock, the timings of the start time of the erase operation and the start time of data input may be before or after each other, and there is no problem even if they are before or after each other. The timings of the end time of the erase operation and the completion time of data input may also be before or after each other, and there is no problem even if they are before or after each other. When both the writing operation of the input data to the data register specified by ADr and ADc and the erase operation of the memory cell(s) connected to the word lines of the bank address and row address specified by ADr are completed, according to the automatic sequence, in the state transition diagram shown in FIG. 3, it has transitioned to the active state of 032, and in the state transition diagram shown in FIG. 4, it has transitioned to the active state of 047. Each memory cell specified by the ADr maintains an erased state. Among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and have not been written retain the data they held before the memory cell(s) specified by the ADr were erased. Among the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and further by BL8 and have been written retain the written data.

[0140] The fact that there is no inconvenience due to the data not being completely written to the memory cell will be described when explaining the operation waveforms of FIGS. 9 and 10 for the SDRAM according to the first embodiment.

[0141] After data input, at time T19 after the elapse of tWR (Write Recovery Time), the PRE command can be input. When the SDRAM according to the first embodiment receives a PRE command at time T19 shown in the operation waveform diagram of FIG. 7, it starts a write operation to the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr for the data in the data register(s) specified by the ADr. In the state transition diagram of FIG. 3, it has transitioned to the precharge state shown as 037, and in the state transition diagram of FIG. 4, it has transitioned to the precharge state shown as 053. Since substantially "0" data has already been written by the erase operation, in the write sequence here, a "1" is written to the memory cell(s) corresponding to the data register that holds "1" data, and the state where "0" data has already been written is maintained for the memory cells corresponding to the data register that holds "0" data.

[0142] The potential of the word line (WL) of the bank address and row address specified by the ADr is selected and driven by the row decoder and global word line driver shown in 130 of FIG. 2, and further by the global word line and local word line driver, and is biased from the potential VIWL to the potential VWWLH at the time T20 shown in the operation waveform diagram of FIG. 7. Among the word lines (groups) not specified by the ADr, the sub-cell array is in a selected state, and the non-selected word lines (groups) are driven to a non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2, and by the global word line and local word line driver, and are biased from the potential VIWL to the potential VWWLL at the time T20 shown in the operation waveform diagram of FIG. 7. The word lines (groups) belonging to the sub-array of the address not specified by the ADr are driven to a non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2, and further by the global word line and local word line driver, and remain at the potential VIWL. The source line (group) of the sub-cell array specified by the ADr is biased from a floating state to 0V at the time T20 shown in the operation waveform diagram of FIG. 7. The potential of the bit line (group) of the sub-cell array specified by the ADr is biased according to the data stored in the data register (group) corresponding to the bit line (group). When the data in the data register is "0", the bit line (BL) is biased from a floating state to 0V at the time T20. When the data in the data register is "1", the bit line (BL) is biased from a floating state to the potential VWBL at the time T20. On the other hand, the source line (group) and bit line (group) of the sub-cell array not specified by the ADr remain in a floating state.

[0143] With the above potential setting, among the memory cell(s) connected to the word line of the bank address and row address specified by the ADr, the memory cell in which the VWBL is biased to the bit line (BL) allows current to flow, causing the impact ionization phenomenon. The hole(s) generated by the impact ionization phenomenon accumulate in the floating body of the memory cell, and the electron(s) generated by the same impact ionization phenomenon are discharged to the bit line (BL), indicating that data "1" has been written to the memory cell. On the other hand, the memory cell with 0V biased to the bit line (BL) does not allow current to flow because the potentials of the bit line (BL) and the source (line) are the same. Therefore, the impact ionization phenomenon does not occur, and the floating body of the memory cell maintains the erased state, indicating that data "0" has been written. That is, data is read from each data register specified by the ADr, and the read data is written to each memory cell specified by the ADr corresponding to the data register. In addition to the data written by the WR command, the data lost during the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cell due to the erase operation.

[0144] Among the memory cell(s) connected to the word line of the bank address and row address not specified by ADr, the memory cell connected to the non-selected word line(s) in the selected sub-cell array is not in a state of conducting current due to the potential relationship between the word line and the source line, so the impact ionization phenomenon does not occur, and the accumulation of holes in the floating body does not occur. Also, if the device design and manufacturing of the memory cell are appropriately carried out, due to the potential relationship between the floating body, bit line, and word line of the memory cell, the BTBT (Band to Band Tunneling) phenomenon (which may be called the GIDL (Gate Induced Drain Leakage) phenomenon) does not occur, and the accumulation of holes in the floating body does not occur. Further, due to the potential relationship between the word line, floating body, and bit line of the memory cell, holes are not emitted to the bit line or the source line. Based on the above, among the memory cell(s) connected to the word line of the bank address and row address not specified by ADr, the charge of the floating body of each memory cell connected to the non-selected word line(s) in the selected sub-cell array is maintained.

[0145] Since the memory cell(s) connected to the word line of the bank address and row address not specified by ADr is in an idle state, the state of the floating body of each memory cell is maintained.

[0146] To end the writing operation, at time T21 after the elapse of the time set inside the SDRAM device from time T20 shown in the operation waveform diagram of FIG. 7, the source line(s) and bit line(s) of the sub-cell array specified by ADr are set to a floating state. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T21. The potential of each word line, each bit line, and each source line state continue until time T22 shown in the operation waveform diagram of FIG. 7. By an automatic sequence without a command, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the state transition diagram of FIG. 3, it stays in the precharge state shown as 037. The state of the floating body of each memory cell designated by the ADr is maintained, and the data register designated by the ADr is reset. Furthermore, by an automatic sequence without a command, it transitions to the idle state shown as 030 in the state transition diagram of FIG. 3 and the idle state shown as 040 in the state transition diagram of FIG. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr maintains the reset state.

[0147] It receives the ACT command input from a device external to the SDRAM at time T22 shown in the operation waveform diagram of FIG. 7. However, since the address signal received at time T22 shown in the operation waveform diagram of FIG. 7 is ADp, which is different from ADr, the memory cell(s) and data register(s) designated by ADr stay in the idle state shown as 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the ACT command and the address signal synchronized with the ACT command, after time T22 shown in the operation waveform diagram of FIG. 7, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, as for the SDRAM, it transitions from the idle state of 030 shown in the state transition diagram of FIG. 3 to the active state of 031.

[0148] FIG. 8 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate the memory cell(s) of the bank address and row address designated by ADr, a WRA command is input to write to the memory cell(s) of the bank address and column address designated by ADc, and then, by an automatic sequence without a command, the memory cell(s) of the bank address and row address designated by ADr, which are in the active state, transition to the idle state.

[0149] When the operation waveform shown in FIG. 8 is compared with the state transition diagram shown in FIG. 3, the following results are obtained. In the state transition diagram shown in FIG. 3, from the idle state indicated by 030, by receiving the ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 8, the state transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram of FIG. 3 by an automatic sequence without a command. By receiving the WRA command input from a device external to the SDRAM at time T14 shown in the operation waveform diagram of FIG. 8, the state transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3. After a predetermined time has elapsed since receiving the data input from a device external to the SDRAM, it transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3 by an automatic sequence, and then transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. This is the sequence of receiving the ACT command input from a device external to the SDRAM at time T22 shown in the operation waveform diagram of FIG. 8.

[0150] When the operation waveform shown in FIG. 8 is compared with the state transition diagram of the first embodiment shown in FIG. 4, the following results are obtained. In the state transition diagram shown in FIG. 4, starting from the idle state indicated by 040, when the ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 8 and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command are received, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. When the WRA command input from a device external to the SDRAM at time T14 shown in the operation waveform diagram of FIG. 8 is received, the state transitions to the write state indicated by 050 in the state transition diagram shown in FIG. 4. After a predetermined time has elapsed, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and then, via the precharge state indicated by 045 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command, the memory cell(s) and data register(s) specified by the ADr transition to the idle state indicated by 040 in the state transition diagram shown in FIG. 4. At time T22 in the operation waveform diagram shown in FIG. 8, the ACT command input from a device external to the SDRAM is received. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T22 shown in the operation waveform diagram of FIG. 8 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by the ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, and this is the sequence.

[0151] Furthermore, the operation waveforms of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment shown in FIG. 8 will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When receiving an ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 8, in the state transition diagram of FIG. 3, it transitions from the idle state indicated by 030 to the activation state indicated by 031. In the state transition diagram of FIG. 4, it transitions from the idle state indicated by 040 to the activation state indicated by 041.

[0152] Synchronized with the timing of receiving the ACT command, at time T11 shown in the operation waveform diagram of FIG. 8, an address signal is received as an input signal from a device external to the SDRAM. In the operation waveform diagram of FIG. 8, it is indicated by ADr. The address signal from a device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in FIG. 1, and the word lines (WL) of the designated bank address and row address are selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, biased from the potential VIWL to the potential VRWL at time T12 shown in the operation waveform diagram of FIG. 8. The potential of the word lines (WL) (group) of the addresses not designated by the ADr, the word lines (WL) (group) of the sub-cell array (group) remains at VIWL, which is driven to a non-selective state by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line.

[0153] The source lines (SL) (group) of the sub-cell array designated by the ADr are biased from the floating state to 0V at time T12 shown in the operation waveform diagram of FIG. 8. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T12 shown in the operation waveform diagram of FIG. 8, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0154] At time T13 shown in the operation waveform diagram of FIG. 8 when the data storage in the data register is completed, the potential of the word line (WL) designated by the ADr is driven to the potential VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V, and then the bit line(s) (BL) becomes a floating state together with the source line(s) (SL) designated by the ADr. It means that it has shifted to the active state shown as 032 in the state transition diagram of FIG. 3 and the active state shown as 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T15 shown in the operation waveform diagram of FIG. 8. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0155] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), at time T14 shown in the operation waveform diagram of FIG. 8, when a WRA command is received from a device external to the SDRAM without ever receiving a WR command after receiving the ACT command, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr that is input in synchronization with the ACT command. When compared with the state transition diagram, in the state transition diagram shown in FIG. 3, it has transitioned to the write state of 036, and in the state transition diagram shown in FIG. 4, it has transitioned to the write state of 050.

[0156] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the global word line selected by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, from time T15 shown in the operation waveform diagram of FIG. 8, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the sub-cell array is in a selected state, and the non-selected word line(s) are driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2 and the global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, also from time T15 shown in the operation waveform diagram of FIG. 8, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2 and the global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, and remain at the potential VIWL.

[0157] The source line(s) and bit line(s) of the sub-cell array designated by the ADr are biased to the potential VEBL from the floating state starting from time T15 shown in the operation waveform diagram of FIG. 8 as well. On the other hand, the source line(s) and bit line(s) of the sub-cell array not designated by the ADr remain in the floating state.

[0158] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the memory cell(s) connected to the word line of the bank address and row address designated by the ADr are erased. At this point, the data held by the memory cell(s) designated by the ADr is erased. However, the SDRAM according to the first embodiment, after transitioning to the state 053 shown in the state transition diagram of FIG. 4, rewrites the data remaining after being copied to the data register(s) designated by the ADr into the memory cell(s), so that the loss of data in the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word line of the bank address and row address not designated by the ADr, the memory cell(s) belonging to the non-selected sub-cell array are in the idle state, and the potential relationship between the floating body of each memory cell(s) connected to the non-selected word line(s) where the sub-cell array is in the selected state and the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0159] To end the erasing operation, starting from time T15 shown in the operation waveform diagram of FIG. 8, the source line(s) and bit line(s) of the sub-cell array designated by the ADr start to discharge to 0V at time T16 after the elapse of the time set inside the SDRAM device, and then become floating. The potential of the word line of the sub-cell array designated by the ADr is biased from VEWLH or VEWLL to VIWL at time T16 shown in the operation waveform diagram of FIG. 8, and the sub-cell array designated by the ADr becomes idle. The potential of each word line, and the states of each bit line and each source line continue until time T20 shown in the operation waveform diagram of FIG. 7. Accordingly, the state of the floating body of each memory cell designated by the ADr is maintained.

[0160] From time T17 after a predetermined time has elapsed (CWL; CAS Write Latency) since receiving the WRA command, since the burst length is 8 (BL8), as shown in the operation waveform diagram of FIG. 8, eight sets of data are sequentially input from the DQ signal line in FIG. 1. The input data is sense-amplified by the data input receiver shown in 118 of FIG. 1 and then stored in the data input register shown in 119 of FIG. 1. After storage, from the data input register shown in 119 of FIG. 1, writing is performed to the data register existing in 133 of FIG. 2, which is designated by the ADc and BL8 among the data register(s) designated by the ADr, by the IO driver shown in 123 of FIG. 1. On the other hand, among the data register(s) designated by the ADr, the data register not designated by the ADc and further BL8 holds the same data as the memory cells connectable to the same bit line (BL) designated by the ADr.

[0161] During data input, since writing to the memory cells is not performed, at time T16 shown in the operation waveform diagram of FIG. 8, the potential of the selected word line starts to be biased to VIWL, and the potentials of the selected bit lines and source lines are discharged to 0V and then in a floating state. Each non-selected word line is biased to VIWL, and the non-selected bit lines and non-selected source lines are also in a floating state after being discharged to 0V at some previous stage. The potential of each word line, and the states of each bit line and each source line continue until time T20 shown in the operation waveform diagram of FIG. 8.

[0162] As described in the explanation of the operation waveform of FIG. 7, the operation of writing the input data to the data register(s) specified by the ADr and further specified by the ADc and BL8, which is the region shown by 133 in FIG. 2, and the erasing operation on the memory cell(s) connected to the word line of the bank address and row address specified by the ADr are performed in parallel and independently. Therefore, depending on the set value of CWL (CAS Write Latency) and the period of the clock, the timings of the erasing operation start time and the data input start time may be before or after each other, and there is no problem even if they are before or after each other. The timings of the erasing operation end time and the data input completion time may also be before or after each other, and there is no problem even if they are before or after each other. When both the operation of writing the input data to the data register specified by the ADr and the ADc and the erasing operation on the memory cell(s) connected to the word line of the bank address and row address specified by the ADr are completed, according to the automatic sequence, in the state transition diagram shown in FIG. 3, it will transition to the active state of 032, and in the state transition diagram shown in FIG. 4, it will transition to the active state of 047. Each memory cell specified by the ADr maintains the erased state. Among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and further BL8 and for which writing has not been performed hold the data that they held before the memory cell(s) specified by the ADr were erased. Among the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and further BL8 and for which writing has been performed hold the written data.

[0163] The fact that there is no inconvenience due to the data not being completely written to the memory cell will be described when explaining the operation waveforms of FIGS. 9 and 10 for the SDRAM according to the first embodiment.

[0164] After the data input is completed, at time T19 after the elapse of tWR (Write Recovery Time), even if no PRE command is input, the SDRAM automatically transitions to the precharge state shown as 037 in the state transition diagram of FIG. 3 in accordance with the SDRAM specification. The SDRAM according to the first embodiment causes the memory cell(s) and data register(s) specified by the ADr to transition to the precharge state shown as 053 in FIG. 4. That is, at time T19 shown in the operation waveform diagram of FIG. 8, the writing operation to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr for the data in the data register(s) specified by the ADr is started. Since "0" data has already been substantially written by the erasing operation, in the writing sequence here, "1" is written to the memory cell(s) corresponding to the data register that holds "1" data, and the state where "0" data is already written is maintained for the memory cells corresponding to the data registers that hold "0" data.

[0165] The potential of the word line (WL) of the bank address and row address specified by the ADr is selected and driven by the row decoder and global word line driver shown in 130 of FIG. 2 to be the global word line, and further by the global word line and local word line driver, it is biased from the potential VIWL to the potential VWWLH at time T20 shown in the operation waveform diagram of FIG. 8. Among the word line(s) not specified by the ADr, the sub-cell array is in the selected state and the non-selected word line(s) are driven to the non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2 to be the global word line and local word line driver, and are biased from the potential VIWL to the potential VWWLL at time T20 shown in the operation waveform diagram of FIG. 8. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to the non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2 to be the global word line, and further by the global word line and local word line driver, and remain at the potential VIWL. The source line(s) of the sub-cell array specified by the ADr is biased from the floating state to 0V at time T20 shown in the operation waveform diagram of FIG. 8. The bit line(s) of the sub-cell array specified by the ADr is biased in potential according to the data stored in the data register(s) corresponding to the bit line(s). When the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T20. When the data in the data register is "1", the bit line (BL) is biased from the floating state to the potential VWBL at time T20. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0166] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, among the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr, the memory cell(s) to which VWBL is biased on the bit line (BL) has data "1" written therein. On the other hand, for the memory cell(s) to which 0V is biased on the bit line (BL), the floating body of each memory cell maintains the erased state, and it is considered that data "0" has been written. That is, data is read from each data register specified by the ADr, and the read data is written into each memory cell specified by the ADr corresponding to the data register. In addition to the data written by the WR command or WRA command, the data lost by the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cell due to the erase operation. Since the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr is in the idle state, the state of the floating body of each memory cell is maintained.

[0167] In order to end the write operation, after the time T21 which is the time elapsed after being set inside the SDRAM device from the time T20 shown in the operation waveform diagram of FIG. 8, the source line(s) and bit line(s) of the sub-cell array designated by the ADr are set to a floating state. The potential of the word line of the sub-cell array designated by the ADr is biased from VWWLH or VWWLL to 0V at the time T21. The potential of each word line, the state of each bit line, and each source line continue until the time T22 shown in the operation waveform diagram of FIG. 8. By an automatic sequence without a command, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the state transition diagram of FIG. 3, it stays in the precharge state shown as 037. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is reset. Furthermore, by an automatic sequence without a command, it transitions to the idle state shown as 030 in the state transition diagram of FIG. 3 and the idle state shown as 040 in the state transition diagram of FIG. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr maintains the reset state.

[0168] It receives the ACT command input from a device external to the SDRAM at the time T22 shown in the operation waveform diagram of FIG. 8. However, since the address signal received at the time T22 shown in the operation waveform diagram of FIG. 8 is ADp, which is different from ADr, the memory cell(s) and data register(s) designated by the ADr stay in the idle state shown as 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the ACT command and the address signal synchronized with the ACT command, after the time T22 shown in the operation waveform diagram of FIG. 8 as well, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, as for the SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the activation state 031.

[0169] Fig. 9 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate a memory cell (group) with a bank address and a row address specified by ADr, writing is performed to a memory cell (group) with a bank address and a column address specified by ADc, reading is then performed from a memory cell (group) with an address specified by ADd which has the same bank address as ADc but a different column address, and a PRE command is input to shift the memory cell (group) with the bank address and row address specified by ADr, which is in the active state, to the idle state. The operation waveform diagram shown in Fig. 10 is different from the operation waveform diagram shown in Fig. 9. It is an operation waveform diagram in which, after writing to a memory cell (group) with a bank address and a column address specified by ADc, reading is performed from the memory cell (group) with the same bank address and column address specified by ADc. The difference between the operation waveform diagram shown in Fig. 9 and the operation waveform diagram shown in Fig. 10 is only that the column address input in synchronization with the WR command and the column address input in synchronization with the RD command are different (Fig. 9) or the same (Fig. 10). Therefore, the descriptions of the operation waveform diagram shown in Fig. 9 and the operation waveform diagram shown in Fig. 10 are given together.

[0170] When the operation waveforms shown in Figs. 9 and 10 are compared with the state transition diagram shown in Fig. 3, the following results are obtained. In the state transition diagram shown in FIG. 3, by receiving the ACT command input from a device external to the SDRAM at time T31 in the operation waveform diagrams shown in FIGS. 9 and 10 from the idle state indicated by 030, the state transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. By receiving the WR command input from a device external to the SDRAM at time T34 in the operation waveform diagrams shown in FIGS. 9 and 10, the state transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3. Further, by receiving the RD command input from a device external to the SDRAM at time T39 shown in FIGS. 9 and 10, the state transitions to the read state of 033 in the state transition diagram shown in FIG. 3. By receiving the PRE command input from a device external to the SDRAM at time T42 in the operation waveform diagrams shown in FIGS. 9 and 10, the state transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3, and then transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. This is the sequence of receiving the ACT command input from a device external to the SDRAM at time T45 in the operation waveform diagrams shown in FIGS. 9 and 10.

[0171] When the operation waveforms shown in FIGS. 9 and 10 are compared with the state transition diagram of the first embodiment shown in FIG. 4, the following results are obtained. The operation waveforms shown in FIGS. 9 and 10 start from the idle state indicated by 040 in the state transition diagram shown in FIG. 4. By receiving the ACT command input from a device external to the SDRAM at time T31 shown in FIGS. 9 and 10 and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the WR command input from a device external to the SDRAM at time T34 shown in FIGS. 9 and 10, it transitions to the write state indicated by 046 in the state transition diagram shown in FIG. 4, and then transitions to the active state indicated by 047 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the RD command input from a device external to the SDRAM at time T39 shown in the operation waveform diagrams of FIGS. 9 and 10, it transitions to the read state indicated by 048 in the state transition diagram shown in FIG. 4. By receiving the PRE command input from a device external to the SDRAM at time T42 shown in the operation waveform diagrams of FIGS. 9 and 10, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and further, by an automatic sequence without a command, it passes through the precharge state indicated by 045 in the state transition diagram shown in FIG. 4 and transitions to the idle state indicated by 040 in the state transition diagram shown in FIGS. 9 and 10. At time T45 shown in the operation waveform diagrams of FIGS. 9 and 10, it receives the ACT command input from a device external to the SDRAM. However, the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T45 shown in the operation waveform diagrams of FIGS. 9 and 10 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by the ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, which is the sequence described above.

[0172] Furthermore, the operation waveforms shown in FIGS. 9 and 10 of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When the ACT command input from the external device of the SDRAM is received at time T31 shown in the operation waveform diagrams of FIGS. 9 and 10, in the state transition diagram of FIG. 3, the transition is made from the idle state indicated by 030 to the activation state indicated by 031. In the state transition diagram of FIG. 4, the transition is made from the idle state indicated by 040 to the activation state indicated by 041.

[0173] Synchronized with the timing of receiving the ACT command, an address signal is received as an input signal from the external device of the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 9 and 10. In the operation waveform diagrams of FIGS. 9 and 10, it is indicated by ADr. The address signal from the external device of the SDRAM is discriminated by the address receiver and address decoder shown as 112 in FIG. 1, and the word line (WL) of the specified bank address and row address is selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be a global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, at time T32 shown in the operation waveform diagrams of FIGS. 9 and 10, it is biased from the potential VIWL to the potential VRWL. The potential of the word line (WL) (group) of the address not specified by the ADr and the word line (WL) (group) of the sub-cell array (group) is driven to be in a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2 to be a global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, and remains at VIWL.

[0174] The source line (SL) (group) of the sub-cell array specified by the ADr is biased from the floating state to 0V at time T32 shown in the operation waveform diagrams of FIGS. 9 and 10. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T32 shown in the operation waveform diagrams of FIGS. 9 and 10, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0175] At time T33 shown in the operation waveform diagrams of FIGS. 9 and 10 when the data storage into the data register is completed, the potential of the word line (WL) designated by the ADr is driven to the potential VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V, and then the bit line(s) (BL) becomes a floating state together with the source line(s) (SL) designated by the ADr. It means that it has shifted to the active state shown as 032 in the state transition diagram of FIG. 3 and the active state shown as 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T35 shown in the operation waveform diagrams of FIGS. 9 and 10. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0176] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), at time T34 shown in the operation waveform diagrams of FIGS. 9 and 10, when the first WR command is received from an external device of the SDRAM after receiving the ACT command, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by the ADr input in synchronization with the ACT command. It means that the writing state shown as 034 in the state transition diagram of FIG. 3 and the writing state shown as 046 in the state transition diagram of FIG. 4 are entered.

[0177] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the global word line selected by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, from time T35 shown in the operation waveform diagrams of FIGS. 9 and 10, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the sub-cell array is in a selected state and the non-selected word line(s) are driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2 and the global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, from time T35 shown in the operation waveform diagrams of FIGS. 9 and 10, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2 and the global word line, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, and remain at the potential VIWL.

[0178] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased to the potential VEBL from the floating state starting from time T35 shown in the operation waveform diagrams of FIGS. 9 and 10 as well. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0179] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr are erased. At this point, the data held by the memory cell(s) specified by the ADr is erased. However, in the SDRAM according to the first embodiment, after receiving the PRE command, the data remaining after being copied to the data register(s) specified by the ADr is rewritten to the memory cell(s), so that the loss of data in the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr, the memory cell(s) belonging to the non-selected sub-cell array are in the idle state, and the potential relationship between the floating body of each memory cell(s) connected to the non-selected word line(s) in the sub-cell array in the selected state and the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0180] To end the erasing operation, starting from time T35 shown in the operation waveform diagrams of FIGS. 9 and 10, the source line(s) and bit line(s) of the sub-cell array specified by the ADr start to discharge to 0V after the elapse of the time set inside the SDRAM device at time T37. Thereafter, the bit line(s) (BL) become floating together with the source line(s) (SL) specified by the ADr. The potential of the word line of the sub-cell array specified by the ADr changes from VEWLH or VEWLL to VIWL at time T37 shown in the operation waveform diagrams of FIGS. 9 and 10, and the sub-cell array specified by the ADr becomes idle. The potential of each word line, the states of each bit line and each source line continue until time T43 shown in the operation waveform diagrams of FIGS. 9 and 10. Therefore, the states of the floating bodies of the memory cells designated by the ADr are maintained.

[0181] From the time T36 after a predetermined time (CWL; CAS Write Latency) has elapsed since receiving the WR command, since the burst length is 8 (BL8), as shown in the operation waveform diagrams of FIGS. 9 and 10, eight sets of data are sequentially input from the DQ signal line in FIG. 1. After the input signal is sense-amplified by the data input receiver shown in 118 of FIG. 1, it is stored in the data input register shown in 119 of FIG. 1. After storage, from the data input register shown in 119 of FIG. 1, the IO driver shown in 123 of FIG. 1 writes to the data register (group) existing in 133 of FIG. 2, which is designated by the ADc and further by BL8 among the data registers (group) designated by the ADr. On the other hand, among the data registers (group) designated by the ADr, the data registers not designated by the ADc and further by BL8 hold the same data as the memory cells connectable to the same bit line (BL) designated by the ADr.

[0182] As also described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the operation of writing to the data register in the area of 133 of FIG. 2, which is designated by the ADc and further by BL8 among the data registers (group) designated by the ADr, and the erasing operation on the memory cell (group) connected to the word line of the bank address and row address designated by the ADr are performed in parallel and independently. Therefore, depending on the set value of WL (Write Latency) and the period of the clock, the timings of the erasing operation start time and the data input start time may be before or after each other, and there is no problem even if they are before or after each other. The timings of the erasing operation end time and the data input completion time may also be before or after each other, and there is no problem even if they are before or after each other. When both the operation of writing the input data to the data register specified by the ADr and ADc and the erasing operation of the memory cell(s) connected to the word line of the bank address and row address specified by the ADr are completed, the state transitions to the active state 032 in the state transition diagram shown in FIG. 3 and to the active state 047 in the state transition diagram shown in FIG. 4 by an automatic sequence. The memory cell(s) specified by the ADr maintains the erased state, and the data register(s) specified by the ADr holds the data that it held before the memory cell(s) specified by the ADr was erased.

[0183] Each non-selected word line is biased to VIWL, and the non-selected bit line and non-selected source line have been discharged to 0V at some previous stage and are now in a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0184] After the data input is completed, at time T39 after the elapse of tWTR (Delay from start of internal WRITE transaction to internal Read command), the input of the RD command becomes possible. When the RD command is input at time T39 shown in the operation waveform diagrams of FIGS. 9 and 10, in the state transition diagram of FIG. 3, it transitions from the write state 034 to the read state 033 upon receiving the RD command. In the state transition diagram of FIG. 4, it transitions from the active state 047 to the read state 048 upon receiving the RD command. In the operation waveform diagram of FIG. 9, the data of the memory cell(s) of the address signal input in synchronization with the RD command, the bank address specified by the ADc, and the column address received from the external device of the SDRAM by the RD command received from the external device of the SDRAM at time T39 is read out to the external device of the SDRAM. Also, in the operation waveform diagram of FIG. 10, due to the RD command received from a device external to the SDRAM at time T39, the data of the memory cell(s) corresponding to the address signal input in synchronization with the RD command, the bank address specified by ADc, and the column address is read out to the device external to the SDRAM. In the case of the BL8 setting, data output starts from time T40 after the elapse of CL (Column Latency) from the reception of the RD command at time T39 shown in the operation waveform diagrams of FIGS. 9 and 10, so the data is output eight times. In the case of the operation waveform diagram of FIG. 9, substantially, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADd and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than those specified by ADd and BL8 are in a data holding state. In the case of the operation waveform diagram of FIG. 10, substantially, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than those specified by ADc and BL8 are in a data holding state.

[0185] In the operation waveform diagram of FIG. 9, when an RD command is input at time T39, the data of the memory cell(s) with the bank address and column address designated by ADd, which is different from the ADc designated at time T34 shown in the operation waveform diagram of FIG. 9, is read out to a device external to the SDRAM. The data of the memory cell(s) with the bank address and row address designated by the aforementioned ADr, which was performed inside the SDRAM by receiving an ACT command, is copied to the data register(s) of the bank address designated by the ADr. Since it is different from the ADc where writing is performed at time T34 shown in the operation waveform diagram of FIG. 9, no writing has been performed to the data register(s) designated by the ADd and the burst length, and it remains in the state read out from the memory cell(s) by receiving an ACT command. Designating the ADd and reading with an RD command means specifying the column address from among the memory cell(s) with the bank address and row address designated by the ADr and reading it out to a device external to the SDRAM. Since the column address of the data register corresponds to the column address of the memory cell, there is no problem in reading the data of the memory cell(s) with the bank address and column address designated by the ADd from the data register(s) with the bank address and column address designated by the ADd.

[0186] In the operation waveform diagram of FIG. 10, when an RD command is input at time T39, the data of the memory cell(s) with the bank address and column address designated by the same ADc as the ADc designated at time T34 shown in the operation waveform diagram of FIG. 10 is read out to a device external to the SDRAM. According to this embodiment, the writing to the memory cell(s) with the bank address and column address designated by the ADc designated at time T34 shown in the operation waveform diagram of FIG. 10 and the burst length is not completed at time T39, but in the process from time T34 to time T38 shown in the operation waveform diagram of FIG. 10, the writing to the data register(s) with the bank address and column address designated by the ADc and the burst length is completed. Since the read operation by the RD command is substantially a read from the data register(s), the data written by the write operation after time T34 shown in the operation waveform diagram of FIG. 10 can be read without problems.

[0187] Although not presented as a waveform diagram, until the PRE command is received, even if there is a rewrite request by receiving the WR command for the same address, only the data in the data register(s) is rewritten, and no writing to the memory cell(s) is performed. As for the operation of the SDRAM, although the RD command and the WR command may be input multiple times after receiving the ACT command until the PRE command is received, since the data exchange with the external device of the SDRAM is performed with the data register, there is no inconvenience regarding the operation of not immediately writing to the memory cell when receiving the WR command, which is a feature of this embodiment.

[0188] Specifying an address different from ADr in the same sub-cell array as the sub-cell array in the situation where the memory cell has not been written yet and inputting the ACT command will cause data destruction even in an SDRAM using a memory cell composed of a current 1 transistor and 1 capacitor, so it is prohibited as an operation specification. Therefore, the same applies to the SDRAM according to this embodiment. Thus, there is no inconvenience regarding the operation of not immediately writing to the memory cell when receiving the WR command, which is a feature of this embodiment.

[0189] After receiving the RD command, the PRE command can be input at time T42 shown in the operation waveform diagrams of FIGS. 9 and 10 after the elapse of tRTP (Internal READ Command to PRECHARGE Command delay). When the SDRAM according to the first embodiment receives a PRE command at time T42 shown in the operation waveform diagrams of FIGS. 9 and 10, it starts a write operation of the data in the data register to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr. It is considered that the SDRAM has shifted to the precharge state shown as 037 in the state transition diagram of FIG. 3 and the precharge state shown as 053 in the state transition diagram of FIG. 4. Since substantially "0" data has already been written by the erase operation, in the write sequence here, "1" is written to the memory cell(s) corresponding to the data register holding "1" data, and the state where "0" data has already been written is maintained for the memory cells corresponding to the data register holding "0" data.

[0190] The potential of the word line (WL) of the bank address and row address specified by the ADr is selected and driven by the row decoder and global word line driver shown in 130 of FIG. 2 to be a global word line, and further biased from the potential VIWL to the potential VWWLH at time T43 shown in the operation waveform diagrams of FIGS. 9 and 10 by the global word line and local word line driver. Among the word line(s) not specified by the ADr, the global word line and local word line driver drive the non-selected word line(s) in the sub-cell array that are in the selected state to be in the non-selected state and biased from the potential VIWL to the potential VWWLL at time T43 shown in the operation waveform diagrams of FIGS. 9 and 10. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to be in the non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2 to be a global word line, and further maintained at the potential VIWL by the global word line and local word line driver. The source line(s) of the sub-cell array specified by the ADr are biased from the floating state to 0V at time T43 shown in the operation waveform diagrams of FIGS. 9 and 10. The bit line(s) of the sub-cell array designated by the ADr is biased in potential according to the data stored in the data register(s) designated by the ADr corresponding to the bit line(s). When the data in the data register is "0", the bit line (BL) is changed from the floating state to 0V at time T43. When the data in the data register is "1", the bit line (BL) is biased from the floating state to the potential VWBL at time T43. On the other hand, the source line(s) and bit line(s) of the sub-cell array not designated by the ADr remain in the floating state.

[0191] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, among the memory cell(s) connected to the word lines of the bank address and row address designated by the ADr, the memory cell(s) to which VWBL is biased on the bit line (BL) has the data "1" written therein. On the other hand, for the memory cell(s) to which 0V is biased on the bit line (BL), the floating body of each memory cell maintains the erased state, indicating that the data "0" has been written. That is, data is read from each data register designated by the ADr, and the read data is written into each memory cell designated by the ADr corresponding to the data register. In addition to the data written by the WR command, the data lost due to the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cell due to the erase operation. Since the memory cell(s) connected to the word lines of the bank address and row address not designated by the ADr is in the idle state, the state of the floating body of each memory cell is maintained.

[0192] To end the write operation, after the time period set internally in the SDRAM device has elapsed from time T43 shown in the operation waveform diagrams of FIGS. 9 and 10 to time T44, the source line(s) and bit line(s) of the sub-cell array specified by the ADr are put in a floating state. The potential of the word line of the sub-cell array specified by the ADr starts to discharge from VWWLH or VWWLL to 0V at time T44 shown in the operation waveform diagrams of FIGS. 9 and 10. The potential of each word line, the state of each bit line, and the state of each source line continue until time T45 shown in the operation waveform diagrams of FIGS. 9 and 10. By an automatic sequence without a command, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the state transition diagram of FIG. 3, it stays in the precharge state shown as 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, by an automatic sequence without a command, it transitions to the idle state shown as 030 in the state transition diagram of FIG. 3 and to the idle state shown as 040 in the state transition diagram of FIG. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr maintains the reset state.

[0193] At time T45 shown in the operation waveform diagrams of FIGS. 9 and 10, it receives the ACT command input from a device external to the SDRAM. However, since the address signal received at time T45 shown in the operation waveform diagrams of FIGS. 9 and 10 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by the ADr stay in the idle state shown as 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the ACT command and the address signal synchronized with the ACT command, after time T45 shown in the operation waveform diagrams of FIGS. 9 and 10, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, as for the SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the active state 031.

[0194] Fig. 11 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate a memory cell (group) with a bank address and row address specified by ADr, writing is performed to a memory cell (group) with a bank address and column address specified by ADc, reading is then performed from a memory cell (group) with an address specified by ADd which has the same bank address as ADc but a different column address by an RDA command, and then, by an automatic sequence without a command, the memory cell (group) with the bank address and row address specified by ADr which is in an active state is shifted to an idle state. The operation waveform diagram shown in Fig. 12 is different from the operation waveform diagram shown in Fig. 11 and is an operation waveform diagram in which, after writing to a memory cell (group) with a bank address and column address specified by ADc, reading is performed from the memory cell (group) with the bank address and column address specified by the same ADc. The difference between the operation waveform diagram shown in Fig. 11 and the operation waveform diagram shown in Fig. 12 is only that the column address input in synchronization with the WR command and the column address input in synchronization with the RDA command are different (Fig. 11) or the same (Fig. 12). Therefore, the descriptions of the operation waveform diagram shown in Fig. 11 and the operation waveform diagram shown in Fig. 12 are given together.

[0195] When the operation waveforms shown in Figs. 11 and 12 are compared with the state transition diagram shown in Fig. 3, the following results. In the state transition diagram shown in FIG. 3, starting from the idle state indicated by 030, by receiving the ACT command input from a device external to the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12, it transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. By receiving the WR command input from a device external to the SDRAM at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, it transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3. Further, by receiving the RDA command input from a device external to the SDRAM at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12, it transitions to the read state indicated by 035 in the state transition diagram shown in FIG. 3. After a predetermined time has elapsed since receiving the RDA command, it transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command, and then transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. This is the sequence of receiving the ACT command input from a device external to the SDRAM at time T45 shown in FIGS. 11 and 12.

[0196] The operation waveforms shown in FIGS. 11 and 12 will be described in light of the state transition diagram of the first embodiment shown in FIG. 4. In the state transition diagram shown in FIG. 4, starting from the idle state indicated by 040, by receiving the ACT command input from a device external to the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12, and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the WR command input from a device external to the SDRAM at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, it transitions to the write state indicated by 046 in the state transition diagram shown in FIG. 4, and then transitions to the active state indicated by 047 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the RDA command input from a device external to the SDRAM at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12, it transitions to the read state indicated by 051 in the state transition diagram shown in FIG. 18. At time T42 shown in the operation waveform diagrams of FIGS. 11 and 12 after a predetermined time has elapsed, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and further, by an automatic sequence without a command, it transitions to the idle state indicated by 040 in the state transition diagram shown in FIG. 4 via the precharge state indicated by 045 in the state transition diagram shown in FIG. 4. At time T45 shown in the operation waveform diagrams of FIGS. 11 and 12, it receives the ACT command input from a device external to the SDRAM. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T45 shown in the operation waveform diagrams of FIGS. 11 and 12 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by the ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, and this is the sequence.

[0197] Furthermore, the operation waveforms shown in FIGS. 11 and 12 of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When the ACT command input from a device external to the SDRAM is received at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12, in the state transition diagram of FIG. 3, the state transitions from the idle state indicated by 030 to the activation state indicated by 031. In the state transition diagram of FIG. 4, the state transitions from the idle state indicated by 040 to the activation state indicated by 041.

[0198] Synchronized with the timing of receiving the ACT command, an address signal is received as an input signal from a device external to the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12. In the operation waveform diagrams of FIGS. 11 and 12, it is indicated by ADr. The address signal from a device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in FIG. 1, and the word lines (WL) of the specified bank address and row address are selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, at time T32 shown in the operation waveform diagrams of FIGS. 11 and 12, are biased from the potential VIWL to the potential VRWL. The potential of the word lines (WL) (group) of the addresses not specified by the ADr and the word lines (WL) (group) of the sub-cell array (group) are driven to a non-selective state by the row decoder and global word line driver shown as 130 in FIG. 2 to be global word lines, and further by the local word line driver shown as 134 in FIG. 2 and the global word line, and remain at VIWL.

[0199] The source lines (SL) (group) of the sub-cell array specified by the ADr are biased from the floating state to 0V at time T32 shown in the operation waveform diagrams of FIGS. 11 and 12. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T32 shown in the operation waveform diagrams of FIGS. 11 and 12, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0200] At time T33 shown in the operation waveform diagrams of FIGS. 11 and 12 when the data storage in the data register is completed, the potential of the word line (WL) designated by the ADr is driven to the potential VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V. Thereafter, the bit line(s) (BL) becomes a floating state together with the source line(s) (SL) designated by the ADr. It means that the state transitions to the active state shown as 032 in the state transition diagram of FIG. 3 and the active state shown as 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T35 shown in the operation waveform diagrams of FIGS. 11 and 12. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0201] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), when the first WR command is received from an external device of the SDRAM at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr that is input in synchronization with the ACT command. It means that the writing state shown as 034 in the state transition diagram of FIG. 3 and the writing state shown as 046 in the state transition diagram of FIG. 4 are entered.

[0202] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the global word line selected by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 from time T35 shown in the operation waveform diagrams of FIGS. 11 and 12, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the sub-cell array is in a selected state, and the non-selected word line(s) is driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 from time T35 shown in the operation waveform diagrams of FIGS. 11 and 12, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr is driven to a non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2, and remains at the potential VIWL.

[0203] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased to the potential VEBL from the floating state at time T35 shown in the operation waveform diagrams of FIGS. 11 and 12 as well. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0204] With the above potential setting, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr are erased. At this point, the data held by the memory cell(s) specified by the ADr is erased. However, after the SDRAM according to the first embodiment transitions to the state 053 shown in the state transition diagram of FIG. 4, the data remaining after being copied to the data register(s) specified by the ADr is rewritten to the memory cell(s), so that the loss of data in the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr, the memory cell(s) belonging to the non-selected sub-cell array are in the idle state, and the potential relationship between the floating body of each of the memory cell(s) connected to the non-selected word line(s) in which the sub-cell array is in the selected state and the bit line and source line is almost the same as in the idle state, so that the charge of the floating body is maintained.

[0205] To end the erasing operation, the source line(s) and bit line(s) of the sub-cell array specified by the ADr start to discharge to 0V at time T37 after the elapse of the time set inside the SDRAM device from time T35 shown in the operation waveform diagrams of FIGS. 11 and 12. Thereafter, the bit line(s) (BL) become floating together with the source line(s) (SL) specified by the ADr. The potential of the word line of the sub-cell array specified by the ADr is biased from VEWLH or VEWLL to VIWL at time T37 shown in the operation waveform diagrams of FIGS. 11 and 12, and the sub-cell array specified by the ADr becomes in the idle state. The potential of each word line, and the states of each bit line and each source line continue until time T43 shown in the operation waveform diagrams of FIGS. 11 and 12. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained.

[0206] From time T36 shown in the operation waveform diagrams of FIGS. 11 and 12 after a predetermined time (CWL; CAS Write Latency) has elapsed since receiving the WR command, since the burst length is 8 (BL8), as shown in the operation waveform diagrams of FIGS. 11 and 12, eight sets of data are sequentially input from the DQ signal line in FIG. 1. After the input signal is sense-amplified by the data input receiver shown in 118 in FIG. 1, it is stored in the data input register shown in 119 in FIG. 1. After storage, from the data input register shown in 119 in FIG. 1, writing is performed to the data register(s) existing in 133 in FIG. 2, which is specified by the ADc and BL8 among the data register(s) designated by the ADr, by the IO driver shown in 123 in FIG. 1. On the other hand, among the data register(s) designated by the ADr, the data registers not specified by the ADc and BL8 hold the same data as the memory cells connectable to the same bit line (BL) designated by the ADr.

[0207] As also described in the explanation of FIG. 7, the operation of writing to the data register in the area of 133 in FIG. 2, which is specified by the ADc and further BL8 among the data register(s) designated by the ADr, and the erasing operation on the memory cell(s) connected to the word line of the bank address and row address designated by the ADr are performed in parallel and independently. Therefore, depending on the set value of WL (Write Latency) and the period of the clock, the timings of the erasing operation start time and the data input start time may be before or after each other, and there is no problem even if they are before or after each other. The timings of the erasing operation end time and the data input completion time may also be before or after each other, and there is no problem even if they are before or after each other. When both the writing operation of the input data to the data register specified by the ADr and ADc and the erasing operation of the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr are completed, according to the automatic sequence, in the state transition diagram shown in FIG. 3, it will transition to the active state of 032, and in the state transition diagram shown in FIG. 4, it will transition to the active state of 047. Each memory cell specified by the ADr maintains the erased state. Among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and for which writing has not been performed hold the data they held before the memory cell(s) specified by the ADr were erased. Among the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and for which writing has been performed hold the written data.

[0208] Each non-selected word line is biased to VIWL, and the non-selected bit line and non-selected source line have been discharged to 0V at some previous stage and are in a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0209] After the data input is completed, at time T39 after the elapse of tWTR (Delay from start of internal WRITE transaction to internal Read command), the RDA command can be input. When the RDA command is input at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12, in the state transition diagram of FIG. 3, it transitions from the writing state of 034 to the reading state of 035 upon receiving the RDA command. In the state transition diagram of FIG. 4, the one in the active state of 047 according to the automatic sequence transitions from the writing state of 046 to the reading state of 051 upon receiving the RDA command. In the operation waveform diagram of FIG. 11, according to the RDA command received from a device external to the SDRAM at time T39, the data of the memory cell(s) corresponding to the address signal input in synchronization with the RDA command, the bank address specified by ADd, and the column address is read out to the device external to the SDRAM. Also, in the operation waveform diagram of FIG. 12, according to the RDA command received from a device external to the SDRAM at time T39, the data of the memory cell(s) corresponding to the address signal input in synchronization with the RDA command, the bank address specified by ADc, and the column address is read out to the device external to the SDRAM. In the case of the BL8 setting, data output starts from time T40 after the elapse of CL (Column Latency) from the reception of the RDA command at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12, so the data is output 8 times. In the case of the operation waveform diagram of FIG. 11, substantially, among the data register(s) specified by ADr that holds the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADd and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than those specified by ADd and BL8 are in a data holding state. Also, in the case of the operation waveform diagram of FIG. 12, substantially, among the data register(s) specified by ADr that holds the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than those specified by ADc and BL8 are in a data holding state.

[0210] As for the SDRAM according to the first embodiment, as described in the explanation regarding the operation waveforms of FIGS. 9 and 10, when an RDA command is input at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12, the bank address and column address specified may be the same as or different from the bank address and column address specified when a WR command is input at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, and there is no problem, and no inconvenience occurs due to the fact that data writing to the memory cell is not completed.

[0211] After receiving the RDA command, at time T42 shown in the operation waveform diagrams of FIGS. 11 and 12 after the elapse of tRTP (Internal READ Command to PRECHARGE Command delay), even without input of a PRE command, by an automatic sequence, in the state transition diagram of FIG. 3, it transitions to the precharge state shown as 037. The SDRAM of the first embodiment transitions the memory cell(s) and data register(s) specified by the ADr to the precharge state shown as 053 in the state transition diagram of FIG. 4. At time T43 shown in the operation waveform diagrams of FIGS. 11 and 12, the data writing operation of the data register(s) specified by the ADr to the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr is started. Since substantially "0" data has already been written by an erase operation, in the writing sequence here, "1" is written to the memory cell(s) corresponding to the data register(s) holding "1" data, and the state where "0" data has already been written is maintained for the memory cells corresponding to the data register(s) holding "0" data.

[0212] The potential of the word line (WL) of the bank address and row address specified by the above-mentioned ADr is selected and driven by the row decoder and global word line driver shown in 130 of FIG. 2, and further by the global word line and local word line driver, and is biased from the potential VIWL to the potential VWWLH at the time T43 shown in the operation waveform diagrams of FIGS. 11 and 12. Among the word lines (groups) not specified by the ADr, the sub-cell array is in a selected state, and the non-selected word lines (groups) are driven to a non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2, and by the global word line and local word line driver, and are biased from the potential VIWL to the potential VWWLL at the time T43 shown in the operation waveform diagrams of FIGS. 11 and 12. The word lines (groups) belonging to the sub-array of the address not specified by the ADr are driven to a non-selected state by the row decoder and global word line driver shown in 130 of FIG. 2, and further by the global word line and local word line driver, and remain at the potential VIWL. The source line (group) of the sub-cell array specified by the ADr is biased from a floating state to 0V at the time T43 shown in the operation waveform diagrams of FIGS. 11 and 12. The potential of the bit line (group) of the sub-cell array specified by the ADr is biased according to the data stored in the data register (group) corresponding to the bit line (group). When the data in the data register is "0", the bit line (BL) is biased from a floating state to 0V at the time T43. When the data in the data register is "1", the bit line (BL) is biased from a floating state to the potential VWBL at the time T43.

[0213] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, among the memory cell(s) connected to the word line of the bank address and row address specified by the ADr, the memory cell(s) to which the VWBL is biased on the bit line (BL) has the data "1" written therein. On the other hand, for the memory cell(s) to which 0V is biased on the bit line (BL), the floating body of each memory cell maintains the erased state, and it is considered that the data "0" has been written. That is, data is read from each data register specified by the ADr, and the read data is written into each memory cell specified by the ADr corresponding to the data register. In addition to the data written by the WR command, the data lost by the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cell due to the erase operation. Since the memory cell(s) connected to the word line of the bank address and row address not specified by the ADr is in the idle state, the state of the floating body of each memory cell is maintained.

[0214] To end the write operation, after the time set inside the SDRAM device has elapsed from the time T43 shown in the operation waveform diagrams of FIGS. 11 and 12, the source line(s) and bit line(s) of the sub-cell array specified by the ADr are set to the floating state at the time T44 shown in the operation waveform diagrams of FIGS. 11 and 12. The potential of the word line of the sub-cell array specified by the ADr is biased from VWWLH or VWWLL to 0V at the time T44 shown in the operation waveform diagrams of FIGS. 11 and 12. The potential of each word line, each bit line, and each source line state continue until the time T45 shown in the operation waveform diagrams of FIGS. 11 and 12. By the automatic sequence without a command, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the state transition diagram of FIG. 3, it stays in the precharge state shown as 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, through an automatic sequence without commands, it transitions to the idle state shown as 030 in the state transition diagram of FIG. 3 and the idle state shown as 040 in the state transition diagram of FIG. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr remains in the reset state.

[0215] Since the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr are in the idle state, the state of the floating body of each memory cell is maintained. However, in the case of an SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the active state 031.

[0216] It receives the ACT command input from an external device of the SDRAM at time T45 shown in FIGS. 11 and 12. However, since the address signal received at time T45 shown in FIGS. 11 and 12 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state shown as 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the address signal synchronized with the ACT command, after time T45 shown in the operation waveform diagrams of FIGS. 11 and 12, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, in the case of an SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the active state 031.

[0217] Fig. 13 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate a memory cell (group) with a bank address and a row address specified by ADr, data is read from a memory cell (group) with a bank address and a column address specified by ADc, and then writing is performed to a memory cell (group) with an address specified by ADd whose bank address is the same as that of ADc but whose column address is different, and a PRE command is input to shift the memory cell (group) with the bank address and the row address specified by ADr, which is in an active state, to an idle state. The operation waveform diagram shown in Fig. 14 is different from the operation waveform diagram shown in Fig. 13. It is an operation waveform diagram in which, after reading from a memory cell (group) with a bank address and a column address specified by ADc, writing is performed to the memory cell (group) with the same bank address and column address specified by ADc. The difference between the operation waveform diagram shown in Fig. 13 and the operation waveform diagram shown in Fig. 14 is only that the column address input in synchronization with the RD command is different from (Fig. 13) or the same as (Fig. 14) the column address input in synchronization with the WR command. Therefore, the descriptions of the operation waveform diagram shown in Fig. 13 and the operation waveform diagram shown in Fig. 14 are given together.

[0218] When the operation waveforms shown in Figs. 13 and 14 are compared with the state transition diagram shown in Fig. 3, the following results are obtained. In the state transition diagram shown in FIG. 3, starting from the idle state indicated by 030, by receiving the ACT command input from an external device of the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14, it transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. By receiving the RD command input from an external device of the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14, it transitions to the read state indicated by 033 in the state transition diagram shown in FIG. 3. Further, by receiving the WR command input from an external device of the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 13 and 14, it transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3. By receiving the PRE command input from an external device of the SDRAM at time T62 shown in the operation waveform diagrams of FIGS. 13 and 14, it transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3, and then transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. This is the sequence of receiving the ACT command input from an external device of the SDRAM at time T65.

[0219] The operation waveforms shown in FIGS. 13 and 14 will be described in light of the state transition diagram of the first embodiment shown in FIG. 4. In the state transition diagram shown in FIG. 4, from the idle state indicated by 040, by receiving the ACT command input from a device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14, and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the startup state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command, and transition to the read state indicated by 043 in the state transition diagram shown in FIG. 4 by receiving the RD command input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14. Further, by receiving the WR command input from a device external to the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 13 and 14, it transitions to the write state indicated by 046 in the state transition diagram shown in FIG. 4, and then transitions to the active state indicated by 047 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the PRE command input from a device external to the SDRAM at time T62 shown in the operation waveform diagrams of FIGS. 13 and 14, and the address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and further transition to the idle state indicated by 040 in the state transition diagram shown in FIG. 4 via the precharge state indicated by 045 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. At time T65 shown in the operation waveform diagrams of FIGS. 13 and 14, it receives the ACT command input from a device external to the SDRAM. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T65 shown in the operation waveform diagrams of FIGS. 13 and 14 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, which is the sequence described above.

[0220] Furthermore, the operation waveforms shown in FIGS. 13 and 14 of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device of the SDRAM is received at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14, in the state transition diagram of FIG. 3, a transition is made from the idle state indicated by 030 to the activation state indicated by 031. In the state transition diagram of FIG. 4, a transition is made from the idle state indicated by 040 to the activation state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from an external device of the SDRAM is received at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14. In the operation waveform diagrams of FIGS. 13 and 14, it is indicated by ADr. The address receiver and address decoder shown as 112 in FIG. 1 discriminate the address signal from an external device of the SDRAM, and the word line (WL) of the specified bank address and row address is selected and driven by the row decoder shown as 130 in FIG. 2 and the global word line driver to be a global word line, and further by the global word line and the local word line driver shown as 134 in FIG. 2, and is biased from the potential VIWL to the potential VRWL at time T52 shown in the operation waveform diagrams of FIGS. 13 and 14. The potential of the word line (WL) (group) of the address not specified by the ADr and the word line (WL) (group) of the sub-cell array (group) is driven to a non-selected state by the row decoder shown as 130 in FIG. 2 and the global word line driver to be a global word line, and further by the global word line and the local word line driver shown in FIG. 2 as 134, and the potential remains at VIWL.

[0221] The source line (SL) (group) of the sub-cell array specified by the ADr is biased from the floating state to 0V at time T52 shown in the operation waveform diagrams of FIGS. 13 and 14. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T52 shown in the operation waveform diagrams of FIGS. 13 and 14, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0222] At time T53 shown in the operation waveform diagrams of FIGS. 13 and 14 when the data storage in the data register is completed, the potential of the word line (WL) designated by the ADr is driven to VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V at time T53. Thereafter, the bit line(s) (BL) becomes a floating state together with the source line(s) (SL) designated by the ADr. It means that it has shifted to the active state shown as 032 in the state transition diagram of FIG. 3 and the active state shown as 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T58 shown in the operation waveform diagrams of FIGS. 13 and 14. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0223] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), when an RD command is input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14, the data of the memory cell(s) of the bank address and column address specified by the address signal ADc input in synchronization with the RD command is read out to the device external to the SDRAM. This is the read state indicated by 033 in the state transition diagram of FIG. 3, and the state transitions to the read state indicated by 043 in the state transition diagram of FIG. 4. After receiving the RD command at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14 and after the elapse of CL (Column Latency), data output starts from time T55 shown in the operation waveform diagrams of FIGS. 13 and 14. Since it is the BL8 setting, the data is output 8 times. Substantially, among the data register(s) holding the same data as the memory cell(s) specified by the ADr, the data of the data register(s) specified by ADc and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by the ADr, the data register(s) other than those specified by ADc and BL8 are in the data holding state.

[0224] After receiving the RD command and after the elapse of the READ to WRITE command delay time, when, at time T57 shown in the operation waveform diagrams of FIGS. 13 and 14, an ACT command is received from a device external to the SDRAM and then the first WR command is received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by the ADr input in synchronization with the ACT command. This means that the state has transitioned to the write state indicated by 034 in the state transition diagram of FIG. 3 and the write state indicated by 046 in the state transition diagram of FIG. 4.

[0225] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 for the global word line, from the time T58 shown in the operation waveform diagrams of FIGS. 13 and 14, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the non-selected word line(s) for which the sub-cell array becomes the selected state is driven to the non-selected state by the row decoder global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 for the global word line, also from the time T58 shown in the operation waveform diagrams of FIGS. 13 and 14, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr is driven to the non-selected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 for the global word line, and remains at the potential VIWL.

[0226] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased to the potential VEBL from the floating state, also from the time T58 shown in the operation waveform diagrams of FIGS. 13 and 14. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0227] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by the ADr is erased. At this point, the data held in the memory cell(s) specified by the ADr is erased. However, in the SDRAM according to the first embodiment, after receiving the PRE command, the data remaining after being copied to the data register(s) specified by the ADr is rewritten to the memory cell(s), so that the loss of data in the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr, the memory cell(s) belonging to the non-selected sub-cell array is in an idle state, and the sub-cell array is in a selected state. The potential relationship between the floating body potential of each memory cell connected to the non-selected word line(s), the bit line, and the source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0228] To end the erasing operation, from time T58 shown in the operation waveform diagrams of FIGS. 13 and 14 until time T60 after the elapse of the time set inside the SDRAM device, the source line(s) and bit line(s) of the sub-cell array specified by the ADr start to discharge to 0V, and then become floating states. The potential of the word line of the sub-cell array specified by the ADr is biased from VEWLH or VEWLL to VIWL at time T60 shown in the operation waveform diagrams of FIGS. 13 and 14, and the sub-cell array specified by the ADr becomes an idle state. The potential of each word line, the state of each bit line, and each source line continue until time T63 shown in the operation waveform diagrams of FIGS. 13 and 14. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0229] Starting from time T59 shown in the operation waveform diagrams of FIGS. 13 and 14 after the elapse of a predetermined WL (Write Latency) time after receiving the WR command, since the burst length is 8 (BL8), as shown in the operation waveform diagrams of FIGS. 13 and 14, eight sets of data are sequentially input from the DQ signal lines shown in FIG. 1. The input data is sense-amplified by the data input receiver shown as 118 in FIG. 1 and then stored in the data input register shown as 119 in FIG. 1. In the case of the operation waveform diagram of FIG. 13, after being stored in the data input register, from the data input register shown as 119 in FIG. 1, by the IO driver shown as 123 in FIG. 1, among the data register(s) specified by the ADr, writing is performed on the data register(s) within the area of 133 in FIG. 2, which is specified by the ADd and further by being BL8. On the other hand, among the data register(s) specified by the ADr, the data registers not specified by the ADd and further by being BL8 hold the same data as the memory cells connectable to the same bit line (BL) specified by the ADr. Also, in the case of the operation waveform diagram of FIG. 14, after being stored in the data input register, from the data input register shown as 119 in FIG. 1, by the IO driver shown as 123 in FIG. 1, among the data register(s) specified by the ADr, writing is performed on the data register(s) within the area of 133 in FIG. 2, which is specified by the ADc and further by being BL8. On the other hand, among the data register(s) specified by the ADr, the data registers not specified by the ADc and further by being BL8 hold the same data as the memory cells connectable to the same bit line (BL) specified by the ADr. In the case of the SDRAM according to the first embodiment, depending on the WR command, writing is not performed on the memory cell(s), and input data is only written to the data register existing within 133 in FIG. 2, which is associated with the sub-cell array of the address specified by the ADr and the ADd (in the case of the operation waveform diagram of FIG. 13) or the ADc (in the case of the operation waveform diagram of FIG. 14), and further by being BL8. That no inconvenience occurs due to the fact that data writing to the memory cell is not completed was described when explaining the operation waveforms of FIGS. 9 and 10 as the SDRAM according to the first embodiment. Also, it was described when explaining the operation waveforms of FIGS. 9 and 10 as the SDRAM according to the first embodiment that there is no problem whether the bank address and column address specified when the RD command is input are the same as or different from the bank address and column address specified when the WR command is input.

[0230] As described in the description of FIG. 7, among the data register(s) specified by the ADr, for the data register(s) within the area 133 of FIG. 2 specified by further being the ADc and BL8, the operation of writing to the data register(s) and the erasing operation for the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr are performed in parallel and independently. Therefore, depending on the set value of WL (Write Latency) and the period of the clock, the timings of the erasing operation start time and the data input start time may be before or after each other, and there is no problem even if they are before or after each other. The timings of the erasing operation end time and the data input completion time may also be before or after each other, and there is no problem even if they are before or after each other. The waveform diagrams shown in FIGS. 13 and 14 are examples where the erasing completion timing and the data input timing are different from the operation waveform diagrams shown in FIGS. 7 and 8. When both the operation of writing the input data to the data register specified by the ADr and ADc (in the case of the operation waveform diagram of FIG. 13) or ADd (in the case of the operation waveform diagram of FIG. 14) and the erasing operation of the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr are completed, by an automatic sequence, in the state transition diagram shown in FIG. 3, it is considered to have transitioned to the active state of 032, and in the state transition diagram shown in FIG. 4, it is considered to have transitioned to the active state of 047. Each memory cell specified by the ADr maintains the erased state. In the case of the operation waveform diagram of FIG. 13, among the data register(s) specified by the ADr, the data register(s) that are not specified by further being the ADd and BL8 and for which writing was not performed hold the data that they held before the memory cell(s) specified by the ADr were erased. In the case of the operation waveform diagram of FIG. 13, among the data register(s) specified by the ADr, the data register(s) that are specified by further being the ADd and BL8 and for which writing was performed hold the written data. In the case of the operation waveform diagram of FIG. 14, among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and for which writing has not been performed hold the data that they held before the memory cell(s) specified by the ADr were erased. In the case of the operation waveform diagram of FIG. 14, among the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and for which writing has been performed hold the written data.

[0231] After data input is completed, at time T62 after the elapse of tWR (WRITE Recovery Time), the PRE command can be input. When the SDRAM according to the first embodiment receives the PRE command at time T62 shown in the operation waveform diagrams of FIGS. 13 and 14, it starts the writing operation of the data in the data register to the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr. It transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3 and to the precharge state indicated by 053 in the state transition diagram of FIG. 4. Since substantially "0" data has already been written by the erase operation, in the writing sequence here, "1" is written to the memory cell(s) corresponding to the data register holding "1" data, and the state where "0" data has already been written is maintained for the memory cells corresponding to the data register holding "0" data.

[0232] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the row decoder and global word line driver shown in FIG. 2, and further by the global word line and local word line driver, and is biased from the potential VIWL to the potential VWWLH at the time T63 shown in the operation waveform diagrams of FIGS. 13 and 14. Among the word line(s) not specified by the ADr, the sub-cell array of the non-selected word line(s) that becomes the selected state is driven to the non-selected state by the row decoder and global word line driver shown in FIG. 2, and by the global word line and local word line driver, and is biased from the potential VIWL to the potential VWWLL at the time T63 shown in the operation waveform diagrams of FIGS. 13 and 14. The word line(s) belonging to the sub-array of the address not specified by the ADr is driven to the non-selected state by the row decoder and global word line driver shown in FIG. 2, and further by the global word line and local word line driver, and remains at the potential VIWL. The source line(s) of the sub-cell array specified by the ADr is biased from the floating state to 0V at the time T63 shown in the operation waveform diagrams of FIGS. 13 and 14. The potential of the bit line(s) of the sub-cell array specified by the ADr is biased according to the data stored in the data register(s) corresponding to the bit line(s). When the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at the time T63 shown in the operation waveform diagrams of FIGS. 13 and 14. When the data in the data register is "1", the bit line (BL) is biased from the floating state to the potential VWBL at the time T63. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0233] With the above potential setting, among the memory cell(s) connected to the word line of the bank address and row address specified by the ADr, the memory cell(s) to which VWBL is biased on the bit line (BL) allows current to flow, causing the impact ionization phenomenon to occur. The generated hole(s) accumulates in the floating body of each memory cell, and the electron(s) is discharged to the bit line (BL), indicating that data "1" has been written. On the other hand, for the memory cell(s) to which 0V is biased on the bit line (BL), since the potentials of the bit line (BL) and the source (line) are the same, no current flows. Therefore, the impact ionization phenomenon does not occur, and the floating body of each memory cell maintains the erased state, indicating that data "0" has been written. That is, data is read from each data register specified by the ADr, and the read data is written to each memory cell specified by the ADr corresponding to the data register. In addition to the data written by the WR command, the data lost due to the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cell due to the erase operation. Since the memory cell(s) connected to the word line of the bank address and row address not specified by the ADr is in the idle state, the state of the floating body of each memory cell is maintained.

[0234] To end the write operation, at time T64 after the elapse of the time set inside the SDRAM device from time T63 shown in the operation waveform diagrams of FIGS. 13 and 14, the source line(s) and bit line(s) of the sub-cell array specified by the ADr are set to the floating state. The potential of the word line of the sub-cell array specified by the ADr is biased from VWWLH or VWWLL to 0V at time T64, and the sub-cell array specified by the ADr enters the idle state. The potential of each word line, the state of each bit line and each source line continue until time T65 shown in the operation waveform diagrams of FIGS. 13 and 14. By an automatic sequence without commands, it transitions to the precharge state shown as 045 in the state transition diagram of FIG. 4. In the state transition diagram of FIG. 3, it stays in the precharge state shown as 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, by an automatic sequence without commands, it transitions to the idle state shown as 030 in the state transition diagram of FIG. 3 and the idle state shown as 040 in the state transition diagram of FIG. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr maintains the reset state.

[0235] It receives the ACT command input from an external device of the SDRAM at time T65 shown in the operation waveform diagrams of FIGS. 13 and 14. However, since the address signal received at time T65 shown in the operation waveform diagrams of FIGS. 13 and 14 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr stay in the idle state shown as 040 in the state transition diagram of FIG. 4. Therefore, until it receives ADp as the address signal synchronized with the ACT command, after time T65 shown in the operation waveform diagrams of FIGS. 13 and 14, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain the floating state. However, as for the SDRAM, it transitions from the idle state 030 shown in the state transition diagram of FIG. 3 to the activation state 031.

[0236] Fig. 15 shows an operation waveform diagram of a series of sequences in which an ACT command is input to activate a memory cell (group) with a bank address and a row address specified by ADr, data is read from a memory cell (group) with a bank address and a column address specified by ADc, then a write operation is performed on a memory cell (group) with an address specified by ADd, which has the same bank address as ADc but a different column address, by a WRA command, and then, by an automatic sequence without a command, the memory cell (group) with the bank address and the row address specified by ADr, which is in an active state, is shifted to an idle state. The operation waveform diagram shown in Fig. 16 is different from the operation waveform diagram shown in Fig. 15, and it is an operation waveform diagram in which, after reading from a memory cell (group) with a bank address and a column address specified by ADc, a write operation is performed on the memory cell (group) with the same bank address and column address specified by ADc. The difference between the operation waveform diagram shown in Fig. 15 and the operation waveform diagram shown in Fig. 16 is only that the column address input in synchronization with the RD command and the column address input in synchronization with the WRA command are different (Fig. 15) or the same (Fig. 16). Therefore, the operation waveform diagrams shown in Fig. 15 and Fig. 16 will be described together.

[0237] The operation waveforms shown in Figs. 15 and 16 will be described in light of the state transition diagram shown in Fig. 3. In the state transition diagram shown in FIG. 3, from the idle state indicated by 030, by receiving the ACT command input from a device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 15 and 16, it transitions to the startup state indicated by 031 in the state transition diagram shown in FIG. 3, and then transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. By receiving the RD command input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 15 and 16, it transitions to the read state indicated by 033 in the state transition diagram shown in FIG. 3. Further, by receiving the WRA command input from a device external to the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 15 and 16, it transitions to the write state of 036 in the state transition diagram shown in FIG. 3. After a predetermined time has elapsed since receiving the data input from a device external to the SDRAM, it transitions to the precharge state indicated by 037 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command at time T62 shown in the operation waveform diagrams of FIGS. 15 and 16, and then further transitions to the idle state indicated by 030 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. This is the sequence of receiving the ACT command input from a device external to the SDRAM at time T65 shown in the operation waveform diagrams of FIGS. 15 and 16.

[0238] When the operation waveforms shown in FIGS. 15 and 16 are compared with the state transition diagram of the first embodiment shown in FIG. 4, the following results. In the state transition diagram shown in FIG. 4, from the idle state indicated by 040, by receiving the ACT command input from a device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 15 and 16, and the address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the activation state indicated by 041 in the state transition diagram shown in FIG. 4, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By receiving the RD command input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 15 and 16, it transitions to the read state indicated by 043 in the state transition diagram shown in FIG. 4. Further, by receiving the WRA command input from a device external to the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 15 and 16, it transitions to the write state indicated by 050 in the state transition diagram shown in FIG. 4. At time T62 shown in the operation waveform diagrams of FIGS. 15 and 16 after a predetermined time has elapsed, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in FIG. 4, and further, by an automatic sequence without a command, it transitions to the idle state indicated by 040 in the state transition diagram shown in FIG. 4 via the precharge state indicated by 045 in the state transition diagram shown in FIG. 4. It receives the ACT command input from a device external to the SDRAM at time T65 shown in the operation waveform diagrams of FIGS. 15 and 16. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T65 shown in the operation waveform diagrams of FIGS. 15 and 16 is ADp which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in FIG. 4, which is the sequence described above.

[0239] Furthermore, the operation waveforms shown in FIGS. 15 and 16 of the word line (WL), bit line (BL), and source line (SL) of the SDRAM according to the first embodiment will be described in light of the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When receiving the ACT command input from a device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 15 and 16, in the state transition diagram of FIG. 3, it transitions from the idle state indicated by 030 to the startup state indicated by 031. In the state transition diagram of FIG. 4, it transitions from the idle state indicated by 040 to the startup state indicated by 041. Synchronously with the timing of receiving the ACT command, the address signal input from the device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 15 and 16 is received. In the operation waveform diagrams of FIGS. 15 and 16, it is indicated by ADr. The address receiver and address decoder shown as 112 in FIG. 1 discriminate the address signal from the device external to the SDRAM, and the word lines (WL) of the designated bank address and row address are selected and driven by the row decoder shown as 130 in FIG. 2 and the global word line driver to be global word lines, and further by the global word line shown as 134 in FIG. 2 and the local word line driver, and are biased from the potential VIWL to the potential VRWL at time T52 shown in the operation waveform diagrams of FIGS. 15 and 16. The potential of the word lines (WL) (group) of the addresses not designated by the ADr and the word lines (WL) (group) of the sub-cell array (group) is driven to a non-select state by the row decoder shown as 130 in FIG. 2 and the global word line driver to be global word lines, and further by the global word line and the local word line driver shown as 134 in FIG. 2, and the potential remains at VIWL.

[0240] The source lines (SL) (group) of the sub-cell array designated by the ADr are biased from the floating state to 0V at time T52 shown in the operation waveform diagrams of FIGS. 15 and 16. The bit line(s) (BL) of the sub-cell array designated by the ADr is biased to the potential VRBL at time T52, once passing through 0V from the floating state. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and after the data is discriminated as "1" or "0" by the converted voltage, or while being discriminated, it is stored in each data register existing along with each bit line (BL). That is, the data read from each memory cell designated by the ADr is written into each data register designated by the ADr corresponding to each memory cell. Therefore, the data held by the memory cell(s) designated by the ADr is copied to the data register(s) designated by the ADr.

[0241] At time T53 shown in the operation waveform diagrams of FIGS. 15 and 16 when the data storage into the data register is completed, the word line (WL) potential designated by the ADr is driven to VIWL, and the bit line(s) (BL) of the sub-cell array designated by the ADr starts to discharge to 0V at time T53, and then the bit line(s) (BL) becomes a floating state together with the source line(s) (SL) designated by the ADr. It means that the state transitions to the active state indicated by 032 in the state transition diagram of FIG. 3 and the active state indicated by 042 in the state transition diagram of FIG. 4. The potential of each word line, the state of each bit line, and each source line continue until time T58 shown in the operation waveform diagrams of FIGS. 15 and 16. Therefore, the state of the floating body of each memory cell designated by the ADr is maintained. On the other hand, the data register(s) designated by the ADr holds the same data as the data held by the memory cell(s) designated by the ADr.

[0242] After receiving the ACT command and after the elapse of tRCD (ACT Command to internal read or write delay time), when an RD command is input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 15 and 16, the data of the memory cell(s) corresponding to the address signal input in synchronization with the RD command, the bank address and column address specified by ADc is read out to the device external to the SDRAM. In the state transition diagram of FIG. 3, it is the read state indicated by 033, and in the state transition diagram of FIG. 4, it transitions to the read state indicated by 043. After receiving the RD command at time T54 shown in the operation waveform diagrams of FIGS. 15 and 16 and after the elapse of CL (Column Latency), data output starts from time T55 shown in the operation waveform diagrams of FIGS. 15 and 16. Since it is the BL8 setting, data is output 8 times. Substantially, among the data register(s) holding the same data as the memory cell(s) specified by the ADr, the data of the data register(s) specified by ADc and BL8 is read out to the device external to the SDRAM. Among the data register(s) specified by the ADr, the data register(s) other than those specified by ADc and BL8 are in the data holding state.

[0243] After receiving the RD command and after the elapse of the READ to WRITE command delay time, when, at time T57 shown in the operation waveform diagrams of FIGS. 15 and 16, a WRA command is received from a device external to the SDRAM without receiving a WR command even once after receiving the ACT command, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr input in synchronization with the ACT command. In the state transition diagram of FIG. 3, it has transitioned to the write state shown as 036, and in the state transition diagram of FIG. 4, it has transitioned to the write state shown as 050.

[0244] The potential of the word line of the bank address and row address specified by the ADr is selected and driven by the row decoder shown as 130 in FIG. 2 and the global word line driver, and further by the local word line driver shown as 134 in FIG. 2 with respect to the global word line, from the time T58 shown in the operation waveform diagrams of FIGS. 15 and 16, biased from the potential VIWL to the potential VEWLH. Among the word line(s) not specified by the ADr, the non-selected word line(s) for which the sub-cell array becomes the selected state are driven to the non-selected state by the row decoder global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 with respect to the global word line, also from the time T58 shown in the operation waveform diagrams of FIGS. 15 and 16, biased from the potential VIWL to the potential VEWLL. The word line(s) belonging to the sub-array of the address not specified by the ADr are driven to the non-selected state by the row decoder and the global word line driver shown as 130 in FIG. 2, and further by the local word line driver shown as 134 in FIG. 2 with respect to the global word line, and remain at the potential VIWL.

[0245] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased to the potential VEBL from the floating state, also from the time T58 shown in the operation waveform diagrams of FIGS. 15 and 16. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0246] With the above potential settings, as described in the explanation of the operation waveform diagram of FIG. 7 for the SDRAM according to the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by the ADr are erased. At this point, the data held by the memory cell(s) specified by the ADr is erased. However, the SDRAM according to the first embodiment rewrites the data remaining after being copied to the data register(s) specified by the ADr into the memory cell(s) after transitioning to the state 053 shown in the state transition diagram of FIG. 4. Therefore, data loss of the memory cell(s) does not occur. On the other hand, among the memory cell(s) connected to the word lines of the bank address and row address not specified by the ADr, the memory cell(s) belonging to the non - selected sub - cell array is in an idle state. Since the potential relationship between the floating body potential of each memory cell connected to the non - selected word line(s) where the sub - cell array is in a selected state and the bit line and source line is almost the same as the idle state, the charge of the floating body is maintained.

[0247] To end the erasing operation, after the source line(s) and bit line(s) of the sub - cell array specified by the ADr are discharged to 0V at time T60 after the elapse of the time set inside the SDRAM device from time T58 shown in the operation waveform diagrams of FIGS. 15 and 16, they enter a floating state. The potential of the word line of the sub - cell array specified by the ADr is biased from VEWLH or VEWLL to VIWL at time T60 shown in the operation waveform diagrams of FIGS. 15 and 16, and the sub - cell array specified by the ADr enters an idle state. The state of the potential of each word line, each bit line, and each source line continues until time T63 shown in the operation waveform diagrams of FIGS. 15 and 16. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0248] Starting from time T59 shown in the operation waveform diagrams of FIGS. 15 and 16 after a predetermined WL (Write Latency) time has elapsed since the WRA command was received, since the burst length is 8 (BL8), as shown in the operation waveform diagrams of FIGS. 15 and 16, eight sets of data are sequentially input from the DQ signal lines shown in FIG. 1. The input data is sense-amplified by the data input receiver shown as 118 in FIG. 1 and then stored in the data input register shown as 119 in FIG. 1. In the case of the operation waveform diagram of FIG. 15, after being stored in the data input register, from the data input register shown as 119 in FIG. 1, by the IO driver shown as 123 in FIG. 1, writing is performed on the data register (group) within the area of 133 in FIG. 2, which is specified by the ADd and further specified as BL8 within the data register (group) specified by the ADr. On the other hand, among the data register (group) specified by the ADr, the data register not specified by the ADd and further specified as BL8 holds the same data as the memory cell connectable to the same bit line (BL) specified by the ADr. Also, in the case of the operation waveform diagram of FIG. 16, after being stored in the data input register, from the data input register shown as 119 in FIG. 1, by the IO driver shown as 123 in FIG. 1, writing is performed on the data register (group) within the area of 133 in FIG. 2, which is specified by the ADc and further specified as BL8 within the data register (group) specified by the ADr. On the other hand, among the data register (group) specified by the ADr, the data register not specified by the ADc and further specified as BL8 holds the same data as the memory cell connectable to the same bit line (BL) specified by the ADr. In the case of the SDRAM according to the first embodiment, depending on the WRA command, writing is not performed on the memory cell (group), and the input data is only written to the data register existing within 133 in FIG. 2, which is associated with the sub-cell array of the address specified by the ADr and ADd (in the case of the operation waveform diagram of FIG. 15) or ADc (in the case of the operation waveform diagram of FIG. 16), and further specified as BL8. That no inconvenience occurs due to the fact that data writing to the memory cell is not completed was described when explaining the operation waveforms of FIGS. 9 and 10 for the SDRAM according to the first embodiment. Also, as described when explaining the operation waveforms of FIGS. 9 and 10 for the SDRAM according to the first embodiment, it does not matter whether the bank address and column address specified when the RD command is input are the same as or different from the bank address and column address specified when the WRA command is input.

[0249] As also described in the explanation of FIG. 7, for the data register(s) specified by the ADr, among which the data register(s) within the area 133 of FIG. 2 specified by further being the ADc and BL8, the operation of writing to the data register(s) and the erasure operation for the memory cell(s) connected to the word line of the bank address and row address specified by the ADr are performed in parallel and independently. Therefore, depending on the set value of WL (Write Latency) and the period of the clock, the timings of the erasure operation start time and the data input start time may be before or after each other, and there is no problem even if they are before or after each other. The timings of the erasure operation end time and the data input / output completion time may also be before or after each other, and there is no problem even if they are before or after each other.

[0250] After the data input is completed, at time T62 after the elapse of tWR (Write Recovery Time), even if the PRE command is not input, the SDRAM automatically transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3 according to the SDRAM specification by an automatic sequence. In the SDRAM according to this embodiment, the memory cell and data register that were in the active state transition to the precharge state indicated by 053 in FIG. 4. That is, at time T62 shown in the operation waveform diagram of FIG. 8, the operation of writing the data of the data register(s) specified by the ADr to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr is started. In the state transition diagram of FIG. 3, it is considered to have transitioned to the precharge state indicated by 037, and in the state transition diagram of FIG. 4, it is considered to have transitioned to the precharge state indicated by 053. Since substantially "0" data has already been written by the erasure operation, in the writing sequence here, a "1" is written to the memory cell(s) corresponding to the data register holding "1" data, and for the memory cell corresponding to the data register holding "0" data, the state where "0" data has already been written is maintained.

[0251] The potential of the word line of the bank address and row address specified by the ADr is biased from the potential VIWL to the potential VWWLH at time T63 shown in the operation waveform diagrams of FIGS. 15 and 16 by the row decoder and global word line driver shown in FIG. 2, the global word line, and further by the global word line and local word line driver. Among the word line(s) not specified by the ADr, the global word line driven to be in a non-selected state by the row decoder and global word line driver shown in FIG. 2 and the local word line driver biases the non-selected word line(s) in the sub-cell array from the potential VIWL to the potential VWWLL at time T63 shown in the operation waveform diagrams of FIGS. 15 and 16. The word line(s) belonging to the sub-array of the address not specified by the ADr is / are driven to be in a non-selected state by the row decoder and global word line driver shown in FIG. 2, the global word line, and further by the global word line and local word line driver, and remains at the potential VIWL. The source line(s) of the sub-cell array specified by the ADr is biased from a floating state to 0V at time T63 shown in the operation waveform diagrams of FIGS. 15 and 16. The potential of the bit line(s) of the sub-cell array specified by the ADr is biased according to the data stored in the data register(s) corresponding to the bit line(s). When the data in the data register is "0", the bit line (BL) is biased from a floating state to 0V at time T63 shown in the operation waveform diagrams of FIGS. 15 and 16. When the data in the data register is "1", the bit line (BL) is biased from a floating state to the potential VWBL at time T63. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in a floating state.

[0252] With the above potential settings, among the memory cell(s) connected to the word lines of the bank address and row address specified by the ADr, the memory cell(s) to which VWBL is biased on the bit line (BL) allows current to flow, causing the impact ionization phenomenon to occur. The generated hole(s) accumulate in the floating body of each memory cell, and the electron(s) are discharged to the bit line (BL), indicating that data "1" has been written. On the other hand, for the memory cell(s) to which 0V is biased on the bit line (BL), since the potentials of the bit line (BL) and the source (line) are the same, no current flows, and thus the impact ionization phenomenon does not occur. Therefore, the floating body of each memory cell maintains the erased state, indicating that data "0" has been written. That is, data is read from each data register specified by the ADr, and the read data is written to each memory cell specified by the ADr corresponding to the data register. In addition to the data written by the WR command or the WRA command, the data lost during the erase operation is copied and stored in the data register(s). Therefore, there is no loss of data in the memory cells due to the erase operation....

Claims

1. A clock-synchronized semiconductor memory device having a memory cell array in which memory cells are arranged in a matrix in two orthogonal directions in a plan view on a semiconductor substrate, having a data register for temporarily storing data between the memory cell array and input / output terminals of the clock-synchronized semiconductor memory device, furthermore, the clock-synchronized semiconductor memory device having an instruction set which is a collection of instructions (commands) for operating the clock-synchronized semiconductor memory device, the instruction set including an active command for putting the memory cell into a selected state, a precharge command for releasing the selected state of the memory cell, a write command for inputting data from the input / output terminals, including a plurality of commands with auto-precharge for releasing the selected state of the memory cell without depending on the precharge command, by the write command, data input from the input / output terminals of the clock-synchronized semiconductor memory device is written into the data register, while the selected state of the memory cell is released after receiving either the precharge command or any of the plurality of commands with auto-precharge, the data stored in the data register is written into the memory cell selected by the active command A clock-synchronized semiconductor memory device characterized by the above.

2. The instruction set includes a read command for outputting data from the input / output terminals, a write command with auto-precharge for data input from the input / output terminals and releasing the selected state of the memory cell after completion of the data input, and a read command with auto-precharge for data output from the input / output terminals and releasing the selected state of the memory cell after starting the data output, by the write command, the data input from the input / output terminals is written into the data register, after receiving the precharge command, or after a first time has elapsed after receiving the read command with auto-precharge, or after a second time different from the first time has elapsed after receiving the write command with auto-precharge, an operation of writing the data stored in the data register into the memory cell selected by the active command is started The clock-synchronized semiconductor memory device according to claim 1, characterized in that...

3. The data register is disposed adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command. The clock-synchronized semiconductor memory device according to claim 1, characterized in that...

4. (Figs. 30 and 42) The data register is disposed adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command within the memory cell array disposed adjacent to the data register. The clock-synchronized semiconductor memory device according to claim 1, characterized in that...

5. The memory cell has a structure including a MOS field-effect transistor in which at least a part of a floating body serving as a memory node forms a current path. The clock-synchronized semiconductor memory device according to claim 1, characterized in that...

6. The data storable in the memory cell is binary as a logic level, and after the data stored in the selected memory cell is written into the data register by the active command, a writing operation of data of one of the binary logics is performed on all of the selected memory cells. The clock-synchronized semiconductor memory device according to claim 1, characterized in that...

7. The data storable in the memory cell is binary as a logic level, and the data stored in the data register is written into the memory cell selected by the active command by a signal different from a control signal for performing a writing operation of data of one of the binary logics on all of the selected memory cells. The clock-synchronized semiconductor memory device according to claim 6, characterized in that...

8. The operation of inputting data via the input / output terminal or the operation of outputting data via the input / output terminal, and the operation of performing a writing operation of data of one of the binary logics on all of the selected memory cells are performed independently and in parallel. The clock-synchronized semiconductor memory device according to claim 6, characterized in that...

9. By receiving the write command or the write command with auto precharge, the write operation of data of one of the two logics in the binary logic is performed on all the selected memory cells. The clock synchronous semiconductor memory device according to claim 6, characterized in that.

10. Only when one of the write command or the write command with auto precharge is first received after receiving the active command, the write operation of data of one of the two values is performed on all the selected memory cells by the write command or the write command with auto precharge. The clock synchronous semiconductor memory device according to claim 9, characterized in that.

11. Even when the read command or the read command with auto precharge is received, the write operation of data of one of the two logics is performed on all the selected memory cells. The clock synchronous semiconductor memory device according to claim 9, characterized in that.

12. Only when one of the write command, the write command with auto precharge, the read command, or the read command with auto precharge is first received after receiving the active command, the write operation of data of one of the two values is performed on all the selected memory cells. The clock synchronous semiconductor memory device according to claim 11, characterized in that.

13. One end of the memory cell is connected to a bit line, the other end is connected to a source line, and the data stored in the memory cell is determined by the amount of current flowing between the bit line and the source line, and the extension direction of the bit line and the extension direction of the source line are arranged in parallel. The clock synchronous semiconductor memory device according to claim 1, characterized in that.

14. The bit line connected to one end of one of the memory cells and the source line connected to the other end are different wiring layers, all the bit lines in the memory cell array are the same wiring, and all the source lines are the same wiring layer. The clock synchronous semiconductor memory device according to claim 13, characterized in that.

15. The bit line connected to one end of the memory cell and the source line connected to the other end are different wiring layers, and in the memory cell array, the bit lines formed in different wiring layers exist. The clock synchronous type semiconductor memory device according to claim 13, characterized by the above.

16. The bit line connected to one end of the memory cell and the source line connected to the other end are different wiring layers, and in the memory cell array, the source lines formed in different wiring layers exist. The clock synchronous type semiconductor memory device according to claim 13, characterized by the above.

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