Semiconductor element, and manufacturing method of semiconductor element

Abstract

To provide a semiconductor element capable of suppressing unintended etching and suppressing a loss of light, and a manufacturing method thereof.SOLUTION: A semiconductor element is formed from a substrate including a silicon layer and a compound semiconductor and joined to the silicon layer. In the semiconductor element, the silicon layer includes a first waveguide, a second waveguide, a first recess, a second recess, a terrace and a first slab part. The first waveguide is connected to one end of the first slab part, and the second waveguide is connected to the other end of the first slab part. The first slab part is connected to the terrace and positioned between the first recess and the second recess. The semiconductor element comprises a protrusion, a second slab part and the third slab part. The second slab part is joined to the first slab part, the protrusion protrudes from the second slab part onto the first waveguide and the third slab part is positioned on the second waveguide, the second recess and the terrace on both the sides of the second waveguide.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present disclosure relates to a semiconductor optical element and a method for manufacturing the semiconductor optical element.

Background Art

[0002] A semiconductor element formed of a compound semiconductor and having optical gain can be bonded to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed to form a hybrid semiconductor optical element (for example, Non-Patent Document 1). After bonding, etching or the like is performed on the semiconductor element. Light is transitioned between the silicon waveguide and the semiconductor element.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A groove (trench) is provided in the substrate. The etchant may enter the groove and the semiconductor element may be etched from the bonding interface. In order to suppress damage to the semiconductor element, it is required to suppress unintentional etching. In order to suppress light loss, it is required to increase the coupling efficiency between the waveguide and the semiconductor element. Therefore, an object is to provide a semiconductor optical element and a method for manufacturing the semiconductor optical element capable of suppressing unintentional etching and suppressing light loss.

Means for Solving the Problems

[0005] The semiconductor optical element according to the present disclosure includes a substrate having a silicon layer, and a semiconductor element formed of a Group III-V compound semiconductor and bonded to the silicon layer. The silicon layer has a first waveguide, a second waveguide, a first recess, a second recess, a terrace, and a first slab portion. The first recess and the second recess are portions recessed from the surfaces of the first waveguide, the second waveguide, the terrace, and the first slab portion. The first recess and the terrace are arranged in this order on both sides of the first waveguide. The second recess and the terrace are arranged in this order on both sides of the second waveguide. The first waveguide is connected to one end of the first slab portion, and the second waveguide is connected to the other end of the first slab portion. The first slab portion is connected to the terrace and is located between the first recess and the second recess. The semiconductor element has a protruding portion, a second slab portion, and a third slab portion. The second slab portion is bonded to the first slab portion. The protruding portion protrudes from the second slab portion onto the first waveguide. The third slab portion is located on the second waveguide, the second recess, and the terraces on both sides of the second waveguide.

Advantages of the Invention

[0006] According to the present disclosure, it is possible to provide a semiconductor optical element and a method for manufacturing the semiconductor optical element that can suppress unintentional etching and suppress light loss.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One embodiment of the present disclosure includes (1) a substrate having a silicon layer, and a semiconductor element formed of a III-V compound semiconductor and bonded to the silicon layer. The silicon layer has a first waveguide, a second waveguide, a first recess, a second recess, a terrace, and a first slab portion. The first recess and the second recess are portions that are recessed from the surfaces of the first waveguide, the second waveguide, the terrace, and the first slab portion. On both sides of the first waveguide, the first recess and the terrace are arranged in this order. On both sides of the second waveguide, the second recess and the terrace are arranged in this order. The first waveguide is connected to one end of the first slab portion, and the second waveguide is connected to the other end of the first slab portion. The first slab portion is connected to the terrace and is located between the first recess and the second recess. The semiconductor element has a protruding portion, a second slab portion, and a third slab portion. The second slab portion is bonded to the first slab portion. The protruding portion protrudes from the second slab portion onto the first waveguide. The third slab portion is a semiconductor optical element located on the second waveguide, the second recess, and the terraces on both sides of the second waveguide. Since the second recess is sealed by the first slab portion and the third slab portion, the intrusion of the etchant into the second recess is suppressed. Unintended etching of the semiconductor element can be suppressed. Since an MMI is formed, light loss can be suppressed. (2) In the above (1), the width of the first slab portion may be larger than the widths of the first waveguide and the second waveguide. Since the MMI is formed, light loss can be suppressed. (3) In the above (1) or (2), the width of the second slab portion may be larger than the width of the protruding portion. Since the MMI is formed, light loss can be suppressed. (4) In any one of the above (1) to (3), the planar shapes of the first slab portion and the second slab portion may be rectangular. Since the MMI is formed, light loss can be suppressed. (5) In any one of the above (1) to (4), the first waveguide has a first tapered portion, and the width of the first tapered portion is larger closer to the first slab portion and smaller farther from the first slab portion. The second waveguide has a second tapered portion, and the width of the second tapered portion may be larger closer to the first slab portion and smaller farther from the first slab portion. Since the coupling efficiency between the substrate and the semiconductor element is increased, light loss can be suppressed. (6) In any one of the above (1) to (5), the protruding portion has a third tapered portion, and the width of the protruding portion may be larger closer to the second slab portion and smaller farther from the second slab portion. Since the optical mode shape changes gradually, light loss can be suppressed. (7) In any one of the above (1) to (6), the second slab portion, the third slab portion, and the protruding portion of the semiconductor element may be formed of indium phosphide. The semiconductor element is processed by wet etching. The intrusion of the etchant into the second recess is suppressed. Unintended etching of the semiconductor element can be suppressed. (8) In any one of the above (1) to (7), an insulating film covering the silicon layer and the semiconductor element may be provided. The insulating film covers the first waveguide and the MMI and functions as a cladding layer. Light loss can be suppressed. (9) A step of bonding a semiconductor element formed of a group III-V compound semiconductor to a silicon layer of a substrate, and a step of performing wet etching on the bonded semiconductor element, wherein the silicon layer has a first waveguide, a second waveguide, a first recess, a second recess, a terrace, and a first slab portion, the first recess and the second recess are portions recessed from the surfaces of the first waveguide, the second waveguide, the terrace, and the first slab portion, the first recess and the terrace are arranged in this order on both sides of the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide, the first waveguide is connected to one end of the first slab portion, the second waveguide is connected to the other end of the first slab portion, the first slab portion is connected to the terrace and is located between the first recess and the second recess, the step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slab portion, the second waveguide, and the terraces on both sides of the first waveguide and the second waveguide, in the step of performing wet etching, a protrusion, a second slab portion, and a third slab portion are formed on the semiconductor element, the second slab portion is bonded to the first slab portion, the protrusion protrudes from the second slab portion onto the first waveguide, and the third slab portion is located on the second waveguide, the second recess, and the terraces on both sides of the second waveguide. A method for manufacturing a semiconductor optical element. The second recess is sealed by the first slab portion and the third slab portion. The intrusion of the etchant into the second recess is suppressed. Unintended etching of the semiconductor element can be suppressed. Since an MMI is formed, light loss can be suppressed.

[0010] [Details of Embodiments of the Present Disclosure] Specific examples of a semiconductor optical element and a method for manufacturing the semiconductor optical element according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] [Embodiment] (Semiconductor Optical Element) FIG. 1 is a plan view illustrating a semiconductor optical element 100 according to an embodiment. The semiconductor optical element 100 is a hybrid type wavelength tunable laser element, and includes a substrate 10 and a semiconductor element 30. The semiconductor element 30 has optical gain and is bonded to one surface of the substrate 10. The Z-axis direction is the normal direction of the upper surface of the substrate 10. The X-axis direction is a direction parallel to the waveguide. One direction along the X-axis is defined as the +X direction. The direction opposite to the +X direction is defined as the -X direction. The Y-axis direction is orthogonal to the X-axis direction and the Z-axis direction.

[0012] The semiconductor optical element 100 includes MMI (Multi Mode Interferometer) 101, MMI 102, two ring resonators 103, and two loop mirrors 104. From the -X direction to the +X direction, the loop mirror 104, the ring resonator 103, MMI 102, the semiconductor element 30, MMI 101, the ring resonator 103, and the loop mirror 104 are arranged in this order. A laser resonator is formed by these configurations.

[0013] MMI 101 and MMI 102 are each a 1-input 1-output MMI, and are formed by the substrate 10 and the semiconductor element 30. The ring resonator 103 and the loop mirror 104 are provided on the substrate 10.

[0014] FIG. 2A is an enlarged plan view of the vicinity of MMI 101. FIG. 2B is a plan view illustrating the substrate 10, with the semiconductor element 30 removed from FIG. 2A. FIGS. 3A to 4B are cross-sectional views illustrating the semiconductor optical element 100, and illustrate cross-sections along lines A1, A2, A3, and A4 in FIG. 2A, respectively. The light distribution is illustrated by a broken line in FIGS. 3A to 4B.

[0015] As shown in FIGS. 3A to 4B, the substrate 10 is a SOI (Silicon on Insulator) substrate and includes a substrate 12, a box layer 14, and a silicon (Si) layer 16 laminated in order in the Z-axis direction. The substrate 12 is formed of, for example, Si. The box layer 14 is formed of, for example, silicon oxide (SiO2). The thickness of the box layer 14 is, for example, 3 μm. The thickness of the silicon layer 16 is, for example, 220 nm. The upper surface of the substrate 10 and the surface of the semiconductor element 30 are covered with an insulating film 11. The insulating film 11 is formed of, for example, SiO2 with a thickness of 1 μm. The refractive index of the silicon layer 16 is 3.45. The refractive indices of the box layer 14 and the insulating film 11 are lower than that of the silicon layer 16 and are 1.45. Functional parts such as waveguides are provided in the silicon layer 16 of the substrate 10.

[0016] As shown in FIGS. 2A and 2B, the substrate 10 has a waveguide 20 (first waveguide), a waveguide 22 (second waveguide), a recess 24 (first recess), a recess 26 (second recess), a terrace 27, and a slab portion 28 (first slab portion).

[0017] From the +X side to the -X side, the waveguide 20, the slab portion 28, and the waveguide 22 are arranged in this order. The waveguide 20 is connected to one end (the +X side end) of the slab portion 28. The waveguide 22 is connected to the other end (the -X side end) of the slab portion 28. The waveguide 20 and the waveguide 22 are parallel to the X-axis direction.

[0018] The waveguide 20 has a taper portion 21 (first taper portion). The waveguide 22 has a taper portion 23 (second taper portion). The widths of the taper portion 21 and the taper portion 23 are larger the closer they are to the slab portion 28 and smaller the farther they are from the slab portion 28.

[0019] In the Y-axis direction, a recess 24 and a terrace 27 are provided on both sides of the waveguide 20 in this order. That is, the recess 24 is disposed adjacent to the waveguide 20. The terrace 27 is disposed opposite to the waveguide 20 of the recess 24. On both sides of the waveguide 22, a recess 26 and a terrace 27 are provided in this order. The recess 24 extends along the waveguide 20 and has a tapered shape corresponding to the tapered portion 21 of the waveguide 20. The recess 26 extends along the waveguide 22 and has a tapered shape corresponding to the tapered portion 23 of the waveguide 22.

[0020] The slab portion 28 is located between the recess 24 and the recess 26 in the X-axis direction and is connected to the two terraces 27 on both sides of the waveguide. The space between the recess 24 and the recess 26 is blocked by the slab portion 28. The planar shape of the slab portion 28 is rectangular. The slab portion 28 is plate-shaped and has no grooves, holes, etc.

[0021] The width W1 of the tip of the waveguide 20 shown in FIG. 2B is, for example, 400 nm. The width W2 of the portion of the tapered portion 21 connected to the slab portion 28 is, for example, 2.4 μm. The width W3 of the recess 24 is, for example, 1 μm or more and 10 μm or less, and may be 2 μm, 3 μm, 4 μm, etc. The dimensions of the waveguide 22 may be the same as or different from the dimensions of the waveguide 20. The dimensions of the recess 26 may be the same as or different from the dimensions of the recess 24. The length L1 of the slab portion 32 in the X-axis direction is, for example, 37.8 μm.

[0022] As shown in FIGS. 3A and 3B, the waveguide 20 and the terrace 27 are portions of the silicon layer 16 that protrude in the Z-axis direction (upward) from the recess 24. The surface of the waveguide 20 is located at the same height as the surface of the terrace 27. The recess 24 is a portion that is recessed from the surfaces of the waveguide 20 and the terrace 27. As shown in FIG. 4B, the surface of the waveguide 22 is located at the same height as the surface of the terrace 27. The recess 26 is a portion that is recessed from the surfaces of the waveguide 22 and the terrace 27. The silicon layer 16 serves as the bottom surface of the recesses 24 and 26. The thickness of the silicon layer 16 in the recesses is, for example, 30 nm. The recesses 24 and 26 may extend halfway through the silicon layer 16 in the Z-axis direction, or may penetrate the silicon layer 16 and extend to the box layer 14. The insulating film 11 is embedded in the recesses 24 and 26.

[0023] As shown in FIG. 4A, the surface of the slab portion 28 is located at the same height as the surface of the terrace 27. The slab portion 28 is integrated with the terrace 27, extends parallel to the XY plane, and forms the surface of the silicon layer 16.

[0024] As shown in FIG. 1, the semiconductor element 30 includes two slab portions 32 (second slab portions), two protruding portions 34, two slab portions 36 (third slab portions), a mesa 38, an electrode 48, and an electrode 49. From the +X side to the -X side, the protruding portion 34, the slab portion 32, the slab portion 36, the mesa 38, the slab portion 36, the slab portion 32, and the protruding portion 34 are arranged in order. The slab portions 32 and 36 are plate-shaped.

[0025] As shown in FIG. 2A, the planar shapes of the slab portion 32 and the slab portion 36 are rectangular. The width W4 of the slab portion 32 is, for example, 4 μm. The length L2 of the slab portion 32 in the X-axis direction is smaller than the length L1 of the slab portion 28 of the silicon layer 16, and is, for example, 33.8 μm. The slab portion 32 is located on the slab portion 28 of the silicon layer 16 and does not protrude outside the slab portion 28. It extends from the position where the slab portion 28 overlaps the slab portion 32 to the outside of the slab portion 32. The distance D1 from the end of the slab portion 32 to the end of the slab portion 28 is, for example, 2 μm. As shown in FIGS. 2A and 4A, the slab portion 32 is joined to the slab portion 28 of the substrate 10.

[0026] As shown in FIG. 2A, the protruding portion 34 of the semiconductor element 30 extends parallel to the X-axis, protrudes from the slab portion 32 onto the waveguide 20, and is located on the tapered portion 21 of the waveguide 20. The protruding portion 34 has a tapered shape. The width of the protruding portion 34 is larger closer to the slab portion 32 and smaller farther from the slab portion 32. The width W5 at the connection position of the protruding portion 34 with the slab portion 32 is, for example, 2 μm. As shown in FIGS. 2A and 3B, the protruding portion 34 is joined to the waveguide 20 and the slab portion 28 of the substrate 10.

[0027] As shown in FIG. 2A, the slab portion 36 is located opposite to the protruding portion 34 of the slab portion 32 in the X-axis direction. The slab portion 36 is located on the waveguide 22, the recess 26, and the terraces 27 on both sides of the waveguide 22, and the slab portion 28, and is joined to the waveguide 22, the terraces 27, and the slab portion 28. The distance D2 from the recess 26 of the silicon layer 16 to the end of the slab portion 36 is, for example, 2 μm.

[0028] The protruding portion 34 does not protrude outside the waveguide 20 and is located inside the waveguide 20. The waveguide 20 protrudes from under the protruding portion 34 to the outside of the protruding portion 34.

[0029] As shown in FIG. 1, MMI 102 has the same configuration as MMI 101. The waveguide 22, the recess 26, and the terrace 27 extend from MMI 101 to MMI 102. The recess 26 is located between the waveguide 22 and the terrace 27. The slab portion 36 of the semiconductor element 30 extends from MMI 101 to MMI 102 and is located above the recess 26, the terrace 27, and the waveguide 22. The recess 26 is sealed by the slab portion 28 and the slab portion 36.

[0030] FIG. 5 is a cross-sectional view illustrating the semiconductor optical element 100, showing a cross-section along the line L in FIG. 1. The semiconductor element 30 has a cladding layer 40, an active layer 42, a cladding layer 44, and a contact layer 46. The cladding layer 40 contacts the silicon layer 16 and forms the protruding portion 34, the slab portion 32, and the slab portion 36 shown in FIG. 2A.

[0031] As shown in FIG. 5, on the cladding layer 40, the active layer 42, the cladding layer 44, and the contact layer 46 are laminated in this order. The active layer 42 is located above the waveguide 22, the recess 26, and the terrace 27. The cladding layer 44 and the contact layer 46 are laminated on the active layer 42, located above the waveguide 22, and form the mesa 38.

[0032] The insulating film 11 covers the upper surface of the cladding layer 40, the upper surface and the side surfaces of the active layer 42, and the side surfaces of the mesa 38. The insulating film 11 has an opening on the active layer 42 and also has an opening on the mesa 38. The electrode 48 is a p-type electrode and extends from above the mesa 38 to outside the mesa 38. The electrode 48 is electrically connected to the contact layer 46 through the opening of the insulating film 11. The electrode 49 is spaced apart from the mesa 38 and is electrically connected to the cladding layer 40 through the opening of the insulating film 11.

[0033] As shown in FIG. 1, the end portion of the mesa 38 in the X-axis direction may have a tapered shape. The end portion of the active layer 42 in the X-axis direction may have a tapered shape. By providing the tapered shape, the coupling efficiency is increased.

[0034] The cladding layer 40 is formed of, for example, n-type indium phosphide (n-InP) with a thickness of 0.4 μm. The active layer 42 has a quantum well structure (MQW: Multiple Quantum Well) and includes barrier layers and well layers. A plurality of barrier layers and a plurality of well layers are alternately stacked. The barrier layers and the well layers are formed of, for example, gallium indium arsenide phosphide (GaInAsP). The cladding layer 44 is formed of, for example, p-type indium phosphide (p-InP). The contact layer 46 is formed of, for example, p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 30 may be formed of III-V compound semiconductors other than those described above.

[0035] The electrodes 48 and 49 are formed of metal. The electrode 48 is formed of, for example, a laminate of titanium (Ti), platinum (Pt), and gold (Au) from the side closer to the mesa 38. The electrode 49 is formed of, for example, an alloy of gold, germanium, and nickel (AuGeNi).

[0036] A voltage is applied to the semiconductor element 30 using the electrodes 48 and 49, and carriers are injected into the active layer 42. The active layer 42 has optical gain and generates light by carrier injection. The wavelength of the light is, for example, 1.5 μm. The semiconductor element 30 and the substrate 10 are coupled by evanescent light. The light generated in the semiconductor element 30 propagates through the waveguide 22 and transfers to the waveguide 20 at the MMI 101 and the MM 102. The light resonates in the ring resonator 103 and is reflected by the loop mirror 104. The reflected light propagates toward the semiconductor element 30 and transfers from the waveguide 20 to the waveguide 22 at the MMI 101 and the MMI 102. By repeatedly reflecting the light, laser oscillation occurs.

[0037] The diameter of one of the two ring resonators 103 is different from that of the other. The oscillation wavelength is determined by the Vernier effect of the two ring resonators 103. The transmittance of one of the two loop mirrors 104 is higher than that of the other. A part of the laser light passes through the loop mirror 104 and is emitted outside the semiconductor optical element 100.

[0038] In FIGS. 3A to 4B, the shape of the light is schematically illustrated as a dashed ellipse. The optical mode is defined by the waveguides 20 and 22, and in the MMI, it is defined by the slab portion 32. Light is intensively distributed in the waveguides 20 and 22. In the MMI, the light is widely distributed over the width of the slab portion 32.

[0039] When light enters the MMI and when light is output from the MMI, the optical mode is converted. By adjusting the length and width of the slab portion 28 and the slab portion 32, the optical mode can be controlled. The same mode is imaged at the output portion and the input portion of the MMI. For example, a single mode propagates in the waveguide 20. When light enters the MMI101 from the waveguide 20, a multi-mode is generated. When the light is output from the MMI101 to the waveguide 22, the mode is converted to a single mode. The same mode propagates in the waveguide 20 and the waveguide 22. Also in the MMI102, the input and output mode shapes can be made closer to the same. The optical loss in the semiconductor optical element 100 can be suppressed.

[0040] FIG. 6 is a diagram illustrating the calculation result of the transmittance. The horizontal axis represents the MMI length. The MMI length is the length L2 of the slab portion 32 of the semiconductor element 30 shown in FIG. 2A. The vertical axis represents the transmittance of light in the MMI. The wavelength of the light is set to 1.5 μm. The transmittance is calculated by changing the length L2 from 32 μm to 36 μm. The transmittance is 0.9 or more for any value of the length L2 from 32 μm to 36 μm. The optical loss in the MMI is suppressed.

[0041] (Manufacturing method) FIG. 7, FIG. 10, and FIG. 13 are plan views illustrating a method for manufacturing the semiconductor optical element 100. FIGS. 8A to 9B are cross-sectional views illustrating the method for manufacturing the semiconductor optical element 100, and illustrate cross-sections along lines A1, A2, A3, and A4 in FIG. 7, respectively. FIGS. 11A to 12B are cross-sectional views illustrating the method for manufacturing the semiconductor optical element 100, and illustrate cross-sections along lines A1, A2, A3, and A4 in FIG. 10, respectively. FIGS. 14A to 15B are cross-sectional views illustrating the method for manufacturing the semiconductor optical element 100, and illustrate cross-sections along lines A1, A2, A3, and A4 in FIG. 13, respectively.

[0042] In a step prior to FIG. 7, for example, dry etching is performed on the silicon layer 16 of the substrate 10. Portions exposed from a mask (not shown) are etched to form recesses 24 and 26. Portions covered with the mask (not shown) are not etched. As shown in FIG. 2B, the waveguides 20 and 22, the terraces 27, and the slab portions 28 are formed.

[0043] On an InP wafer different from the silicon wafer (substrate 10), the contact layer 46, the cladding layer 44, the active layer 42, and the cladding layer 40 are epitaxially grown in order by, for example, metal organic chemical vapor deposition (MOCVD). After film formation, the wafer is diced to form the semiconductor element 30. The semiconductor element 30 immediately after dicing is a rectangular parallelepiped and does not have slab portions, protruding portions 34, or the like.

[0044] As shown in FIGS. 7 to 9B, the semiconductor element 30 is bonded to the upper surface of the substrate 10. One surface of the silicon layer 16 and the clad layer 40 of the semiconductor element 30 are irradiated with plasma to activate these surfaces. The clad layer 40 is brought into contact with the surface of the silicon layer 16, and the semiconductor element 30 is bonded to the silicon layer 16. For example, the bonding strength is increased by pressurization and heat treatment. The semiconductor element 30 covers, for example, the entire surface of the silicon layer 16 and is located above the waveguide 20, the waveguide 22, the recess 24, the recess 26, the terrace 27, and the slab portion 28. After bonding, wet etching is performed to remove the InP substrate. The semiconductor layer from the contact layer 46 to the clad layer 40 remains.

[0045] As shown in FIGS. 10 to 12B, wet etching is performed to remove the active layer 42 from the contact layer 46 of the semiconductor element 30. The clad layer 40 remains. At the position L shown in FIG. 5, the active layer 42 remains from the contact layer 46 to form the mesa 38.

[0046] As shown in FIGS. 13 to 15B, for example, wet etching is performed to form the slab portion 32, the slab portion 36, and the protruding portion 34. For example, a hydrochloric acid-based chemical solution is used as the etchant. The portion of the semiconductor element 30 protected by a mask (not shown) is not etched. The portion exposed from the mask is removed by etching.

[0047] In the wet etching process, the etchant enters the recess 24. A slab portion 28 is provided between the recess 24 and the recess 26, and the recess 26 is blocked by the slab portion 28 and the slab portion 36. Since the entry of the etchant into the recess 26 is suppressed, the etching of the semiconductor element 30 from the bonding interface is suppressed.

[0048] The insulating film 11 is formed as shown in FIGS. 3A to 4B by, for example, plasma CVD (PECVD, Plasma Enhanced Chemical Vapor Deposition). The electrodes 48 and 49 are formed by vacuum evaporation. The semiconductor optical element 100 is formed by the above steps.

[0049] (Comparative Example) FIG. 16 is a plan view illustrating a semiconductor optical element 110 according to a comparative example. FIGS. 17A to 17C are cross-sectional views illustrating the semiconductor optical element 110, and illustrate cross-sections along line B1, line B2, and line B3 in FIG. 16, respectively. Description of the same configuration as in the embodiment will be omitted.

[0050] As shown in FIGS. 16 to 17C, the substrate 10 has a waveguide 20, a recess 24, and a terrace 27, and does not have a slab portion. The waveguide 20, the recess 24, and the terrace 27 extend from one end of the substrate 10 in the X-axis direction to the other end. The waveguide 20 has a tapered portion 21, a portion 29, and a portion 25. In the X-axis direction, the portion 29, the tapered portion 21, the portion 25, the tapered portion 21, and the portion 29 are arranged in this order. The portion 25 is wider than the portion 29. The tapered portion 21 is connected to the portion 29 and the portion 25.

[0051] The semiconductor element 30 has a slab portion 31 and a protruding portion 34. The protruding portion 34 protrudes in the X-axis direction from the slab portion 31 and is located above the portion 25 of the waveguide 20. The slab portion 31 is located above the waveguide 20, the recess 24, and the terrace 27.

[0052] The recess 24 is located on both sides of the waveguide 20 and extends from outside the semiconductor element 30 to below the semiconductor element 30. In the process of performing wet etching on the semiconductor element 30, a liquid such as an etchant enters the recess 24 and flows to below the semiconductor element 30. When the semiconductor element 30 is etched from the lower surface (bonding interface), damage occurs to the semiconductor element 30. The bonding strength of the semiconductor element 30 to the substrate 10 decreases.

[0053] According to this embodiment, the silicon layer 16 of the substrate 10 has a waveguide 20, a waveguide 22, a recess 24, a recess 26, and a slab portion 28. The slab portion 28 is located between the recess 24 and the recess 26 and blocks the space between the recess 24 and the recess 26. The semiconductor element 30 is bonded to the silicon layer 16 and has a slab portion 32 and a slab portion 36. The slab portion 36 is located above the waveguide 22, the recess 26, and the terrace 27. The recess 26 is sealed by the slab portion 28 and the slab portion 36. It is difficult for a liquid such as an etchant to enter the recess 26. Unintended etching of the semiconductor element 30 can be suppressed.

[0054] The semiconductor element 30 is formed of a III-V compound semiconductor. Wet etching is performed after bonding to form a protrusion 34, a slab portion 32, a slab portion 36, and the like. The semiconductor element 30 includes an InP cladding layer, an InGaAsP active layer 42, and an InGaAs contact layer 46. In wet etching, an etchant suitable for these semiconductors is used. For example, a hydrochloric acid-based solution is used as the etchant. Since the intrusion of the etchant into the recess 26 is suppressed by the slab portion 28 and the slab portion 36, unintended etching of the semiconductor element 30 can be suppressed.

[0055] When the slab portion 32 extends over the recess 24, the slab portion 32 is etched by the etchant entering the recess 24. As shown in FIG. 2A, the slab portion 32 does not extend over the recess 24 and is located above the slab portion 28 of the silicon layer 16. The slab portion 32 is difficult to be etched from the bonding interface. The distance D1 from the slab portion 32 to the recess 24 may be 2 μm or more, or may be 2 μm or less. The distance D2 from the end of the slab portion 36 to the recess 26 may be 2 μm or more, or may be 2 μm or less. Since the slab portion 36 covers the entire recess 26 and the recess 26 is not exposed from the slab portion 36, the intrusion of the etchant into the recess 26 is suppressed.

[0056] The MMI101 and MMI102 are formed by the silicon layer 16 and the semiconductor element 30. As shown in FIG. 2A, the waveguide 20 and the waveguide 22 extend from the slab portion 28. The slab portion 32 of the semiconductor element 30 is joined to the slab portion 28. The protruding portion 34 protrudes from the slab portion 32 above the waveguide 20. Single-mode light propagates through the waveguide 20. When the light enters the slab portion 28, the mode is converted into a multi-mode. When the light is output from the MMI to the waveguide 22, single-mode light is imaged and propagates through the waveguide 22. By making the mode shapes of the light closer to the same on the input side and the output side, the light loss can be suppressed.

[0057] By adjusting the widths and lengths of the waveguide and the slab portion, the mode shape can be controlled. The mode shapes at the time of input to the MMI and at the time of output from the MMI can be made closer to the same. As shown in FIG. 6, when the MMI length L2 is 32 μm or more and 36 μm or less, the transmittance is high and the light loss is suppressed. This is because the mode shapes are close to the same.

[0058] The width of the slab portion 28 of the silicon layer 16 is larger than the widths of the waveguide 20 and the waveguide 22. The width of the slab portion 32 of the semiconductor element 30 is larger than the width of the protruding portion 34. The MMI101 and MMI102 are formed. The mode is converted in the input and output of light to the MMI. By adjusting the length L2 etc. of the slab portion 32, the mode shape when inputting to the MMI and the mode shape when outputting become closer to the same. The coupling efficiency is increased and the light loss can be suppressed.

[0059] The planar shapes of the slab portion 28 and the slab portion 32 are rectangular. The MMI101 and MMI102 are formed. The light loss can be suppressed.

[0060] The waveguide 20 has a tapered portion 21, and the waveguide 22 has a tapered portion 23. Since the mode shape of the light gradually changes, the light loss can be suppressed.

[0061] The protruding portion 34 of the semiconductor element 30 has a tapered portion (third tapered portion), and for example, the entire protruding portion 34 has a tapered shape. Light gradually transfers to the semiconductor element 30. Since the coupling efficiency between the semiconductor element 30 and the silicon layer 16 is improved, light loss can be suppressed.

[0062] The insulating film 11 covers the silicon layer 16 and the semiconductor element 30 of the substrate 10. Since the insulating film 11 functions as a cladding layer, light loss can be suppressed.

[0063] The semiconductor optical element 100 in FIG. 1 is a wavelength tunable laser element. The semiconductor optical element 100 may be another optical device different from the wavelength tunable laser element.

[0064] As described above in detail for the embodiments of the present disclosure, the present disclosure is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present disclosure described in the claims.

Description of Reference Numerals

[0065] 10, 12 Substrate 11 Insulating film 14 Box layer 16 Silicon layer 20, 22 Waveguide 21, 23 Tapered portion 24, 26 Recess 25, 29 Portion 27 Terrace 28, 31, 32, 36 Slab portion 30 Semiconductor element 34 Protruding portion 38 Mesa 40, 44 Cladding layer 42 Active layer 46 Contact layer 48, 49 Electrode 100, 110 Semiconductor optical element 101, 102 MMI 103 Ring resonator 104 Loop mirror

Claims

1. A substrate having a silicon layer, a semiconductor element formed of a group III-V compound semiconductor and bonded to the silicon layer, and the silicon layer has a first waveguide, a second waveguide, a first recess, a second recess, a terrace, and a first slab portion, the first recess and the second recess are portions recessed from the surfaces of the first waveguide, the second waveguide, the terrace, and the first slab portion, the first recess and the terrace are arranged in this order on both sides of the first waveguide, the second recess and the terrace are arranged in this order on both sides of the second waveguide, the first waveguide is connected to one end of the first slab portion, and the second waveguide is connected to the other end of the first slab portion, the first slab portion is connected to the terrace and is located between the first recess and the second recess, the semiconductor element has a protruding portion, a second slab portion, and a third slab portion, the second slab portion is bonded to the first slab portion, the protruding portion protrudes from the second slab portion onto the first waveguide, the third slab portion is a semiconductor optical element located on the second waveguide, the second recess, and the terraces on both sides of the second waveguide.

2. The semiconductor optical element according to claim 1, wherein the width of the first slab portion is larger than the widths of the first waveguide and the second waveguide.

3. The semiconductor optical element according to claim 1 or claim 2, wherein the width of the second slab portion is larger than the width of the protruding portion.

4. The semiconductor optical element according to claim 1 or claim 2, wherein the planar shapes of the first slab portion and the second slab portion are rectangular.

5. The first waveguide has a first taper portion, the width of the first taper portion is larger as it is closer to the first slab portion and smaller as it is farther from the first slab portion, the second waveguide has a second taper portion, The semiconductor optical element according to claim 1 or claim 2, wherein the width of the second taper portion is larger as it is closer to the first slab portion and smaller as it is farther from the first slab portion.

6. The protruding portion has a third taper portion, The semiconductor optical element according to claim 1 or claim 2, wherein the width of the protruding portion is larger as it is closer to the second slab portion and smaller as it is farther from the second slab portion.

7. The semiconductor optical element according to claim 1 or claim 2, wherein the second slab portion, the third slab portion, and the protruding portion of the semiconductor element are formed of indium phosphide.

8. The semiconductor optical element according to claim 1 or claim 2, comprising an insulating film covering the silicon layer and the semiconductor element.

9. A step of bonding a semiconductor element formed of a group III-V compound semiconductor to a silicon layer of a substrate; A step of performing wet etching on the bonded semiconductor element, and having, The silicon layer has a first waveguide, a second waveguide, a first recess, a second recess, a terrace, and a first slab portion. The first recess and the second recess are portions recessed from the surfaces of the first waveguide, the second waveguide, the terrace, and the first slab portion. On both sides of the first waveguide, the first recess and the terrace are arranged in this order. On both sides of the second waveguide, the second recess and the terrace are arranged in this order. One end of the first slab portion is connected to the first waveguide, and the other end of the first slab portion is connected to the second waveguide. The first slab portion is connected to the terrace and is located between the first recess and the second recess. The step of bonding the semiconductor element is a step of bonding the semiconductor element to the first waveguide, the first slab portion, the second waveguide, and the terraces on both sides of the first waveguide and the second waveguide. In the step of performing the wet etching, a protruding portion, a second slab portion, and a third slab portion are formed on the semiconductor element. The second slab portion is bonded to the first slab portion. The protruding portion protrudes from the second slab portion onto the first waveguide. A method for manufacturing a semiconductor optical element, wherein the third slab portion is located on the second waveguide, the second recess, and the terraces on both sides of the second waveguide.

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