Display

Abstract

To form multiple types of circuits on the same substrate and to provide emitting devices with multiple types of thin film transistors that are respectively matched to the characteristics of multiple types of circuits.SOLUTION: A color filter layer is provided between the thin film transistor and the light emitting element at a position overlapping the light emitting element that is electrically connected to the thin film transistor for the pixel by using a reverse coplanar type with oxide semiconductor layers overlapping on the source and drain electrode layers as the thin film transistor for pixels and by using a channel stop type as the thin film transistor for drive circuits.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a light-emitting device having a layer containing an organic compound as a light-emitting layer, and a method for manufacturing the same. The present invention relates to an electronic device that incorporates a light-emitting display device having a light-emitting element as a component. [Background technology]

[0002] The organic compound used as the light emitter has characteristics such as being thin and lightweight, having high-speed response, and being driven by low DC voltage. The light-emitting element used is being considered for application in next-generation flat panel displays and lighting. In particular, display devices in which light-emitting elements are arranged in a matrix are being considered as being superior to conventional liquid crystal display devices. Compared to conventional LCD devices, it is believed that its advantages lie in its wider viewing angle and superior visibility.

[0003] The light-emitting mechanism of a light-emitting element is to sandwich an EL layer between a pair of electrodes and apply a voltage to the layer. Electrons injected from the electrode and holes injected from the anode recombine and split at the luminescence centers of the EL layer. When the molecular excitons relax to the ground state, they release energy and emit light. There are two types of excited states: singlet and triplet. It is believed that this is possible even after passing through a wake-up state.

[0004] The EL layer constituting the light-emitting element has at least a light-emitting layer. In addition, a laminated structure having a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. may be used. It is also possible.

[0005] Metal oxides are also attracting attention as materials that exhibit semiconducting properties. Examples of oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Yes, a thin film transistor having a metal oxide showing such semiconductor characteristics as a channel formation region is already known (Patent Document 1 and Patent Document 2).

[0006] In addition, a TFT applying an oxide semiconductor has a high field effect mobility. Therefore, a drive circuit such as a display device can be configured using the TFT.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a drive circuit on the same substrate, the thin film transistor used for the pixel portion is required to have excellent switching characteristics, for example, a large on-off ratio, and the thin film transistor used for the drive circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image, so it is preferable that the thin film transistor used for the drive circuit has a high operating speed. The higher the definition of the display device, the shorter the writing time of the display image, so it is preferable that the thin film transistor used for the drive circuit has a high operating speed.

[0009] One object of the present invention is to provide a light emitting device that forms a plurality of types of circuits on the same substrate and includes a plurality of types of thin film transistors adapted to the characteristics of the plurality of types of circuits.

[0010] One aspect of the present invention is a switching element of a thin film transistor having good electrical characteristics and high reliability. ​​​​​​​It is an object of the present invention to manufacture a highly reliable light-emitting device by using the organic EL element as a semiconductor material. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driving circuit portion has a gate electrode layer, a source electrode layer, and a drain electrode layer formed of a metal conductive film. A thin film transistor for a driving circuit, the thin film transistor being configured so that a channel layer is configured from an oxide semiconductor. and a driving circuit wiring formed of a metal conductive film, and the display unit has a source electrode The drain electrode layer and the drain electrode layer are made of an oxide conductor and the semiconductor layer is made of an oxide semiconductor. and a pixel thin film transistor configured as above.

[0012] Bottom-gate thin-film transistors are used as thin-film transistors for pixels and thin-film transistors for driver circuits. The pixel thin film transistor is formed on the source electrode layer and the drain electrode layer. A thin film transistor having an inverted coplanar type (also called a bottom-contact type) and an oxide semiconductor layer overlapping the It is a transistor.

[0013] In addition, light-emitting elements of multiple types of luminescent colors and pixel elements electrically connected to the light-emitting elements are formed on the same substrate. Thin film transistors can be formed to manufacture light emitting devices such as displays.

[0014] In addition, a plurality of light-emitting elements that emit white light are provided, and the light-emitting areas of the respective light-emitting elements are overlapped. An optical film, specifically a color filter, is provided on the display to create a full-color light-emitting display device. A color filter is placed between the white light-emitting element and the pixel thin-film transistor. When light emitted from a light-emitting element is passed through a color filter to display a picture, a thin film for a pixel is provided. When a conductive film having translucency is used as the material for the gate electrode layer, source electrode layer, and drain electrode layer of the transistor, the aperture ratio can be improved. Here, the color filter does not refer to the entire film including the black matrix and overcoat, but rather to a single-color color filter, including the three-color color filter layer (such as a red color filter, blue color filter, green color filter, etc.).

[0015] In addition, the thin-film transistor for the driving circuit has a different structure from the thin-film transistor for the pixel, and is a bottom-gate type thin-film transistor provided with an oxide insulating layer in contact with the oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer.

[0016] The thin-film transistor for the driving circuit has a drain electrode layer made of a metal conductive film such as Ti, and is an oxygen-deficient type high-resistance drain region (also called the HRD (High Resistance Drain) region) that is in contact with a part of the upper surface of the oxide semiconductor layer and overlaps the drain electrode layer. Specifically, the carrier concentration in the high-resistance drain region is in the range of 1×10 / cm 3 or more, and is higher than at least the carrier concentration (less than 1×10 / cm 18 / cm 3 in the channel formation region). Here, the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0017] In addition, the source electrode layer is in contact with a part of the upper surface of the oxide semiconductor layer, and an oxygen-deficient type high-resistance source region (also called the HRS (High Resistance Source ) region) that overlaps the source electrode layer is formed.​​​​​​

[0018] One embodiment of the present invention disclosed in this specification is a pixel having a first thin film transistor over the same substrate. A driving circuit having a second thin film transistor having a structure different from that of the first thin film transistor. The first thin film transistor has a gate electrode layer on the substrate and a gate electrode layer on the gate electrode layer. A source electrode layer and a drain electrode layer are formed on the gate insulating layer, and a source insulating layer and a drain electrode layer are formed on the gate insulating layer. An oxide semiconductor layer overlapping the source electrode layer and the drain electrode layer, and an oxide semiconductor layer in contact with the oxide semiconductor layer a connection electrode layer electrically connected to the drain electrode layer on the oxide insulating layer; A color filter layer is formed on the insulating layer, and a third electrode layer is formed on the color filter layer and electrically connected to the connection electrode layer. A first electrode is provided on the first electrode, a light-emitting layer is provided on the light-emitting layer, and a second electrode is provided on the light-emitting layer. Transistor gate electrode layer, gate insulating layer, oxide semiconductor layer, source electrode layer, drain electrode The layer, the oxide insulating layer, and the first electrode constitute a light-transmitting light-emitting device.

[0019] The above configuration solves at least one of the above problems.

[0020] In the above configuration, the connection electrode layer is made of Al, Cr, Cu, Ta, Ti, Mo, or W. Using a laminated film that combines a film mainly composed of the selected element or an alloy film of the selected element The source electrode layer and the drain electrode layer of the first thin film transistor are made of indium oxide. Indium oxide, tin oxide, indium oxide zinc oxide, or zinc oxide do.

[0021] Also, the source electrode layer and the drain electrode layer of the second thin film transistor, which is a thin film transistor for a driving circuit, The rain electrode layer is made of the same material as the connection electrode layer, and is made of Ti, Mo, W, Al, Cr, Cu, T an element selected from a, an alloy containing the above-described element as a component, or an alloy obtained by combining the above-described elements, etc. is used. The source electrode layer and the drain electrode layer are not limited to a single layer containing the above-described element, and a laminate of two or more layers can be used. Further, the source electrode layer and the drain electrode layer of the second thin film transistor are configured not to overlap with the channel formation region of the oxide semiconductor layer. Also, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface is wider than the width of the oxide insulating layer functioning as a channel protection layer. In order to increase the operating speed of the thin film transistor for the driving circuit, if the width (width in the channel length direction) of the oxide insulating layer functioning as a channel protection layer is designed to be small, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface also becomes small, and there is a risk that the source electrode layer and the drain electrode layer may be short-circuited. Therefore, it is useful to widen the distance. Also, by using a thin film transistor with a high operating speed, the integration degree of the circuit is improved.

[0022] Further, the source electrode layer and the drain electrode layer of the second thin film transistor are configured not to overlap with the channel formation region of the oxide semiconductor layer. Also, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface is wider than the width of the oxide insulating layer functioning as a channel protection layer. In order to increase the operating speed of the thin film transistor for the driving circuit, if the width (width in the channel length direction) of the oxide insulating layer functioning as a channel protection layer is designed to be small, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface also becomes small, and there is a risk that the source electrode layer and the drain electrode layer may be short-circuited. Therefore, it is useful to widen the distance. Also, by using a thin film transistor with a high operating speed, the integration degree of the circuit is improved.

[0023] Also, in the above configuration, the second thin film transistor has an oxide semiconductor layer, has an oxide insulating layer on the oxide semiconductor layer, and the channel formation region of the oxide semiconductor layer and the peripheral portion of the oxide semiconductor layer are in contact with the oxide insulating layer. The oxide insulating layer in contact with the channel formation region of the oxide semiconductor layer functions as a channel protection layer.

[0024] Also, in the above configuration, the oxide insulating layer functioning as a channel protection layer of the thin film transistor for the driving circuit uses an inorganic insulating film using a sputtering method, typically a silicon oxide film, a silicon oxynitride film A silicon film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0025] Further, the second thin film transistor may be configured to have oxide conductive layers both between the oxide semiconductor layer and the source electrode layer and between the oxide semiconductor layer and the drain electrode layer. By adopting this configuration, the contact resistance can be reduced, and a thin film transistor capable of high-speed operation can be realized. Note that as the oxide conductive layer, those containing zinc oxide as a component are preferably used, and those not containing indium oxide are preferably used. Examples of such oxide conductive layers include zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride, and gallium zinc oxide.

[0026] Further, the oxide semiconductor layer of the thin film transistor for a driving circuit has, on the upper surface of the oxide semiconductor layer, a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, that is, a third region . The width of this third region in the channel length direction is determined by the patterning position of the oxide semiconductor layer and the patterning positions of the drain electrode layer and the source electrode layer. If the width of this third region in the channel length direction is widened, the off-current of the thin film transistor for a driving circuit can be reduced. Also, if the width of this third region in the channel length direction is narrowed, the operating speed of the thin film transistor for a driving circuit can be increased.

[0027] Further, the insulating layer in contact with the third region also uses an inorganic insulating film formed by a sputtering method. Typically, a silicon nitride film, a silicon oxynitride film, or an aluminum nitride film is used.

[0028] Note that as the oxide semiconductor layer, InMO3(ZnO) m ​A thin film represented by (m>0) is formed, and a thin film transistor using the thin film as an oxide semiconductor layer is manufactured. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal element included as M, as impurities, Fe, Ni, and other transition metal elements, and there are some that contain oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m>0), the oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an In-Ga- m Zn-O-based non-single crystal film. In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga -Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-

[0029] Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Also, silicon oxide may be included in the oxide semiconductor layer made of the above metal oxide.

[0030] Also, in one aspect of the present invention, a first gate electrode layer and a second gate electrode layer are formed on a substrate having an insulating surface, a gate insulating layer is formed on the first gate electrode layer and the second gate electrode layer, a first source electrode layer and a first drain electrode layer overlapping the first gate electrode layer are formed on the gate insulating layer, and on the gate insulating layer, the first gate electrode layer and a part of the first source electrode layer are formed, and on the gate insulating layer, the first gate electrode layer, a part of the first source electrode layer a first oxide semiconductor layer overlapping a part of the first drain electrode layer; and a second gate electrode. a second oxide semiconductor layer overlapping the first oxide semiconductor layer and being in contact with a part of the second oxide semiconductor layer; forming an oxide insulating layer in contact with an upper surface and a side surface of the second oxide semiconductor layer; A second source electrode layer and a second drain electrode layer are formed on the semiconductor layer, and a first drain electrode layer is formed on the oxide insulating layer. A connection electrode layer is formed to be electrically connected to the first oxide semiconductor layer, and an oxide semiconductor layer is formed to overlap the first oxide semiconductor layer. A color filter layer is formed on the insulating layer, and the color filter layer is electrically connected to the connection electrode layer. The method for producing a light emitting device includes forming a first electrode, a light emitting layer, and a second electrode in succession.

[0031] In the above-described manufacturing method, The oxide insulating layer is formed by dehydrating or dehydrogenating the oxide semiconductor layer and then exposing it to the air. In this case, impurities such as water and hydrogen are prevented from re-entering the oxide semiconductor layer.

[0032] Dehydration or dehydrogenation is performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). The heat treatment is performed at a temperature of 400° C. or higher and lower than the distortion point of the substrate in an atmosphere, and the moisture content of the oxide semiconductor layer is Reduces impurities such as minerals.

[0033] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient and has low resistance. , that is, N-type (N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer. By carrying out the above process, the oxide semiconductor layer is made into an oxygen-excessive state, and thus the resistance is increased, that is, the oxide semiconductor layer is made into an I-type. It can be said that it has a thin film transistor with good electrical characteristics and high reliability. Thus, it becomes possible to fabricate and provide a semiconductor device having the same.

[0034] The oxide semiconductor layer that has undergone dehydration or dehydrogenation is subjected to TDS measurement up to 450 °C for the oxide semiconductor layer after dehydration or dehydrogenation, and the heat treatment conditions are such that two peaks of water are not detected, and at least one peak that appears around 300 °C is not detected. Therefore, even when TDS measurement is performed up to 450 °C on a thin film transistor using the oxide semiconductor layer that has undergone dehydration or dehydrogenation, a peak of water that appears around at least 300 °C is not detected. And, from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, slow cooling is performed to a sufficient temperature at which impurities such as water and hydrogen do not enter again, specifically, until the temperature drops by 100 °C or more from the heating temperature T. It is important not to expose the oxide semiconductor layer that has undergone dehydration or dehydrogenation to the atmosphere in the same furnace so that water or hydrogen is not mixed in again. After performing dehydration or dehydrogenation to lower the resistance of the oxide semiconductor layer, that is, to make it N-type (N, N, etc.), and then increasing the resistance to make it an I-type oxide semiconductor layer, when a thin film transistor is fabricated using this oxide semiconductor layer, the threshold voltage value of the thin film transistor can be made positive, and a so-called normally-off switching element can be realized. It is desirable for a display device that a channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin film transistor. When the threshold voltage value of the thin film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, which is so-called normally-on. In an active matrix type display device

[0035] - + - + - Therefore, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin-film transistors, the threshold voltage (Vth) is important. Even if the field-effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin-film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, when the driving voltage is low, it cannot perform the switching function as an TFT and may become a load. In the case of an n-channel type thin-film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin-film transistor used in a circuit. In addition, the gas atmosphere for lowering the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere heated up to the heating temperature T. For example, without exposing to the atmosphere in the same furnace after dehydration or dehydrogenation, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) and cooled. After reducing the contained moisture in the film by the heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin-film transistor are improved by using an oxide semiconductor film slowly cooled (or cooled) under an atmosphere free of moisture (dew point is -40°C or lower, preferably -60°C or lower), and a thin-film transistor having both mass productivity and high performance is realized.

[0036]

[0037] ​​​​​​​​​​​​​​​

[0038] In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or heat treatment under reduced pressure is referred to as heat treatment for dehydration or dehydrogenation. In this specification, only the desorption as H2 by this heat treatment is not the only thing called dehydrogenation, but for the sake of convenience, it is also called dehydration or dehydrogenation including the desorption of H, OH, etc. is done.

[0039] In a light-emitting display device using a light-emitting element, the pixel portion has a plurality of thin-film transistors, and in the pixel portion, there is a location where the gate electrode of a certain thin-film transistor is connected to the source wiring or, alternatively, the drain wiring of another transistor. Also, in the drive circuit of a light-emitting display device using a light-emitting element, there is a location where the gate electrode of a thin-film transistor is connected to the source wiring or, alternatively, the drain wiring of that thin-film transistor.

[0040] Also, since thin-film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin-film transistors in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. is preferred.

[0041] Note that the ordinal numbers attached as first, second, etc. are used for the sake of convenience and do not indicate the process order or the stacking order. Also, they do not indicate names specific to the matters for specifying the invention in this specification.

[0042] A semiconductor device according to one aspect of the present invention has a drive circuit having a drive circuit TFT on the same substrate. ​​A circuit section and a display section having TFTs for pixels are fabricated. Therefore, the manufacturing cost of the light-emitting device can be reduced.

[0043] In addition, a light-emitting device such as an illumination device can be manufactured by forming a white light-emitting element on a substrate . Note that the illumination device is an illumination device using a light-emitting element having a layer containing a light-emitting substance from which electroluminescence (hereinafter abbreviated as EL) can be obtained .

Advantages of the Invention

[0044] By using an oxide semiconductor layer that has been subjected to a heat treatment for dehydration or dehydrogenation, a thin-film transistor with good electrical characteristics and high reliability can be used as a switching element, and a light-emitting device with high reliability can be fabricated. In addition, a light-emitting device can be fabricated by forming different structures for the TFT for pixels and the TFT for the driving circuit on the same substrate according to their respective circuits . .

Brief Description of the Drawings

[0045]

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Embodiments for Carrying Out the Invention

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. In the drawings in this specification, the same parts or parts having the same function may be denoted by the same reference numerals, and the description thereof may be omitted.

[0047] (Embodiment 1) In this embodiment, one form of a light-emitting device and a method for manufacturing the light-emitting device will be described with reference to FIG. 1. FIG. 1(E) shows an example of the cross-sectional structure of two thin-film transistors having different structures fabricated on the same substrate.

[0048] The thin-film transistor 450 shown in FIG. 1(E) is one of the bottom-gate structures, and the thin-film transistor 460 is one of the bottom-gate structures called the bottom-contact type (also called the inverted coplanar type).

[0049] ​​​​​ The thin film transistor 460 disposed on the pixel is a bottom contact type thin film transistor. On a substrate 400 having an insulating surface, a gate electrode layer 451a, a gate insulating layer 402, a oxide semiconductor layer 454 including a channel formation region, a source electrode layer 455a, and a drain electrode layer 455b are included. Further, an oxide insulating layer 426b that covers the thin film transistor 460 and contacts the upper surface and side surfaces of the oxide semiconductor layer 454 is provided.

[0050] Also, although the thin film transistor 460 disposed on the pixel has been described using a single gate structure thin film transistor, if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed.

[0051] Note that the oxide semiconductor layer 454 is formed above the source electrode layer 455a and the drain electrode layer 455b and partially overlaps them. Also, the oxide semiconductor layer 454 overlaps with the gate electrode layer 451 a with the gate insulating layer 402 interposed therebetween. The channel formation region of the thin film transistor 46 0 is a region of the oxide semiconductor layer 454 that is sandwiched between the side surface of the source electrode layer 455a and the side surface of the drain electrode layer 455b facing the side surface, that is, a region that contacts the gate insulating layer 402 and overlaps with the gate electrode layer 451a.

[0052] Also, in order to realize a light-emitting device having a high aperture ratio with the thin film transistor 460 being a light-transmissive thin film transistor, the source electrode layer 455a and the drain electrode layer 455b use a conductive film having light-transmittance.

[0053] Also, the gate electrode layer 451a of the thin film transistor 460 also uses a conductive film having light-transmittance. In this specification, a film having translucency to visible light refers to a film having a film thickness with a visible light transmittance of 75 to 10 0%, and when the film has conductivity, it is also called a transparent conductive film. In addition, a semitransparent conductive film to visible light may be used. Semitransparent to visible light means that the transmittance of visible light is 50 to 75%.

[0054] In addition, the thin film transistor 450 disposed in the drive circuit is on a substrate 400 having an insulating surface and includes a gate electrode layer 421a, a gate insulating layer 402, at least a channel formation region 423, a high resistance source region 424a, and an oxide semiconductor layer having a high resistance drain region 424b, a source electrode layer 425a, and a drain electrode layer 425b. In addition, an oxide insulating layer 426a in contact with the channel formation region 42 3 is provided. In addition, an insulating layer 428 is provided on the source electrode layer 425a and the drain electrode layer 425b.

[0055] In addition, a first region 424c and a second region 42 4d of the oxide semiconductor layer overlapping with the oxide insulating layer 426b are in the same oxygen-excessive state as the channel formation region 423, and also function to reduce leakage current and parasitic capacitance. In addition, a third region 424e of the oxide semiconductor layer in contact with the insulating layer 428 is provided between the channel formation region 423 and the high resistance source region 424a. In addition, a fourth region 424f of the oxide semiconductor layer in contact with the insulating layer 428 is provided between the channel formation region 423 and the high resistance drain region 424b. The third region 424e and the fourth region 424f of the oxide semiconductor layer in contact with the insulating layer 428 can reduce the off-current. region 423 and the high resistance drain region 424b. The third region 424e and the fourth region 424f of the oxide semiconductor layer in contact with the insulating layer 428 can reduce the off-current. semiconductor layer in contact with the insulating layer 428 can reduce the off-current.

[0056] ​In addition, for a channel protection type thin film transistor, in order to shorten the channel length L of the channel formation region, the width of the oxide insulating layer is narrowed, and there is a risk of short circuit on the oxide insulating layer when the source electrode layer and the drain electrode layer are provided on the narrow oxide insulating layer. Therefore, the source electrode layer 425a and the drain electrode layer 425b are provided leaving the ends from the narrow oxide insulating layer 426a. That is, it is the configuration. In addition, in FIG. 1(E), the region of the oxide semiconductor layer where the oxide insulating layer 426a functioning as a channel protection layer and the gate electrode layer overlap via the gate insulating layer is called the channel formation region. Therefore, the channel length L of the thin film transistor 450 is equal to the width in the channel length direction of the oxide insulating layer 426a. Note that the channel length L of the thin film transistor 450 is the length at the interface with the oxide insulating layer 426a, that is, in the cross-sectional view shown in FIG. 1(E), the oxide insulating layer 426a is shown as a trapezoid, and it is the length of the bottom side of the trapezoid.

[0057]

[0058] Hereinafter, the process of manufacturing the thin film transistor 450 and the thin film transistor 460 on the same substrate will be described with reference to FIGS. 1(A), 1(B), 1(C), 1(D), and 1(E).

[0059] First, after forming a conductive film on the substrate 400 having an insulating surface, the gate electrode layers 421a and 421b are formed by the first photolithography process.

[0060] Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0061] ​​​​​​​​​​​​As the conductive film for forming the gate electrode layers 421a and 421b, Al, Cr, Ta, Ti, an element selected from Mo and W, an alloy containing the above-described elements as components, or an alloy film formed by combining the above-described elements, etc. can be mentioned.

[0062] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. A glass substrate can be used for the substrate 400 having an insulating surface.

[0063] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. For the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. By including more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0064] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, a crystallized glass or the like can also be used.

[0065] Also, an insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode layers 421a and 421b. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400, and is formed by a laminated structure composed of one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0066] Next, after forming a conductive film having translucency covering the gate electrode layers 421a and 421b, The gate electrode layers 451a and 451b are formed by a second photolithography process. In this embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 421b, and the material of the gate electrode layer 451a that overlaps with the oxide semiconductor layer and the gate insulating layer 40 2 via is formed of a conductive film having translucency.

[0067] Next, a gate insulating layer 402 is formed on the gate electrode layers 421a, 421b, 451a, and 451b.

[0068] The gate insulating layer 402 is formed of a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as a film-forming gas. The film thickness of the gate insulating layer 402 is 100 nm or more and 5 00 nm or less. In the case of a laminate, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer are laminated. In this embodiment, a gate insulating layer 402 having a film thickness of 100 nm of silicon oxynitride (SiON (composition ratio N < O)) is formed by a plasma CVD method.

[0069] In this embodiment, a gate insulating layer 402 having a film thickness of 100 nm of silicon oxynitride (SiON (composition ratio N < O)) is formed.

[0070] Next, after forming a conductive film having translucency on the gate insulating layer 402, a source electrode layer 455a and a drain electrode layer 455b are formed by a third photolithography process. ([ Refer to Fig. 1(A). The conductive film having translucency is a conductive material having translucency to visible light. , for example, In-Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn- Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system of metal oxides can be applied, and the film thickness can be appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the conductive film having translucency, and it is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step.

[0071] The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. Dehydration or dehydrogenation is effective for making the oxide semiconductor layer of type I (intrinsic).

[0072] Next, the gate insulating layer 402 is selectively etched by the fourth photolithography process to form a contact hole reaching the gate electrode layer 421b.

[0073] Next, an oxide semiconductor film having a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 20 nm or less, is formed on the gate insulating layer 402. After the formation of the oxide semiconductor film, even if a heat treatment for dehydration or dehydrogenation is performed, in order to make the oxide semiconductor film in an amorphous state, it is preferable to make the film thickness 50 nm or less. By making the film thickness of the oxide semiconductor film thin, the oxide When heat treatment is performed after the formation of the semiconductor layer, crystallization can be suppressed.

[0074] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, In-Sn-Zn-O system, In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, S n-O system, Zn-O system oxide semiconductor films are used. Also, the oxide semiconductor film is formed by sputtering in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. When using the sputtering method, it is preferable to perform film formation using a target containing 2 wt% or more and 10 wt% or less of SiO2, include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film, and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mole ratio]) is used, the distance between the substrate and the target is 1 00 mm, the pressure is 0.6 Pa, the DC (direct current) power supply is 0.5 kW, and film formation is performed in an oxygen (oxygen flow rate ratio 100% ) atmosphere. When using a pulsed DC power supply, it is preferable because dust can be reduced and the film thickness distribution becomes uniform. In this embodiment, as the oxide semiconductor film, an In-

[0075] Ga-Zn-O based oxide semiconductor target is used to form an In -Ga-Zn-O based non-single crystal film with a film thickness of 15 nm by sputtering. 00 mm, the pressure is 0.6 Pa, the DC (direct current) power supply is 0.5 kW, and film formation is performed in an oxygen (oxygen flow rate ratio 100% ) atmosphere. When using a pulsed DC power supply, it is preferable because dust can be reduced and the film thickness distribution becomes uniform. In this embodiment, as the oxide semiconductor film, an In- Ga-Zn-O based oxide semiconductor target is used to form an In -Ga-Zn-O based non-single crystal film with a film thickness of 15 nm by sputtering. -Ga-Zn-O based non-single crystal film with a film thickness of 15 nm by sputtering.

[0076] For the sputtering method, there are the RF sputtering method that uses a high-frequency power supply as the sputtering power supply and the DC sputtering method. There is also a pulsed DC sputtering method that applies bias pulsingly. RF sputtering The method is mainly used when forming an insulating film, and the DC sputtering method is mainly used for forming a metal conductive film in the case.

[0077] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. Multi-source sputtering The apparatus can stack and form different material films in the same chamber, or discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0078] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber or an ECR sputtering apparatus that uses plasma generated using microwaves without using glow discharge.

[0079] Also, as a film forming method using the sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to the substrate during film formation is also available.

[0080] Before forming an oxide semiconductor film by the sputtering method, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove dust adhering to the surface of the gate insulating layer 402. Reverse sputtering is a method in which a voltage is not applied to the target side, but a voltage is applied to the substrate side using an RF power source in an argon atmosphere to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere as well. is also acceptable.

[0081] In this embodiment, a contact hole reaching the gate electrode layer 421b is formed by selectively etching the gate insulating layer in a fourth photolithography process, but it is not particularly limited. After etching the oxide semiconductor film, a resist mask may be formed on the oxide semiconductor layer, and a contact hole reaching the gate electrode layer 421b may be formed. In that case, reverse sputtering is preferably performed to remove resist residues adhering to the surfaces of the oxide semiconductor layer and the gate insulating layer 402. Also, after forming an oxide semiconductor film on the gate insulating layer, a resist mask is formed on the oxide semiconductor film, a contact hole reaching the gate electrode layer 421b is formed, the resist mask is removed, and then a resist mask is formed again on the oxide semiconductor film, and the oxide semiconductor

[0082] film may be selectively etched to be processed into an island-shaped oxide semiconductor layer. Further, before forming the oxide semiconductor film, heat treatment (400°C or higher and lower than the distortion point of the substrate) may be performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and the gate insulating layer may be used. In this embodiment, since a contact hole reaching the gate electrode layer 421b is formed by selectively etching the gate insulating layer in a fourth photolithography process, after forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film.

[0083] Also, before forming the oxide semiconductor film, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and the gate insulating layer may be used. In this embodiment, since a contact hole reaching the gate electrode layer 421b is formed by selectively etching the gate insulating layer in a fourth photolithography process, after forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film.

[0084] In this embodiment, a contact hole reaching the gate electrode layer 421b is formed by selectively etching the gate insulating layer in a fourth photolithography process. Therefore, after forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film. For forming a contact hole reaching the gate electrode layer 421b by selectively etching the gate insulating layer in a fourth photolithography process, after forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film. After forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film. After forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film. After forming the contact, heat treatment (400°C or higher and lower than the distortion point of the substrate) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the layer, and then it is preferable to form an oxide semiconductor film.

[0085] Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers by a fifth photolithography process. Also, a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. Forming the resist mask by the inkjet method eliminates the need to use a photomask, thus reducing the manufacturing cost.

[0086] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and lower than the strain point of the substrate, preferably 425°C or higher. Note that if the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. However, if the temperature is lower than 425°C, the heat treatment time shall be longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere. After that, without exposing the oxide semiconductor layer to the atmosphere, re-mixing of impurities such as water and hydrogen into the oxide semiconductor layer is prevented, and an oxide semiconductor layer is obtained. In this embodiment, using the same furnace, the oxide semiconductor layer is slowly cooled in a nitrogen atmosphere from the heating temperature T for dehydration or dehydrogenation to a sufficient temperature at which water does not enter again. Specifically, it is cooled slowly until the temperature drops by 100°C or more from the heating temperature T. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation may be performed in an atmosphere of other inert gases (helium, neon, argon, etc.).

[0087] In the first heat treatment, it is preferable that nitrogen or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher. , preferably 7N (99.99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0088] Also, depending on the conditions of the first heat treatment, the material of the oxide semiconductor film, or the material of the gate electrode layers 451a, 4 51b, crystallization may occur, resulting in a microcrystalline film or a polycrystalline film. After the first heat treatment, oxygen-deficient type oxide semiconductor layers 403, 453 with reduced resistance are formed ( see Fig. 1(B)). After the first heat treatment, the carrier concentration is higher than that of the oxide semiconductor film immediately after film formation, preferably 1×10 / cm 18 / cm 3 or higher, and oxide semiconductor layers 403, 453 are formed. For example, when indium tin oxide alloy films are used as the gate electrode layers 451a, 451b, crystallization occurs with a first heat treatment at 450 °C for 1 hour. When indium tin oxide alloy films containing silicon oxide are used as the gate electrode layers 451a, 451b no crystallization occurs.

[0089] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device, and the fifth photolithography process is performed.

[0090] Next, after forming an oxide insulating film by sputtering on the gate insulating layers 402 and the oxide semiconductor layers 403, 453, a resist mask is formed by the sixth photolithography process, selectively etched to form oxide insulating layers 426a, 426b, and then the resist mask is removed. At this stage, in the region where the oxide semiconductor layer is in contact with the oxide insulating layer, is formed, and among this region, the region overlapping with the gate electrode layer, the gate insulating layer, and the oxide insulating layer 426a becomes the channel formation region. Also, a region overlapping with the oxide insulating layer 426b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Further, by the sixth photolithography process, formation of contact holes reaching the gate insulating layer 421b and formation of contact holes reaching the drain electrode layer 455b are also performed. The oxide insulating film has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film. In this embodiment, a silicon oxide film is formed as the oxide insulating film by using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. Film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by the sputtering method in an oxygen and rare gas atmosphere using a silicon target. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used. Typically, a silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride is used. In this embodiment, a silicon target that is 6N in purity and columnar polycrystalline B-doped (resistance value 0)

[0091] is used. -

[0092] .01 Ωcm) is used, and the distance between the substrate and the target (T-S distance) is 89 mm, and the pressure is 0.4 Pa, a direct current (DC) power supply of 6 kW, and a pulsed DC sputtering method is used to form a film in an oxygen (oxygen flow rate ratio 100%) atmosphere. The film thickness is 300 nm.

[0093] Next, a second heat treatment (preferably at 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 1(C). ). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 403 overlapping the oxide insulating layer 426b and a part of the oxide semiconductor layer 403 overlapping the oxide insulating layer 426a are heated in a state of being in contact with the oxide insulating layer. . Note that when the second heat treatment is performed, a part of the oxide semiconductor layer that does not overlap the oxide insulating layer is exposed and heated. When the oxide semiconductor layer 403 is exposed and heat treatment is performed in a nitrogen or inert gas atmosphere, the highly resistive (type-I) region exposed in the oxide semiconductor layer can be made low resistive. Also, the oxide insulating layer 426a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer and functions as a channel protection layer.

[0094] Also, the timing of performing the second heat treatment is not limited to immediately after the end of the sixth photolithography process, and is not particularly limited as long as it is a process after the sixth photolithography process.

[0095] Next, after forming a conductive film on the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer, a resist mask is formed by the seventh photolithography process. ​​​​​, selectively etch to form the source electrode layer 425a and the drain electrode layer 425b (see Fig. 1(D)). Also, as shown in Fig. 1(D), a connection electrode layer 429 that is electrically connected to the gate electrode layer 421b and a connection electrode layer 452 that is electrically connected to the drain electrode layer 455b are also formed. As the method for forming the conductive film, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method can be used. As the conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc. is used. The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment, a three-layer conductive film of a titanium film (film thickness 100 nm), an aluminum film (film thickness 200 nm), and a titanium film (film thickness 100 nm) is formed. Also, a titanium nitride film may be used instead of the Ti film. In the seventh photolithography process, there is a portion for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Moreover, in the seventh photolithography process, there is a part for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. In addition, in the seventh photolithography process, there is a portion for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Furthermore, in the seventh photolithography process, there is a part for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Also, in the seventh photolithography process, there is a portion for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0096] In addition, in the seventh photolithography process, there is a part for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Moreover, in the seventh photolithography process, there is a portion for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Also, in the seventh photolithography process, there is a part for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, if ammonia peroxide (hydrogen peroxide water: ammonia water: water = 5:2:2) or the like is used as an alkaline etchant, the conductive film can be selectively removed and the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left remaining.

[0097] Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Note that the resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0098] Next, an insulating layer 428 is formed on the oxide insulating layers 426a and 426b, the source electrode layer 425a, the drain electrode layer 42 5b, the connection electrode layer 429, and the connection electrode layer 452 (see Fig. 1(E ).). As the insulating layer 428, a silicon nitride film, a silicon oxynitride film, or an aluminum nitride film or the like is used. In this embodiment, the insulating layer 4 of the silicon nitride film is formed by the RF sputtering method 28 is formed.

[0099] Through the above steps, two types of thin film transistors, a channel protection type thin film tra nsistor 450, and a bottom contact type thin film transistor 460 can be fabricated on the same substrate .

[0100] The channel protection type thin film transistor 450 shortens the channel length L of the channel formation region to 0.1 μm or more and 2 μm or less, so as to narrow the width of the oxide insulating layer, and realizes a thin film tra nsistor with a high operating speed. Also, the bottom contact type thin film transistor 460 has a channel length longer than that of the channel protection type thin film transistor 450, and realizes a thin film tra nsistor with a reduced off-current. Also, the bottom contact type thin film transistor 460 is composed of a light-transmissive material except for the connection electrode layer 452. When manufacturing a light-emitting device, a plurality of thin film transistors are arranged in one pixel. For example, the driving TFT electrically connected to the light-emitting element has a channel length L of 55 μm and a channel width W of 2

[0101] 0 μm, and the selection TFT electrically connected to the gate electrode layer of the driving TFT has a channel length L of 25 μm and a channel width W of 60 μm. Note that the source electrode layer in the channel length direction 0 μm, and the selection TFT electrically connected to the gate electrode layer of the driving TFT has a channel length L of 25 μm and a channel width W of 60 μm. In addition, the source electrode layer in the channel length direction The overlapping width with the gate electrode layer is set to 5 μm, and the overlapping width between the drain electrode layer and the gate electrode layer in the channel length direction is set to 5 μm. The structure of the bottom contact type thin film transistor 460 is used as the driving TFT and the selection TFT. When manufacturing the light emitting device, a power supply line electrically connected to the source electrode layer of the driving TFT is provided. The power supply line intersects with the gate wiring and is formed of the same material and in the same process as the connection electrode layer 429 made of a conductive film. Alternatively, the power supply line intersects with the source wiring and is formed of the same material and in the same process as the gate electrode layer 421b. Also, when manufacturing the light emitting device, one electrode of the light emitting element is electrically connected to the drain electrode layer of the driving TFT, and a common potential line electrically connected to the other electrode of the light emitting element is provided. The common potential line is formed of the same material and in the same process as the connection electrode layer 429 made of a conductive film. Alternatively, the common potential line is formed of the same material and in the same process as the gate electrode layer 421b.

[0102] When manufacturing the light emitting device, a connection portion that connects the gate electrode layer of one thin film transistor and the drain electrode layer of the other thin film transistor is provided in one pixel. This connection portion is formed in the same process as the connection electrode layer 429 that is electrically connected to the gate electrode layer 421b. When forming a driving circuit on the same substrate, for example, a channel protection type thin film transistor 450 is used, and the channel length L is 2 μm and the channel width W is 50 μm. The overlapping width with the gate electrode layer is set to 5 μm, and the overlapping width between the drain electrode layer and the gate electrode layer in the channel length direction is set to 5 μm. The structure of the bottom contact type thin film transistor 460 is used as the driving TFT and the selection TFT. When manufacturing the light emitting device, a power supply line electrically connected to the source electrode layer of the driving TFT is provided. The power supply line intersects with the gate wiring and is formed of the same material and in the same process as the connection electrode layer 429 made of a conductive film. Alternatively, the power supply line intersects with the source wiring and is formed of the same material and in the same process as the gate electrode layer 421b.

[0103] When manufacturing the light emitting device, one electrode of the light emitting element is electrically connected to the drain electrode layer of the driving TFT, and a common potential line electrically connected to the other electrode of the light emitting element is provided. The common potential line is formed of the same material and in the same process as the connection electrode layer 429 made of a conductive film. Alternatively, the common potential line is formed of the same material and in the same process as the gate electrode layer 421b. When manufacturing the light emitting device, a connection portion that connects the gate electrode layer of one thin film transistor and the drain electrode layer of the other thin film transistor is provided in one pixel. This connection portion is formed in the same process as the connection electrode layer 429 that is electrically connected to the gate electrode layer 421b. When forming a driving circuit on the same substrate, for example, a channel protection type thin film transistor 450 is used, and the channel length L is 2 μm and the channel width W is 50 μm.

[0104] When manufacturing the light emitting device, one pixel has a plurality of thin film transistors, and a connection portion that connects the gate electrode layer of one thin film transistor and the drain electrode layer of the other thin film transistor is provided. This connection portion is formed in the same process as the connection electrode layer 429 that is electrically connected to the gate electrode layer 421b. When forming a driving circuit on the same substrate, for example, a channel protection type thin film transistor 450 is used, and the channel length L is 2 μm and the channel width W is 50 μm. The overlapping width with the gate electrode layer is set to 5 μm, and the overlapping width between the drain electrode layer and the gate electrode layer in the channel length direction is set to 5 μm. The structure of the bottom contact type thin film transistor 460 is used as the driving TFT and the selection TFT.

[0105] When manufacturing the light emitting device, a power supply line electrically connected to the source electrode layer of the driving TFT is provided. The power supply line intersects with the gate wiring and is formed of the same material and in the same process as the connection electrode layer 429 made of a conductive film. Alternatively, the power supply line intersects with the source wiring and is formed of the same material and in the same process as the gate electrode layer 421b. The widths of the third region and the fourth region in the channel length direction are each set to 2 μm. Also, in the channel length direction the overlapping width of the source electrode layer and the gate electrode layer is 2 μm, and in the channel length direction, the drain electrode layer and the overlapping width of the gate electrode layer is 2 μm.

[0106] On the same substrate, a plurality of types of circuits are formed. In this embodiment, a driving circuit and a pixel portion are formed, and according to the characteristics of the driving circuit and the pixel portion respectively, optimization can be achieved by using the channel protection type thin film transistor 450 or the bottom contact type thin film transistor 460. .

[0107] (Embodiment 2) In this embodiment, an example of manufacturing an active matrix type light emitting display device using a plurality of thin film transistors shown in Embodiment 1 and a light emitting element utilizing electroluminescence is shown.

[0108] The light emitting element utilizing electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0109] In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from a pair of electrodes into a layer containing a light emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light emitting organic compound forms an excited state , and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.

[0110] Inorganic EL elements are classified into distributed inorganic EL elements and thin-film inorganic EL elements according to their element configurations. Distributed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The light-emitting mechanism is donor-acceptor recombination light emission that utilizes donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes. The light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0111] FIG. 2 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device.

[0112] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an example in which two n-channel transistors using an oxide semiconductor layer in a channel formation region are used in one pixel is shown.

[0113] Pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has a gate connected to a scanning line 6406, a first electrode (one of a source electrode and a drain electrode) connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) connected to the gate of the driving transistor 6402. The driving transistor 6402 has a gate connected to a power supply line 6407 via the capacitive element 6403, a first electrode connected to the power supply line 640 7, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. ​​​​​The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0114] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential that satisfies the low power supply potential < high power supply potential with respect to the high power supply potential set on the power supply line 6407. As the low power supply potential, for example, GND, 0V, etc. may be set. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or higher than the forward threshold voltage of the light-emitting element 6404.

[0115] Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

[0116] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, fully on or off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage of (power supply line voltage + Vth of the driving transistor 6402) or higher is applied to the signal line 6405.

[0117] In addition, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as that in FIG. 2 can be used by varying the input of the signal.

[0118] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light-emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, thereby allowing current to flow through the light-emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light-emitting element 6404, thereby performing analog gradation driving.

[0119] Note that the pixel configuration shown in FIG. 2 is not limited thereto. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 2.

[0120] Next, the configuration of the light-emitting element will be described with reference to FIG. 3. Here, the case where the driving TFT is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The driving TFTs TFT7001, 7011, and 7021 used in the semiconductor devices of FIGS. 3(A), 3(B), and 3(C) can be manufactured in the same manner as the thin-film transistors shown in Embodiment Mode 1, and are highly reliable thin-film transistors including an oxide semiconductor layer.

[0121] For the light-emitting element, at least one of the anode and the cathode may be transparent in order to extract light. A thin film transistor and a light emitting element are formed on a substrate, and light emission is extracted from the surface opposite to the substrate, such as an upper surface emission structure, a lower surface emission structure for extracting light emission from the surface on the substrate side, or a double-sided emission structure for extracting light emission from the surface on the substrate side and the surface opposite to the substrate. There is a light emitting element, and the pixel configuration shown in FIG. 2 can be applied to the light emitting elements of any emission structure.

[0122] The light emitting element with the lower surface emission structure will be described with reference to FIG. 3(A).

[0123] A cross-sectional view of a pixel is shown when the driving TFT 7011 is of the n-type and the light emitted from the light emitting element 7012 is emitted toward the cathode 7013 side. In FIG. 3(A), on the light-transmissive conductive film 7017 electrically connected via the connection electrode layer 7030 to the driving TFT 7011, the cathode 7013 of the light emitting element 7012 is formed, and the EL layer 7014 and the anode 70 15 are sequentially laminated on the cathode 7013. Note that the connection electrode layer 7030 is electrically connected to the drain electrode layer of the driving TFT 7011 through a contact hole formed in the oxide insulating layer 7031.

[0124] As the light-transmissive conductive film 7017, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide doped with silicon oxide, or other light-transmissive conductive films can be used.

[0125] Also, various materials can be used for the cathode 7013, but materials with a small work function, for example, ​​​​​​​​​then, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and in addition to alloys containing these (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er, etc. are preferable. In Fig. 3(A), the film thickness of the cathode 7013 is set to a degree that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode 7013.

[0126] In addition, after laminating and forming a conductive film having light transmittance and an aluminum film, they may be selectively etched to form a conductive film 7017 having light transmittance and a cathode 7013. In this case, etching can be performed using the same mask and is preferable.

[0127] Also, the peripheral portion of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane and is formed. The partition wall 7019 is formed using a photosensitive resin material in particular, and an opening portion is formed on the cathode 7013 so that the side wall of the opening portion becomes an inclined surface formed with a continuous curvature and is preferably formed. When a photosensitive resin material is used as the partition wall 7019, the process of forming a resist mask can be omitted.

[0128] Also, the EL layer 7014 formed on the cathode 7013 and the partition wall 7019 may be composed of a single layer or may be configured such that a plurality of layers are laminated. When the EL layer 70 14 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7013. Note that it is not necessary to provide all of these layers necessarily.

[0129] Also, it is not limited to the above lamination order, and a hole injection layer, a hole transport layer, and a light-emitting layer may be laminated on the cathode 7013 , an electron transport layer, and an electron injection layer in this order. However, when comparing power consumption, it is preferable to laminate the layers in the order of an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer on the cathode 7013 because the power consumption is lower.

[0130] Also, as the anode 7015 formed on the EL layer 7014, various materials can be used, but materials with a large work function, such as ZrN, Ti, W, Ni, Pt, Cr, etc., and transparent conductive materials such as ITO, IZO, ZnO are preferable. Further, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, etc. is used on the anode 7015. In this embodiment, an ITO film is used as the anode 7015 and a Ti film is used as the shielding film 7016.

[0131] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the element structure shown in Fig. 3(A), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0132] Note that Fig. 3(A) shows an example in which a conductive film having translucency is used as the gate electrode layer, and the light emitted from the light-emitting element 7012 passes through the color filter layer 7033 and is emitted through the gate electrode layer and the source electrode layer of the thin film transistor 7011. By using a conductive film having translucency as the gate electrode layer and the source electrode layer of the thin film transistor 7011, the aperture ratio can be improved.

[0133] The color filter layer 7033 can be formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method Each is formed by an etching method using a graphic technique or the like.

[0134] Further, the color filter layer 7033 is covered with an overcoat layer 7034, and is further covered with a protective insulating layer 7035. In FIG. 3(A), the overcoat layer 7034 is shown with a thin film thickness, but the overcoat layer 7034 has a function of planarizing the unevenness caused by the color filter layer 7033.

[0135] Further, contact holes formed in the protective insulating layer 7035 and the insulating layer 7032 and reaching the connection electrode layer 7030 are arranged at positions overlapping the partition wall 7019. In FIG. 3(A), since the connection electrode layer 7030 is an example using a metal conductive film, a layout in which the contact hole reaching the connection electrode layer 7030, the partition wall 7019, and the connection electrode layer 7030 are overlapped is adopted to improve the aperture ratio.

[0136] Next, a light-emitting element having a double-sided injection structure will be described with reference to FIG. 3(B).

[0137] In FIG. 3(B), the cathode 7023 of the light-emitting element 7022 is formed on a conductive film 7027 having translucency, which is electrically connected to the driving TFT 7021 via the connection electrode layer 7040. On the cathode 7023, an EL layer 7024 and an anode 7025 are laminated in this order. Note that the connection electrode layer 7040 is electrically connected to the drain electrode layer of the driving TFT 7021 through a contact hole formed in the oxide insulating layer 7041.

[0138] Examples of the conductive film 7027 having translucency include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and oxidation ​ Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, silicon oxide A conductive transparent film having translucency such as indium tin oxide to which iodine is added can be used.

[0139] Also, although various materials can be used for the cathode 7023, materials with a small work function, for example, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (such as Mg:Ag and Al:Li), as well as rare earth metals such as Yb and Er are preferred. In this embodiment, the film thickness of the cathode 7023 is set to a degree that allows light transmission (preferably, about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode 7023.

[0140] Note that after laminating and forming a conductive film having translucency and an aluminum film, they may be selectively etched to form a conductive film 7027 having translucency and a cathode 7023. In this case, etching can be performed using the same mask, which is preferable.

[0141] Also, the peripheral portion of the cathode 7023 is covered with a partition wall 7029. The partition wall 7029 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7029 is preferably formed using a photosensitive resin material, and an opening portion is formed on the cathode 7023 so that the side wall of the opening portion becomes an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7029, the step of forming a resist mask can be omitted.

[0142] ​​​​​​In addition, the EL layer 7024 formed on the cathode 7023 and the partition wall 7029 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When the EL layer 7024 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7023. Note that it is not necessary to provide all of these layers. Moreover, it may be either case, whether it is composed of a single layer or configured such that a plurality of layers are stacked. When the EL layer 7024 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7023. Note that it is not necessary to provide all of these layers.

[0143] In addition, the stacking order is not limited to the above, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the cathode 7023. However, when comparing power consumption, it is preferable to stack the layers in the order of an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer on the cathode 7023 because the power consumption is lower. Moreover, when comparing power consumption, it is preferable to stack the layers in the order of an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer on the cathode 7023 because the power consumption is lower. In addition, the stacking order is not limited to the above, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the cathode 7023.

[0144] As the anode 7025 formed on the EL layer 7024, various materials can be used, but materials having a large work function, for example, transparent conductive materials such as ITO, IZO, and ZnO are preferable. In this embodiment, an ITO film containing silicon oxide is used as the anode 7025. Moreover, as the anode 7025 formed on the EL layer 7024, various materials can be used, but materials having a large work function, for example, transparent conductive materials such as ITO, IZO, and ZnO are preferable. In this embodiment, an ITO film containing silicon oxide is used as the anode 7025.

[0145] The region sandwiching the light-emitting layer 7024 between the cathode 7023 and the anode 7025 corresponds to the light-emitting element 7022. In the case of the element structure shown in Fig. 3(B), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0146] Note that Fig. 3(B) shows an example in which a conductive film having translucency is used as the gate electrode layer, and the light emitted from the light-emitting element 7022 to the cathode 7023 side passes through the color filter layer 7043 and is emitted through the gate electrode layer and the source electrode layer of the thin film transistor 7021. Note that Fig. 3(B) shows an example in which a conductive film having translucency is used as the gate electrode layer, and the light emitted from the light-emitting element 7022 to the cathode 7023 side passes through the color filter layer 7043. and is emitted through the gate electrode layer and the source electrode layer of the thin film transistor 7021. ​​​A conductive film having light transmittance is used as the gate electrode layer and the source electrode layer of the thin film transistor 7021. By using this, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be made substantially the same.

[0147] The color filter layer 7043 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

[0148] Further, the color filter layer 7043 is covered with an overcoat layer 7044 and further covered with a protective insulating layer 7045.

[0149] In addition, contact holes formed in the protective insulating layer 7045 and the insulating layer 7042 and reaching the connection electrode layer 7040 are arranged at positions overlapping the partition wall 7029. In FIG. 3(B), since the connection electrode layer 7040 is an example using a metal conductive film, the contact holes reaching the connection electrode layer 7040, the partition wall 7029, and the connection electrode layer 7040 are arranged in a layout where they overlap each other. In this way, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be made substantially the same.

[0150] However, when a light emitting element having a double-sided injection structure is used and full-color display is performed on both display surfaces, since the light from the anode 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate having a separate color filter layer above the anode 7025.

[0151] Next, the light emitting element having the top emission structure will be described with reference to FIG. 3(C).

[0152] In FIG. 3(C), the driving TFT 7001 is of the n-type, and light is emitted from the light emitting element 7002. ​​​​​​​The cross-sectional view of the pixel when the emitted light leaks to the anode 7005 side is shown. In FIG. 3(C), the light-emitting element 7002 electrically connected via the driving TFT 7001 and the connection electrode layer 7050 has a cathode 7003 formed thereon, and an EL layer 7004 and an anode 7005 are sequentially

[0153] stacked on the cathode 7003. In addition, although various materials can be used for the cathode 7003, materials with a small work function, for example, specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (such as Mg:Ag and Al:Li), as well as rare earth metals such as Yb and Er

[0154] are preferred. Also, the peripheral portion of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane and is formed. The partition wall 7009 is preferably formed using a photosensitive resin material to form an opening portion on the cathode 7003, and the side wall of the opening portion is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used as the partition wall 7009, the step of forming a resist mask can be omitted.

[0155] In addition, the EL layer 7004 formed on the cathode 7003 and the partition wall 7009 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When the EL layer 70 04 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers.

[0156] ​Also, it is not limited to the above lamination order, and a hole injection layer, a hole transport layer, and a light-emitting layer may be laminated on the cathode 7003 , an electron transport layer, and an electron injection layer in this order. When laminating in this order, the cathode 700 3 will function as an anode.

[0157] In FIG. 3(C), on a laminated film laminated in the order of a Ti film, an aluminum film, and a Ti film, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are laminated in this order, and a laminate of an Mg:Ag alloy thin film and ITO is formed thereon.

[0158] However, when comparing power consumption, it is preferable to laminate an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the cathode 7003 because the power consumption is lower.

[0159] The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tantalum oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide oxide, indium zinc oxide, or a light-transmitting conductive film such as indium tin oxide added with silicon oxide may be used.

[0160] The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 3(C), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 side as indicated by the arrow .

[0161] Also, in FIG. 3(C), the TFT 7001 shows an example using the thin-film transistor 460, but it is not particularly limited, and the thin-film transistor 450 can be used. The TFT70 ​When using the thin film transistor 450 as 01, the cathode 7003 and the drain electrode layer are electrically connected so as to be in contact with each other. To be electrically connected as such.

[0162] Also, in FIG. 3(C), the drain electrode layer of the TFT 7001 is electrically connected via the connection electrode layer 7050 and the oxide insulating layer 7051, and the connection electrode layer 7050 is electrically connected to the cathode 7003 via the protective insulating layer 7052 and the insulating layer 7055. The planarization insulating layer 7053 can be made of resin materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy. To be electrically connected via the oxide insulating layer 7051, and the connection electrode layer 7050 is electrically connected to the cathode 7003 via the protective insulating layer 7052 and the insulating layer 7055. 52 and the insulating layer 7055. The planarization insulating layer 7053 Can use resin materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Can be used. Note that by laminating a plurality of insulating films formed of these materials, the planarization insulating layer 7053 can be formed. The method for forming the planarization insulating layer 7053 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. To form the planarization insulating layer 7053. The method for forming the planarization insulating layer 7053 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. According to the material, sputtering, SOG method, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. Out method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. Can be used.

[0163] Also, a partition wall 7009 is provided to insulate the cathode 7003 from the cathode 7008 of an adjacent pixel. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is preferably formed using a photosensitive resin material, forming an opening on the cathode 7003, and forming an inclined surface with a continuous curvature on the side wall of the opening. To form an inclined surface with a continuous curvature on the side wall of the opening. It is preferably formed so as to be an inclined surface with a continuous curvature on the side wall of the opening. As the partition wall 7009, a photosensitive When a photosensitive resin material is used, the step of forming a resist mask can be omitted.

[0164] In the structure of FIG. 3C, when a full-color display is performed, for example, the light-emitting element 700 The first light-emitting element is a green light-emitting element, the second light-emitting element is a red light-emitting element, and the third light-emitting element is a red light-emitting element. The light elements are blue light emitting elements. In addition to the three types of light emitting elements, a white element is added, making a total of four types. A light-emitting display device capable of full-color display may be manufactured using such light-emitting elements.

[0165] In the structure of FIG. 3C, all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of displaying multiple colors may be fabricated. By forming a color filter and combining it with a color conversion layer, a full color display can be achieved. This can be done.

[0166] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0167] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0168] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0169] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. It may also be a continuous configuration.

[0170] (Embodiment 3) In this embodiment, using the plurality of thin film transistors shown in Embodiment 1, on the same substrate a pixel portion and a driving circuit are formed, and an example of manufacturing an active matrix type light emitting display device is shown.

[0171] In Embodiment 1, two thin film transistors and a cross section of a connection portion were illustrated, but in this embodiment a wiring intersection portion and a capacitor portion will also be illustrated and described.

[0172] FIG. 4 is a cross-sectional view showing the state of the substrate before forming the EL layer on the first electrode (pixel electrode). Note that the same reference numerals are used for the same portions as in FIG. 1(E) for explanation.

[0173] In FIG. 4, the driving TFT electrically connected to the first electrode 457 is a bottom contact type thin film transistor 460, and in this embodiment, it can be manufactured according to Embodiment 1 in this way.

[0174] After forming the insulating layer 428 according to Embodiment 1, a green color filter layer 456, a blue color filter layer, and a red color filter layer are sequentially formed. Each color filter layer is formed by a printing method, an inkjet method, an etching method using photolithography technology, etc. respectively. By providing the color filter layer, alignment between the color filter layer and the light emitting region of the light emitting element can be performed without depending on the bonding accuracy of the sealing substrate and can be achieved.

[0175] Next, the green color filter layer 456, the blue color filter layer, and the red color filter An overcoat layer 458 covering the filter layer is formed. The overcoat layer 458 uses a resin having light transmissivity.

[0176] Here, an example of full-color display using three colors of RGB is shown, but it is not particularly limited, and full-color display may be performed using four colors of RG BW.

[0177] Next, a protective insulating layer 413 covering the overcoat layer 458 and the insulating layer 428 is formed. The protective insulating layer 413 uses an inorganic insulating film, for example, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. As the protective insulating layer 413, if an insulating film having the same composition as the insulating layer 428 is used, it can be etched in one step during the subsequent contact hole formation, which is preferable.

[0178] Next, the protective insulating layer 413 and the insulating layer 428 are selectively etched by a photolithography process to form a contact hole reaching the connection electrode layer 452. Also, by this photolithography process, the protective insulating layer 413 and the insulating layer 428 of the terminal portion are selectively etched to expose a part of the terminal electrode. Also, a contact hole reaching the common potential line is formed to connect the second electrode of the light-emitting element to be formed later and the common potential line.

[0179] Next, a conductive film having light transmissivity is formed, and a first electrode 457 electrically connected to the connection electrode layer 452 is formed by a photolithography process.

[0180] Next, a partition wall 459 is formed so as to cover the peripheral portion of the first electrode 457. The partition wall 459 is an organic resin film such as polyimide, acrylic, polyamide, epoxy, an inorganic insulating film, or an organic poly ​​​​​​​​​​The partition wall 459 is formed by using a photosensitive resin material. 57, and an opening is formed on the surface of the substrate 10, and the side wall of the opening is an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition wall 459, a resist mask is formed. The step of forming the insulating film can be omitted.

[0181] Through the above steps, the substrate state shown in FIG. 4 can be obtained. The following steps are the same as those in the second embodiment. As shown in FIG. 1, an EL layer is formed on the first electrode 457, and a second electrode is formed on the EL layer. The second electrode is electrically connected to a common potential line.

[0182] In addition, a capacitance section is formed in the pixel section as shown in FIG. The gate insulating layer 402 serves as a dielectric, and the capacitor is formed of a capacitor wiring layer 430 and a capacitor electrode layer 431 . In the light emitting device, the capacitance wiring layer 430 is a part of the power supply line, and the capacitance electrode layer 4 Reference numeral 31 denotes a part of the gate electrode layer of the driving TFT.

[0183] In addition, in order to reduce parasitic capacitance at the wiring intersections as shown in FIG. Between the gate insulating layer 402 and the source wiring layer 422, the gate insulating layer 402 and the oxide insulating layer 426b are provided. In addition, in FIG. 4, the gate wiring layer 421c is a metal conductive film. However, the conductive layer 451a has the same light-transmitting property as the gate electrode layer 451a of the thin film transistor 460. It can also be formed using a film.

[0184] In addition, in FIG. 4, the TFT arranged in the driving circuit is a channel protection type thin film transistor. 450, and in this embodiment, it can be manufactured according to the first embodiment.

[0185] Also, in FIG. 4, at least one TFT arranged in the drive circuit is a thin film transistor 450, and in this embodiment, it can be manufactured according to Embodiment 1.

[0186] Also, a conductive layer 417 may be provided above the oxide semiconductor layer of the thin film transistor 450 in the drive circuit The conductive layer 417 can be formed of the same material and in the same process as the first electrode 457

[0187] By providing the conductive layer 417 at a position overlapping the channel formation region 423 of the oxide semiconductor layer in a bias - thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor the change amount of the threshold voltage of the thin film transistor 450 before and after the BT test can be reduced Also, the potential of the conductive layer 417 may be the same as or different from that of the gate electrode layer 421a, and it can also function as a second gate electrode layer Also, the potential of the conductive layer 417 may be GND, 0V, or in a floating state

[0188] Also, since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit The protection circuit is preferably configured using a non - linear element using an oxide semiconductor layer For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal In this embodiment, a plurality of protection circuits are arranged so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line by static electricity or the like, and the pixel transistor or the like is not damaged Therefore, the protection circuit is provided with a surge voltage ​​​When a voltage is applied, the protection circuit is configured to release the electric charge to the common wiring. The nonlinear element is arranged in parallel with the scanning line. It is composed of a two-terminal element such as an electrode or a three-terminal element such as a transistor. For example, It is possible to form the thin film transistor 460 in the pixel portion in the same process. For example, By connecting the drain terminal to the terminal, it can have the same characteristics as a diode. do.

[0189] This embodiment mode can be freely combined with embodiment mode 1 or 2.

[0190] (Embodiment 4) In this embodiment, one of the configurations of the terminal portion provided on the same substrate as the thin film transistor is An example is shown in Fig. 5. In Fig. 5, the same parts as in Fig. 4 are described using the same reference numerals.

[0191] FIG. 5(A1) and FIG. 5(A2) are a cross-sectional view and a top view, respectively, of a gate line terminal portion. FIG. 5(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 5(A2). In (A1), a conductive layer 415 is formed on a laminate of an insulating layer 428 and a protective insulating layer 413. is a terminal electrode for connection that functions as an input terminal. In the sub-portion, a first terminal 411 made of the same material as the gate wiring layer 421c and a source wiring The line layer 422 and the connection electrode layer 412 made of the same material are overlapped with each other via the gate insulating layer 402. The conductive layer 415 is electrically connected to the first electrode 457. The optical material can be formed in the same process.

[0192] Also, FIGS. 5(B1) and 5(B2) respectively illustrate a cross-sectional view and a top view of the source wiring terminal portion. Also, FIG. 5(B1) corresponds to a cross-sectional view taken along line C3-C4 in FIG. 5(B2). In FIG. 5(B1), a conductive layer 418 formed on the stack of the insulating layer 428 and the protective insulating layer 413 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, an electrode layer 416 formed of the same material as the gate wiring layer 421c overlaps below the second terminal 414 that is electrically connected to the source wiring with a gate insulating layer 402 interposed therebetween. The electrode layer 416 is not electrically connected to the second terminal 414, and if the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 414 is electrically connected to the conductive layer 418 via the insulating layer 428 and the protective insulating layer 413. Also, the conductive layer 418 can be formed of the same light-transmissive material as the first electrode 457 and in the same process. FIGS. 5(B1) and 5(B2) respectively illustrate a cross-sectional view and a top view of the source wiring terminal portion. Also, FIG. 5(B1) corresponds to a cross-sectional view taken along line C3-C4 in FIG. 5(B2). In FIG. 5(B1), a conductive layer 418 formed on the stack of the insulating layer 428 and the protective insulating layer 413 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, an electrode layer 416 formed of the same material as the gate wiring layer 421c overlaps below the second terminal 414 that is electrically connected to the source wiring with a gate insulating layer 402 interposed therebetween. In FIG. 5(B1), a conductive layer 418 formed on the stack of the insulating layer 428 and the protective insulating layer 413 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, an electrode layer 416 formed of the same material as the gate wiring layer 421c overlaps below the second terminal 414 that is electrically connected to the source wiring with a gate insulating layer 402 interposed therebetween. The electrode layer 416 is not electrically connected to the second terminal 414, and if the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. The electrode layer 416 is not electrically connected to the second terminal 414, and if the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. The electrode layer 416 is not electrically connected to the second terminal 414, and if the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. The electrode layer 416 is not electrically connected to the second terminal 414, and if the electrode layer 416 is set to a potential different from that of the second terminal 414, such as floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 414 is electrically connected to the conductive layer 418 via the insulating layer 428 and the protective insulating layer 413. Also, the conductive layer 418 can be formed of the same light-transmissive material as the first electrode 457 and in the same process. Also, the second terminal 414 is electrically connected to the conductive layer 418 via the insulating layer 428 and the protective insulating layer 413. Also, the conductive layer 418 can be formed of the same light-transmissive material as the first electrode 457 and in the same process. Also, the second terminal 414 is electrically connected to the conductive layer 418 via the insulating layer 428 and the protective insulating layer 413. Also, the conductive layer 418 can be formed of the same light-transmissive material as the first electrode 457 and in the same process.

[0193] A plurality of gate wirings, source wirings, common potential lines, and power supply lines are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals at the same potential as the gate wiring, second terminals at the same potential as the source wiring, third terminals at the same potential as the power supply line, fourth terminals at the same potential as the common potential line, etc. are arranged side by side. The number of each terminal can be set to an arbitrary number, and the implementer can appropriately determine it. A plurality of gate wirings, source wirings, common potential lines, and power supply lines are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals at the same potential as the gate wiring, second terminals at the same potential as the source wiring, third terminals at the same potential as the power supply line, fourth terminals at the same potential as the common potential line, etc. are arranged side by side. The number of each terminal can be set to an arbitrary number, and the implementer can appropriately determine it. The number of each terminal can be set to an arbitrary number, and the implementer can appropriately determine it. The number of each terminal can be set to an arbitrary number, and the implementer can appropriately determine it.

[0194] This embodiment can be freely combined with Embodiment 1, Embodiment 2, or Embodiment 3. This embodiment can be freely combined with Embodiment 1, Embodiment 2, or Embodiment 3.

[0195] (Embodiment 5) In this embodiment, an example of the element structure of the light-emitting element used in FIGS. 3(A) and 3(C) shown in Embodiment 2 will be described. An example of the element structure will be described.

[0196] The element structure shown in FIG. 6(A) has a structure in which an EL layer 1003 including a light-emitting region is sandwiched between a pair of electrodes (first electrode 1001 and second electrode 1002). In the following description of this embodiment, for example, the first electrode 1001 is used as the anode, and the second electrode 100 2 is used as the cathode. In addition, the EL layer 1003 only needs to be formed including at least a light-emitting layer, and may have a stacked structure including functional layers other than the light-emitting layer. As functional layers other than the light-emitting layer, layers containing substances with high hole injection properties, high hole transport properties, high electron transport properties, high electron injection properties, bipolar arity (substances with high electron and hole transport properties), etc. can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used.

[0197] Moreover, the EL layer 1003 only needs to be formed including at least a light-emitting layer, and may have a stacked structure including functional layers other than the light-emitting layer. As functional layers other than the light-emitting layer, layers containing substances with high hole injection properties, high hole transport properties, high electron transport properties, high electron injection properties, bipolar ity (substances with high electron and hole transport properties), etc. can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used. layers containing substances with high hole injection properties, high hole transport properties, high electron transport properties, high electron injection properties, bipolar arity (substances with high electron and hole transport properties), etc. can be used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used. Specifically, functional layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be appropriately combined and used.

[0198] In the light-emitting element shown in FIG. 6(A), a current flows due to the potential difference generated between the first electrode 1001 and the second electrode 1002, and holes and electrons recombine in the EL layer 1003 to emit light. That is, the structure is such that a light-emitting region is formed in the EL layer 1003. That is, the structure is such that a light-emitting region is formed in the EL layer 1003. That is, the structure is such that a light-emitting region is formed in the EL layer 1003.

[0199] The light emission is taken out to the outside through either one or both of the first electrode 1001 and the second electrode 1002. Therefore, either one or both of the first electrode 1001 and the second electrode 1002 are made of a light-transmissive substance. Therefore, either one or both of the first electrode 1001 and the second electrode 1002 are made of a light-transmissive substance. Therefore, either one or both of the first electrode 1001 and the second electrode 1002 are made of a light-transmissive substance. ​

[0200] As shown in FIG. 6B, the EL layer is formed between the first electrode 1001 and the second electrode 1002. In the case of a laminated structure of n layers (n is a natural number of 2 or more), A charge generating layer 1004 is provided between the (m+1)th EL layer and the (m+2)th EL layer. Here, m is a natural number and is 1 or more and (n-1) or less.

[0201] The charge generating layer 1004 may be a composite material of an organic compound and a metal oxide, a metal oxide, an organic compound, Alkali metals, alkaline earth metals, or composite materials with these compounds, as well as Examples of composite materials of organic compounds and metal oxides include Examples include organic compounds and metal oxides such as V2O5, MoO3, and WO3. The following compounds are considered to be suitable for use: aromatic amine compounds, carbazole derivatives, aromatic hydrocarbons, polymer compounds (oligosaccharides, etc.) Various compounds such as carboxymers, dendrimers, polymers, etc. can be used. As an organic compound, a hole-transporting organic compound with a hole mobility of 10 -6 cm 2 / Vs or later However, it is preferable that the material has a higher hole transporting property than the electron transporting property. If necessary, materials other than these may be used. The material has excellent carrier injection and carrier transport properties, enabling low current operation of light-emitting devices. It is possible.

[0202] The charge generating layer 1004 is made of a composite material of an organic compound and a metal oxide, and other materials. For example, a layer including a composite material of an organic compound and a metal oxide and a layer including an electron transport layer may be formed. It may be formed by combining a layer containing a compound selected from sex pheromones and a compound with high electron transport properties. Further, it may be formed by combining a layer containing a composite material of an organic compound and a metal oxide with a transparent conductive film.

[0203] A light-emitting device having such a configuration is less likely to cause problems such as energy transfer and quenching, and by widening the range of material selection, it is easy to make a light-emitting device having high luminous efficiency and long life. Also, it is easy to obtain phosphorescent emission in one EL layer and fluorescent emission in the other.

[0204] Note that the charge generation layer 1004 has a function of injecting holes into one EL layer 1003 formed in contact with the charge generation layer 1004 when a voltage is applied to the first electrode 1001 and the second electrode 1002, and has a function of injecting electrons into the other EL layer 1003.

[0205] The light-emitting device shown in Fig. 6(B) can obtain various emission colors by changing the type of light-emitting substance used in the light-emitting layer. Also, by using a plurality of light-emitting substances having different emission colors as the light-emitting substance, broad-spectrum emission or white emission can be obtained.

[0206] When obtaining white light using the light-emitting device shown in Fig. 6(B), in combination with a plurality of light-emitting layers, any configuration that emits white light including red, blue, and green light may be used. For example, a configuration having a first EL layer containing a blue fluorescent material as the light-emitting substance and a second EL layer containing green and red phosphorescent materials as the light-emitting substance can be mentioned. Also, a configuration having a first EL layer showing red emission, a second EL layer showing green emission, and a third EL layer showing blue emission can be used. This is also possible. Alternatively, a white light emission can be obtained even with a configuration having a light-emitting layer that emits light in a complementary color relationship. In a stacked element in which two EL layers are stacked, when the emission color of the light obtained from the first EL layer and the emission color of the light obtained from the second EL layer are in a complementary color relationship, examples of the complementary color relationship include blue and yellow, or blue-green and red. relationship include blue and yellow, or blue-green and red. relationship include blue and yellow, or blue-green and red.

[0207] In the configuration of the stacked element described above, by disposing a charge generation layer between the stacked EL layers, it is possible to realize a long-life element in a high-luminance region while keeping the current density low. In the configuration of the stacked element described above, by disposing a charge generation layer between the stacked EL layers, it is possible to realize a long-life element in a high-luminance region while keeping the current density low. In addition, since the voltage drop due to the resistance of the electrode material can be reduced, uniform light emission over a large area becomes possible. In addition, since the voltage drop due to the resistance of the electrode material can be reduced, uniform light emission over a large area becomes possible.

[0208] This embodiment can be combined with any one of Embodiments 1 to 4.

[0209] (Embodiment 6) In this embodiment, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) will be described with reference to FIG. 7. FIG. 7(A) is a plan view of the panel in which the thin-film transistors and light-emitting elements formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 7 (B) corresponds to the cross-sectional view taken along the line H-I in FIG. 7(A). (B) corresponds to the cross-sectional view taken along the line H-I in FIG. 7(A). (B) corresponds to the cross-sectional view taken along the line H-I in FIG. 7(A).

[0210] A sealing material 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. A sealing material 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. A sealing material 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. A sealing material 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0211] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 7B, a thin film transistor 4510 included in a pixel portion 4502 and a signal A thin film transistor 4509 included in the line driver circuit 4503a is illustrated.

[0212] The thin film transistors 4509 and 4510 are the signal transistors including the oxide semiconductor layer described in Embodiment 1. Thin film transistors with high reliability can be used. Thin film transistors for driving circuits 4 As the transistor 509, the thin film transistor 450 shown in the embodiment mode 1, the thin film transistor for a pixel A thin film transistor 460 can be used as the transistor 4510. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0213] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the channel forming region. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, The variation in the threshold voltage of the thin film transistor 4509 can be reduced. Also, the conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509, or it may be different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4 540 may be GND, 0V, or in a floating state.

[0214] The thin film transistor 4509 is formed with an insulating layer 4541a that functions as a channel protection layer and an insulating layer 4541b that covers the peripheral portion (including the side surface) of the stack of the oxide semiconductor layer.

[0215] Also, the thin film transistor 4510 is electrically connected to the first electrode 4517 via a connection electrode layer 4548. Further, an oxide insulating layer 4542 that covers the oxide semiconductor layer of the thin film transistor 4510 is formed.

[0216] The oxide insulating layers 4541a, 4541b, and 4542 may be formed by the same materials and methods as the oxide insulating layers 4 26a and 426b shown in Embodiment 1. Further, an insulating layer 4544 that covers the oxide insulating layers 4541 a, 4541b, and 4542 is formed. The insulating layer 4544 may be formed by the same materials and methods as the insulating layer 428 shown in Embodiment 1.

[0217] A color filter layer 4545 is formed on the thin film transistor 4510 so as to overlap with the light emitting region of the light emitting element 4511.

[0218] Also, it is configured to be covered with an overcoat layer 4543 that functions as a planarization insulating film to reduce the surface unevenness of the color filter layer 4545.

[0219] An insulating layer 4546 is formed on the overcoat layer 4543. The insulating layer 4546 may be formed of the same material and by the same method as the protective insulating layer 413 shown in Embodiment 1.

[0220] Also, 4511 corresponds to a light-emitting element, and the first electrode 4 517 is electrically connected to the source electrode layer or the drain electrode layer of the thin-film transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode 4517, the electroluminescent layer 4512 , and the second electrode 4513, but is not limited to the shown structure. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0221] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and it is preferable to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature.

[0222] The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are stacked.

[0223] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0224] Also, various signals and potentials applied to the signal line drive circuits 4503a, 4503b, the scan line drive circuits 4504a, 4504b , or the pixel portion 4502 are transmitted through the FPCs 4518a, 4518 ​​It is supplied by b.

[0225] The connection terminal electrode 4515 is made of the same conductive film as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is a source electrode layer and a drain electrode layer of the thin film transistor 4509. It is formed from the same conductive film as the electrode layer.

[0226] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0227] The second substrate is not transparent to light, and is located in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0228] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0229] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0230] The signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b may be mounted by a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof may be separately formed and mounted, and the present invention is not limited to the configuration of FIG. 7. By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0231]

[0232] (Embodiment 7) In this embodiment, an example of manufacturing at least a part of a driving circuit and a thin film transistor disposed in a pixel portion on the same substrate will be described below.

[0233] The thin film transistor disposed in the pixel portion is formed according to Embodiment 1. Further, since the thin film transistor shown in Embodiment 1 is an n-channel type TFT, a part of the driving circuit that can be configured by an n-channel type TFT among the driving circuits is formed on the same substrate as the thin film transistor in the pixel portion.

[0234] An example of a block diagram of an active matrix type display device is shown in FIG. 9(A). On a substrate 5300 of the display device, there are a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. A plurality of signal lines extend from the signal line driving circuit 5304 and are disposed in the pixel portion 5301, and a plurality of scanning lines extend from the first scanning line driving circuit 5302 and the scanning line driving circuit 5303 and are disposed. In the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Also ​​​​​​​​​​​​, the substrate 5300 of the display device is connected to the timing control circuit 5305 (also referred to as a controller or a control IC) via a connection part such as an FPC (Flexible Printed Circuit). In FIG. 9(A), the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on the same substrate 5300 as the pixel part 5301. Therefore, the number of components such as driving circuits provided externally can be reduced, so that the cost can be reduced. Also,

[0235] when the driving circuit is provided outside the substrate 5300, the number of connections at the connection part due to extending the wiring can be reduced, and the reliability or the yield can be improved. Note that the timing control circuit 5305 supplies, for example, a start signal for the first scanning line driving circuit (GSP1) and a clock signal for the scanning line driving circuit (GCK1) to the first scanning line driving circuit 5302. Also, the timing control circuit 5305 supplies, for example, a start signal for the second scanning line driving circuit (GSP2) (also referred to as a start pulse) and a clock signal for the scanning line driving circuit (GCK2) to the second scanning line driving circuit 5303. The signal line driving circuit 5304 is supplied with a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), video signal data (DATA) (simply referred to as a video signal), and a latch signal (LAT). Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303. Since the number of components such as external driving circuits is reduced, cost reduction can be achieved. Also, when a driving circuit is provided outside the substrate 5300, the number of continuities at the connection part due to extending the wiring can be reduced, and improvement in reliability or yield can be achieved.

[0236] Note that the timing control circuit 5305 supplies, as an example, a start signal for the first scanning line driving circuit (GSP1) and a clock signal for the scanning line driving circuit (GCK1) to the first scanning line driving circuit 5302. Also, the timing control circuit 5305 supplies, as an example, a start signal for the second scanning line driving circuit (GSP2) (also referred to as a start pulse) and a clock signal for the scanning line driving circuit (GCK2) to the second scanning line driving circuit 5303. The signal line driving circuit 5304 is supplied with a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), video signal data (DATA) (simply referred to as a video signal), and a latch signal (LAT). Note that each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303. For the signal line driving circuit 5304, a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), video signal data (DATA) (simply referred to as a video signal), and a latch signal (LAT) are to be supplied. Note that each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303. Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303. ​​

[0237] In FIG. 9(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301. With this configuration, compared with a transistor using a single crystal semiconductor, a thin film transistor having a small field effect mobility can be used to configure the driving circuit formed on the substrate 5300. Therefore, it is possible to increase the size of the display device, reduce the cost, or improve the yield, etc.

[0238] Also, the thin film transistor shown in Embodiment 1 is an n-channel type TFT. In FIGS. 10(A ), 10(B), an example of the configuration and operation of a signal line driving circuit configured by n-channel type TFTs will be shown and described.

[0239] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits such as switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). An example where the thin film transistors 5603_1 to 5603_k are N-channel type TFTs will be described.

[0240] Regarding the connection relationship of the signal line driving circuit, the switching circuit 5602_1 will be described as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to a wiring 5604_1 ~5604_k. The second terminals of thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of thin film transistors 5603_1 to 5603_ k are connected to wiring 5605_1.

[0241] The shift register 5601 outputs signals of H level (also referred to as H signal , high power supply potential level) to wiring 5605_1 to 5605_N in sequence, and has a function of selecting switching circuits 5602_1 to 56 02_N in sequence.

[0242] The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between wiring 5604_1 to 5604_k and signal lines S1 to Sk, that is, a function of controlling whether or not to supply the potentials of wiring 5604_ 1 to 5604_k to signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. Also, thin film transistors 5603_1 to 5603_k each have a function of controlling the conduction state between wiring 5604_1 to 5604_k and signal lines S1 to Sk, that is, a function of supplying the potentials of wiring 5604_1 to 5604_k to signal lines S1 to Sk. In this way, thin film transistors 56 03_1 to 5603_k each have a function as a switch.

[0243] Note that video signal data (DATA) is input to wiring 5604_1 to 5604_k, respectively. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

[0244] Next, regarding the operation of the signal line driving circuit in Fig. 10(A), the timing chart in Fig. 10(B) This will be described with reference to FIG. FIG. 10(B) shows an example of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata _k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row. There is.

[0245] Note that the blurring of the signal waveforms of each configuration shown in the drawings and the like of the present embodiment may be exaggerated for clarity. Therefore, it is noted that it is not necessarily limited to that scale. is. is added.

[0246] During periods T1 to TN, the shift register 5601 sequentially outputs H-level signals to the wirings 560 5_1 to 5605_N. For example, in period T1, the shift register 5 601 outputs a high-level signal to the wiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k turn on, so that the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state. At this time, Data(S1) to Data(Sk) are input to the wirings 5604_1 to 5604_k. Data(S1) to Data(Sk ) are each written to the pixels in the first to k-th columns among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k. Thus, in periods T1 to TN ) are each written to the pixels in the first to k-th columns among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k. Thus, in periods T1 to TN belonging to the selected row. Thus, in periods T1 to TN Then, video signal data (DATA) is sequentially written pixel by pixel, k columns at a time, to the pixels belonging to the selected row. is written.

[0247] As described above, by writing the video signal data (DATA) pixel by pixel in multiple columns at a time, the number of video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal pixel by pixel in multiple columns at a time, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0248] Note that as the shift register 5601 and the switching circuit 5602, it is possible to use a circuit composed of thin film transistors shown in Embodiments 1, 2, 5, and 6. In this case, all the transistors of the shift register 5601 can be configured with only one of the polarities of N-channel type or P-channel type.

[0249] A form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 11 and 12.

[0250] Note that the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, or the like. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, pixel data for one line is supplied. ​​​​The gate electrode of the bare transistor is connected. And since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. Since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. Since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used.

[0251] The shift registers of the scanning line drive circuit and the signal line drive circuit will be described with reference to FIGS. 11 and 12. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 11(A)). The shift registers of the scanning line drive circuit and the signal line drive circuit will be described with reference to FIGS. 11 and 12. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 11(A)). The shift registers of the scanning line drive circuit and the signal line drive circuit will be described with reference to FIGS. 11 and 12. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 11(A)). For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. For the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 11(A), a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14 are supplied. Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. In the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) from the second stage onwards, a signal (referred to as a previous stage signal OUT(n - 1)) from the previous stage pulse output circuit 10_n - 1 is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. Similarly, in the nth pulse output circuit 10_n from the second stage onwards, a signal (referred to as a subsequent stage signal OUT(n + 2)) from the (n + 2)th pulse output circuit 10_(n + 2) two stages later is input. Similarly, in the nth pulse output circuit 10_n from the second stage onwards, a signal (referred to as a subsequent stage signal OUT(n + 2)) from the (n + 2)th pulse output circuit 10_(n + 2) two stages later is input. Therefore, from each stage of the pulse output circuit, a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or two stages before, and a second output signal (OUT(1) to OU Therefore, from each stage of the pulse output circuit, a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or two stages before, and a second output signal (OUT(1) to OU Therefore, from each stage of the pulse output circuit, a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or two stages before, and a second output signal (OUT(1) to OU T(N)) is output. However, as shown in FIG. 11(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, the second start pulse SP2 and the third start pulse SP3 may be separately input. Since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a configuration may be adopted in which the second start pulse SP2 and the third start pulse SP3 are separately input. That is, it is sufficient to have such a configuration.

[0252] The clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. The clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK. That is, the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. The clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK. That is, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. The clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK. That is, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. The clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK. That is, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit, etc. The clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK. That is, the clock signal may be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK.

[0253] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 11(B)). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 11(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is the second​ is electrically connected to the wiring 13 of 3, and the third input terminal 23 is electrically connected to the fourth wiring 14 is being.

[0254] In the first pulse output circuit 10_1, a first clock signal CK 1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third input terminal 23 is input with a third clock signal CK3, a first start pulse SP1 is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, and the first output signal OUT(1)(SR) is output from the first output terminal 26, and the second output terminal 2 7 outputs a second output signal OUT(1).

[0255] Note that the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are, in addition to the three-terminal thin film transistor (also referred to as TFT: Thin Film Transistor), the above described four-terminal thin film transistor can be used. FIG. 11(C) shows the symbol of the four-terminal thin film transistor 28 described in the above embodiment. FIG The symbol of the thin film transistor 28 shown in 11(C) means the four-terminal thin film transistor described in any one of the above embodiments 1, 2, 5, and 6 and will be used hereinafter in the drawings and the like. In this specification, when a thin film transistor has two gate electrodes via a semiconductor layer the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode. The thin film transistor 28 has a first control signal G1 input to the lower gate electrode and a second control signal G2 input to the upper gate electrode ​is an element capable of performing electrical control between the In terminal and the Out terminal.

[0256] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, the threshold voltage may shift to the negative side or the positive side during the manufacturing process. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the thin film transistor 28 shown in FIG. 11(C) can be controlled to a desired value by providing a gate electrode via a gate insulating film above and below the channel formation region of the thin film transistor 28 and controlling the potential of the upper and / or lower gate electrodes. Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 11(D). The first pulse output circuit 10_1 includes the first transistor 31 to the thirteenth transistor 43 (see FIG. 11(D)). Also, signals or power supply potentials are supplied to the first transistor 31 to the thirteenth transistor 43 from a power supply line 51 to which a first high power supply potential VDD is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 11(D) is such that the first power supply potential VDD is at a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is at a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are at VDD when at the H level and at VSS when at the L level. Note that the potential VDD of the power supply line 51

[0257]

[0258] ​​​​​​​​​​​​​ By making it higher than the potential VCC of the power supply line 52, without affecting the operation, the potential applied to the gate electrode of the transistor can be kept low, reducing the shift of the threshold value of the transistor and suppressing deterioration. As shown in FIG. 11(D), among the first transistor 31 to the thirteenth transistor 43, for the first transistor 3 1, the sixth transistor 36 to the ninth transistor 39, it is preferable to use the four-terminal thin-film transistor 28 shown in FIG. 11(C). The operation of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 is a transistor that requires switching the potential of the node to which one of the electrodes serving as the source or drain is connected by the control signal of the gate electrode, and has a fast response to the control signal input to the gate electrode ( the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be further reduced. Therefore, by using the four-terminal thin-film transistor 28 shown in FIG. 11(C), the threshold voltage can be controlled, and a pulse output circuit with further reduced malfunction can be obtained. In FIG. 11(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used. In FIG. 11(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the third transistor 33, the first terminal is electrically connected to the power supply line 54, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the fourth transistor 34, the first terminal is electrically connected to the power supply line 55, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the fifth transistor 35, the first terminal is electrically connected to the power supply line 56, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the fourth input terminal 24. For the sixth transistor 36, the first terminal is electrically connected to the power supply line 57, and the second terminal

[0259] In FIG. 11(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, and the second terminal (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the third transistor 33, the first terminal is electrically connected to the power supply line 54, and the second terminal (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the fourth transistor 34, the first terminal is electrically connected to the power supply line 55, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21 and its second terminal electrically connected to the first output terminal 26 . The fourth transistor 34 has its first terminal electrically connected to the power supply line 53 and its second terminal electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power supply line 53 and its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is electrically connected to the fourth input terminal 24. The sixth transistor 36 has its first terminal electrically connected to the power supply line 52 and its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power supply line 52 and its second terminal electrically connected to the second terminal of the eighth transistor 38, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 . 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 ​​​​​​​​​​​ electrically connected, and the gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power line 52 electrically connected thereto. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 2 1, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the second terminal of the ninth transistor 39 41 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) ). The thirteenth transistor 43 has its first terminal electrically connected to the power line 5 3, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) ).

[0260] In FIG. 11(D), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is defined as node A . Also, the connection point of the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is defined as node B

[0261] Figure 12(A) shows the signals input to or output from the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 when the pulse output circuit described in Figure 11(D) is applied to the first pulse output circuit 10_ 1. and the second output terminal 27.

[0262] Specifically, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, a third clock signal CK3 is input to the third input terminal 23, a start pulse is input to the fourth input terminal 24, and a subsequent stage signal OUT(3) is input to the fifth input terminal 25. A first output signal OUT (1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27. (1)(SR) is output, and a second output signal OUT(1) is output from the second output terminal 27. is output.

[0263] Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure and operating conditions of the thin film transistor, etc., it is difficult to limit which one is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case as an example, they may be denoted as the first terminal and the second terminal, respectively. In addition, in Figures 11(D) and 12(A), a capacitive element may be separately provided to perform a bootstrap strap operation by making the node A in a floating state. Also, the potential of the node B may be held .

[0264] Note that in Figures 11(D) and 12(A), a capacitive element may be separately provided to perform a bootstrap strap operation by making the node A in a floating state. Also, the potential of the node B may be held Therefore, a capacitive element with one electrode electrically connected to node B may be separately provided.

[0265] Here, the timing chart of a shift register having a plurality of pulse output circuits shown in Fig. 12(A) is shown in Fig. 12(B). When the shift register is a scanning line driving circuit, the period 61 in Fig. 12(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period. Here, the timing chart of a shift register having a plurality of pulse output circuits shown in Fig. 12(A) is shown in Fig. 12(B). When the shift register is a scanning line driving circuit, the period 61 in Fig. 12(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period. Here, the timing chart of a shift register having a plurality of pulse output circuits shown in Fig. 12(A) is shown in Fig. 12(B). When the shift register is a scanning line driving circuit, the period 61 in Fig. 12(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period. Here, the timing chart of a shift register having a plurality of pulse output circuits shown in Fig. 12(A) is shown in Fig. 12(B). When the shift register is a scanning line driving circuit, the period 61 in Fig. 12(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period.

[0266] As shown in Fig. 12(A), by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate, there are the following advantages before and after the bootstrap operation. As shown in Fig. 12(A), by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate, there are the following advantages before and after the bootstrap operation. As shown in Fig. 12(A), by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate, there are the following advantages before and after the bootstrap operation.

[0267] When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor When there is no ninth transistor 39 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause transistor degradation. Therefore, by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the first transistor The value of the negative bias voltage applied between the gate and the source of the transistor 31 can be reduced. Therefore, by adopting the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that the degradation of the first transistor 31 due to stress can be suppressed.

[0268] Regarding the location where the ninth transistor 39 is provided, it may be configured to be connected via the first terminal and the second terminal between the second terminal of the first transistor 31 and the gate of the third transistor 33. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, and the advantage is that the number of transistors can be reduced.

[0269] By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin film transistor can be reduced, and the on-current and the field effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunctions in the circuit can be reduced. In addition, compared with a transistor using amorphous silicon, a transistor using an oxide semiconductor has a smaller degree of degradation of the transistor due to the application of a high potential to the gate electrode. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, and the number of power supply lines for routing between circuits can be reduced, so that the circuit can be miniaturized.

[0270] Note that the gate electrodes of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The clock signal supplied to the third input terminal 23, and the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 38 are supplied by the second input terminal 22 The clock signal is the same as the clock signal supplied to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 by the second input terminal 22, and the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38 is supplied by the third input terminal 23 The same operation can be achieved by changing the wiring relationship so that the clock signal supplied by the third input terminal 23 is obtained. In the shift register shown in Fig. 12(A), when both the seventh transistor 37 and the eighth transistor 38 are in the on state, when the seventh transistor 37 is turned off and the eighth transistor 38 is in the on state, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 decreases twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, when the shift register shown in Fig. 12(A) is changed as shown in Fig. 12(B), from the state where both the seventh transistor 37 and the eighth transistor 38 are on, when the seventh transistor 37 is on and the eighth transistor 38 is off, and then the seventh transistor 37 is off and the eighth transistor 38 is off, the decrease in the potential of node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. When the seventh transistor 37 is off and the eighth transistor 38 is off, the decrease in the potential of node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. The decrease in the potential of node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, a clock signal is supplied from the third input terminal 23 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. Such a wiring relationship is preferable. This is because the number of fluctuations in the potential of node B is reduced, and noise can be reduced.

[0271] In this way, by adopting a configuration in which a signal of the H level is periodically supplied to node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, malfunction of the pulse output circuit can be suppressed.

[0272] (Embodiment 8) In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of Embodiment 1 is shown in FIG. 8. Since FIG. 8 is the same as FIG. 1 except for the part where the process is different, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted.

[0273] First, according to Embodiment 1, two types of gate electrode layers and a gate insulating layer 402 are formed on the substrate, and a source electrode layer 455a and a drain electrode layer 455b that partially overlap via one of the gate electrode layers and the gate insulating layer are formed. Then, an oxide semiconductor film is formed on the gate insulating layer 402, the source electrode layer 455a, and the drain electrode layer 455b.

[0274] Next, dehydration or dehydrogenation of the oxide semiconductor film is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400°C or higher and lower than the strain point of the substrate, preferably 425°C or higher. ​​​​​​​​​​​​. If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. If the temperature is lower than 425°C, the heat treatment time shall be longer than 1 hour. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor film is heat-treated in a nitrogen atmosphere. After that, without exposing it to the atmosphere, re-mixing of impurities such as water and hydrogen into the oxide semiconductor film is prevented to obtain an oxide semiconductor film. Then, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) is introduced into the same furnace for cooling. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or N2O gas. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher , preferably 7N (99.99999%) or higher (that is, the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower). Also, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed in an oxygen gas or N2O gas atmosphere at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower. By going through the above steps, the entire oxide semiconductor film is made in an oxygen-excessive state, thereby achieving high resistivity, that is, type I conversion. In this embodiment, an example of performing the first heat treatment for dehydration or dehydrogenation immediately after forming the oxide semiconductor film is shown, but it is not particularly limited as long as it is a process after forming the oxide semiconductor film.

[0275] Next, the oxide semiconductor film and the gate insulating layer 402 are selectively processed by a photolithography process.

[0276]

[0277] Etch to reach the gate electrode layer 421b to form a contact hole. Oxide semi- By forming a resist on the conductor film, contamination at the interface between the gate insulating layer 402 and the oxide semiconductor film can be prevented. The state after removing the resist mask is shown in FIG. 8(A).

[0278] Next, after removing the resist mask, a resist mask is formed again, and the oxide semiconductor film is selectively etched to be processed into an island-shaped oxide semiconductor layer. Then, the resist mask is removed to obtain oxide semiconductor layers 404 and 405 on the gate insulating layer 402 (see FIG. 8(B). )

[0279] Next, an oxide insulating film is formed by sputtering on the gate insulating layer 402 and the oxide semiconductor layers 404 and 405. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 426a and 426b. Then, the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the gate electrode layer, the gate insulating layer, and the oxide insulating layer 426a becomes the channel formation region. Also, a region overlapping the oxide insulating layer 426b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, the formation of a contact hole reaching the gate electrode layer 421b and the formation of a contact hole reaching the drain electrode layer 455b are also performed (see FIG. 8(C).

[0280] The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH - and blocks the intrusion of these from the outside. An inorganic insulating film is used, typically a silicon oxide film, a silicon oxynitride film ​​​​​​​​​​​​​A film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0281] Next, a stack of an oxide conductive film and a metal conductive film is formed on the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer. When using the sputtering method, the stack of the oxide conductive film and the metal conductive film can be continuously formed without exposure to the atmosphere.

[0282] The oxide conductive film preferably contains zinc oxide as a component and preferably does not contain indium oxide. Examples of such an oxide conductive film include zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide. In this embodiment, a zinc oxide film is used.

[0283] Also, as the metal conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc. is used. Further, it is not limited to a single layer containing the above-described elements, and a stack of two or more layers can be used. In this embodiment, a three-layer stack film in which a molybdenum film, an aluminum film, and a molybdenum film are stacked is used.

[0284] Next, a resist mask is formed, the metal conductive film is selectively etched to form the source electrode layer 445a, the drain electrode layer 445b, the connection electrode layer 449, and the connection electrode layer 442, and then the resist mask is removed. Note that the resist stripping solution used to remove the resist mask is an alkaline solution. When using the resist stripping solution, the source electrode layer 445a, the drain electrode layer 445b, the connection electrode layer 449, and the connection electrode layer 442 are used as masks. The zinc oxide film is also selectively etched. An oxide conductive layer 446a is formed in contact with the lower side of the source electrode layer 445a, and an oxide conductive layer 446b is formed in contact with the lower side of the drain electrode layer 445b. By providing the oxide conductive layer 446a between the source electrode layer 445a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, enabling a thin film transistor capable of high-speed operation to be realized. The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer functions as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer functions as a drain region, so it is effective for improving the frequency characteristics of the peripheral circuit (drive circuit). Also, when the molybdenum film and the oxide semiconductor layer are in direct contact, there is a problem that the contact resistance becomes high. This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing the oxide conductive layer 446a between the oxide semiconductor layer and the source electrode layer and interposing the oxide conductive layer 446b between the oxide semiconductor layer and the drain electrode layer, the contact resistance can be reduced and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the same process, an oxide conductive layer 448 is formed in contact with the lower side of the connection electrode layer 449, and an oxide conductive layer 447 is formed in contact with the lower side of the connection electrode layer 442 (see Fig. 8(D)). By forming the oxide conductive layer 448 between the connection electrode layer 449 and the gate electrode layer 421b, it serves as a buffer, which is preferable, and furthermore, it is preferable because it does not form an oxide that is insulating from the metal. The zinc oxide film is also selectively etched. An oxide conductive layer 446a is formed in contact with the lower side of the source electrode layer 445a, and an oxide conductive layer 446b is formed in contact with the lower side of the drain electrode layer 445b. By providing the oxide conductive layer 446a between the source electrode layer 445a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, enabling a thin film transistor capable of high-speed operation to be realized. The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer functions as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer functions as a drain region, so it is effective for improving the frequency characteristics of the peripheral circuit (drive circuit). Also, when the molybdenum film and the oxide semiconductor layer are in direct contact, there is a problem that the contact resistance becomes high. This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing the oxide conductive layer 446a between the oxide semiconductor layer and the source electrode layer and interposing the oxide conductive layer 446b between the oxide semiconductor layer and the drain electrode layer, the contact resistance can be reduced and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the same process, an oxide conductive layer 448 is formed in contact with the lower side of the connection electrode layer 449, and an oxide conductive layer 447 is formed in contact with the lower side of the connection electrode layer 442 (see Fig. 8(D)). By forming the oxide conductive layer 448 between the connection electrode layer 449 and the gate electrode layer 421b, it serves as a buffer, which is preferable, and furthermore, it is preferable because it does not form an oxide that is insulating from the metal. The zinc oxide film is also selectively etched. An oxide conductive layer 446a is formed in contact with the lower side of the source electrode layer 445a, and an oxide conductive layer 446b is formed in contact with the lower side of the drain electrode layer 445b. By providing the oxide conductive layer 446a between the source electrode layer 445a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, enabling a thin film transistor capable of high-speed operation to be realized. The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer functions as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer functions as a drain region, so it is effective for improving the frequency characteristics of the peripheral circuit (drive circuit). Also, when the molybdenum film and the oxide semiconductor layer are in direct contact, there is a problem that the contact resistance becomes high. This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing the oxide conductive layer 446a between the oxide semiconductor layer and the source electrode layer and interposing the oxide conductive layer 446b between the oxide semiconductor layer and the drain electrode layer, the contact resistance can be reduced and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the same process, an oxide conductive layer 448 is formed in contact with the lower side of the connection electrode layer 449, and an oxide conductive layer 447 is formed in contact with the lower side of the connection electrode layer 442 (see Fig. 8(D)). By forming the oxide conductive layer 448 between the connection electrode layer 449 and the gate electrode layer 421b, it serves as a buffer, which is preferable, and furthermore, it is preferable because it does not form an oxide that is insulating from the metal. The zinc oxide film is also selectively etched. An oxide conductive layer 446a is formed in contact with the lower side of the source electrode layer 445a, and an oxide conductive layer 446b is formed in contact with the lower side of the drain electrode layer 445b. By providing the oxide conductive layer 446a between the source electrode layer 445a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, enabling a thin film transistor capable of high-speed operation to be realized. The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer functions as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer functions as a drain region, so it is effective for improving the frequency characteristics of the peripheral circuit (drive circuit).

[0285] Also, when the molybdenum film and the oxide semiconductor layer are in direct contact, there is a problem that the contact resistance becomes high. This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer does not become n-type. However, even in such a case, by interposing the oxide conductive layer 446a between the oxide semiconductor layer and the source electrode layer and interposing the oxide conductive layer 446b between the oxide semiconductor layer and the drain electrode layer, the contact resistance can be reduced and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Moreover, in the same process, an oxide conductive layer 448 is formed in contact with the lower side of the connection electrode layer 449, and an oxide conductive layer 447 is formed in contact with the lower side of the connection electrode layer 442 (see Fig. 8(D)). By forming the oxide conductive layer 448 between the connection electrode layer 449 and the gate electrode layer 421b, it serves as a buffer, which is preferable, and furthermore, it is preferable because it does not form an oxide that is insulating from the metal. The zinc oxide film is also selectively etched. An oxide conductive layer 446a is formed in contact with the lower side of the source electrode layer 445a, and an oxide conductive layer 446b is formed in contact with the lower side of the drain electrode layer 445b. By providing the oxide conductive layer 446a between the source electrode layer 445a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, enabling a thin film transistor capable of high-speed operation to be realized. The oxide conductive layer 446a provided between the source electrode layer 445a and the oxide semiconductor layer functions as a source region, and the oxide conductive layer 446b provided between the drain electrode layer 445b and the oxide semiconductor layer functions as a drain region, so it is effective for improving the frequency characteristics of the peripheral circuit (drive circuit).

[0286] Note that since there is a difference in etching rate between the oxide semiconductor layer and the oxide conductive layer, the oxide conductive layer in contact with the oxide semiconductor layer can be removed by time control.

[0287] Also, after selectively etching the metal conductive film, the resist mask is removed by oxygen ashing treatment, and after leaving the zinc oxide film, the source electrode layer 445a, the drain electrode layer 445b , the connection electrode layer 449, and the connection electrode layer 442 can be used as masks to selectively etch the zinc oxide film. , the connection electrode layer 449, and the connection electrode layer 442 can be used as masks to selectively etch the zinc oxide film. It may be etched.

[0288] Also, when performing the first heat treatment after selectively etching the metal conductive film, unless the oxide conductive layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer. layers 446a, 446b, 447, and 448 contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 446a, 446b, 447, and 448 will crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of an undercut in the lower oxide conductive layer.

[0289] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a second heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere , or in a nitrogen gas atmosphere. For example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Note that by the second heat treatment, oxygen diffuses into the oxide semiconductor layer. By diffusing oxygen into the oxide semiconductor layer, it is possible to increase the resistance (type I) of the channel formation region. Thereby Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a second heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a second heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a second heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere , a thin film transistor that becomes normally off can be obtained. Also, in the second heat treatment , the oxide conductive layers 446a, 446b, 447, and 448 can be crystallized to improve conductivity .

[0290] Next, an insulating layer 428 is formed on the oxide insulating layers 426a, 426b, the source electrode layer 445a, and the drain electrode layer 44 5b (see Fig. 8(E)).

[0291] Through the above steps, the thin film transistor 440 and the thin film transistor 460 can be fabricated on the same substrate .

[0292] The thin film transistor 440 disposed in the driving circuit includes a gate electrode layer 421a, a gate insulating layer 402, at least a channel formation region 443, a high-resistance source region 444a, and a high-resistance drain region 444b on a substrate 400 having an insulating surface, an oxide semiconductor layer, oxide conductive layers 446a, 446b, a source electrode layer 445a, and a drain electrode layer 445b. Also, an oxide insulating layer 426a in contact with the channel formation region 443 is provided. Further, an insulating layer 428 is provided on the source electrode layer 445a and the drain electrode layer 445b. An oxide conductive layer 446a that functions as a source region is provided between the high-resistance source region 444a and the source electrode layer 445a, and an oxide conductive layer 446b that functions as a drain region is provided between the high-resistance drain region 444b and the drain electrode layer 445 b to reduce the contact resistance.

[0293] Also, a first region 444c and a second region 44 of the oxide semiconductor layer overlapping the oxide insulating layer 426b

[0294] 4d is in the same oxygen-excess state as the channel formation region 443, and is effective in reducing leakage current and reducing parasitic capacitance. The insulating layer 428 also serves to reduce parasitic capacitance. The third region 444e is provided between the channel formation region 443 and the high resistance source region 444a. The fourth region 444f of the oxide semiconductor layer in contact with the insulating layer 428 is a channel formation region. The oxide layer 428 is disposed between the high-resistance drain region 443 and the high-resistance drain region 444b. The third region 444e and the fourth region 444f of the semiconductor layer can reduce the off current. do.

[0295] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 7.

[0296] (Embodiment 9) The light emitting device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (a television or a television receiver). (also called "transmitting devices"), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. .

[0297] FIG. 13A shows an example of a mobile phone 1100. The mobile phone 1100 has a housing. In addition to the display unit 1102 incorporated in the 1101, the operation buttons 1103 and the external connection port 11 04, a speaker 1105, a microphone 1106, etc.

[0298] In the mobile phone 1100 shown in FIG. 13A, information is displayed by touching a display unit 1102 with a finger or the like. A report can be input. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1102 with a finger or the like. The screen of the display unit 1102 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters, and the third is a display + input mode in which the two modes of the display mode and the input mode are mixed.

[0299] For example, when making a phone call or creating an email, the display unit 1102 can be set to the character input mode mainly for character input, and an input operation on the characters displayed on the screen can be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102. Moreover, by providing a detection device having sensors for detecting inclination such as a gyro and an acceleration sensor inside the mobile phone 1100, the orientation (vertical or horizontal) of the mobile phone 1100 can be determined, and the screen display of the display unit 1102 can be automatically switched.

[0300] Also, the switching of the screen mode is performed by touching the display unit 1102 or operating the operation button 1103 of the housing 1101. It can also be switched according to the type of image displayed on the display unit 1102. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode. In addition, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected and displayed. Preferably.

[0301] Furthermore, inside the mobile phone 1100, by providing a detection device having sensors for detecting inclination such as a gyro and an acceleration sensor, the orientation (vertical or horizontal) of the mobile phone 1100 can be determined, and the screen display of the display unit 1102 can be automatically switched. Also, the switching of the screen mode is performed by touching the display unit 1102 or operating the operation button 1103 of the housing 1101. It can also be switched according to the type of image displayed on the display unit 1102. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0302] Moreover, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected and displayed. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1102 with a finger or the like. For example, when making a phone call or creating an email, the display unit 1102 can be set to the character input mode mainly for character input, and an input operation on the characters displayed on the screen can be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102.

[0303] In addition, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected and the display ​​When there is no input by touch operation on the unit 1102 for a certain period, the screen mode may be controlled to switch from the input mode to the display mode.

[0304] The display unit 1102 can also function as an image sensor. For example, by touching the palm or finger on the display unit 11 02, it is possible to perform personal authentication by imaging palm prints, fingerprints, etc. In addition, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, it is also possible to image finger veins, palm veins, etc.

[0305] A plurality of thin film transistors 460 shown in Embodiment 1 are arranged in the display unit 1102. Since the thin film transistor 460 has light transmittance, it is effective because the incident light is not blocked by the thin film transistor 460 when a light sensor is provided in the display unit 1102. Also, when a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, it is preferable because the thin film transistor 460 does not block the light.

[0306] FIG. 13(B) is also an example of a mobile phone. The portable information terminal taking FIG. 13(B) as an example can have a plurality of functions. For example, in addition to the telephone function, it can incorporate a computer and have various data processing functions.

[0307] The portable information terminal shown in FIG. 13(B) is composed of two housings, namely, a housing 1800 and a housing 1801. The housing 1800 is provided with a display panel 1802, a speaker 1803, a microphone 1804, operation keys 1805, a pointing device 1806, a camera lens 1807, an external connection terminal 1808, etc. The housing 1801 is provided with a keyboard 1810. , it is equipped with an external memory slot 1811, etc. Also, the antenna is inside the housing 1801 built-in.

[0308] Also, the display panel 1802 is equipped with a touch panel, and in Fig. 13(B), a plurality of operation keys 1805 being displayed as video are shown by dotted lines.

[0309] In addition to the above configuration, it may also incorporate a non-contact IC chip, a small recording device, etc. .

[0310] The light-emitting device can be used for the display panel 1802, and the display direction changes appropriately according to the usage form. Also, since a camera lens 1807 is provided on the same plane as the display panel 1802 , video phone is possible. The speaker 1803 and the microphone 1804 are capable not only of voice calls but also of video phone, recording, playback, etc. Furthermore, the housing 1800 and the housing 1801 can be slid and changed from the unfolded state as shown in Fig. 13(B) to an overlapping state, enabling miniaturization suitable for portability.

[0311] The external connection terminal 1808 can be connected to various cables such as an AC adapter and a USB cable , enabling charging and data communication with a personal computer, etc. Also, by inserting a recording medium into the external memory slot 1811, it can support storage and transfer of a larger amount of data. .

[0312] In addition to the above functions, it may also be equipped with an infrared communication function, a television reception function, etc. .

[0313] Fig. 14(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in the housing 9601. The display unit 9603 can display an image. Also, here, a configuration in which the housing 9601 is supported by the stand 9605 is shown. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or by a separate remote control operation device 9610. The operation keys 9609 provided in the remote control operation device 9610 can be used to operate the channel and volume, and can also be used to operate the image displayed on the display unit 9603. Further, the remote control operation device 9610 may be provided with a display unit 9607 for displaying information output from the remote control operation device 9610.

[0314]

[0315] Note that the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a wired or wireless connection through the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers, etc.) information communication can also be performed.

[0316] In the display unit 9603, in order to arrange a plurality of thin film transistors 460 shown in the first embodiment, when the light emitting device is particularly of the bottom emission type, the aperture ratio can be increased.

[0317] FIG. 14(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in the housing 9701. The display unit 9703 can display various images, for example, images taken with a digital camera, etc. By displaying the following image data, it can function in the same way as a normal photo frame.

[0318] Since a plurality of the thin film transistors 460 shown in Embodiment 1 are arranged in the display unit 9703, when the light emitting device is particularly of the bottom emission type, the aperture ratio can be increased.

[0319] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals, terminals connectable to various cables such as a US B cable), a recording medium insertion unit, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, an image data memory stored with image data photographed by a digital camera is inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

[0320] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0321] FIG. 15 shows a portable game machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected so as to be openable and closable by a connecting portion 9893. A display unit 988 2 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891.

[0322] Since a plurality of the thin film transistors 460 shown in Embodiment 1 are arranged in the display unit 9883, when the light emitting device is particularly of the bottom emission type, the aperture ratio can be increased.

[0323] ​In addition, the portable gaming machine shown in FIG. 15 also includes a speaker unit 9884, a recording medium insertion unit 9 886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be at least a configuration including the thin film transistor disclosed in this specification, and other accessory equipment can be appropriately provided to form a configuration. The portable gaming machine shown in FIG. 15 has functions of reading programs or data recorded on a recording medium and displaying them on a display unit, and functions of wirelessly communicating with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in FIG. 15 are not limited to this, and it can have various functions.

[0324] FIG. 16 shows an example in which the light emitting device formed by applying the above embodiment is used as an indoor lighting device 3001. Since the light emitting device shown in Embodiment 2 can be made larger in area, it can be used as a large area lighting device. In addition, the light emitting device shown in Embodiment 2 above can also be used as a desktop lighting fixture 3000. Note that lighting fixtures include ceiling-fixed lighting fixtures, desktop lighting fixtures, as well as wall-mounted lighting fixtures, in-vehicle lighting, induction lamps, etc. are also included.

[0325] As described above, the light emitting devices shown in Embodiment 2 and Embodiment 3 can be arranged on the display panels of the above various electronic devices. The thin film transistor 450 is used as a driving circuit ​ used as, and using the thin film transistor 460 as a switching element of the display panel Thereby, when the light emitting device is particularly a bottom emission type, a highly reliable electronic device having a display portion with a high aperture ratio can be provided.

Explanation of Signs

[0326] 400 Substrate 402 Gate insulating layer 403 Oxide semiconductor layer 404 Oxide semiconductor layer 411 First terminal 412 Connection electrode layer 413 Protection insulating layer 414 Second terminal 415 Conductive layer 416 Electrode layer 417 Conductive layer 418 Conductive layer 421a Gate electrode layer 421b Gate electrode layer 421c Gate wiring layer 422 Source wiring layer 423 Channel formation region 424a High-resistance source region 424b High-resistance drain region 424c First region 424d Second region 424e Third region 424f Fourth region 425a Source electrode layer 425b Drain electrode layer 426a Oxide insulating layer 426b Oxide insulating layer 428 Insulating layer 429 Connection electrode layer 430 Capacitance wiring layer 431 Capacitance electrode layer 440 Thin film transistor 441 Oxide semiconductor layer 442 Connection electrode layer 443 Channel formation region 444a High-resistance source region 444b High-resistance drain region 444c First region 444d Second region 444e Third region 444f Fourth region 445a Source electrode layer 445b Drain electrode layer 446a Oxide conductive layer 446b Oxide conductive layer 447 Oxide conductive layer 448 Oxide conductive layer 449 Connection electrode layer 450 Thin film transistor 451a Gate electrode layer 451b Gate electrode layer 452 Connection electrode layer 453 Oxide semiconductor layer 454 Oxide semiconductor layer 455a Source electrode layer 455b Drain electrode layer 456 Color filter layer 457 First electrode 458 Overcoat layer 459 Partition wall 460 Thin film transistor

Claims

Claim 1 A pixel portion having a first thin film transistor on the same substrate, and a driving circuit having a second thin film transistor with a structure different from that of the first thin film transistor, The first thin film transistor has a gate electrode layer on a substrate, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, an oxide semiconductor layer overlapping the source electrode layer and the drain electrode layer on the gate insulating layer, an oxide insulating layer in contact with the oxide semiconductor layer, a connection electrode layer electrically connected to the drain electrode layer on the oxide insulating layer, a color filter layer on the oxide insulating layer, and a first electrode electrically connected to the connection electrode layer on the color filter layer. The first electrode has a light emitting layer thereon, and a second electrode on the light emitting layer, The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulating layer, and the first electrode of the first thin film transistor are a light emitting device having translucency.

Images