Semiconductor device

Abstract

To provide a semiconductor device capable of optimizing a PCB layout.SOLUTION: A semiconductor device 1a includes a package 100 having a rectangular shape in plan view, the package 100 having a first side 101, a second side 102, a third side 103, and a fourth side 104, a power supply terminal PVIN1 / 2 provided on the first side 101 or the second side 102, a power ground terminal PGND1 / 2 provided on the first side 101 or the second side 102 or the fourth side 104, a switch output terminal SW1 / 2 provided on the second side 102, an upper switch 11H connected between the power supply terminal PVIN1 / 2 and the switch output terminal SW1 / 2, and a lower switch 11L connected between the switch output terminal SW1 / 2 and the power ground terminal PGND1 / 2. The upper switch 11H, the lower switch 11L, the power supply terminal PVIN1 / 2, and the power ground terminal PGND1 / 2 are provided for each of a plurality of channels.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The invention disclosed in this specification relates to a semiconductor device.

Background Art

[0002] Conventionally, various proposals have been made regarding the pin arrangement of semiconductor devices (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in order to optimize the PCB [printed circuit board] layout, there was still room for further consideration regarding the pin arrangement of the semiconductor device.

[0005] In view of the above problems found by the inventors of the present application, the invention disclosed in this specification aims to provide a semiconductor device capable of optimizing the PCB layout.

Means for Solving the Problems

[0006] The semiconductor device disclosed in this specification has a rectangular package in plan view having a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side; a power supply terminal provided on the first side, or the third side or the fourth side; a power ground terminal provided on the second side, or the third side or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; and a lower switch connected between the switch output terminal and the power ground terminal (first configuration).

[0007] In addition, in the semiconductor device having the first configuration, the upper switch, the lower switch, and the switch output terminal may each be provided for each of a plurality of channels (second configuration).

[0008] Further, in the semiconductor device having the second configuration, the switch output terminals provided for each of the plurality of channels may be arranged symmetrically between at least two channels (third configuration).

[0009] Also, in the semiconductor device having the second or third configuration, the power supply terminal and the power ground terminal may each be provided for each of the plurality of channels (fourth configuration).

[0010] Furthermore, in the semiconductor device having the fourth configuration, the power supply terminals provided for each of the plurality of channels may be arranged symmetrically between at least two channels (fifth configuration).

[0011] Also, in the semiconductor device having the fourth or fifth configuration, the power ground terminals provided for each of the plurality of channels may be arranged symmetrically between at least two channels (sixth configuration).

[0012] Alternatively, in the semiconductor device having the above-described second or third configuration, at least one of the power supply terminal and the power ground terminal may be shared by the plurality of channels (seventh configuration).

[0013] Further, the semiconductor device having any of the above-described first to seventh configurations may have a configuration (eighth configuration) in which a heat dissipation pad exposed on the top surface of the package is further provided.

[0014] Further, in the semiconductor device having any of the above-described first to eighth configurations, the thermal resistance from the semiconductor chip sealed in the package to the top surface may be smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package (ninth configuration).

[0015] Further, in the semiconductor device having any of the above-described first to ninth configurations, the upper switch and the lower switch may be arranged in a biased manner closer to the second side in a plan view (tenth configuration).

[0016] Further, in the semiconductor device having any of the above-described first to tenth configurations, the upper switch and the lower switch may be arranged in a vertical row along a second direction orthogonal to a first direction in which the first side and the second side extend in a plan view (eleventh configuration).

[0017] Further, in the semiconductor device having any of the above-described first to eleventh configurations, the lower switch may have a larger element size than the upper switch (twelfth configuration).

[0018] Further, in the semiconductor device having any of the above-described first to twelfth configurations, both the power supply terminal and the power ground terminal are provided on the third side or the fourth side, and the power ground terminal is arranged closer to the second side than the power supply terminal (thirteenth configuration).

[0019] Further, the semiconductor device having any one of the above-described first to thirteenth configurations may be configured (a fourteenth configuration) to include an output feedback control unit that drives the upper switch and the lower switch so that the output current supplied from the switch output terminal to the load matches a predetermined target value.

[0020] Further, in the semiconductor device having the above-described fourteenth configuration, the output feedback control unit may be configured (a fifteenth configuration) to perform output feedback control in a bottom detection on-time fixed method.

[0021] Also, the module disclosed in this specification is configured (a sixteenth configuration) to include a printed circuit board, a semiconductor device having any one of the above-described first to fifteenth configurations, and a load that receives supply of an output current from the semiconductor device.

[0022] In the module having the above-described sixteenth configuration, the semiconductor device may be mounted on a first main surface of the printed circuit board, and a power supply line connected to the power supply terminal, a power ground line connected to the power ground terminal, and a switch output line connected to the switch output terminal may be laid on a second main surface of the printed circuit board (a seventeenth configuration).

[0023] Note that, in the module having the above-described seventeenth configuration, the main trunk portions of the power supply line and the power ground line may be configured (an eighteenth configuration) to be laid in parallel along a first direction in which the first side and the second side extend in a plan view.

[0024] Further, in the module having the above-described eighteenth configuration, a plurality of the semiconductor devices may be mounted on the first main surface along the first direction (a nineteenth configuration).

[0025] Also, in the module having any one of the configurations of the 17th to 19th ones described above, at least one of the power supply line and the power ground line may be laid so as to overlap with the semiconductor device in a plan view (20th configuration).

[0026] Also, in the module having any one of the configurations of the 17th to 20th ones described above, a bypass capacitor may be connected between the power supply line and the power ground line on the second main surface (21st configuration).

[0027] Also, in the module having the 21st configuration described above, the bypass capacitor may be mounted so as to overlap with the semiconductor device in a plan view (22nd configuration).

[0028] Also, in the module having the 21st or 22nd configuration described above, the bypass capacitor may be mounted at a position where a closed loop formed with the upper switch and the lower switch is minimized (23rd configuration).

[0029] Also, in the module having any one of the configurations of the 16th to 23rd ones described above, the power supply terminal, the switch output terminal, the power ground terminal provided for each of the plurality of channels, and discrete components externally attached thereto may be symmetrically arranged between at least two channels (24th configuration).

[0030] Also, the module having any one of the configurations of the 16th to 24th ones described above may further have a heat sink attached to the semiconductor device (25th configuration).

[0031] Also, in the module having the 16th configuration described above, at least a part of the semiconductor device and discrete components externally attached thereto may all be mounted on the same surface of the printed circuit board (26th configuration).

[0032] Further, the module having the 26th configuration may further have a heat sink that is commonly attached to both the semiconductor device and the discrete components mounted on the same surface of the printed circuit board (27th configuration).

[0033] Further, the module having any one of the 16th to 27th configurations may preferably have a configuration (28th configuration) in which a booster circuit that generates a boosted voltage from the battery voltage and supplies it to the power supply terminal is further provided.

[0034] Further, in the module having any one of the 16th to 28th configurations, the load may preferably be a light-emitting diode (29th configuration).

Advantages of the Invention

[0035] According to the invention disclosed in this specification, it becomes possible to provide a semiconductor device capable of optimizing the PCB layout.

Brief Description of the Drawings

[0036]

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Mode for Carrying Out the Invention

[0037] <LED [light emitting diode] driver IC> FIG. 1 is a diagram showing a configuration example of an LED lamp module to which a 2-channel LED driver IC is applied. The LED lamp module X of this configuration example includes a 2-channel LED driver IC 1a, a boost circuit 2, an MCU [micro control unit] 3, light emitting diodes LED1 and LED2 (in this figure, an LED string in which a plurality of light emitting diode elements are connected in series), and various discrete components (capacitors C1 and C2, capacitors C11 to C13, capacitors C21 to C23, inductors L1 and L2, resistors R1 and R2, and sense resistors Rs1 and Rs2).

[0038] The LED driver IC 1a is a semiconductor device that steps down the boost voltage Vbst to supply power to the light emitting diodes LED1 and LED2. The LED driver IC 1a has a plurality of external terminals (VIN pin, VREG5 pin, GND pin, TON pin, SO pin, CSB pin, SCK pin, SI pin, PVIN1 pin, BOOT1 pin, SW1 pin, PGND1 pin, SNSP1 pin, SNSN1 pin, PVIN2 pin, BOOT2 pin, SW2 pin, PGND2 pin, SNSP2 pin, and SNSN2 pin, etc.) as means for establishing electrical connection with the outside of the IC.

[0039] The VIN pin is the input voltage supply terminal of the signal system. The VREG5 pin is the output terminal of the internal regulator. The GND pin is the ground terminal of the signal system. The TON pin is the resistor connection terminal for on-time setting. The SO pin is the serial data output terminal for SPI [serial peripheral interface] communication. The CSB pin is the chip select input terminal for SPI communication. The SCK pin is the serial clock input terminal for SPI communication. The SI pin is the serial data input terminal for SPI communication.

[0040] The PVIN1 pin and the PVIN2 pin are respectively the input voltage supply terminals (= power supply terminals) of the power system. The BOOT1 pin and the BOOT2 pin are respectively the bootstrap capacitor connection terminals for upper-side gate drive. The SW1 pin and the SW2 pin are respectively the switch output terminals. The PGND1 pin and the PGND2 pin are respectively the ground terminals (= power ground terminals) of the power system. The SNSP1 pin and the SNSP2 pin are respectively the output current sense input terminals (+). The SNSN1 pin and the SNSN2 pin are respectively the output current sense input terminals (-).

[0041] Note that the external terminal group with "1" appended to the symbol end (PVIN1, SW1, PGND1, SNSP1, and SNSN1) are all for the first channel. On the other hand, the external terminal group with "2" appended to the symbol end (PVIN2, SW2, PGND2, SNSP2, and SNSN2) are all for the second channel.

[0042] The VIN pin is connected to the applied end of the battery voltage +B (e.g., 13V). The GND pin is connected to the ground terminal. A capacitor C1 (= input smoothing capacitor) is connected between the VIN pin and the GND pin. A capacitor C2 (= output smoothing capacitor of the internal regulator) is connected between the VREG5 pin and the GND pin. A resistor R1 (= on-time setting resistor) is connected between the TON pin and the ground terminal. A resistor R2 (= pull-up resistor) is connected between the SO pin and the applied end of the power supply voltage Vcc (e.g., 5V). The SO pin, the CSB pin, the SCK pin, and the SI pin are each connected to the MCU3.

[0043] The PVIN1 pin is connected to the applied end of the boost voltage Vbst (e.g., 65V). The SW1 pin is connected to the first end of the inductor L1. The second end of the inductor L1 is connected to the first end of the sense resistor Rs1. The second end of the sense resistor Rs1 is connected to the anode of the light-emitting diode LED1. The cathode of the light-emitting diode LED1 is connected to the ground terminal. A capacitor C11 (= bypass capacitor) is connected between the PVIN1 pin and the PGND1 pin. A capacitor C12 (= bootstrap capacitor) is connected between the BOOT1 pin and the SW1 pin. A capacitor C13 (= output smoothing capacitor) is connected between the anode of the light-emitting diode LED1 and the ground terminal. Both ends of the sense resistor Rs1 are respectively connected to the SNSP1 pin and the SNSN1 pin.

[0044] The PVIN2 pin is connected to the application end of the boost voltage Vbst. The SW2 pin is connected to the first end of the inductor L2. The second end of the inductor L2 is connected to the first end of the sense resistor Rs2. The second end of the sense resistor Rs2 is connected to the anode of the light-emitting diode LED2. The cathode of the light-emitting diode LED2 is connected to the ground terminal. A capacitor C21 (= bypass capacitor) is connected between the PVIN2 pin and the PGND2 pin. A capacitor C22 (= bootstrap capacitor) is connected between the BOOT2 pin and the SW2 pin. A capacitor C23 (= output smoothing capacitor) is connected between the anode of the light-emitting diode LED2 and the ground terminal. Both ends of the sense resistor Rs2 are respectively connected to the SNSP2 pin and the SNSN2 pin.

[0045] The boost circuit 2 is a DC / DC converter that boosts the battery voltage +B to generate the boost voltage Vbst.

[0046] The MCU3 operates by receiving the supply of the power supply voltage Vcc and performs SPI communication with the LED driver IC1a.

[0047] Figure 2 is a diagram showing a configuration example of an LED lamp module to which a 3-channel LED driver IC is applied. The LED lamp module X of this configuration example has a 3-channel LED driver IC1b instead of the 2-channel LED driver IC1a while based on the above-mentioned Figure 1.

[0048] Note that with the 3-channel configuration of the LED driver IC1b, in addition to the above-mentioned external terminals, an external terminal group for the third channel (PVIN3 pin, BOOT3 pin, SW3 pin, PGND3 pin, SNSP3 pin, and SNSN3 pin) is provided.

[0049] Also, in addition to the above-mentioned components, the LED lamp module X is provided with a light-emitting diode LED3 for the third channel and various discrete components (capacitors C31 to C33, inductor L3, and sense resistor Rs3).

[0050] The PVIN3 pin is the input voltage supply terminal of the power system (= power supply terminal). The BOOT3 pin is the bootstrap capacitor connection terminal for the upper gate drive. The SW3 pin is the switch output terminal. The PGND3 pin is the ground terminal of the power system (= power ground terminal). The SNSP3 pin is the output current sense input terminal (+). The SNSN3 pin is the output current sense input terminal (-).

[0051] The PVIN3 pin is connected to the application end of the boost voltage Vbst. The SW3 pin is connected to the first end of the inductor L3. The second end of the inductor L3 is connected to the first end of the sense resistor Rs3. The second end of the sense resistor Rs3 is connected to the anode of the light-emitting diode LED3. The cathode of the light-emitting diode LED3 is connected to the ground terminal. A capacitor C31 (= bypass capacitor) is connected between the PVIN3 pin and the PGND3 pin. A capacitor C32 (= bootstrap capacitor) is connected between the BOOT3 pin and the SW3 pin. A capacitor C33 (= output smoothing capacitor) is connected between the anode of the light-emitting diode LED3 and the ground terminal. Both ends of the sense resistor Rs3 are connected to the SNSP3 pin and the SNSN3 pin respectively.

[0052] Note that in the following, when there is no need to distinguish between the LED driver ICs 1a and 1b, they may simply be abbreviated as the LED driver IC1.

[0053] <Circuit Configuration> FIG. 3 is a diagram showing the circuit configuration (particularly around the output stage) of the LED driver IC1. The LED driver IC1 in this configuration example integrates, as means for driving the light-emitting diode LED* of the *-th channel (where *=1, 2, or 3), an upper switch 11H, a lower switch 11L, an upper driver 12H, a lower driver 12L, a controller 13, an on-time setting unit 14, a slope voltage generation unit 15, a sense amplifier 16, an error amplifier 17, a comparator 18, and a bootstrap diode D1. Of course, other components (such as various protection circuits) may be integrated into the LED driver IC1.

[0054] The upper switch 11H is connected between the PVIN pin and the SW* pin and is turned on / off in response to the upper gate signal GH. As the upper switch 11H, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor] or the like can be preferably used. In that case, the upper switch 11H turns on when GH = H (= BOOT*) and turns off when GH = L (= SW*). It is also possible to use a PMOSFET [P-channel type MOSFET] instead of the NMOSFET as the upper switch 11H. In that case, the bootstrap diode D1, the capacitor C*2, and the BOOT* pin become unnecessary.

[0055] The lower switch 11L is connected between the SW* pin and the PGND* pin and is turned on / off in response to the lower gate signal GL. As the lower switch 11L, an NMOSFET or the like can be preferably used. In that case, the lower switch 11L turns on when GL = H (= VDRV5) and turns off when GL = L (= PGND*).

[0056] The upper switch 11H and the lower switch 11L connected in this way form a half-bridge output stage that outputs a rectangular-wave switch voltage Vsw from the SW* pin. In this figure, a half-bridge output stage of the synchronous rectification method is shown. However, when the diode rectification method is adopted, a diode may be used as the lower switch 11L.

[0057] The upper driver 12H generates an upper gate signal GH based on the upper control signal SH input from the controller 13. Note that the high level of the upper gate signal GH is the terminal voltage of the BOOT* pin (≈Vsw + VDRV5). On the other hand, the low level of the upper gate signal GH is the terminal voltage of the SW* pin (≈Vsw).

[0058] The lower driver 12L generates a lower gate signal GL based on the lower control signal SL input from the controller 13. Note that the high level of the lower gate signal GL is the constant voltage VDRV5 (the internal power supply voltage VREG or a separate external input voltage). On the other hand, the low level of the lower gate signal GL is the terminal voltage of the PGND* pin (ground voltage).

[0059] The controller 13 includes, for example, an RS flip-flop that receives inputs of a set signal SET and a reset signal RST, and generates an upper control signal SH and a lower control signal SL so as to turn on and off the upper switch 11H and the lower switch 11L complementarily.

[0060] More specifically, the controller 13 generates the upper control signal SH and the lower control signal SL such that the upper switch 11H is turned on and the lower switch 11L is turned off at the rising timing of the set signal SET, while the upper switch 11H is turned off and the lower switch 11L is turned on at the rising timing of the reset signal RST.

[0061] However, the term "complementary" in this specification should be understood in a broad sense, including not only the case where the on / off states of the upper switch 11H and the lower switch 11L are completely reversed, but also the case where a simultaneous off period (so-called dead time) is provided to prevent through current.

[0062] The on-time setting unit 14 raises the reset signal RST to a high level when a predetermined on-time Ton has elapsed from the rising timing of the set signal SET (and thus the on-timing of the upper switch 11H). The on-time setting unit 14 has a function of arbitrarily setting the on-time Ton according to the resistance value of the resistor R1 connected to the TON pin. The on-time setting unit 14 also has a function of varying the on-time Ton so as to suppress the variation of the switching frequency Fsw based on the terminal voltages of the PVIN pin and the SNSN pin respectively.

[0063] The slope voltage generation unit 15 detects the inductor current IL flowing during the on-period of the lower switch 11L and generates a slope voltage Vslp including information on the inductor current IL. The slope voltage Vslp increases as the inductor current IL flowing during the on-period of the lower switch 11L increases, and decreases as the inductor current IL decreases.

[0064] The sense amplifier 16 amplifies the voltage between the SNSP* pin and the SNSN* pin (= the voltage across the sense resistor Rs*) to generate a sense voltage Vs. The sense voltage Vs increases as the output current ILED (= average inductor current IL_ave) flowing through the sense resistor Rs* increases, and decreases as the output current ILED decreases.

[0065] Error amplifier 17 outputs a current according to the difference between the reference voltage VISET (= analog dimming voltage) input to the non-inverting input terminal (+) and the sense voltage Vs (more precisely, the sum voltage of the offset voltage Vofs and the sense voltage Vs) input to the inverting input terminal (-), and generates a control voltage Vc by charging and discharging a capacitor (not shown). Note that the control voltage Vc rises when VISET > Vs and falls when VISET < Vs.

[0066] Comparator 18 generates a set signal SET by comparing the slope voltage Vslp input to the inverting input terminal (-) with the control voltage Vc input to the non-inverting input terminal (+). The set signal SET becomes low level when Vc < Vslp and high level when Vc > Vslp. Therefore, the lower the control voltage Vc, the later the rising timing of the set signal SET (and thus the on-timing of the upper switch 11H), and conversely, the higher the control voltage Vc, the earlier the rising timing of the set signal SET.

[0067] Among the above components, the upper driver 12H, the lower driver 12L, the controller 13, the on-time setting unit 14, the slope voltage generation unit 15, the sense amplifier 16, the error amplifier 17, and the comparator 18 function as an output feedback control unit of the bottom detection on-time fixed method, and the upper switch 11H and the lower switch 11L are driven complementarily so that the output current ILED supplied from the switch output terminal SW* to the light-emitting diode LED* matches a predetermined target value.

[0068] <Output Feedback Control> Figure 4 is a diagram showing the output feedback control of the bottom detection on-time fixed method, and the inductor current IL and the switch voltage Vsw are depicted in order from the top.

[0069] While the upper switch 11H is off and the lower switch 11L is on, the switch voltage Vsw becomes a low level (= the negative voltage -VDSW generated between the drain and source of the lower switch 11L). At this time, the inductor current IL flowing from the PGND* pin through the lower switch 11L to the SW* pin decreases as the energy of the inductor L* is released.

[0070] Then, when the inductor current IL decreases to the bottom value IL_btm corresponding to the control voltage Vc, Vc > Vslp, and the set signal SET rises to a high level. As a result, the upper switch 11H turns on and the lower switch 11L turns off. At this time, since the switch voltage Vsw becomes a high level (≒ PVIN), the inductor current IL flowing from the PVIN pin through the upper switch 11H to the SW* pin increases.

[0071] After that, when a predetermined on-time Ton elapses, the reset signal RST rises to a high level, the upper switch 11H turns off and the lower switch 11L turns on, so the inductor current IL changes from increasing to decreasing again. As a result, the inductor current IL becomes a ripple waveform that repeats increasing and decreasing between the peak value IL_pk and the bottom value IL_btm.

[0072] Here, the bottom value IL_btm of the inductor current IL varies according to the difference between the sense voltage Vs (corresponding to the average inductor current IL_ave) and the reference voltage VISET (corresponding to the target value of the average inductor current IL_ave). Also, the ripple amplitude ΔIL (= IL_pk - IL_btm) of the inductor current IL is determined according to the on-time Ton.

[0073] Therefore, by repeating the above series of operations, in the LED driver IC1, output feedback control of the bottom detection on-time fixed method is performed so that the average inductor current IL_ave (and thus the output current ILED) matches a predetermined target value.

[0074] However, the output feedback control method of the LED driver IC1 is not necessarily limited to the above. For example, instead of the bottom detection on-time fixed method, a peak detection off-time fixed method may be adopted, or a hysteresis window method may be adopted. Alternatively, a PWM [pulse width modulation] control method can also be adopted.

[0075] <Power loss> FIG. 5 is a diagram for evaluating the power loss of the LED driver IC1. Note that the switch current Isw and the switch voltage Vsw are depicted in the upper part of this figure, and the power loss Psw (= Isw × Vsw) is depicted in the lower part of this figure.

[0076] As shown in this figure, in the LED driver IC1, when driving the upper switch 11H and the lower switch 11L complementarily, switching loss Psw_loss (= Vbst × ILED / 2 + (Tsw_on + Tsw_off) × Fsw) and conduction loss Pcon_loss (= ILED × ILED × Fsw × (RonH × Ton + RonL × Toff)) occur.

[0077] In particular, when the boost voltage Vbst is several tens of volts (for example, 65V) and the switching frequency Fsw is several MHz (for example, 2.2MHz), the above-described power loss (= Psw_loss + Pcon_loss) of the LED driver IC1 becomes large, and consequently, the heat generation of the LED driver IC1 becomes large. Therefore, high heat dissipation is required for the package of the LED driver IC1.

[0078] <Package> FIGS. 6 and 7 are respectively a three-sided view (planar, front, side) and a perspective view showing the package of the LED driver IC1. The package 100 illustrated here is a 48-pin HTSSOP [heat-sink thin-shrink small outline package], and is formed in a rectangular shape (rectangular shape in plan view) having a first side 101, a second side 102, a third side 103, and a fourth side 104.

[0079] The first side 101 corresponds to the first long side (e.g., 12.5 mm), and a total of 24 external terminals are provided. In FIG. 6, pins 1 to 24 are sequentially arranged from the left end to the right end of the first side 101.

[0080] The second side 102 corresponds to the second long side parallel to the first side 101. Similar to the first side 101, a total of 24 external terminals are provided. In FIG. 6, pins 25 to 48 are sequentially arranged from the right end to the left end of the second side 102.

[0081] The third side 103 corresponds to the first short side (e.g., 6.1 mm) orthogonal to the first side 101 and the second side 102. Note that no external terminal is provided on the third side 103.

[0082] The fourth side 104 corresponds to the second short side parallel to the third side 103 and orthogonal to the first side 102 and the second side 102. Note that no external terminal is provided on the fourth side 104 either.

[0083] Note that each of the 48 external terminals is led out from the long side surface of the package 100 (corresponding to the first side 101 and the second side 102 in plan view) toward the outside. Also, each external terminal has a shape (so-called gullwing shape) that is bent midway so as to form a step between the root portion and the tip portion in the side view of the package 100.

[0084] Also, a heat dissipation pad 111 and a 1-pin mark 112 are formed on the top surface 110 of the package 100 (corresponding to the first main surface that does not face the printed circuit board). On the other hand, nothing is formed on the bottom surface 120 of the package 100 (corresponding to the second main surface that faces the printed circuit board).

[0085] The heat dissipation pad 111 exposes the back surface of the island on which the semiconductor chip is mounted to the top surface 110 of the package 100. Regarding the size of the heat dissipation pad 111, the length of the long side (= the length of one side parallel to the long side of the package 100) may be about 0.4 times that of the first side 101 and the second side 102 (for example, 5 mm), and the length of the short side (= the length of one side parallel to the short side of the package 100) may be about 0.7 times that of the third side 103 and the fourth side 104 (for example, 4.2 mm).

[0086] By providing such a heat dissipation pad 111, it becomes possible to enhance the heat dissipation performance of the package 100. In particular, if the heat dissipation pad 111 is exposed on the top surface 110 of the package 100 instead of the bottom surface 120 of the package 100, a heat sink can be attached to the heat dissipation pad 111, so that it becomes possible to further enhance the heat dissipation performance of the package 100.

[0087] FIG. 8 is a perspective view showing an example of a heat sink attached to the LED driver IC1. The heat sink 200 of this configuration example has a base portion 210 (for example, 60 mm × 50 mm) and a plurality of heat dissipation fins 220 (for example, 50 mm × 50 mm).

[0088] A plurality of heat dissipation fins 220 are provided on the top surface of the base portion 210 (corresponding to the first main surface that does not face the package 100 of the LED driver IC1). By adopting such a configuration, the surface area of the heat sink 200 can be increased, so that it becomes possible to enhance the heat dissipation performance of the package 100. Note that the base portion 210 and the heat dissipation fins 220 may be integrally formed or separately formed and assembled.

[0089] When attaching the heat sink 200 to the LED driver IC1, heat dissipation grease 230 may be applied to the bottom surface of the base portion 210 (corresponding to the second main surface that faces the package 100 of the LED driver IC1) and attached to the package 100 of the LED driver IC1 (particularly the heat dissipation pad 111).

[0090] FIG. 9 is a schematic vertical cross-sectional view for evaluating the thermal resistance of the LED driver IC1. As shown in this figure, in the LED driver IC1 where the heat dissipation pad 111 is exposed on the top surface 110 of the package 100, the thermal resistance θ1 from the semiconductor chip 130 sealed in the package 100 to the top surface 110 is extremely small compared to the thermal resistance θ2 from the semiconductor chip 130 to the bottom surface 120 (θ1 << θ2, for example, θ1 = 3 °C / W, θ2 = 100 °C / W). Therefore, since heat can be quickly dissipated from the heat dissipation pad 111 (and further from the heat sink 200 attached thereto), it is possible to increase the maximum allowable loss of the LED driver IC1.

[0091] <Pin arrangement> Next, a new pin arrangement that can optimize the PCB layout for the LED driver IC1 described so far is proposed.

[0092] FIG. 10A is a plan view showing the pin arrangement (first example) of the LED driver IC1a (2ch). Note that the dashed lines in the figure are auxiliary lines for schematically showing the connection relationship between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), and the switch output terminals (SW1, SW2), and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0093] In the following description, in the plan view of the package 100, the first direction in which the first side 101 and the second side 102 extend is called the x direction (the vertical direction of the paper surface in this figure), and the second direction orthogonal to this (= the direction in which the third side 103 and the fourth side 104 extend) is called the y direction (the left - right direction of the paper surface in this figure).

[0094] Pins 1 to 3 are assigned to the power supply terminal (PVIN1) of the first channel. Pins 5 to 7 and 9 are assigned to the external terminal group (SI, SCK, CSB, SO) for SPI communication. Pins 11 to 13 and 15 are assigned to the external terminal group (GND, TON, VIN, VREG5) of the signal system. Pins 22 to 24 are assigned to the power supply terminal (PVIN2) of the second channel.

[0095] Pins 25 and 26 are assigned to the output current sense input terminals (SNSN2, SNSP2) of the second channel. Pin 28 is assigned to the bootstrap capacitor connection terminal (BOOT2) of the second channel. Pins 30 to 32 are assigned to the switch output terminals (SW2) of the second channel. Pins 34 to 36 are assigned to the power ground terminal (PGND2) of the second channel.

[0096] Pins 37 to 39 are assigned to the power ground terminal (PGND1) of the first channel. Pins 41 to 43 are assigned to the switch output terminals (SW1) of the first channel. Pin 45 is assigned to the bootstrap capacitor connection terminal (BOOT1) of the first channel. Pins 47 and 48 are assigned to the output current sense input terminals (SNSN1, SNSP1) of the first channel.

[0097] Thus, in the LED driver IC1a of this configuration example, the power supply terminals (PVIN1, PVIN2) are provided on the first side 101 (the left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1, PGND2) and the switch output terminals (SW1, SW2) are provided on the second side 102 (the right side in this figure) of the package 100.

[0098] Figure 10B is a plan view showing the pin arrangement (second example) of the LED driver IC1a (2 channels). The broken lines in the figure are auxiliary lines for schematically showing the connection relationships between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), and the switch output terminals (SW1, SW2), and the upper switch 11H and the lower switch 11L, and are different from the actual wiring pattern and the element formation pattern.

[0099] The output current sense input terminals (SNSN1, SNSP1) of the first channel are assigned to pins 1 and 2. The power ground terminal (PGND1) of the first channel is assigned to pins 3, 4, and 15. The switch output terminal (SW1) of the first channel is assigned to pins 6 and 7. The bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned to pin 8.

[0100] The power ground terminal (PGND2) of the second channel is assigned to pins 16, 21, and 22. The bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned to pin 17. The switch output terminals (SW2) of the second channel are assigned to pins 18 and 19. The output current sense input terminals (SNSP2, SNSN2) of the second channel are assigned to pins 23 and 24.

[0101] The power supply terminal (PVIN2) of the second channel is assigned to pins 25 and 33. The power supply terminal (PVIN1) of the first channel is assigned to pins 34 and 48.

[0102] The external terminal group for the signal system (VIN, TON, 5VREG, and GND) is assigned to pins 36 to 39. The external terminal group for SPI communication (SI, SCK, CSB, SO) is assigned to pins 41 to 43 and 45.

[0103] As can be seen from FIGS. 10A and 10B, various variations can be considered for the pin arrangement of the LED driver IC1a (2ch) as long as it does not deviate from the basic concept of providing the power supply terminals (PVIN1, PVIN2) on the first side 101 (the left side in this figure) of the package 100 and providing the power ground terminals (PGND1, PGND2) and the switch output terminals (SW1, SW2) on the second side 102 (the right side in this figure) of the package 100.

[0104] FIG. 11A is a plan view showing the pin arrangement (first example) of the LED driver IC1b (3ch). The broken lines in the figure are auxiliary lines for schematically showing the connection relationships between the power supply terminals (PVIN1 to PVIN3), the power ground terminals (PGND1 to PGND3), the switch output terminals (SW1 to SW3), the upper switch 11H, and the lower switch 11L, and are different from the actual wiring pattern and the element formation pattern.

[0105] The power supply terminal (PVIN1) of the first channel is assigned to pins 1 and 2. The external terminal group (SI, SCK, CSB, and SO) for SPI communication is assigned to pins 4 to 6 and 8. The external terminal group (VREG5, GND, TON, VIN5) of the signal system is assigned to pins 10 to 13. The power supply terminal (PVIN2) of the second channel is assigned to pins 14 and 15. The power supply terminal (PVIN3) of the third channel is assigned to pins 23 and 24.

[0106] The switch output terminal (SW3) of the third channel is assigned to pins 25 and 26. The bootstrap capacitor connection terminal (BOOT3) of the third channel is assigned to pin 27. The power ground terminals (PGND3) of the third channel are assigned to pins 28 and 29. The output current sense input terminals (SNSP3, SNSN3) of the third channel are assigned to pins 30 and 31.

[0107] To pins 34 and 35, the switch output terminal (SW2) of the second channel is assigned. To pin 36, the bootstrap capacitor connection terminal (BOOT2) of the second channel is assigned. To pins 37 and 38, the power ground terminal (PGND2) of the second channel is assigned. To pins 39 and 40, the output current sense input terminals (SNSP2, SNSN2) of the second channel are assigned.

[0108] To pins 42 and 43, the output current sense input terminals (SNSN1, SNSP1) of the first channel are assigned. To pins 44 and 45, the power ground terminal (PGND1) of the first channel is assigned. To pin 46, the bootstrap capacitor connection terminal (BOOT1) of the first channel is assigned. To pins 47 and 48, the switch output terminal (SW1) of the first channel is assigned.

[0109] Thus, in the LED driver IC1b of this configuration example, the power supply terminals (PVIN1~PVIN3) are provided on the first side 101 (the left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1~PGND3) and the switch output terminals (SW1~SW3) are provided on the second side 102 (the right side in this figure) of the package 100.

[0110] FIG. 11B is a plan view showing the pin arrangement (second example) of the LED driver IC1b (3ch). Note that the broken lines in the figure are auxiliary lines for schematically showing the connection relationships between the power supply terminals (PVIN1, PVIN2), the power ground terminals (PGND1, PGND2), the switch output terminals (SW1~SW3), the upper switch 11H, and the lower switch 11L, and are different from the actual wiring pattern and element formation pattern.

[0111] Pins 1 and 2 are assigned the output current sense input terminals (SNSN1, SNSP1) of the first channel. Pins 3 and 4 are assigned the power ground terminal PGND1 of the first channel. Pins 6 and 7 are assigned the switch output terminals (SW1) of the first channel. Pin 8 is assigned the bootstrap capacitor connection terminal (BOOT1) of the first channel.

[0112] Pin 10 is assigned the bootstrap capacitor connection terminal (BOOT3) of the third channel. Pins 11 and 12 are assigned the switch output terminals (SW3) of the third channel. Pins 13 and 14 are assigned the output current sense input terminals (SNSP3, SNSN3) of the third channel. Pins 15 and 16 are assigned the power ground terminal PGND3 of the third channel.

[0113] Pin 17 is assigned the bootstrap capacitor connection terminal (BOOT2) of the second channel. Pins 18 and 19 are assigned the switch output terminals (SW2) of the second channel. Pins 21 and 22 are assigned the power ground terminal (PGND2) of the second channel. Pins 23 and 24 are assigned the output current sense input terminals (SNSP2, SNSN2) of the second channel.

[0114] Pin 25 is assigned the power supply terminal (PVIN2) of the second channel. Pins 33 and 34 are assigned the power supply terminal (PVIN3) of the third channel. Pin 48 is assigned the power supply terminal (PVIN1) of the first channel.

[0115] Pins 36 to 39 are assigned the external terminal group (VIN, TON, 5VREG and GND) of the signal system. Pins 41 to 43 and 45 are assigned the external terminal group (SI, SCK, CSB, SO) for SPI communication.

[0116] As can be seen from FIGS. 11A and 11B, as long as it does not deviate from the basic concept of providing the power supply terminals (PVIN1 to PVIN3) on the first side 101 (the left side in this figure) of the package 100 and providing the power ground terminals (PGND1 to PGND3) and the switch output terminals (SW1 to SW3) on the second side 102 (the right side in this figure) of the package 100, various variations can be considered for the pin arrangement of the LED driver IC1b (3ch).

[0117] <Internal Structure> FIG. 12 is a bottom perspective view showing the internal structure of the LED driver IC1a (2ch) shown in FIG. 10A (= a view of the package 100 seen through from the bottom surface 120). Therefore, in this figure, contrary to the previous FIG. 10A, the first side 101 is the right side and the second side 102 is the left side.

[0118] The semiconductor chip 130 in which the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel, and the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are integrated respectively is die-bonded to an island 140 having a rectangular shape in plan view. The island 140 is supported inside the package 100 by a support frame 151 extending toward the third side 103 and a support frame 152 extending toward the fourth side 104. Also, the back surface of the island 140 is exposed to the top surface 110 of the package 100 as the previous heat dissipation pad 111.

[0119] Wires W11 are respectively stretched between the drain pad of the upper switch 11H (ch1) and the three PVIN1 pins. Wires W12 are respectively stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the three SW1 pins. Wires W13 are respectively stretched between the source pad of the lower switch 11L (ch1) and the three PGND1 pins.

[0120] Wires W21 are respectively stretched between the drain pads of the upper switch 11H (ch2) and the three PVIN2 pins. Wires W22 are respectively stretched between the source pads of the upper switch 11H (ch2) and the drain pads of the lower switch 11L (ch2) and the three SW2 pins. Wires W23 are respectively stretched between the source pads of the lower switch 11L (ch2) and the three PGND2 pins.

[0121] Note that the lower switches 11L (ch1 / ch2) have a larger element size than the upper switches 11H (ch1 / ch2). According to such an element design, it is possible to increase the current capacity of the lower switches 11L (ch1 / ch2) compared to the current capacity of the upper switches 11H (ch1 / ch2). For example, when it is desired to maintain a constant output power, the higher the output voltage VLED, the smaller the output current ILED needs to be, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. That is, since it is necessary to flow a larger output current ILED as the on-duty of the half-bridge output stage is lower, the above element design is effective.

[0122] Also, the upper switch 11H (ch1) and the lower switch 11L (ch1), as well as the upper switch 11H (ch2) and the lower switch 11L (ch2), are respectively arranged in a vertical column in the order shown along the y-direction orthogonal to the first side 101 in a plan view of the semiconductor chip 130.

[0123] Also, the switch formation regions where the upper switches 11H (ch1 / ch2) and the lower switches 11L (ch1 / ch2) are formed are unevenly distributed near the second side 102 of the package 100 in a plan view of the semiconductor chip 130.

[0124] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are arranged near the third side 103 of the package 100 in a plan view of the semiconductor chip 130 so that their distances from the external terminal groups (PVIN1, PGND1, SW1) of the first channel are as close as possible.

[0125] On one hand, the upper switch 11H(ch2) and the lower switch 11L(ch2) of the second channel are respectively arranged closer to the fourth side 104 of the package 100 in the plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN2, PGND, SW2) of the second channel are as close as possible.

[0126] By adopting such an element layout, the lengths of the wires W11 to W13 and the wires W21 to W23 can be minimized, so that the respective resistance components, capacitance components, and inductance components can be reduced as much as possible.

[0127] FIG. 13A is a bottom perspective view showing the internal structure of the LED driver IC1b(3ch) shown in FIG. 11A. Therefore, contrary to the previous FIG. 11A, the first side 101 is on the right side and the second side 102 is on the left side.

[0128] In the semiconductor chip 130, the upper switch 11H(ch1) and the lower switch 11L(ch1) of the first channel, the upper switch 11H(ch2) and the lower switch 11L(ch2) of the second channel, and the upper switch 11H(ch3) and the lower switch 11L(ch3) of the third channel are respectively integrated.

[0129] Wires W11 are respectively stretched between the drain pad of the upper switch 11H(ch1) and the two PVIN1 pins. Wires W12 are respectively stretched between the source pad of the upper switch 11H(ch1) and the drain pad of the lower switch 11L(ch1) and the two SW1 pins. Wires W13 are respectively stretched between the source pad of the lower switch 11L(ch1) and the two PGND1 pins.

[0130] Between the drain pad of the upper switch 11H (ch2) and the two PVIN2 pins, wires W21 are respectively stretched. Between the source pad of the upper switch 11H (ch2) and the drain pad of the lower switch 11L (ch2) and the two SW2 pins, wires W22 are respectively stretched. Between the source pad of the lower switch 11L (ch2) and the two PGND2 pins, wires W23 are respectively stretched.

[0131] Between the drain pad of the upper switch 11H (ch3) and the two PVIN3 pins, wires W31 are respectively stretched. Between the source pad of the upper switch 11H (ch3) and the drain pad of the lower switch 11L (ch3) and the two SW3 pins, wires W32 are respectively stretched. Between the source pad of the lower switch 11L (ch3) and the two PGND3 pins, wires W33 are respectively stretched.

[0132] Note that the lower switches 11L (ch1 / ch2 / ch3) have a larger element size than the upper switches 11H (ch1 / ch2 / ch3). According to such an element design, it is possible to increase the current capacity of the lower switches 11L (ch1 / ch2 / ch3) compared to the current capacity of the upper switches 11H (ch1 / ch2 / ch3). For example, when it is desired to maintain the output power constant, the higher the output voltage VLED, the smaller the output current ILED, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. That is, since it is necessary to pass a larger output current ILED when the on-duty of the half-bridge output stage is lower, the above element design is effective.

[0133] Also, the upper switch 11H (ch1) and the lower switch 11L (ch1), the upper switch 11H (ch2) and the lower switch 11L (ch2), and the upper switch 11H (ch3) and the lower switch 11L (ch3) are respectively arranged in a vertical column in the order shown along the y direction orthogonal to the first side 101 in the plan view of the semiconductor chip 130.

[0134] In addition, the switch formation regions where the upper switches 11H (ch1 / ch2 / ch3) and the lower switches 11L (ch1 / ch2 / ch3) are formed are unevenly distributed near the second side 102 of the package 100 in a plan view of the semiconductor chip 130.

[0135] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are arranged near the third side 103 of the package 100 in a plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN1, PGND1, SW1) of the first channel are as close as possible.

[0136] On the other hand, the upper switch 11H (ch2) and the lower switch 11L (ch2) of the second channel are arranged at the central part in the y direction in a plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN2, PGND2, SW2) of the second channel are as close as possible.

[0137] Also, the upper switch 11H (ch3) and the lower switch 11L (ch3) of the third channel are arranged near the fourth side 104 of the package 100 in a plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN3, PGND3, SW3) of the third channel are as close as possible.

[0138] By adopting such an element layout, the lengths of the wires W11 to W13, the wires W21 to W23, and the wires W31 to W33 can be minimized, so that the respective resistance components, capacitance components, and inductance components can be reduced as much as possible.

[0139] FIG. 13B is a bottom perspective view showing the internal structure of the LED driver IC1b (3ch) shown in FIG. 11B. Therefore, contrary to the previous FIG. 11B, the first side 101 is on the right side and the second side 102 is on the left side.

[0140] The semiconductor chip 130 integrates an upper switch 11H(ch1) and a lower switch 11L(ch1) of the first channel, an upper switch 11H(ch2) and a lower switch 11L(ch2) of the second channel, and an upper switch 11H(ch3) and a lower switch 11L(ch3) of the third channel, respectively.

[0141] A wire W11 is stretched between the drain pad of the upper switch 11H(ch1) and the PVIN1 pin. Wires W12 are stretched between the source pad of the upper switch 11H(ch1) and the drain pad of the lower switch 11L(ch1) and the two SW1 pins, respectively. Wires W13 are stretched between the source pad of the lower switch 11L(ch1) and the two PGND1 pins, respectively.

[0142] A wire W21 is stretched between the drain pad of the upper switch 11H(ch2) and the PVIN2 pin. Wires W22 are stretched between the source pad of the upper switch 11H(ch2) and the drain pad of the lower switch 11L(ch2) and the two SW2 pins, respectively. Wires W23 are stretched between the source pad of the lower switch 11L(ch2) and the two PGND2 pins, respectively.

[0143] Wires W31 are stretched between the drain pad of the upper switch 11H(ch3) and the PVIN3 pin and the PVIN3(S) pin, respectively. Also, a wire W31S is stretched between the PVIN3(S) pin and the sub-pad of the semiconductor chip 130. Wires W32 are stretched between the source pad of the upper switch 11H(ch3) and the drain pad of the lower switch 11L(ch3) and the two SW3 pins, respectively. Wires W33 are stretched between the source pad of the lower switch 11L(ch3) and the two PGND3 pins, respectively.

[0144] Note that the lower switches 11L (ch1 / ch2 / ch3) have a larger element size than the upper switches 11H (ch1 / ch2 / ch3). According to such an element design, it is possible to increase the current capacity of the lower switches 11L (ch1 / ch2 / ch3) compared to the current capacity of the upper switches 11H (ch1 / ch2 / ch3). For example, when it is desired to maintain a constant output power, the higher the output voltage VLED, the smaller the output current ILED needs to be, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. That is, since it is necessary to pass a larger output current ILED when the on-duty of the half-bridge output stage is lower, the above element design becomes effective.

[0145] Also, the upper switch 11H (ch1) and the lower switch 11L (ch1), the upper switch 11H (ch2) and the lower switch 11L (ch2), and the upper switch 11H (ch3) and the lower switch 11L (ch3) are arranged in vertical columns in the order shown along the y-direction orthogonal to the first side 101 in a plan view of the semiconductor chip 130.

[0146] Further, the switch formation regions in which the upper switches 11H (ch1 / ch2 / ch3) and the lower switches 11L (ch1 / ch2 / ch3) are formed are unevenly distributed near the first side 101 of the package 100 in a plan view of the semiconductor chip 130. Also, the logic formation region in which the controller 13 and the like are formed is unevenly distributed near the second side of the package 100 in a plan view of the semiconductor chip 130.

[0147] Furthermore, the upper switch 11H (ch1) and the lower switch 11L (ch1) of the first channel are arranged near the third side 103 of the package 100 in a plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN1, PGND1, SW1) of the first channel are as close as possible.

[0148] On one hand, the upper switch 11H(ch2) and the lower switch 11L(ch2) of the second channel are respectively arranged closer to the fourth side 104 of the package 100 in the plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN2, PGND2, SW2) of the second channel are as short as possible.

[0149] Also, the upper switch 11H(ch3) and the lower switch 11L(ch3) of the third channel are respectively arranged at the central part in the y direction in the plan view of the semiconductor chip 130 so that the distances from the external terminal groups (PVIN3, PGND3, SW3) of the third channel are as short as possible.

[0150] By adopting such an element layout, the lengths of the wires W11~W13, the wires W21~W23, and the wires W31~W33 can be minimized, so that the respective resistance components, capacitance components, and inductance components can be reduced as much as possible.

[0151] Also, in this layout, compared with the above-mentioned FIG. 13A, the upper switches 11H(ch1 / ch2 / ch3) and the lower switches 11L(ch1 / ch2 / ch3) are respectively formed in a vertically long shape (a shape where the length in the x direction is larger than the length in the y direction). As a result, it becomes easier to arrange the PGND pin closer to the end side of the first side 101 than the SW1~SW3 pins.

[0152] <PCB Layout> Next, the optimization of the PCB layout realized by the above pin arrangement will be described in detail with specific examples.

[0153] FIG. 14A is a plan view showing the layout of a printed circuit board on which the LED driver IC1a (2ch) shown in FIG. 10A is mounted. The LED lamp module X of this configuration example includes a printed circuit board 300 (hereinafter referred to as PCB 300), a two-channel LED driver IC1a, various discrete components externally attached thereto (only the capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, and sense resistors Rs1 and Rs2 shown above are exemplified in this figure), and light-emitting diodes LED1 and LED2 (not shown). Although not explicitly shown in this figure, a heat sink 200 is mounted on the heat dissipation pad 111 of the LED driver IC1a.

[0154] As shown by the thin solid line, the LED driver IC1a is mounted on the first main surface (front side of the paper surface) of the PCB 300. More specifically, the LED driver IC1a is mounted in a state where FIG. 10 is rotated 90 degrees counterclockwise. That is, in this figure, the left-right direction of the paper surface corresponds to the aforementioned x direction, and the up-down direction of the paper surface corresponds to the aforementioned y direction. Therefore, the power supply terminals (PVIN1, PVIN2) provided on the first side 101 of the package 100 are led out downward on the paper surface, and the power ground terminals (PGND1, PGND2) and switch output terminals (SW1, SW2) provided on the second side 102 of the package 100 are led out upward on the paper surface.

[0155] On the other hand, various wirings (power supply lines 310 to 312, power ground lines 320 to 322, switch output lines 331 to 333 and 341 to 343, power line 360) connected to the LED driver IC1a, and various discrete components (capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, sense resistors Rs1 and Rs2) are laid or mounted on the second main surface (back side of the paper surface) of the PCB 300 as shown by the broken line. Specific descriptions will be given individually below.

[0156] The main part of the power supply line 310 connected to the power supply terminals (PVIN1, PVIN2) of the LED driver IC1a, and the main part of the power ground line 320 connected to the power ground terminals (PGND1, PGND2) of the LED driver IC1a are laid in parallel along the x-direction (the left-right direction of the paper) in the plan view of the PCB300.

[0157] Also, the main parts of the power supply line 310 and the power ground line 320 are laid so as to overlap the package 100 of the LED driver IC1a in the plan view of the PCB300.

[0158] Specifically described with reference to this figure, the main part of the power supply line 310 is linearly laid in a route that passes from the outside of the third side 103 to near the first side 101 on the back of the package 100 and reaches the outside of the fourth side 104.

[0159] On the other hand, the main part of the power ground line 320 is linearly laid in a route that passes from the outside of the third side 103 to near the second side 102 on the back of the package 100 and reaches the outside of the fourth side 104 while keeping a predetermined gap from the main part of the power supply line 310.

[0160] Note that capacitors C11 and C21 (= bypass capacitors) are connected between the main part of the power supply line 310 and the main part of the power ground line 320. In particular, as shown in this figure, the capacitors C11 and C21 may be mounted so as to overlap the LED driver IC1a in the plan view of the PCB300.

[0161] In addition, branch portions 311 and 312 branched from the main trunk portion are formed on the power supply line 310. Speaking with reference to this figure, the branch portions 311 and 312 are respectively branched downward in the drawing from the main trunk portion of the power supply line 310 passing through the back surface of the package 100 toward the power supply terminals (PVIN1, PVIN2), and are electrically connected to the power supply terminals (PVIN1, PVIN2) via vias, through holes, etc. (not shown) penetrating between the first main surface and the second main surface of the PCB 300.

[0162] In addition, branch portions 321 and 322 branched from the main trunk portion are formed on the power ground line 320. Speaking with reference to this figure, the branch portions 321 and 322 are respectively branched upward in the drawing from the main trunk portion of the power ground line 320 passing through the back surface of the package 100 toward the power ground terminals (PGND1, PGND2), and are electrically connected to the power ground terminals (PGND1, PGND2) via vias, through holes, etc. (not shown) penetrating between the first main surface and the second main surface of the PCB 300. Note that the power ground lines 321 and 322 may be shared. When the power ground lines 321 and 322 are shared, the branch portion branched from the main trunk portion of the power supply line 310 becomes one line.

[0163] The switch output lines 331 to 333 conducting between the switch output terminal (SW1) of the first channel and the light emitting diode LED1 are laid upward in the drawing from the back region of the switch output terminal (SW1). An inductor L1 is mounted between the switch output line 331 and the switch output line 332. A sense resistor Rs1 is also mounted between the switch output line 332 and the switch output line 333. A capacitor C13 is mounted between the switch output line 333 and the branch portion 321 of the power ground line 320 extending to a position adjacent thereto.

[0164] The switch output lines 341 to 343 that conduct between the switch output terminal (SW2) of the second channel and the light-emitting diode LED2 are laid out upward from the back region of the switch output terminal (SW2) in the plane of the paper. An inductor L2 is mounted between the switch output line 341 and the switch output line 342. Also, a sense resistor Rs2 is mounted between the switch output line 342 and the switch output line 343. Further, a capacitor C23 is mounted between the switch output line 343 and a branch portion 322 of the power ground line 320 that extends to a position adjacent thereto.

[0165] Also, in the LED lamp module X of this configuration example, the power supply terminals (PVIN1, PVIN2), switch output terminals (SW1, SW2), power ground terminals (PGND1, PGND2) provided for each of the plurality of channels, and the discrete components (C11 and C21, C13 and C23, L1 and L2, Rs1 and Rs2) externally attached thereto, as well as the branch portions 311 and 312 of the power supply line 310, the branch portions 321 and 322 of the power ground line 320, and the switch output lines 331 to 333 and 341 to 343 are arranged to be symmetric about the left and right between the first channel and the second channel.

[0166] The external terminals and wirings other than the above will also be briefly described. A power supply line 360 laid out downward from the back region of the paper is connected to the VIN pin provided on the first side 101 of the package 100. Also, logic signals are input from the lower side of the paper to the SPI communication terminals (SI, SCK, CSB, SO) provided on the first side 101.

[0167] The above-mentioned FIG. 14A is a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) having a synchronous rectification type half-bridge output stage is mounted. On the other hand, a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) adopting a diode rectification method instead of the synchronous rectification method is as shown in FIG. 14B.

[0168] The parts that are different from FIG. 14A in FIG. 14B will be described. Diodes D11 and D21 are discrete components externally attached to the LED driver IC1a. As shown by the dashed lines, the diodes D11 and D21 are mounted on the second main surface of the PCB300. Diode D11 is used as the lower switch 11L of the first channel, and diode D21 is used as the lower switch 11L of the second channel.

[0169] Diode D11 may be mounted such that the cathode-side terminal of diode D11 is electrically connected to the switch output line 331 and the anode-side terminal of diode D11 is electrically connected to the power ground line 320. In order to reduce the closed loop of the first channel (see FIG. 16 described later), it is preferable to arrange the anode-side terminal of diode D11 as close as possible to the capacitor C11.

[0170] Diode D21 may be mounted such that the cathode-side terminal of diode D21 is electrically connected to the switch output line 341 and the anode-side terminal of diode D21 is electrically connected to the power ground line 320. In order to reduce the closed loop of the second channel (see FIG. 16 described later), it is preferable to arrange the anode-side terminal of diode D21 as close as possible to the capacitor C21.

[0171] In the configuration example shown in FIG. 14B, one power ground terminal PGND1 and PGND2 is provided for each of the first channel and the second channel. However, as shown in FIG. 19 described later, the power ground terminals may be shared between the first channel and the second channel.

[0172] Next, the layout of the printed circuit board other than the layouts shown in FIGS. 14A and 14B will be described. FIG. 14C is a plan view showing another layout of the printed circuit board on which the LED driver IC1a (2ch) having a synchronous rectification type half-bridge output stage is mounted. FIG. 14D is a plan view showing another layout of the printed circuit board on which the LED driver IC1a (2ch) having a diode rectification type half-bridge output stage is mounted. Hereinafter, the differences between FIG. 14C and FIG. 14A and the differences between FIG. 14D and FIG. 14B will be described.

[0173] The layouts shown in FIGS. 14C and 14D expand the power supply line 310 and the power ground line 320 as compared with the layouts shown in FIGS. 14A and 14B. Therefore, in the layouts shown in FIGS. 14C and 14D, unlike the layouts shown in FIGS. 14A and 14B, the power line 360, the line for transmitting the logic signal (not shown), the switch output line 330, and the switch output line 340 are laid on the first main surface of the PCB 300.

[0174] The switch output line 330 conducts between the switch output terminal (SW1) of the first channel and the switch output line 331. The switch output line 330 is electrically connected to the switch output line 331 through vias, through holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300. In the layouts shown in FIGS. 14C and 14D, unlike the layouts shown in FIGS. 14A and 14B, the switch output line 331 does not overlap the switch output terminal (SW1) in the plan view of the PCB 300.

[0175] The switch output line 340 conducts between the switch output terminal (SW2) of the second channel and the switch output line 341. The switch output line 340 is electrically connected to the switch output line 341 through vias, through-holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300. In the layouts shown in FIGS. 14C and 14D, unlike the layouts shown in FIGS. 14A and 14B, the switch output line 341 does not overlap the switch output terminal (SW2) in the plan view of the PCB 300.

[0176] FIG. 15 is a plan view showing the layout of a printed circuit board on which the LED driver IC1b (3ch) shown in FIG. 11A is mounted. The LED lamp module X of this configuration example includes a PCB 300, a 3-channel LED driver IC1b, various discrete components externally attached thereto (in this figure, only the previously mentioned capacitors C11, C21, and C31, capacitors C13, C23, and C33, inductors L1 to L3, and sense resistors Rs1 to Rs3 are exemplified), and light-emitting diodes LED1 to LED3 (not shown). Although not explicitly shown in this figure, a heat sink 200 is attached to the heat dissipation pad 111 of the LED driver IC1b.

[0177] The LED driver IC1b is mounted on the first main surface (front side of the paper) of the PCB 300 as shown by the thin solid line. More specifically, the LED driver IC1b is mounted in a state where FIG. 11 is rotated counterclockwise by 90 degrees. That is, in this figure, the left-right direction of the paper corresponds to the previously mentioned x direction, and the up-down direction of the paper corresponds to the previously mentioned y direction. Therefore, the power supply terminals (PVIN1 to PVIN3) provided on the first side 101 of the package 100 are led out downward on the paper, and the power ground terminals (PGND1 to PGND3) and the switch output terminals (SW1 to SW3) provided on the second side 102 of the package 100 are led out upward on the paper.

[0178] On one hand, various wirings (power supply lines 310 to 312, power ground lines 320 to 323, switch output lines 331 to 333, 341 to 343, and 351 to 353, power line 360) connected to the LED driver IC1b, and various discrete components (capacitors C11, C21, and C31, capacitors C13, C23, and C33, inductors L1 to L3, sense resistors Rs1 to Rs3) are laid or mounted on the second main surface (the back side of the paper surface) of the PCB 300 as shown by the dashed lines. Specific individual descriptions are given below.

[0179] The main parts of the power supply line 310 connected to the power supply terminals (PVIN1 to PVIN3) of the LED driver IC1b, and the main parts of the power ground line 320 connected to the power ground terminals (PGND1 to PGND3) of the LED driver IC1b are laid in parallel along the x direction (the left - right direction of the paper surface) in the plan view of the PCB 300.

[0180] Also, the main parts of each of the power supply line 310 and the power ground line 320 are laid so as to overlap the package 100 of the LED driver IC1b in the plan view of the PCB 300.

[0181] Specifically described with reference to this figure, the main part of the power supply line 310 is linearly laid in a route that passes from the outside of the third side 103, near the first side 101 on the back of the package 100, and reaches the outside of the fourth side 104.

[0182] On the other hand, the main part of the power ground line 320 is linearly laid in a route that passes from the outside of the third side 103, near the second side 102 on the back of the package 100, and reaches the outside of the fourth side 104 while keeping a predetermined gap from the main part of the power supply line 310.

[0183] Between the main part of the power supply line 310 and the main part of the power ground line 320, capacitors C11, C21, and C31 (bypass capacitors) are connected. In particular, the capacitors C11, C21, and C31 may be mounted so as to overlap with the LED driver IC1b in a plan view of the PCB300, as shown in this figure.

[0184] In addition, branch line portions 311 to 313 branched from the main part are formed on the power supply line 310. Speaking with reference to this figure, the branch line portions 311 to 313 are each branched downward in the paper surface from the main part of the power supply line 310 passing through the back surface of the package 100 toward the power supply terminals (PVIN1 to PVIN3), and are electrically connected to the power supply terminals (PVIN1 to PVIN3) via vias, through holes, etc. (not shown) penetrating between the first main surface and the second main surface of the PCB300.

[0185] In addition, branch line portions 321 to 323 branched from the main part are formed on the power ground line 320. Speaking with reference to this figure, the branch line portions 321 to 323 are each branched upward in the paper surface from the main part of the power ground line 320 passing through the back surface of the package 100 toward the power ground terminals (PGND1 to PGND3), and are electrically connected to the power ground terminals (PGND1 to PGND3) via vias, through holes, etc. (not shown) penetrating between the first main surface and the second main surface of the PCB300.

[0186] Switch output lines 331 to 333 that conduct between the switch output terminal (SW1) of the first channel and the light emitting diode LED1 are laid upward in the paper surface from the back region of the switch output terminal (SW1). An inductor L1 is mounted between the switch output line 331 and the switch output line 332. A sense resistor Rs1 is also mounted between the switch output line 332 and the switch output line 333. In addition, a capacitor C13 is mounted between the switch output line 333 and the branch line portion 321 of the power ground line 320 extending to a position adjacent thereto.

[0187] The switch output lines 341 to 343 that conduct between the switch output terminal (SW2) of the second channel and the light emitting diode LED2 are laid out upward on the paper surface from the back region of the switch output terminal (SW2). An inductor L2 is mounted between the switch output line 341 and the switch output line 342. A sense resistor Rs2 is mounted between the switch output line 342 and the switch output line 343. A capacitor C23 is mounted between the switch output line 343 and a branch portion 322 of the power ground line 320 that extends to a position adjacent thereto.

[0188] The switch output lines 351 to 353 that conduct between the switch output terminal (SW3) of the third channel and the light emitting diode LED3 are laid out upward on the paper surface from the back region of the switch output terminal (SW3). An inductor L3 is mounted between the switch output line 351 and the switch output line 352. A sense resistor Rs3 is mounted between the switch output line 352 and the switch output line 353. A capacitor C33 is mounted between the switch output line 353 and a branch portion 323 of the power ground line 320 that extends to a position adjacent thereto.

[0189] Also, in the LED lamp module X of this configuration example, the power supply terminals (PVIN1 to PVIN3), switch output terminals (SW1 to SW3), power ground terminals (PGND1 to PGND3) provided for each of the plurality of channels, and the discrete components (C11, C21 and C31, C13, C23 and C33, L1 to L3, Rs1 to Rs3) externally attached thereto, and the branch portions 311 to 313 of the power supply line 310, the branch portions 321 to 323 of the power ground line 320, and the switch output lines 331 to 333, 341 to 343 and 351 to 353 are arranged to be symmetric with respect to the left and right between at least two channels. Specifically, between the first channel and the second channel, and between the first channel and the third channel, the respective components are arranged to be symmetric with respect to the left and right.

[0190] The external terminals and wirings other than those described above will also be briefly explained. A power line 360 laid from the back region downward in the drawing plane is connected to the VIN pin provided on the first side 101 of the package 100. Further, logic signals are input from the lower side of the drawing plane to the SPI communication terminals (SI, SCK, CSB, SO) provided on the first side 101.

[0191] It should be noted that the same changes as those from the aforementioned FIG. 14A to the aforementioned FIGS. 14B to 14D can also be made to FIG. 15.

[0192] <Bypass capacitor> Next, the optimal layout of the capacitor C*1 (where *=1, 2, or 3) that functions as a bypass capacitor will be considered with reference to the drawings. FIG. 16 is a diagram showing the formation of a closed loop of the capacitor C*1.

[0193] As shown in this figure, the capacitor C*1 of the *-th channel forms a closed loop (11H → PVIN* → C*1 → PGND* → 11L) together with the upper switch 11H and the lower switch 11L. The smaller this closed loop is, the smaller the influence of the transient current associated with power supply fluctuations can be suppressed. Therefore, it is desirable to mount the capacitor C*1 at a position where the above-mentioned closed loop is minimized.

[0194] Specifically, as shown in the aforementioned FIGS. 14A to 14D and FIG. 15, it is desirable to mount the capacitor C*1 so as to overlap with the LED driver ICs 1a to 1b in a plan view of the PCB 300. Further, it is desirable to mount it on (or in the vicinity of) the line segment connecting the PVIN* pin and the PGND* pin.

[0195] <Vertical arrangement of LED driver ICs> FIG. 17 is a diagram showing a vertical arrangement of the LED driver IC1b (3 channels). In the LED lamp module X of this configuration example, on the first main surface of the PCB 300, m LED driver ICs 1b(1) to 1b(m) (where m ≥ 2) are mounted in a vertical row along the x direction (the left - right direction of the paper).

[0196] Note that, for the LED driver ICs 1b(1) to 1b(m), the pin arrangements shown in the previous FIG. 11 are respectively adopted. Therefore, for the power supply line 310 and the power ground line 320, as shown in the previous FIG. 15, they can be laid in a straight line along the x direction (the left - right direction of the paper) so as to pass through the back surfaces of the respective LED driver ICs 1b(1) to 1b(m).

[0197] Also, since the switch output lines of the respective LED driver ICs 1b(1) to 1b(m) can all be led out upward on the paper, even when the number of channels increases, it is possible to arrange the light - emitting diodes LED1 to LED(3m) of all channels along the x direction (the left - right direction of the paper).

[0198] In this way, by adopting the above - mentioned pin arrangement, it is possible to simplify the wiring pattern laid on the PCB 300, and thus, it is possible to realize the optimization of the PCB layout, such as preventing short - circuits between wiring patterns and reducing the wiring pattern area.

[0199] Note that, in this figure, the vertical arrangement of the LED driver IC1b (3 channels) is taken as an example, but the same can be said for the vertical arrangement of the LED driver IC1a (2 channels).

[0200] <Comparative Example> Next, in order to more clearly understand the effects of the pin arrangements (FIGS. 10 to 15) described so far, the differences in the PCB layout will be explained while giving a comparative example that adopts a pin arrangement different from the previous one.

[0201] FIG. 18 is a plan view showing the layout of a printed circuit board on which an LED driver IC1c (3 channels) adopting a pin arrangement different from the previous one is mounted.

[0202] As shown in this figure, in the LED driver IC1c, the external terminal groups (PVIN1, PGND1, SW1) of the first channel are collectively arranged on the first side 101 of the package 100. On the other hand, the external terminal groups (PVIN2, PGND2, SW2) of the second channel and the external terminal groups (PVIN3, PGND3, SW3) of the third channel are each collectively arranged on the second side 102 of the package 100.

[0203] Therefore, for the components of the first channel and the components of each of the second and third channels, they have to be separately laid or arranged on both sides of the LED driver IC1c.

[0204] Specifically in this figure, the components of the first channel (power supply line 411, branch portion 421 of the power ground line 420, switch output lines 431 to 433, capacitors C11 and C13, inductor L1, and sense resistor Rs1) are all arranged on the first side 101 side of the package 100.

[0205] On the other hand, the components of the second channel (power supply line 412, branch portion 422 of the power ground line 420, switch output lines 441 to 443, capacitors C21 and C23, inductor L2, and sense resistor Rs2) are all arranged on the second side 102 side of the package 100.

[0206] Also, the components of the third channel (power supply line 413, branch portion 423 of the power ground line 420, switch output lines 451 to 453, capacitors C31 and C33, inductor L3, and sense resistor Rs3) are all arranged on the second side 102 side of the package 100.

[0207] Thus, when adopting the pin arrangement of this comparative example, the wiring pattern laid on the PCB 400 becomes extremely complex, and it becomes impossible to arrange the light-emitting diodes LED1 to LED3 of all channels side by side in the x direction (the left-right direction of the paper surface).

[0208] On the other hand, if the previously proposed pin arrangement (Figs. 10 to 15) is adopted, it becomes possible to avoid such problems and optimize the PCB layout.

[0209] <Modification Example> Note that various modifications are possible for the pin arrangements and PCB layouts described so far. Some modification examples will be briefly described below.

[0210] Fig. 19 is a diagram showing a first modification example of the pin arrangement. As shown in this figure, the power ground terminal (PGND) does not necessarily need to be provided for each of a plurality of channels, and it may be shared among a plurality of channels.

[0211] Fig. 20 is a diagram showing a second modification example of the pin arrangement. As shown in this figure, the power supply terminal (PVIN) does not necessarily need to be provided for each of a plurality of channels, and it may be shared among a plurality of channels.

[0212] Fig. 21 is a diagram showing a third modification example of the pin arrangement. As shown in this figure, the power ground terminal (PGND) and the switch output terminal (SW) provided on the second side 102 may be interchanged with each other in position.

[0213] Fig. 22 is a diagram showing a fourth modification example of the pin arrangement. As shown in this figure, the power supply terminal (VIN) of the signal system does not necessarily need to be provided on the first side 101, and it may be provided on the second side 102.

[0214] FIG. 23 is a diagram showing a modified example of the PCB layout. As shown in this figure, at least one of the power supply line 310 and the power ground line 320 (the power supply line 310 in this figure) may be laid at a position that does not overlap with the package 100.

[0215] FIG. 24 is a diagram showing an adoption example of a QFP [quad flat package]. As shown in this figure, the package 100 is not necessarily limited to the SOP, and a QFP may be adopted.

[0216] In that case, for example, the SW1 pin and the SW2 pin may be arranged on the second side 102, the PVIN1 pin and the PGND1 pin of the first channel may be arranged on the third side 103, and the PVIN2 pin and the PGND2 pin of the second channel may be arranged on the fourth side 104. Also, the PVIN1 pin and the PVIN2 pin may be arranged closer to the first side 101, and the PGND1 pin and the PGND2 pin may be arranged closer to the second side 102. Further, the PVIN1 pin and the PVIN2 pin may be arranged at positions facing each other. Similarly, the PGND1 pin and the PGND2 pin may be arranged at positions facing each other.

[0217] By adopting such a pin arrangement, the power supply line 310 and the power ground line 320 can be laid in parallel and in a straight line, similar to FIG. 14A above.

[0218] <Same-side mounting> FIG. 25 is a plan view showing the layout of a printed circuit board on which the LED driver IC1b (3 channels) shown in FIG. 11B and a plurality of discrete components externally attached thereto are mounted on the same surface. The LED lamp module X of this configuration example includes a PCB 300, the 3-channel LED driver IC1b (three in this figure) shown in FIG. 11B, various discrete components externally attached thereto (exemplified by capacitor C, inductor L, and sense resistor R in this figure), and light-emitting diodes LED1 to LED9 (not shown). Although not explicitly shown in this figure, a heat sink 200 is mounted on the heat dissipation pad 111 of the LED driver IC1b.

[0219] As shown by the thin solid line, the LED driver IC1b is mounted on the first main surface (front side of the paper surface) of the PCB 300. Among various wirings and various discrete components connected to the LED driver IC1b, at least a part thereof is laid or mounted on the first main surface (front side of the paper surface) of the PCB 300 as shown by the solid line, and the rest is laid or mounted on the second main surface (back side of the paper surface) of the PCB 300 as shown by the broken line. Specific individual explanations will be given below.

[0220] The main part of the power supply line 310 connected to the power supply terminals (PVIN1 to PVIN3) of the LED driver IC1b is laid along the x direction at a position on the first main surface of the PCB 300 that does not overlap with the package 100 of the LED driver IC1b.

[0221] On the other hand, the main part of the power ground line 320 connected to the power ground terminals (PGND1 to PGND3) of the LED driver IC1b is laid along the x direction at a position on the second main surface of the PCB 300 that overlaps with the package 100 of the LED driver IC1b.

[0222] In addition, branch portions 311 to 313 branched from the main trunk portion are formed on the power supply line 310. Speaking with reference to this figure, the branch portions 311 to 313 are each branched from the main trunk portion of the power supply line 310 toward the power supply terminals (PVIN1 to PVIN3) on the first main surface of the PCB 300 and are electrically connected to the power supply terminals (PVIN1 to PVIN3).

[0223] In addition, branch portions 321 to 325 branched from the main trunk portion are formed on the power ground line 320. Speaking with reference to this figure, the branch portions 321 to 323 are each branched from the main trunk portion of the power ground line 320 toward the power ground terminals (PGND1 to PGND3) on the second main surface of the PCB 300 and are electrically connected to the power ground terminals (PGND1 to PGND3) via vias, through holes, etc. (not shown) penetrating between the first main surface and the second main surface of the PCB 300.

[0224] In addition, the branch portion 324 is branched from the main trunk portion of the power ground line 320 toward the branch portions 311 to 313 of the power supply line 310 on the second main surface of the PCB 300. A bypass capacitor C is mounted between the branch portions 311 to 313 of the power supply line 310 and the branch portion 324 of the power ground line 320.

[0225] On the other hand, the branch portion 325 is branched from the main trunk portion of the power ground line 320 toward the subsequent switch output lines 333 to 353 on the second main surface of the PCB 300.

[0226] The switch output lines 331 to 333 connected to the respective switch output terminals (SW1) of the LED driver IC1b are laid on the first main surface of the PCB 300 toward the corresponding light-emitting diodes (LED3, LED6, and LED9 in this figure). An inductor L is mounted on the first main surface of the PCB 300 between the switch output line 331 and the switch output line 332. A sense resistor R is mounted on the first main surface of the PCB 300 between the switch output line 332 and the switch output line 333. An output capacitor C is mounted on the first main surface of the PCB 300 between the switch output line 333 and a branch portion 325 of the power ground line 320 extending to a position adjacent thereto.

[0227] The switch output lines 341 to 343 connected to the respective switch output terminals (SW2) of the LED driver IC1b are laid on the first main surface of the PCB 300 toward the corresponding light-emitting diodes (LED1, LED4, and LED7 in this figure). An inductor L is mounted on the first main surface of the PCB 300 between the switch output line 341 and the switch output line 342. A sense resistor R is mounted on the first main surface of the PCB 300 between the switch output line 342 and the switch output line 343. An output capacitor C is mounted on the first main surface of the PCB 300 between the switch output line 343 and a branch portion 325 of the power ground line 320 extending to a position adjacent thereto.

[0228] The switch output lines 351 to 353 connected to the respective switch output terminals (SW3) of the LED driver IC1b are laid on the first main surface of the PCB300 toward the corresponding light-emitting diodes (LED2, LED5, and LED8 in this figure). An inductor L is mounted on the first main surface of the PCB300 between the switch output line 351 and the switch output line 352. Also, a sense resistor R is mounted on the first main surface of the PCB300 between the switch output line 352 and the switch output line 353. An output capacitor C is mounted on the first main surface of the PCB300 between the switch output line 353 and a branch portion 323 of the power ground line 320 extending to a position adjacent thereto.

[0229] Although not shown explicitly in this figure, discrete components of the small signal system may be mounted on the second main surface of the PCB300.

[0230] Also, regarding mounting the LED driver IC and the discrete components externally attached thereto on the same surface of the printed wiring board, the number of channels and the pin arrangement of the LED driver IC are both irrelevant. That is, in this figure, not limited to the LED driver IC1b (3ch) shown in FIG. 11B, either the LED driver IC1b (3ch) shown in FIG. 11A or the LED driver IC1a (2ch) shown in FIGS. 10A and 10B can be mounted on the same surface as the discrete components.

[0231] FIG. 26 is a diagram showing the α-β cross-section of FIG. 25. As described above, in the LED lamp module X of FIG. 25, all of the three LED driver IC1b and at least some of the discrete components externally attached thereto (inductor L, sense resistor R, output capacitor C) are mounted on the same surface (first main surface) of the PCB300.

[0232] Therefore, by devising the shape of the heat sink 200 attached to the LED driver IC 1b, it becomes possible to attach the heat sink 200 in common to both the LED driver IC 1b and discrete components (such as the inductor L) mounted on the same surface of the PCB 300.

[0233] For example, as shown in this figure, an extension part 240 extending from the base part 210 of the heat sink 200 toward the upper part of the inductor L may be provided, heat dissipation grease 250 may be applied to its bottom surface, and it may be attached to the top surface of the inductor L. With such a configuration, it becomes possible to enhance the heat dissipation performance not only of the LED driver IC 1b but also of discrete components.

[0234] For example, as shown in this figure, when discrete components of the same height are arranged in a row, the shape design of the heat sink 200 (especially the extension part 240) becomes easy. Also, in this figure, the LED driver IC 1b and the inductor L are joined to the heat sink 200, but other discrete components can also be joined to the heat sink 200 as needed.

[0235] <Other Modification Examples> Thus, the various technical features disclosed in this specification can be variously modified in addition to the above-described embodiments without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above-described embodiments, but should be understood to include all modifications belonging to the meaning and scope equivalent to the claims.

Industrial Applicability

[0236] The invention disclosed in this specification can be used, for example, in a multi-channel LED driver IC mounted on an in-vehicle LED lamp module.

Explanation of Reference Numerals

[0237] 1, 1a, 1b LED Driver IC (Semiconductor Device) 2 Boost Circuit 3 MCU 11H Upper Switch (NMOSFET) 11L Lower Switch (NMOSFET) 12H Upper Driver 12L Lower Driver 13 Controller 14 On-Time Setting Unit 15 Slope Voltage Generation Unit 16 Sense Amplifier 17 Error Amplifier 18 Comparator 100 Package 101 First Side 102 Second Side 103 Third Side 104 Fourth Side 110 Top Surface 111 Heat Sink 112 1-Pin Mark 120 Bottom Surface 130 Semiconductor Chip 140 Island 151, 152 Support Frame 200 Heat Sink 210 Base Portion 220 Heat Dissipation Fin 230 Heat Dissipation Grease 240 Extension Portion 250 Heat Dissipation Grease 300 Printed Circuit Board 310 Power Supply Line (Main Trunk Portion) 311, 312, 313 Power Supply Lines (Branch Portions) 320 Power Ground Line (Main Trunk Portion) 321, 322, 323, 324, 325 Power Ground Lines (Branch Portions) 330~333, 340~343, 351~353 Switch Lines 360 Power Line C1, C2, C11~C13, C21~C23, C31~C33 Capacitors D1, D11, D21 diodes L1, L2, L3 inductors LED1, LED2, LED3 light-emitting diodes R1, R2 resistors Rs1, Rs2, Rs3 sense resistors W11~W13, W21~W23, W31~W33 wires X LED lamp module

Claims

1. A package having a rectangular shape in plan view, including a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side; A power supply terminal provided on the first side or the second side; A power ground terminal provided on the first side, the second side, or the fourth side; A switch output terminal provided on the second side; An upper switch connected between the power supply terminal and the switch output terminal; A lower switch connected between the switch output terminal and the power ground terminal; And having; The upper switch, the lower switch, the power supply terminal, and the power ground terminal are each provided for each of a plurality of channels. A semiconductor device.

2. The switch output terminal is provided for each of a plurality of channels. The semiconductor device according to Claim 1.

3. And a heat dissipation pad exposed on the top surface of the package. The semiconductor device according to Claim 2.

4. In plan view, the upper switch and the lower switch are unevenly arranged closer to the second side. The semiconductor device according to Claim 3.

5. In plan view, the upper switch and the lower switch are arranged in a vertical row along a second direction orthogonal to a first direction in which the first side and the second side extend. The semiconductor device according to Claim 4.

6. Further comprising an output feedback control unit that drives the upper switch and the lower switch so that an output current supplied from the switch output terminal to a load matches a predetermined target value. The semiconductor device according to Claim 5.

7. The output feedback control unit performs output feedback control in a bottom detection on-time fixed method. The semiconductor device according to Claim 6.

8. The thermal resistance from the semiconductor chip encapsulated in the package to the top surface of the package is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package. The semiconductor device according to Claim 6 or 7.

9. A package having a rectangular shape in plan view, including a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side; A power supply terminal provided on the first side or the second side; The power ground terminal provided on the first side, the second side, or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, A heat dissipation pad exposed on the top surface of the package, A semiconductor device.

10. A package having a rectangular shape in plan view with a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side, The power supply terminal provided on the first side or the second side, The power ground terminal provided on the first side, the second side, or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, Having, In plan view, the upper switch and the lower switch are unevenly distributed near the second side, A semiconductor device.

11. A package having a rectangular shape in plan view with a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side, The power supply terminal provided on the first side or the second side, The power ground terminal provided on the first side, the second side, or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, Having, In plan view, the upper switch and the lower switch are arranged in a vertical row along a second direction perpendicular to a first direction in which the first side and the second side extend, A semiconductor device.

12. A package having a rectangular shape in plan view with a first side, a second side parallel to the first side, a third side perpendicular to the first side and the second side, and a fourth side parallel to the third side and perpendicular to the first side and the second side, The power supply terminal provided on the first side or the second side, The power ground terminal provided on the first side, the second side, or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, An output feedback control unit that drives the upper switch and the lower switch so that the output current supplied from the switch output terminal to the load matches a predetermined target value, A semiconductor device.

13. The output feedback control unit performs output feedback control in a bottom detection on-time fixed method, The semiconductor device according to claim 12.

14. A package having a rectangular shape in plan view with a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side, A power supply terminal provided on the first side or the second side, A power ground terminal provided on the first side, or the second side or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, Having, The thermal resistance from the semiconductor chip encapsulated in the package to the top surface of the package is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package, A semiconductor device.

15. A package having a rectangular shape in plan view with a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side, A power supply terminal provided on the first side or the second side, A power ground terminal provided on the first side, or the second side or the fourth side, The switch output terminal provided on the second side, The upper switch connected between the power supply terminal and the switch output terminal, The lower switch connected between the switch output terminal and the power ground terminal, Having, The lower switch has a larger element size than the upper switch, A semiconductor device.

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