Printed circuit board
The printed circuit board design addresses die-to-die interconnection by using a substrate with insulating and wiring layers and a connection structure with alternating dielectric and metal layers, achieving reliable and high-density connections for semiconductor chips.
Patent Information
- Application Number
- JP2024218745
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-26
- Filing Date
- 2024-12-13
- Publication Date
- 2025-07-08
AI Technical Summary
The challenge lies in effectively performing die-to-die interconnection in printed circuit boards for mounting electronic components and semiconductor chips, while ensuring a reliable connection structure that can enhance the yield and simplify the substrate and package design.
A printed circuit board design incorporating a substrate portion with a first insulating layer, first wiring layer, and first via layer, along with a connection structure featuring a capacitor portion, passivation layer, and wiring portion, which includes alternating dielectric and metal layers connected by specific metals and insulating materials to facilitate die-to-die interconnection.
The solution enables reliable die-to-die interconnection, enhances wiring density, and improves the overall reliability of the printed circuit board, facilitating efficient connection of semiconductor chips and other electronic components.
Smart Images
Figure 2025102706000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a printed circuit board.
Background Art
[0002] Recently, due to the development of technologies such as Artificial Intelligence (AI), multi-chip packages including memory chips such as High Bandwidth Memory (HBM) for geometrically increasing data processing and processor chips such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA) have been used. In particular, as the number of CPU and GPU cores in server products has increased rapidly, the die split technology that can effectively increase the number of cores has become widespread, and die-to-die interconnection is required. Research has continued to design a substrate to include a connection structure for die-to-die interconnection, aiming for a simplified substrate and package structure, and increasing the yield while improving the reliability of the connection structure.
Summary of the Invention
Problems to be Solved by the Invention
[0003] One of several objectives of the present disclosure is to provide a printed circuit board capable of performing die-to-die interconnection in a printed circuit board for mounting electronic components, semiconductor chips, etc.
[0004] Another one of several objectives of the present disclosure is to provide a printed circuit board including a connection structure capable of realizing the functions of elements in addition to die-to-die interconnection.
[0005] Another object of the present disclosure is to provide a printed circuit board that can improve reliability.
Means for Solving the Problems
[0006] One of several solutions proposed through the present disclosure is a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a first via layer penetrating at least a part of the first insulating layer so as to connect the first wiring layers to each other, and a connection structure disposed within the substrate portion and including a capacitor portion, a passivation layer covering the capacitor portion, and a wiring portion disposed on the passivation layer. The capacitor portion of the connection structure includes a plurality of dielectric layers, first and second metal layers alternately disposed with the plurality of dielectric layers interposed therebetween, a first insulating material disposed at the same level as the first metal layer on one side of the capacitor portion, a second insulating material disposed at the same level as the second metal layer on the other side facing the one side of the capacitor portion, a first connection metal connected to the first metal layer, and a second connection metal connected to the second metal layer, and to provide a printed circuit board.
[0007] Another of several solutions proposed through the present disclosure is a substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer, and a connection structure disposed within the substrate portion and including a capacitor portion, a passivation layer covering the capacitor portion, and a wiring portion disposed on the passivation layer. The capacitor portion includes a plurality of dielectric layers, first and second metal layers alternately disposed with the plurality of dielectric layers interposed therebetween, a first connection metal connected to the first metal layer, and a second connection metal connected to the second metal layer, and the first metal layer includes a metal different from the metal of the second metal layer, and to provide a printed circuit board.
Advantages of the Invention
[0008] One of the various advantages of the present disclosure is to provide a printed circuit board capable of performing die-to-die interconnection in a printed circuit board for mounting electronic components and semiconductor chips.
[0009] Another one of the various effects of the present disclosure is that it is possible to provide a printed circuit board including a connection structure that can realize the functions of elements in addition to die-to-die interconnection.
[0010] Another one of the various effects of the present disclosure is that it is possible to provide a printed circuit board that can improve reliability.
Brief Description of the Drawings
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Embodiments for Carrying Out the Invention
[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape, size, etc. of elements in the drawings may be enlarged, reduced (or emphasized or simplified) for clearer explanation.
[0013] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.
[0014] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040, etc. are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described later to form various signal lines 1090.
[0015] Examples of the chip-related components 1020 include, but are not limited to, memory chips such as volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), and flash memories, application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). In addition, other forms of chip-related electronic components can also be included. Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 can also be in the form of packages containing the above-described chips and electronic components.
[0016] Examples of the network-related components 1030 include, but are not limited to, Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth (registered trademark), 3G, 4G, 5G, and any other wireless and wired protocols designated as such and later. In addition, other numerous wireless or wired standards and protocols can also be included. Also, the network-related components 1030 can be combined with the chip-related components 1020 with each other.
[0017] Examples of the other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, the components are not limited thereto, and passive elements in the form of chip components used for various other purposes may also be included. Further, the other components 1040 can be combined with the chip-related components 1020 and / or the network-related components 1030 with each other.
[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of the other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, the components are not limited thereto, and also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a CD (compact disk), a DVD (digital versatile disk), etc. In addition, other electronic components used for various purposes depending on the type of the electronic device 1000 may also be included.
[0019] The electronic device 1000 can be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, Automotive, etc. However, it is not limited to these, and it can also be any other electronic device that processes data.
[0020] FIG. 2 is a perspective view schematically showing an example of an electronic device.
[0021] Referring to the drawings, the electronic device can be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Further, other components that are physically and / or electrically connected or not connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 can be the above-described chip-related components, for example, a component package 1121, but it is not limited thereto. The component package 1121 can be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Or, the component package 1121 can also be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and it can also be other electronic devices as described above.
[0022] Printed Circuit Board Figures 3a and 3b are cross-sectional views schematically showing a printed circuit board according to an example, and Figures 3c and 3d are cross-sectional views schematically showing a connection structure of the printed circuit board according to an example. The printed circuit board according to the example shown in Figures 3a and 3b can be more clearly understood by the connection structure shown in Figures 3c and 3d.
[0023] Referring to Figure 3a, a printed circuit board according to an example includes a substrate portion 100 and a connection structure 200. The substrate portion 100 is a portion for realizing a signal path of the printed circuit board, and the connection structure 200 corresponds to a portion for connecting components such as chips to each other. The connection structure 200 is a portion for realizing a fine signal path corresponding to electronic components such as fine chips, and electronic components such as a plurality of chips can be arranged with the connection structure 200 interposed therebetween, and corresponds to a portion for interconnecting electronic components such as chips and maintaining an electrical signal path.
[0024] The substrate portion 100 may include a first insulating layer 110, a first wiring layer 120 disposed on or in the first insulating layer 110, and a cavity penetrating at least a part of the first insulating layer 110. The substrate portion 100 may include a first via layer 130 penetrating at least a part of the first insulating layer 110 so as to connect the first wiring layers 120 to each other.
[0025] The first insulating layer 110 can be composed of a plurality of insulating layers, and each first insulating layer 110 can contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such a resin. The insulating material can be a photosensitive material and / or a non-photosensitive material. For example, as the insulating material of the first insulating layer 110, there are mentioned insulating materials such as PPG (Prepreg) and RCC (Resin Coated Copper), but it is not limited thereto, and it can also be ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, it is not limited thereto, and if necessary, other polymer materials with excellent rigidity can also be used.
[0026] The first wiring layer 120 can be composed of a plurality of wiring layers, and each first wiring layer 120 can contain a metal substance. As the metal substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used. The first wiring layer 120 can each include an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but it is not limited thereto. A sputtering layer can also be formed instead of the chemical copper as the electroless plating layer. If necessary, a copper foil can be further included. The first wiring layer 120 can each perform various functions according to the design of the corresponding layer. For example, it can include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern can include various signals excluding the ground pattern, the power pattern, etc., such as data signals. These patterns can each include a line pattern, a plane pattern, and / or a pad pattern.
[0027] The first via layer 130 can be composed of a plurality of via layers, and each first via layer 130 can include micro vias. The micro vias can be filled vias that fill the via holes or conformal vias arranged along the wall surfaces of the via holes. The micro vias can be arranged in a stacked type and / or a staggered type. Each first via layer 130 can include a metallic substance. The metallic substance can include metallic substances such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connection via layer can include an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but is not limited thereto. A sputtering layer can also be formed instead of the chemical copper as the electroless plating layer. The first via layer 130 can perform various functions according to the design of the layer. For example, it can include ground vias, power vias, signal vias, and the like. Here, the signal vias can include vias for transmitting various signals such as data signals excluding ground vias, power vias, and the like.
[0028] Each first wiring layer 120 and each first via layer 130 can be integrally formed with each other, but are not limited thereto. The first wiring layer 120 and / or the first via layer 130 can also be formed by any one of the SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive processes, but are not limited thereto, and any process that can form a circuit on a printed circuit board can be used without limitation.
[0029] The fact that the first wiring layer 120 is disposed on or within the first insulating layer 110 means that the first wiring layer 120 can be disposed on the first insulating layer 110 or can be disposed so as to be embedded within the first insulating layer 110, and can mean that it can have a so-called coreless type substrate structure in which the first wiring layer 120 is embedded within the first insulating layer 110. In particular, referring to FIG. 3a, the first wiring layer 120 disposed at the lowermost side can have a structure embedded within the first insulating layer 110.
[0030] On the other hand, the number of layers of the first insulating layer 110, the first wiring layer 120, and the first via layer 130 can be changed according to the design. In particular, the first insulating layer 110 can further include a core insulating layer including a core, the first wiring layer 120 can include a copper foil, and the first via layer 130 can also include through vias penetrating the core insulating layer. Thus, the first insulating layer 110, the first wiring layer 120, and the first via layer 130 of the printed circuit board according to an example can have a configuration that can be utilized by those having ordinary knowledge in the technical field of printed circuit boards.
[0031] The cavity can penetrate at least a part of the first insulating layer 110. The cavity can correspond to the position where the connection structure 200 is mounted. The fact that the cavity can penetrate at least a part of the first insulating layer 110 can also mean penetrating any continuous first insulating layer 110 among the plurality of first insulating layers 110, and can also mean penetrating only a part of any first insulating layer 110, but is not limited thereto, and can also mean penetrating a part of any other first insulating layer 110 while penetrating any continuous first insulating layer 110. Although not shown in FIGS. 3a and 3b, when the cavity penetrates only a part of any first insulating layer 110, the upper surface of the corresponding first insulating layer 110 can have a step.
[0032] The method for forming the cavity can be used without limitation as long as it is a method used in a known cavity formation process. For example, a mechanical drilling process such as laser processing or a blasting process can be used, but it is not limited thereto. At this time, a part of the first wiring layer 120 disposed on the first insulating layer 110 can also function as a stopper layer, and another stopper layer can be disposed in advance on the upper surface of the first insulating layer 110 and then removed by etching or the like after cavity processing. When the stopper layer is formed, the stopper layer can be formed simultaneously with the first wiring layer 120. The wall surface of the cavity penetrating at least a part of the first insulating layer 110 can be constituted by the side surface of the first insulating layer 110, and the bottom surface of the cavity can be constituted by the upper surface of the first insulating layer 110. On the other hand, although not shown in FIGS. 3a and 3b, the bottom surface of the cavity can also be constituted by a stopper layer disposed at the same level as the first wiring layer 120.
[0033] A printed circuit board according to an example includes a connection structure 200. The connection structure 200 can be disposed in the cavity, and the connection structure 200 can include a wiring portion 201 and a capacitor portion 202. The specific configurations of the wiring portion 201 and the capacitor portion 202 of the connection structure 200 can be made clearer by FIGS. 3c and 3d, and thus detailed descriptions will be given later.
[0034] The wiring portion 201 of the connection structure 200 can include a second insulating layer 210, a second wiring layer 220 disposed on or in the second insulating layer 210, and a second via layer 230 penetrating at least a part of the second insulating layer 210 so as to connect the second wiring layers 220 to each other.
[0035] The capacitor section 202 of the connection structure 200 includes a plurality of dielectric layers 240, a first metal layer 251 and a second metal layer 252 that are alternately arranged with the plurality of dielectric layers 240 interposed therebetween, and an insulating material 261 that is arranged at the same level as the first metal layer 251 on one side of the capacitor section 202 or at the same level as the second metal layer 252 on the other side facing one side of the capacitor section 202. A connection metal 270 can be included that penetrates a part of the plurality of dielectric layers 240, a part of the first metal layer 251, and a part of the insulating material 261 so as to connect the first metal layers 251 to each other, or penetrates a part of the plurality of dielectric layers 240, a part of the second metal layer 252, and a part of the insulating material 261 so as to connect the second metal layers 252 to each other. On the other hand, the connection structure can further include a passivation layer 262 that covers the capacitor section 202.
[0036] The wiring portion 201 of the connection structure 200 can have a higher wiring density than the substrate portion 100. The fact that the wiring density is higher is a relative concept. For example, it can be meant that the average pitch of the wirings included in the second wiring layer 220 is even smaller than the average pitch of the wirings included in the first wiring layer 120. The pitch can be measured by photographing a cross-sectional cut of the printed circuit board with a scanning microscope, and the average pitch can be the average value of the pitches between the wirings measured at any five points. Also, the average insulation distance between the second wiring layers 220 can be even smaller than the average insulation distance between the plurality of first wiring layers 120. The interlayer insulation distance can also be measured by photographing a cross-sectional cut of the printed circuit board with a scanning microscope, and the average interlayer insulation distance can be the average value of the insulation distances between the adjacent wiring layers measured at any five points. That is, the wirings included in the second wiring layer 220 can be high-density circuits with an even smaller L / S (Line / Space) than the wirings included in the first wiring layer 120. As a non-limiting example, the wirings included in the second wiring layer 220 can have a line / space of about 2 / 2 μm, but are not limited thereto. Since the wiring portion 201 of the connection structure 200 has a higher density than the wiring of the substrate portion 100, it can be effective when interconnecting electronic components such as semiconductor chips. That is, it can be effective for die-to-die interconnection.
[0037] In this regard, the thickness of the second insulating layer 210 may be thinner than that of the first insulating layer 110, and the thickness of the second wiring layer 220 may be thinner than that of the first wiring layer 120. The thickness of the insulating layer is a concept including approximate values and can mean the distance vertically across the upper and lower surfaces of the insulating layer. The fact that the thickness of the second insulating layer 210 is thinner than that of the first insulating layer 110 can mean that the thickness of any one of the plurality of second insulating layers 210 is thinner than that of any one of the plurality of first insulating layers 110, but is not limited thereto. The thicknesses of the first insulating layer 110 and the second insulating layer 210 can be measured by photographing the cut cross-section of the printed circuit board with a scanning microscope and measuring them respectively, and can be the average value of the thicknesses of the insulating layers measured at any five points. The thickness of the wiring layer can be interpreted in the same sense as the thickness of the insulating layer.
[0038] Specific details regarding other configurations of the connection structure will be described later.
[0039] The printed circuit board according to an example can further include an adhesive layer 300.
[0040] The connection structure 200 is disposed in the cavity of the substrate portion 100, and the connection structure 200 can be attached to the bottom surface of the cavity via the adhesive layer 300. The adhesive layer 300 can be disposed so as to cover the lower surface of the connection structure 200. As the adhesive layer 300, an adhesive film such as a normal die attach film (DAF) can be used, but is not limited thereto, and known tapes etc. can also be used. Any means that can attach other configurations such as electronic components or connection structures to the printed circuit board can be used without limitation.
[0041] Referring to FIG. 3b, a printed circuit board according to an example can include a first semiconductor chip 401 disposed on a part of the substrate portion 100 and a part of the connection structure 200, and a second semiconductor chip 402 disposed on a part of the substrate portion 100 and a part of the connection structure 200. It can include a connecting member 500 that connects the first semiconductor chip 401 and the second semiconductor chip 402 to the substrate portion 100 and the connection structure 200, respectively. The first semiconductor chip 401 can be disposed so as to be electrically connected to a part of the substrate portion 100 and a part of the connection structure 200, and the second semiconductor chip 402 is electrically connected to a part of the substrate portion 100 and a part of the connection structure 200 and can be electrically connected to the first semiconductor chip 401 via the connection structure 200.
[0042] The first semiconductor chip 401 and the second semiconductor chip 402 can each include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated in one chip. At this time, the integrated circuit can be, for example, a logic chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-digital converter, an ASIC (application-specific IC), etc., but is not limited thereto, and can also be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, a high bandwidth memory (HBM), or a power management IC (PMIC), etc. For example, the first semiconductor chip 401 can include a logic chip such as a GPU, and the second semiconductor chip 402 can include a memory chip such as HBM. Alternatively, the first semiconductor chip 401 and the second semiconductor chip 402 can also be divided logic chips that are divided by die splitting and have different cores from each other.
[0043] The first semiconductor chip 401 and the second semiconductor chip 402 can each be formed based on an active wafer. In this case, as the base material forming each main body, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used. Various circuits can be formed in the main body. Connection pads can be formed on each main body, and the connection pads can contain conductive substances such as aluminum (Al) and copper (Cu). The first semiconductor chip 401 and the second semiconductor chip 402 can be bare dies, and in this case, metal bumps can be arranged on the connection pads. Or, the first semiconductor chip 401 and the second semiconductor chip 402 can also be packaged dies, and in this case, a redistribution layer can be further formed on the connection pads, and metal bumps can be arranged on the redistribution layer.
[0044] The first semiconductor chip 401 and the second semiconductor chip 402 can be connected to the substrate portion 100 of the printed circuit board and the connection structure via the connection member 500. The connection member 500 can be formed of a low-melting-point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu), etc., but is not limited thereto. The connection member 500 can be formed as a multilayer or a single layer. When formed as a multilayer, it can include copper pillars and solder, and when formed as a single layer, it can include tin-silver solder or copper, etc., but is not limited thereto. In addition, any means that can play a mediating role so that semiconductor chips or electronic components, etc. are electrically connected to the substrate portion 100 and / or the connection structure 200 can be used without limitation. In FIG. 3b, two semiconductor chips are shown as being mounted, but this is not limiting, and a larger number of semiconductor chips can be mounted, and a larger number of semiconductor chips can also be electrically connected by the connection structure 200.
[0045] Referring to FIG. 3c, a connection structure 200 of a printed circuit board according to an example can include a wiring portion 201 and a capacitor portion 202.
[0046] The wiring portion 201 of the connection structure 200 can include a second insulating layer 210, a second wiring layer 220 disposed on or within the second insulating layer 210, and a second via layer 230 that penetrates at least a part of the second insulating layer 210 so as to connect the second wiring layers 220 to each other.
[0047] The second insulating layer 210 can be composed of a plurality of insulating layers, and each second insulating layer 210 can contain an insulating material. The insulating material can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such a resin. The insulating material can be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the second insulating layer 210 can be, but is not limited to, an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper). It can also be ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc. However, it is not limited to this, and if necessary, other polymer materials with excellent rigidity can also be used. On the other hand, the second insulating layer 210 can contain an insulating substance composed of an organic material. That is, the connecting structure 200 can be an organic bridge. Therefore, even when the connecting structure 200 is disposed above the substrate portion 100, unlike the case where the connecting structure 200 is a silicon bridge, reliability problems due to the coefficient of thermal expansion (CTE) mismatch can hardly occur. Also, when the connecting structure 200 contains an organic insulating substance, the process difficulty and cost for formation can also be reduced. As the organic insulating substance for forming a fine circuit, a photosensitive insulating substance (Photo Imageable Dielectric, PID) can be used, but it is not limited thereto.
[0048] The second wiring layer 220 can be composed of a plurality of wiring layers, and each second wiring layer 220 can contain a metallic substance. As the metallic substance, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used. The second wiring layer 220 can each include an electroless plating layer (or electroless copper) as a seed layer and an electroplating layer (or electroformed copper) as a plating layer, but is not limited thereto. A sputtering layer can also be formed instead of the electroless copper as the electroless plating layer. Optionally, a copper foil can be further included. The second wiring layer 220 can perform various functions according to the design of each corresponding layer. For example, it can include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern can include various signals excluding the ground pattern, the power pattern, etc., such as data signals. These patterns can each include a line pattern, a plane pattern, and / or a pad pattern. The second wiring layer 220 disposed on the uppermost side of the second wiring layers 220 can have a structure exposed from the second insulating layer 210, and a surface treatment layer can be further included on the exposed surface.
[0049] The second via layer 230 can be composed of a plurality of via layers, and each second via layer 230 can include microvias. The microvias can be filled vias that fill the via holes or conformal vias disposed along the wall surfaces of the via holes. The microvias can be arranged in a stacked type and / or a staggered type. Each second via layer 230 can include a metallic substance. The metallic substance can include metallic substances such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second via layer 230 can include an electroless plating layer (or electroless copper) as a seed layer and an electroplating layer (or electroplated copper) as a plating layer respectively, but is not limited thereto. A sputtering layer can also be formed instead of the electroless copper as the electroless plating layer. The second via layer 230 can perform various functions according to the design of the corresponding layer. For example, it can include ground vias, power vias, signal vias, etc. Here, the signal vias can include vias for transmitting various signals excluding ground vias, power vias, etc., such as data signals.
[0050] Each second wiring layer 220 and each second via layer 230 can be integrally formed with each other, but is not limited thereto. The second wiring layer 220 and / or the second via layer 230 can also be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive processes, but is not limited thereto, and any process that can form a circuit on a printed circuit board or a connection structure can be used without limitation.
[0051] The capacitor portion 202 of the connection structure 200 includes a plurality of dielectric layers 240, a first metal layer 251 and a second metal layer 252 that are alternately arranged with the plurality of dielectric layers 240 interposed therebetween, and an insulating material 261 that is arranged at the same level as the first metal layer 251 on one side of the capacitor portion 202 or at the same level as the second metal layer 252 on the other side facing one side of the capacitor portion 202. A connection metal 270 that penetrates a part of the plurality of dielectric layers 240, a part of the first metal layer 251, and a part of the insulating material 261 so as to connect the first metal layers 251 to each other, or penetrates a part of the plurality of dielectric layers 240, a part of the second metal layer 252, and a part of the insulating material 261 so as to connect the second metal layers 252 to each other can be included. On the other hand, the connection structure can further include a passivation layer 262 that covers the capacitor portion 202.
[0052] The dielectric layer 240 can be composed of a plurality of dielectric layers 240, and the dielectric layer 240 can contain a dielectric material. The dielectric material can include oxides or nitrides, and can include one or more materials among SiO2, Si3N4, Al2O3, AlN, MgO, Y2O3, HfO2, ZrO2, Ta2O3. The dielectric layer 240 containing an oxide or a nitride can have various values of dielectric constant from 1 to 80. Also, it is preferable to select a material having a band gap energy (Eg) of 4 eV or more for the dielectric layer 240 in consideration of the functions and characteristics of the material, and it can include at least one of the above-described materials, but it is not necessarily limited thereto, and any material containing an oxide or a nitride can be used without limitation. If a dielectric material with a high dielectric constant is selected but the band gap energy is low, the dielectric characteristics of the dielectric layer 240 may not be realized, so it can include at least one of the above-described materials. The plurality of dielectric layers 240 can contain substantially the same dielectric material as each other, but it is not necessarily limited thereto, and the plurality of dielectric layers 240 can be arranged to contain various materials as needed. On the other hand, the dielectric material of the dielectric layer 240 is not limited to this, and it can be used without limitation as long as it can be arranged between the first metal layer 251 and the second metal layer 252 that perform the function of the internal electrode and perform the function as a dielectric.
[0053] The dielectric layer 240 can be formed by performing a deposition process. Preferably, it can be formed through thin-film deposition. As the thin-film deposition process, it can be selectively performed by methods such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), ALD (Atomic Layer Deposition), and Molecular Vapor Deposition (MVD) process. The dielectric layer 240 can be deposited on a support substrate wafer, and in order to achieve a flat surface, the deposition process can be performed in layer units. However, it is not necessarily limited to this. There is no limitation on the method of forming the dielectric layer 240, such as it can also be formed by a method of laminating sheets through screening. As long as it is a known method of laminating the dielectric layer 240, there is no limitation.
[0054] The first metal layer 251 and the second metal layer 252 can each contain a metallic substance as a material with excellent electrical conductivity. As the metallic substance, one or more of titanium (Ti), molybdenum (Mo), tungsten (W), iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), zinc (Zn), aluminum (Al), tin (Sn), lead (Pb), calcium (Ca), and alloys thereof can be included. The first metal layer 251 and the second metal layer 252 can contain substantially different metallic substances from each other. Since the first metal layer 251 and the second metal layer 252 can contain different metallic substances from each other, in the step of removing a part of the first metal layer 251 in the method for manufacturing a printed circuit board, the second metal layer 252 cannot react, and in the step of removing a part of the second metal layer 252, the first metal layer 251 cannot react. That is, since the first metal layer 251 and the second metal layer 252 contain different metallic substances from each other, in the step of forming the connecting metal 270 for connecting the first metal layers 251 to each other and the connecting metal 270 for connecting the second metal layers 252 to each other, the first metal layer 251 and the second metal layer 252 can be independently connected respectively. As a non-limiting example, the first metal layer 251 can contain molybdenum (Mo), and the second metal layer 252 can contain titanium (Ti).
[0055] On the other hand, without necessarily being limited thereto, when there is a method of forming the first metal layer 251 and the second metal layer 252 by a method capable of connecting the first metal layer 251 and the second metal layer 252 independently of each other using other means or processes, the first metal layer 251 and the second metal layer 252 can also contain substantially the same metal.
[0056] The first metal layer 251 and the second metal layer 252 can each be formed by a vapor deposition process, and can be performed in the same manner as the vapor deposition process for forming the dielectric layer 240, but is not necessarily limited thereto, and different vapor deposition processes can also be used. Note that this is not necessarily limiting, and the first metal layer 251 and the second metal layer 252 can also be formed by printing a conductive paste on a ceramic green sheet, or can be formed via plating, etc., and the method for forming the metal layer is not limited.
[0057] The first metal layer 251 and the second metal layer 252 can be alternately arranged with each other with the dielectric layer 240 interposed therebetween. The fact that the first metal layer 251 and the second metal layer 252 are alternately arranged with each other with the dielectric layer 240 interposed therebetween can mean that the dielectric layer 240, the first metal layer 251, the dielectric layer 240, and the second metal layer 252 are alternately arranged. On the other hand, this is not necessarily limiting, and the first metal layer 251 can be matched a plurality of times, and the second metal layer 252 can be arranged a plurality of times, etc., as long as they are arranged with a certain tendency and the first metal layer 251 and the second metal layer 252 can each function as an internal electrode of the capacitor portion 202, it is sufficient. On the other hand, referring to FIG. 3c, the first metal layer 251 is shown as being arranged at the lowermost side of the capacitor portion 202, but this is not necessarily limiting, and the lowermost side of the capacitor portion 202 can be the dielectric layer 240, and the second metal layer 252 can also be arranged.
[0058] The first metal layer 251 and the second metal layer 252 can each function as an internal electrode of the capacitor portion 202. That is, the first metal layer 251 and the second metal layer 252 can be charged with opposite polarities to each other to have a capacitance. The first metal layer 251 and the second metal layer 252 can be arranged to correspond to each other so as to form a pair, and can be arranged to face each other with the dielectric layer 240 interposed therebetween. With such a structure, charges can be charged to each metal layer to perform the function of a capacitor.
[0059] The insulating material 261 can be disposed at the same level as the first metal layer 251 on one side of the capacitor portion 202 and can be positioned between the dielectric layers 240. The insulating material 261 can also be disposed at the same level as the second metal layer 252 on the other side facing one side of the capacitor portion 202 and can be positioned between the dielectric layers 240. In the method of manufacturing a printed circuit board, after the step of removing a part of the first metal layer 251 on one side, when the step of removing a part of the second metal layer 252 on the other side is performed, grooves from which each metal layer has been removed are generated. Since the insulating material 261 can be disposed so as to fill the grooves, it can be disposed at the same level as the first metal layer 251 on one side of the capacitor portion 202, can be disposed at the same level as the second metal layer 252 on the other side of the capacitor portion 202, and the insulating material 261 can be disposed between the dielectric layers 240. At this time, since the insulating material 261 can be positioned in the grooves of the first metal layer 251 and the second metal layer 252, the thickness of the insulating material 261 can be substantially the same as the thickness of the first metal layer 251 and / or the second metal layer 252.
[0060] The insulating material 261 can include an insulating material. The insulating material can include an organic insulating material or an inorganic insulating material. The organic insulating material can include an organic film, and as an insulating polymer, it can include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, and a material containing an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such resins. As a non-limiting example, the insulating material can include ABF (Ajinomoto Build-up Film). The inorganic insulating material can include a ceramic material and can include a glassy material. The glassy material can be a silicon oxide containing a metal element, but is not limited thereto, and can include a silicon-based oxide or nitride. On the other hand, the material of the insulating material 261 is not limited thereto, and any insulating material that can fill the grooves formed in the first metal layer 251 and the second metal layer 252 can be used without limitation. For example, a known material for passivation can also be used.
[0061] The insulating material 261 can be formed to fill the groove using a deposition process such as ALD (Atomic Layer Deposition), but can also be formed by performing a process such as coating. On the other hand, it is not limited to this, and any process that can fill the groove with an insulating material can be used without limitation.
[0062] By forming the insulating material 261 so as to fill the grooves generated in the first metal layer 251 and the second metal layer 252, the first metal layer 251 of the capacitor portion 202 can be prevented from being connected to the second metal layer 252, the grooves are not emptied, and the capacitor portion 202 can be protected during processing at the stage of forming the subsequent connecting metal 270. On the other hand, the insulating material 261 can also be disposed on the uppermost side of the dielectric layer 240. This can be the result of patterning the insulating material 261 at the stage of forming the insulating material 261, and the insulating material 261 is disposed on the uppermost dielectric layer 240 to adjust the flatness of the connecting metal 270.
[0063] On the other hand, the arrangement of the insulating material 261 is not limited to that shown in FIG. 3c, and it can also extend to cover the side portions of the plurality of dielectric layers 240 while being formed to fill the grooves.
[0064] The connecting metal 270 can connect the first metal layers 251 to each other or connect the second metal layers 252 to each other. That is, the connecting metal 270 can connect the internal electrodes of the capacitor portion 202 to each other and perform the function of an external electrode connected to the outside.
[0065] The connecting metal 270 can penetrate the dielectric layer 240, the second metal layer 252, and the insulating material 261 on one side of the capacitor section 202. Since the connecting metal 270 disposed on one side of the capacitor section 202 penetrates the second metal layer 252 but does not penetrate the first metal layer 251, the second metal layers 252 can be connected to each other. The connecting metal 270 disposed on the other side of the capacitor section 202 can penetrate the dielectric layer 240, the first metal layer 251, and the insulating material 261. Since the connecting metal 270 disposed on the other side penetrates the first metal layer 251 without penetrating the second metal layer 252, the first metal layers 251 can be connected to each other. Therefore, one side of the capacitor section 202 can have the connecting metal 270 connected to the second metal layer 252, and the other side facing one surface of the capacitor section 202 can have the connecting metal 270 connected to the first metal layer 251.
[0066] The connecting metal 270 can contain a metallic substance. Examples of the metallic substance can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, and preferably, it can contain copper (Cu). The connecting metal 270 can contain a metal different from the respective metallic substances of the first metal layer 251 and the second metal layer 252. The connecting metal 270 can be formed by plating after processing via holes penetrating the laminate of the capacitor section 202, but the method of forming the connecting metal 270 is not limited thereto, and any known method for performing interlayer connection can be used without limitation.
[0067] The connecting metal 270 can function as an external electrode for each of the first metal layer 251 or the second metal layer 252 of the capacitor section 202 to be connected to the second wiring layer 220, and the connecting metal 270 can be connected to the second wiring layer 220 via the second via layer 230.
[0068] The connection structure 200 can include a passivation layer 262. The passivation layer 262 can be formed to cover the laminate of the capacitor portion 202. The passivation layer 262 can include an insulating material, and a known passivation resin used in electronic components such as semiconductor chips can be used. As a non-limiting example, the passivation layer 262 can include polyimide as the insulating resin. On the other hand, without being limited thereto, the passivation layer 262 can include, as an insulating polymer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, and a material including an inorganic filler, an organic filler, and / or glass fiber (Glass Fiber, Glass Cloth, and / or Glass Fabric) together with such resins. As a non-limiting example, the insulating material can include ABF (Ajinomoto Build-up Film).
[0069] Since the passivation layer 262 can cover the capacitor portion 202 to form a flat surface, the wiring portion 201 of the connection structure 200 can be disposed on the flattened passivation layer 262.
[0070] On the other hand, referring to FIG. 3d, in the connection structure 200 of a printed circuit board according to an example, the passivation layer 262 can fill the grooves formed in the first metal layer 251 and the second metal layer 252 instead of the insulating material 261. In this case, it can be the result of filling the grooves in the first metal layer 251 and the second metal layer 252 with the passivation layer 262 after omitting the step of forming the insulating material 261. That is, it can mean that the passivation layer 262 is integrated with the insulating material 261 so that the boundary between the insulating material 261 and the passivation layer 262 is not clearly observed, but the passivation layer 262 fills the grooves. In this case, while the process step can be reduced by one step, the insulating structure can be maintained by filling the grooves formed in the first metal layer 251 and the second metal layer 252, and the capacitor portion 202 can be protected at the step of forming the connection metal 270.
[0071] On the one hand, in FIGS. 3a to 3d, it is shown that one capacitor part 202 is arranged in the connection structure 200, but it is not limited thereto. A plurality of capacitor parts 202 can be arranged in parallel in the horizontal direction, and each can be connected to the wiring part or can be connected to each other via the second wiring layer 220, and can also be connected in series in the vertical direction.
[0072] On the one hand, the printed circuit board according to an example is not limited to FIGS. 3a to 3b, and the connection structure is not limited to the configuration shown in FIGS. 3c to 3d, and can further include a general configuration of the printed circuit board. That is, it can further include a configuration that can be used by those having ordinary knowledge in the technical field.
[0073] FIGS. 4a and 4b are cross-sectional views schematically showing a printed circuit board according to another example, and FIG. 4c is a cross-sectional view schematically showing the connection structure of the printed circuit board according to another example. The printed circuit board according to another example shown in FIGS. 4a and 4b can be more clearly understood by the connection structure in FIG. 4c.
[0074] In the connection structure 200 of the printed circuit board according to another example, the connection metal 270 can be arranged on one side and the other side of the capacitor part 202. That is, the connection metal 270 can be arranged on one side and the other side of the capacitor part 202 without penetrating the dielectric layer 240, the first metal layer 251, the second metal layer 252, and the insulating material 261.
[0075] The connection metal 270 can be arranged on one side and the other side via plating after forming the laminate of the capacitor part 202. At this time, the connection metal 270 can include an electroless plating layer and an electrolytic plating layer, and can also include a sputtering layer as needed. In addition, since the connection metal 270 can include a Ti / Cu sputtering layer, in this case, the second metal layer 252 and the connection metal 270 can also include the same metal substance.
[0076] The connecting metal 270 can extend to a part on the dielectric layer 240. That is, the connecting metal 270 can extend to a part of the upper surface of the dielectric layer 240 arranged on the uppermost side. The second via layer 230 can be connected in the region where the connecting metal 270 is arranged on a part of the upper surface. Since the connecting metal 270 does not penetrate the capacitor portion 202, there is a possibility that no defect occurs in the via hole formation stage.
[0077] On the other hand, among the configurations other than the arrangement of the connecting metal 270, the configuration of the connecting structure according to one example can also be applied to the connecting structure according to another example, so overlapping explanations regarding this are omitted.
[0078] FIG. 5a and FIG. 5b are cross-sectional views schematically showing a printed circuit board according to still another example, and FIG. 5c is a cross-sectional view schematically showing a connecting structure of a printed circuit board according to still another example. The printed circuit board according to still another example shown in FIGS. 5a and 5b can be more clearly understood by the connecting structure of FIG. 5c.
[0079] In a printed circuit board connection structure 200 according to still another example, the capacitor portion 202 can have an inclined surface. That is, the capacitor portion 202 can have a trapezoidal shape and can have a tapered shape such that the upper width is narrower than the lower width. This can be the result of connecting the electrodes after forming the capacitor laminate and then processing a part of the laminate to have an inclined surface. Since the capacitor portion 202 can have an inclined surface, vapor deposition can be easier at the stage of forming the insulating material 261, and the connecting metal 270 can be formed uniformly. At this time, the inclined surface formed on the capacitor portion 202 can form an acute angle with the bottom surface of the capacitor portion 202. As a non-limiting example, it is preferable that the angle formed by the inclined surface on the side surface of the capacitor portion 202 and the bottom surface of the capacitor portion 202 is 80 degrees or less. However, as long as the capacitor portion 202 is arranged, the angle formed by the side surface of the capacitor portion 202 and the bottom surface of the capacitor portion 202 is of course always greater than 0 degrees. The smaller the inclination angle of the side surface of the capacitor portion 202, the more the connectivity between the connecting metal 270, the first metal layer 251, and the second metal layer 252 can be improved.
[0080] As the side surface of the capacitor portion 202 has an inclined surface, the connecting metal 270 can also have an inclined surface. The connecting metal 270 and the bottom surface of the capacitor portion 202 can form an acute angle and can have substantially the same inclination angle as the inclination angle of the side surface of the capacitor portion 202. At this time, the inclination angle formed by the inclined surface of the capacitor portion 202 can be measured by photographing a cross-sectional surface in the stacking direction of the connection structure 200 or the capacitor portion 202 with a scanning microscope, and can also be measured using the angle formed by the extension line of the substantially inclined surface of the capacitor portion 202 measured in any five regions and the bottom surface of the capacitor portion 202, or using the angle formed by the extension line of the inclined surface of the connecting metal 270 and the bottom surface of the capacitor portion 202. On the other hand, any known method for measuring the inclination angle formed by the contact of substantially plane surfaces can be used without limitation, rather than a non-uniform inclined surface measured at only one point.
[0081] On the other hand, among the configurations other than the shape of the capacitor unit 202, the configuration of the connection structure according to one example and the configuration of the connection structure according to another example can also be applied to the connection structure according to still another example. Therefore, duplicate explanations regarding this will be omitted.
[0082] Method for manufacturing a printed circuit board A printed circuit board according to one example can include a step of mounting the connection structure 200 at the stage of forming the substrate portion 100 after the stage of forming the connection structure 200. Since the step of forming the substrate portion 100 can be performed by a known build-up process, only the manufacturing method of the connection structure will be described below.
[0083] Figs. 6a to 6j are cross-sectional views schematically showing the manufacturing method of the connection structure among the manufacturing methods of the printed circuit board according to one example.
[0084] Referring to Figs. 6a to 6j, the manufacturing method of the connection structure of the printed circuit board according to one example is shown as completing a single connection structure after forming a laminate of the capacitor units 202 in panel units on the support substrate 600 and then forming each wiring portion 201 on the unit laminate of each capacitor unit 202. At this time, in order to show that a plurality of unit connection structures 200 can be manufactured, it is shown that two connection structures 200 can be formed in parallel. However, the number of connection structures 200 that can be formed simultaneously is not necessarily limited to this. Since the manufacturing method of the connection structure 200 of the printed circuit board according to one example includes a step of singulating with the unit connection structure 200, the productivity can be further improved.
[0085] Referring to FIG. 6a, the method for manufacturing a connection structure includes the step of preparing a support substrate 600 on which a release layer 601 is formed. The support substrate 600 can be a silicon (Si)-based wafer substrate, or can be a High Resolution De-bondable Panel, but is not necessarily limited thereto. After forming the capacitor portion 202 and the wiring portion 201 to complete the connection structure 200, any substrate that can be separated from the connection structure 200 is sufficient. The release layer 601 can use a known material as a means for easily detaching the capacitor portion 202 disposed on the lower side of the connection structure 200 and the support substrate 600. The support substrate 600 can advantageously have a flat surface for laminating the dielectric layer 240, the first metal layer 251, and the second metal layer 252.
[0086] Referring to FIG. 6b, the method for manufacturing a connection structure can include the step of forming a dielectric layer 240, a first metal layer 251, and a second metal layer 252 on the support substrate 600 and the release layer 601. At this time, it can be formed so as to be alternately arranged in the order of the first metal layer 251, the dielectric layer 240, the second metal layer 252, and the dielectric layer 240, and can form a laminate of the capacitor portion 202. However, the lamination order is not limited to that shown in FIG. 6b, and can be laminated so that the dielectric layer 240 is located at the lowermost layer, and it is sufficient as long as the repeating unit of the lamination is constant. However, it is not necessarily limited thereto, and the repeating unit of the laminate can also vary depending on the capacitance of the capacitor portion 202 and the design of the connection structure 200. The laminate of the capacitor portion 202 can be formed in panel units on the support substrate 600, but is not necessarily limited thereto, and can be formed only in a necessary area. In this case, a plurality of the laminates can be formed in a separated form.
[0087] Referring to FIG. 6c, a part of the laminate of the capacitor section 202 can be removed to obtain a unit laminate. The laminate of the capacitor section 202 can be vertically cut to obtain a structure in which each unit laminate is separated. At this time, dry etching can be used as the method for cutting the laminate, but it is not limited thereto, and mechanical and chemical methods for removing a part to cut the laminate into unit laminates can be used without limitation.
[0088] Referring to FIG. 6d, it can include the step of removing a part of the first metal layer 251 on one side of the unit laminate of the capacitor section 202. Since the first metal layer 251 and the second metal layer 252 contain different metals, when an etching solution that reacts with the first metal layer 251 is used, the second metal layer 252 can be prevented from reacting. At this time, the step of removing a part of the first metal layer 251 can proceed only on one side of the unit laminate, and since a part of the second metal layer 252 is to be removed on the other side opposite to one side, the first metal layer 251 can be treated so as not to react on the other side.
[0089] Referring to FIG. 6e, it can include the step of removing a part of the second metal layer 252 on the other side of the unit laminate of the capacitor section 202. Since the first metal layer 251 and the second metal layer 252 contain different metals, when an etching solution that reacts with the second metal layer 252 is used, the first metal layer 251 can be prevented from reacting. At this time, the step of removing a part of the second metal layer 252 can proceed only on the other side of the unit laminate, and the second metal layer 252 can be treated so as not to react on one side of the unit laminate.
[0090] Referring to FIGS. 6d and 6e, grooves can be formed in the first metal layer 251 and the second metal layer 252 through the steps of removing respective parts of the first metal layer 251 and the second metal layer 252. Since the grooves are filled with a structure containing an insulating material later, the portions removed by the corresponding grooves can be electrically shorted.
[0091] Referring to FIG. 6f, it can include the step of forming the insulating material 261 to fill the groove. The method of forming the insulating material 261 can be performed by vapor deposition or coating, and the insulating material 261 can also be disposed on the dielectric layer 240, and is not limited to that shown in FIG. 6f, and can also partially cover the side portion of the unit laminate of the capacitor portion 202. On the other hand, the step of filling the insulating material 261 can be omitted, and in this case, in a subsequent step, the passivation layer 262 can be replaced to fill the groove.
[0092] Referring to FIG. 6g, it can include the step of forming the passivation layer 262 to cover each of the unit laminates of the capacitor portion 202. The passivation layer 262 can be disposed to cover the unit laminate of the capacitor portion 202. At this time, the step of planarizing the upper surface of the passivation layer 262 can also be performed together.
[0093] Referring to FIG. 6h, it can include the step of forming the connecting metal 270 that penetrates at least a part of the passivation layer 262 and the unit laminate of the capacitor portion 202. The step of forming the connecting metal 270 can be performed by the step of forming a through hole and the step of plating to fill it, but is not necessarily limited thereto. By forming the connecting metal 270, one side of the unit laminate of the capacitor portion 202 can be connected to the second metal layer 252. A groove portion for removing a part of the first metal layer 251 is formed on one side of the unit laminate of the capacitor portion 202, and since the groove portion is filled with an insulating material, on one side, the first metal layer 251 and the connecting metal 270 can not contact each other, and the second metal layer 252 and the connecting metal 270 can be connected to each other. On the other side of the unit laminate of the capacitor portion 202, the connecting metal 270 and the first metal layer 251 can be connected.
[0094] Referring to FIG. 6i, it can include the step of forming the wiring portion 201 on the passivation layer 262. The method of forming the wiring portion 201 can be performed by a known build-up process. At this time, the connecting metal 270 can be electrically connected to the second wiring layer 220 through the second via layer 230 of the wiring portion 201.
[0095] After that, referring to FIGS. 6i and 6j, the connecting structure 200 can be cut along the cutting line for singulation, and the connecting structure 200 can be completed by removing the release layer 601 and the support substrate 600.
[0096] FIGS. 7a to 7j are cross-sectional views schematically showing a method of manufacturing a connecting structure in a method of manufacturing a printed circuit board according to another example.
[0097] Referring to FIG. 7g, the step of forming the connecting metal 270 can be performed before the step of forming the passivation layer 262, and can be performed as being formed on each side portion of the unit laminate of the capacitor portion 202. The step of forming the connecting metal 270 can be performed by plating, and can be patterned by performing electrolytic plating, but is not limited thereto, and can further include processes such as electroless plating or sputtering as required.
[0098] Since the steps other than the description of FIG. 7g are the same as those of the method of manufacturing the connecting structure of the printed circuit board according to an example, duplicate descriptions thereof are omitted.
[0099] FIGS. 8a to 8k are cross-sectional views schematically showing a method of manufacturing a connecting structure in a method of manufacturing a printed circuit board according to still another example.
[0100] Referring to FIG. 8c, it can include the step of forming an inclined surface when cutting the laminate of the capacitor portion 202 into unit laminates. After forming a trapezoidal resist 610 on the laminate of the capacitor portion 202, an inclined surface can be formed on the side of the unit laminate through an etching process. At this time, a dry etching method can be used, but it is not necessarily limited to this. Any process in which an inclined surface can be formed along the resist 610 can be used without limitation. A known etching resist can be used for the resist 610. At this time, in FIG. 8c, it is depicted that the inclined surface of the resist 610 and the inclined surface of the laminate are substantially the same, but it is not limited to this. The inclined surface of the resist and the inclined surface of the laminate can also be different from each other. Since the side surface of the laminate has an inclined surface, the solution may easily penetrate when removing a part of the metal layer in a subsequent step, and vapor deposition, coating, or plating can be easily performed in the steps of forming the insulating material 261 and forming the connecting metal 270.
[0101] Thereafter, referring to FIG. 8d, it can include the step of removing the resist 610, and the step of removing the resist 610 can use a known method for removing a resist without limitation.
[0102] Referring to FIG. 8h, the connecting metal 270 can be formed along the inclined surface of the unit laminate of the capacitor portion 202. The step of forming the connecting metal 270 can be performed before the step of forming the passivation layer 262, and can be performed by being formed on each side of the unit laminate of the capacitor portion 202. The step of forming the connecting metal 270 can be performed by plating, and can be electrolytically plated and patterned, but it is not limited to this. If necessary, it can further include processes such as electroless plating or sputtering.
[0103] The steps other than the description for FIGS. 8c, 8d, and 8h are the same as those of the manufacturing method of the connection structure of the printed circuit board according to one example and the manufacturing method of the connection structure of the printed circuit board according to another example. Thus, duplicate descriptions thereof are omitted.
[0104] In the present disclosure, the meaning in cross-section can mean the cross-sectional shape when the object is cut vertically or the cross-sectional shape when the object is viewed in a side view. Further, the meaning on a plane can be the shape when the object is cut horizontally or the planar shape when the object is viewed in a top view or a bottom view.
[0105] In the present disclosure, terms such as upper side, upper part, and upper surface are used to mean the direction toward the surface on which electronic components can be mounted, based on the cross-section of the drawing for convenience, and terms such as lower side, lower part, and lower surface are used for the opposite direction. However, this defines a direction for convenience of explanation, and the scope of rights of the claims is not particularly limited by the description regarding such a direction.
[0106] In the present disclosure, the meaning of "connected" is a concept that includes not only the case of direct connection but also the case of indirect connection via an adhesive layer or the like. Further, the meaning of "electrically connected" is a concept that includes all cases of physical connection and non-connection. Furthermore, expressions such as first, second, etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the component. In some cases, without departing from the scope of rights, the first component can also be named the second component, and similarly, the second component can also be named the first component.
[0107] The expression "an example used in the present disclosure" does not mean the same embodiment as each other, but is provided to emphasize and explain each unique feature different from each other. However, the above-presented example does not exclude being realized in combination with the features of other examples. For example, even if a matter described in a specific example is not described in other examples, it can be understood as an explanation related to other examples as long as there is no explanation contrary to or conflicting with that matter in other examples.
[0108] The terms used in the present disclosure are merely used to explain an example and are not intended to limit the present disclosure. At this time, the singular expression includes the plural expression unless the context clearly indicates otherwise.
Explanation of Reference Numerals
[0109] 100 Substrate portion 110 First insulating layer 120 First wiring layer 130 First via layer 200 Connection structure 201 Wiring portion 202 Capacitor portion 210 Second insulating layer 220 Second wiring layer 230 Second via layer 240 Dielectric layer 251 First metal layer 252 Second metal layer 261 Insulating material 262 Passivation layer 270 Connection metal 300 Adhesive layer 401 First semiconductor chip 402 Second semiconductor chip 500 Connection member 600 Support substrate 601 Release layer 610 Resist 1000 Electronic device 1010 Main board 1020 Chip-related components 1030 Network-related components 1040 Other components 1050 Camera module 1060 Antenna module 1070 Display 1080 Battery 1090 Signal line 1100 Smartphone 1110 Motherboard inside the smartphone 1120 Electronic components inside the smartphone 1121 Antenna module inside the smartphone 1130 Camera module inside the smartphone 1140 Speaker inside the smartphone
Claims
1. A substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a first via layer penetrating at least a part of the first insulating layer so as to connect the first insulating layers to each other; A connection structure disposed within the substrate portion, including a capacitor portion, a passivation layer covering the capacitor portion, and a wiring portion disposed on the passivation layer; The capacitor portion of the connection structure includes a plurality of dielectric layers, a first metal layer and a second metal layer alternately disposed with the plurality of dielectric layers interposed therebetween, a first insulating material disposed at the same level as the first metal layer on one side of the capacitor portion, a second insulating material disposed at the same level as the second metal layer on the other side opposite to the one side of the capacitor portion, a first connection metal connected to the first metal layer, and a second connection metal connected to the second metal layer, a printed circuit board.
2. The wiring portion of the connection structure includes a second insulating layer, a second wiring layer disposed on the second insulating layer, and a second via layer penetrating at least a part of the second insulating layer so as to connect the second wiring layers to each other; The second via layer connects the second wiring layer and the first connection metal to each other and connects the second wiring layer and the second connection metal to each other, the printed circuit board according to claim 1.
3. The wiring density of the second wiring layer is greater than the wiring density of the first wiring layer, the printed circuit board according to claim 2.
4. The first connection metal penetrates the plurality of dielectric layers, the first metal layer, and the second insulating material; The second connection metal penetrates the plurality of dielectric layers, the second metal layer, and the first insulating material, the printed circuit board according to claim 1.
5. The first connection metal is disposed on the other side of the capacitor portion and is connected to the first metal layer; The second connection metal is disposed on one side of the capacitor portion and is connected to the second metal layer, the printed circuit board according to claim 1.
6. The capacitor portion has inclined surfaces on both one side and the other side, the printed circuit board according to claim 1.
7. The capacitor portion has a trapezoidal shape such that the width at the upper side is narrower than the width at the lower side, the printed circuit board according to claim 1.
8. The first insulating material and the second insulating material are respectively disposed between the plurality of dielectric layers, the printed circuit board according to claim 1.
9. The printed circuit board according to claim 8, wherein the thickness of the first insulating material is substantially the same as the thickness of the first metal layer.
10. The printed circuit board according to claim 1, further comprising an adhesive layer interposed between the connection structure and the substrate portion.
11. The printed circuit board according to claim 1, wherein the first insulating material extends to the second insulating material, and the first insulating material and the second insulating material are integrated.
12. A substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer, A connection structure disposed within the substrate portion, including a capacitor portion, a passivation layer covering the capacitor portion, and a wiring portion disposed on the passivation layer, The capacitor portion includes a plurality of dielectric layers, a first metal layer and a second metal layer alternately disposed with the plurality of dielectric layers interposed therebetween, a first connection metal connected to the first metal layer, and a second connection metal connected to the second metal layer. The printed circuit board, wherein the first metal layer includes a metal different from the metal of the second metal layer.
13. The printed circuit board according to claim 12, wherein the first metal layer includes molybdenum (Mo).
14. The printed circuit board according to claim 13, wherein the second metal layer includes titanium (Ti).
15. Each of the first connection metal and the second connection metal includes a metal different from the first metal layer, The printed circuit board according to claim 12, wherein each of the first connection metal and the second connection metal includes a metal different from the second metal layer.
16. The printed circuit board according to claim 15, wherein each of the first connection metal and the second connection metal includes copper (Cu).
17. The printed circuit board according to claim 12, wherein each of the plurality of dielectric layers includes an oxide and / or a nitride.
18. The plurality of dielectric layers are each SiO ２ , Si ３ N ４ , Al ２ O ３ , AlN, MgO, Y ２ O ３ , HfO ２ , ZrO ２ and Ta ２ O ３ The printed circuit board according to claim 17, comprising at least one material of.