Multi-state pulsing for achieving balance between bow control and mask selectivity

Abstract

To provide methods and systems for multi-state pulsing for achieving a balance between bow control and mask selectivity.SOLUTION: A method includes generating a primary radio frequency (RF) signal 212. The primary RF signal is pulsed among three states including a first state S1, a second state S2, and a third state S0. The method further includes generating a secondary RF signal 214. The secondary RF signal is pulsed among the three states. During the first state, a power level P4 of the primary RF signal is greater than a power level P1 of the secondary RF signal. Also, during the second state, a power level P3 of the secondary RF signal is greater than a power level P2 of the primary RF signal. During the third state, power levels of the primary and secondary RF signals are approximately equal.SELECTED DRAWING: Figure 2C

Description

Technical Field

[0001] Embodiments described in the present disclosure relate to a multi-state pulsing system and method for achieving a balance between warp control and mask selection ratio.

Background Art

[0002] The description of the background art provided herein is intended to schematically present the background of the present disclosure. The research by the inventors within the scope described in this background art, and other aspects of the description that may not be recognized as prior art at the time of filing, are not recognized as prior art to the present disclosure, either explicitly or implicitly.

[0003] A radio frequency (RF) generator generates an RF signal and supplies the RF signal to a plasma reactor via a matching circuit. The plasma reactor has a semiconductor wafer, and the semiconductor wafer is etched when an RF signal is supplied to the plasma reactor and an etching gas is supplied. However, a desired selection ratio for the semiconductor wafer cannot be obtained during the etching of the semiconductor wafer.

[0004] In such a situation, embodiments described in the present disclosure are provided.

Summary of the Invention

[0005] Embodiments of the present disclosure provide a multi-state pulsing apparatus, method, and computer program for achieving a balance between warp control and mask selection ratio. It should be recognized that the present embodiments can be realized in various forms, such as, for example, a process, an apparatus, a system, hardware, or a method recorded on a computer-readable medium. Some embodiments will be described below.

[0006] In one embodiment, a three-state radio frequency (RF) pulsing method is described that eliminates the trade-off between sidewall polymer passivation and mask selectivity ratio. The trade-off between sidewall polymer passivation and mask selectivity ratio creates a constraint in achieving a pitch for further device size reduction. As an example, the three-state RF pulsing method includes synchronously pulsing a low-frequency RF generator and a high-frequency RF generator periodically among three states.

[0007] In one embodiment, a multi-state pulsing method is described for achieving a balance between warp control and mask selectivity ratio. The method includes generating a primary RF signal. The primary RF signal is pulsed among three states including a first state, a second state, and a third state. The method further includes generating a secondary RF signal. The secondary RF signal is pulsed among the three states. In the first state, the power level of the primary RF signal is greater than the power level of the secondary RF signal. Also, in the second state, the power level of the secondary RF signal is greater than the power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal.

[0008] In one embodiment, a controller is described. The controller includes a processor that controls a primary RF generator to generate a primary RF signal. The processor controls the primary RF generator to pulse the primary RF signal among three states including a first state, a second state, and a third state. Also, the processor controls a secondary RF generator to generate a secondary RF signal. The processor controls the secondary RF generator to pulse the secondary RF signal among these three states. In the first state, the power level of the primary RF signal is greater than the power level of the secondary RF signal. In the second state, the power level of the secondary RF signal is greater than the power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are approximately equal. The controller includes a memory device coupled to the processor.

[0009] In one embodiment, the processor controls to make the duty cycle of the first state smaller than the duty cycle of the third state. Also, the processor controls to make the duty cycle of the second state smaller than the duty cycle of the third state.

[0010] In one embodiment, the power level of the primary RF signal in the first state is at least 6 times, and at most 10 times greater than the power level of the secondary RF signal in the first state.

[0011] In one embodiment, the power level of the primary RF signal in the second state is at least 20 percent and less than 100 percent of the power level of the secondary RF signal in the second state.

[0012] In one embodiment, a system is described. The system includes a primary RF generator configured to generate a primary RF signal. The system further includes a secondary RF generator configured to generate a secondary RF signal. The system includes an impedance matching circuit coupled to the primary RF generator via a first RF cable and coupled to the secondary RF generator via a second RF cable. The impedance matching circuit receives the primary RF signal via the first RF cable and receives the secondary RF signal via the second RF cable and outputs a modified RF signal. Also, the system includes a plasma chamber coupled to the impedance matching circuit and receiving the modified RF signal. The system includes a computer coupled to the RF generator. The computer controls the primary RF generator to pulse the primary RF signal among three states including a first state, a second state, and a third state. The computer further controls the secondary RF generator to pulse the secondary RF signal among these three states. In the first state, the power level of the primary RF signal is greater than the power level of the secondary RF signal. Also, in the second state, the power level of the secondary RF signal is greater than the power level of the primary RF signal. In the third state, the power levels of the primary RF signal and the secondary RF signal are substantially equal.

[0013] In one embodiment, the computer controls to make the duty cycle of the first state smaller than the duty cycle of the third state. The computer controls to make the duty cycle of the second state smaller than the duty cycle of the third state.

[0014] In one embodiment, the power level of the primary RF signal in the first state is at least six times, and at most ten times, greater than the power level of the secondary RF signal in the first state.

[0015] In one embodiment, the power level of the primary RF signal in the second state is at least 20 percent and less than 100 percent of the power level of the secondary RF signal in the second state.

[0016] In one embodiment, a system is described. The system includes a primary RF generator configured to generate a primary RF signal in a first frequency range. The system further includes a secondary RF generator configured to generate a secondary RF signal in a second frequency range. The system includes an impedance matching circuit coupled to the primary RF generator via a first RF cable and coupled to the secondary RF generator via a second RF cable. The impedance matching circuit receives the primary RF signal via the first RF cable and receives the secondary RF signal via the second RF cable and outputs a modified RF signal. The system includes a plasma chamber coupled to the impedance matching circuit and receiving the modified RF signal. The system further includes a gas source fluidly connected to the plasma chamber. The gas source includes a tungsten-containing gas source and an etching component gas source. The system includes a computer coupled to the RF generators. The computer controls the tungsten-containing gas source and the etching component gas source. The computer further controls the primary RF generator to pulse the primary RF signal among at least three states including a first state, a second state, and a third state. Also, the computer controls the secondary RF generator to pulse the secondary RF signal among these at least three states. The power level of the primary RF signal in the second state is less than 80% of the power level of the primary RF signal in the first state. Also, the power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state. Further, the power level of the secondary RF signal in the third state is less than 20% of the power level of the secondary RF signal in the second state. Gas flows from the tungsten-containing gas source and the etching component gas source in the first state, the second state, and the third state.

[0017] In one embodiment, the computer controls to make the duty cycle of the first state smaller than the duty cycle of the third state. The computer controls to make the duty cycle of the second state smaller than the duty cycle of the third state.

[0018] In one embodiment, the duty cycle of the first state ranges from 3 percent to 25 percent of the clock cycle of the clock signal.

[0019] Also, in one embodiment, the duty cycle of the second state ranges from 3 percent to 50 percent of the clock cycle of the clock signal.

[0020] In one embodiment, the duty cycle of the third state ranges from 25 percent to 94 percent of the clock cycle of the clock signal, and the sum of the duty cycles of the first, second, and third states is equal to 100 percent of the clock cycle.

[0021] In one embodiment, the first frequency range is from 80 kHz to 14 MHz (including the boundaries), and the second frequency range is from 15 MHz to 120 MHz (including the boundaries).

[0022] In one embodiment, the tungsten-containing gas is tungsten fluoride.

[0023] In one embodiment, the tungsten-containing gas is tungsten hexafluoride.

[0024] In one embodiment, the ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and the ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1.

[0025] In one embodiment, the computer adjusts the first state, the second state, and the third state to minimize necking and warping using a metal fluoride or a tungsten-containing passivation agent.

[0026] As an advantage of the three-state RF pulsing method described herein, it is possible to increase the mask selectivity while reducing the warp at the sidewalls of the nitride layer by more than about 1.5 nanometers (nm). For example, by achieving a reduction in warp, the mask selectivity increases by about 15% to 20% compared to the mask selectivity in the case of two-state pulsing.

[0027] A further advantage of the multi-state pulsing system and method described herein is that a balance between warp control and mask selectivity can be achieved. This balance is achieved by pulsing each of the low-frequency RF generator and the high-frequency RF generator in three states. For example, the low-frequency RF generator is pulsed at a much higher power level compared to the power level of the high-frequency RF generator in the first state. The high-frequency RF generator is pulsed at a higher power level compared to the power level of the low-frequency RF generator in the second state. In the third state, the power levels of the low-frequency RF generator and the high-frequency RF generator are nearly zero. By pulsing the low-frequency RF generator and the high-frequency RF generator in this way, a balance is achieved. By achieving this balance, it becomes easier to etch high aspect ratio substrate features.

[0028] Other aspects will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0029] Each embodiment will be understood by referring to the following description in conjunction with the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0052] In the following embodiments, a multi-state pulsing system and method for achieving a balance between warp control and mask selection ratio will be described. It is clear that these embodiments may be implemented with some or all of these specific details excluded. In other examples, to avoid the embodiments becoming unnecessarily ambiguous, detailed descriptions of well-known process steps are omitted.

[0053] FIG. 1 shows an embodiment of a system 100 for explaining the three-state pulsing of a plurality of radio frequency (RF) signals to achieve a balance between warp control and mask selection ratio. System 100 includes an RF generator RFGx, another RF generator RFGy, an impedance matching network IMN, a plasma chamber 106, and a host computer 110.

[0054] Examples of the RF generator RFGx include low-frequency RF generators such as an RF generator having an operating frequency of 400 kilohertz (kHz), 2 megahertz (MHz), or 13.56 MHz. Examples of the RF generator RFGy include high-frequency RF generators such as an RF generator having an operating frequency of 27 MHz or 60 MHz. Note that the operating frequency of the high-frequency RF generator is greater than that of the low-frequency RF generator.

[0055] The impedance matching network IMN is a network of circuit components such as inductors, capacitors, and resistors. For example, the impedance matching network is a circuit including a shunt capacitor and a series capacitor. One end of the shunt capacitor is coupled to the series capacitor, and the other end is coupled to the ground potential. The series capacitor is coupled between the input (such as input I2x or input I2y) of the impedance matching network IMN and the output O2 of the impedance matching network IMN. As another example, one or more circuit components of the impedance matching network IMN are serially or parallely coupled to one or more circuit components of the impedance matching network IMN. The impedance matching network IMN has a branch including one or more circuit components, and this branch is coupled between the input I2x and the output O2. Similarly, the impedance matching network IMN has another branch including one or more circuit components, and this branch is coupled between the input I2y and the output O2.

[0056] The plasma chamber 106 includes a substrate support 104 such as a chuck. The chuck includes a lower electrode embedded in the chuck, a facility plate located below the lower electrode, and a ceramic plate located above the lower electrode. The plasma chamber 106 further includes an upper electrode 118 coupled to the ground potential. Examples of the host computer 110 include a desktop computer, a laptop computer, a controller, a tablet, and a smartphone.

[0057] The RF generator RFGx includes a digital signal processor (DSP) DSPx, a power controller PWRS1x, another power controller PWRS2x, yet another power controller PWRS0x, an automatic frequency tuner (AFT) AFTx, and a power supply PSx. Examples of DSPs used herein include a controller including a microprocessor, an application specific integrated circuit (ASIC), or a programmable logic circuit (PLD). The DSP's controller also includes a memory device capable of fetching multiple data or instructions simultaneously. The DSP's memory device is coupled to the DSP's microprocessor, ASIC, or PLD. Examples of memory devices used herein include ROM, RAM, flash memory, an array of storage disks, a hard disk, and the like.

[0058] Examples of power controllers used herein include a microcontroller. By way of illustration, the power controller includes a microprocessor, an ASIC, or a PLD. The power controller further includes a memory device coupled to the power controller's microprocessor, ASIC, or PLD.

[0059] Examples of tuners used herein include a microcontroller. By way of illustration, the tuner includes a microprocessor, an ASIC, or a PLD. The tuner further includes a memory device coupled to the tuner's microprocessor, ASIC, or PLD.

[0060] Examples of power supplies used herein include an electronic oscillator or an RF oscillator that generates a periodic oscillating electronic signal (such as a sinusoidal RF signal).

[0061] The digital signal processor DSPx is coupled to the power controllers PWRS1x, PWRS2x, PWRS0x and the automatic frequency tuner AFTx. Further, each of the power controllers PWRS1x, PWRS2x, PWRS0x is coupled to the power supply PSx. The automatic frequency tuner AFTSx is also coupled to the power supply PSx.

[0062] The RF generator RFGy includes a digital signal processor DSPy, a power controller PWRS1y, another power controller PWRS2y, yet another power controller PWRS0y, an automatic frequency tuner AFTy, and a power supply PSy. The digital signal processor DSPy is coupled to the power controllers PWRS1y, PWRS2y, PWRS0y and the automatic frequency tuner AFTy. Further, each of the power controllers PWRS1y, PWRS2y, PWRS0y is coupled to the power supply PSy. The automatic frequency tuner AFTSy is also coupled to the power supply PSy.

[0063] The host computer includes a processor 112 and a memory device 114. The processor 112 is coupled to the memory device 114. Examples of processors used herein include microprocessors, ASICs, central processing units (CPUs), or PLDs.

[0064] The processor 112 is coupled to the digital signal processor DSPx via a transfer cable 120x and to the digital signal processor DSPy via another transfer cable 120y. Examples of transfer cables used herein include a parallel transfer cable that facilitates parallel transfer of data between the processor 112 and the DSP, a serial transfer cable that facilitates serial transfer of data between the processor 112 and the DSP, and a USB transfer cable that facilitates data transfer between the processor 112 and the DSP according to the USB standard.

[0065] The power supply PSx is coupled to the input I2x of the impedance matching network IMN via an RF cable 102x. For example, the output O1x of the RF generator RFGx is coupled to the input I2x via an RF cable 120x. Further, the power supply PSy is coupled to the input I2y of the impedance matching network IMN via an RF cable 102y. For example, the output O1y of the RF generator RFGy is coupled to the input I2y via an RF cable 120y.

[0066] The output O2 of the impedance matching network IMN is coupled to the lower electrode of the substrate support 104 via the RF transmission line 122. Examples of the RF transmission line 122 include a conductor surrounded by an insulator surrounded by an RF sleeve (such as a solid aluminum rod). The insulator can be a dielectric material such as Teflon (registered trademark). Another example of the RF transmission line 122 includes a conductor coupled to an RF cylinder having an inner conductive rod and an outer housing via one or more RF straps. The inner conductive rod of the RF cylinder is coupled to the lower electrode. As described in the above examples, the conductor is surrounded by an insulator surrounded by an RF sleeve. The conductor of the RF transmission line 122 is coupled to the output O2 of the impedance matching network IMN.

[0067] The processor 112 generates a clock signal and a digital pulse signal 108 synchronized with the clock signal. Examples of the clock signal and the digital pulse signal 108 will be described later. The digital pulse signal 108 has three states such as state S1, state S2, and state S0 as described later.

[0068] The processor 112 accesses (for example, reads or acquires) from the memory device 114 the power levels for state S1 of the RF signal 102x generated by the RF generator RFGx, the power levels for state S2 of the RF signal 102x, and the power levels for state S0 of the RF signal 102x. Further, the processor 112 accesses from the memory device 114a the power levels for state S1 of the RF signal 102y generated by the RF generator RFGy, the power levels for state S2 of the RF signal 102y, and the power levels for state S0 of the RF signal 102y. The RF signals 102x and 102y are each a sine wave signal.

[0069] Note that, in one embodiment, the power level for a certain state of the RF signal is the power level achieved by the RF signal during that state. For example, the power level for state S1 of the RF signal is the power level achieved during an instance when the digital pulse signal 108 is in state S1, the power level for state S2 of the RF signal is the power level achieved during an instance when the digital pulse signal 108 is in state S2, and the power level for state S0 of the RF signal is the power level achieved during an instance when the digital pulse signal 108 is in state S0.

[0070] The processor 112 transmits the power levels for states S1, S2, and S0 of the generated RF signal 102x, together with the identification information for each of states S1, S2, and S0, to the digital signal processor DSPx via the transfer cable 120x. When the digital signal processor DSPx receives the power levels for states S1, S2, and S0 of the RF signal 102x, together with the identification information for each state, it accesses the correspondence relationship (one-to-one mapping, link, one-to-one relationship, etc.) between the identification information for states S1 to S0 and the power controllers PWRS1x, PWRS2x, and PWRS0x from the memory device of the digital signal processor DSPx. Then, it transmits the power level for state S1 to the power controller PWRS1x, the power level for state S2 to the power controller PWRS2x, and the power level for state S0 to the power controller PWRS0x. Each of the power controllers PWRS1x, PWRS2x, and PWRS0x stores the respective power level received from the digital signal processor DSPx in the memory device of the power controller.

[0071] Similarly, the processor 112 transmits the power levels for the states S1, S2, S0 of the generated RF signal 102y, together with the identification information for each of the states S1, S2, S0, to the digital signal processor DSPy via the transfer cable 120y. When the digital signal processor DSPy receives the power levels for the states S1, S2, S0 of the RF signal 102y together with the identification information for each state, it accesses the correspondence (such as one-to-one mapping, link, one-to-one relationship, etc.) between the identification information for the states S1, S2, S0 and the power controllers PWRS1y, PWRS2y, PWRS0y from the memory device of the digital signal processor DSPy. Then, it transmits the power level for state S1 to the power controller PWRS1y, the power level for state S2 to the power controller PWRS2y, and the power level for state S0 to the power controller PWRS0y. Each of the power controllers PWRS1y, PWRS2y, PWRS0y stores the respective power levels received from the digital signal processor DSPy in the memory device of the power controller.

[0072] The processor 112 transmits the digital pulse signal 108 to the digital signal processor DSPx via the transfer cable 120x and, at the same time, transmits the digital pulse signal 108 to the digital signal processor DSPy via the transfer cable 120y. When receiving the digital pulse signal 108, the digital signal processor DSPx identifies the state of the digital pulse signal 108 from the logic level of the digital pulse signal 108. For example, when the digital signal processor DSPx determines that the logic level of the digital pulse signal 108 is 0, it identifies that the state of the digital pulse signal 108 is S1; when it determines that the logic level of the digital pulse signal 108 is 1, it identifies that the state of the digital pulse signal 108 is S2; and when it determines that the logic level of the digital pulse signal 108 is 2, it identifies that the state of the digital pulse signal 108 is S0.

[0073] When the digital pulse signal 108 is in state S1, upon identifying that the state of the digital pulse signal 108 is S1, the digital signal processor DSPx transmits a control signal to the power controller PWRS1x. Upon receiving the control signal when the digital pulse signal 108 is in state S1, the power controller PWRS1x accesses the power level for state S1 from the memory device of the power controller PWRS1x, generates a signal including the power level for state S1, and transmits that signal to the power supply PSx. When the power supply PSx receives a signal including the power level for state S1 from the power controller PWRS1x when the digital pulse signal 108 is in state S1, the power supply PSx generates a part of the RF signal 102x having the power level for state S1.

[0074] Similarly, when the digital pulse signal 108 is in state S2, upon identifying that the state of the digital pulse signal 108 is S2, the digital signal processor DSPx transmits a control signal to the power controller PWRS2x. Upon receiving the control signal when the digital pulse signal 108 is in state S2, the power controller PWRS2x accesses the power level for state S2 from the memory device of the power controller PWRS2x, generates a signal including the power level for state S2, and transmits that signal to the power supply PSx. When the power supply PSx receives a signal having the power level for state S2 from the power controller PWRS1x when the digital pulse signal 108 is in state S2, the power supply PSx transitions the RF signal 102x from the power level for state S1 to the power level for state S2 and generates a part of the RF signal 102x having the power level for state S2.

[0075] Also, when the digital pulse signal 108 is in state S0, upon identifying that the state of the digital pulse signal 108 is S0, the digital signal processor DSPx transmits a control signal to the power controller PWRS0x. Upon receiving the control signal when the digital pulse signal 108 is in state S0, the power controller PWRS0x accesses the power level for state S0 from the memory device of the power controller PWRS0x, generates a signal including the power level for state S0, and transmits that signal to the power supply PSx. When receiving a signal having the power level for state S0 from the power controller PWRS0x when the digital pulse signal 108 is in state S0, the power supply PSx transitions the RF signal 102x from the power level for state S2 to the power level for state S0 and generates a part of the RF signal 102x having the power level for state S0.

[0076] Similarly, upon receiving the digital pulse signal 108, the digital signal processor DSPy identifies the state of the digital pulse signal 108 from the logic level of the digital pulse signal 108 in the same way as the digital signal processor DSPx described above identifies the state of the digital pulse signal 108. For example, when the digital signal processor DSPy determines that the logic level of the digital pulse signal 108 is 0, it identifies that the state of the digital pulse signal 108 is S1; when it determines that the logic level of the digital pulse signal 108 is 1, it identifies that the state of the digital pulse signal 108 is S2; and when it determines that the logic level of the digital pulse signal 108 is 2, it identifies that the state of the digital pulse signal 108 is S0.

[0077] When the digital pulse signal 108 is in state S1, if it is determined that the state of the digital pulse signal 108 is S1, the digital signal processor DSPy sends a control signal to the power controller PWRS1y. Also, when the power controller PWRS1y receives a control signal while the digital pulse signal 108 is in state S1, the power controller PWRS1y accesses the power level for state S1 from the memory device of the power controller PWRS1y, generates a signal including the power level for state S1, and sends that signal to the power supply PSy. When the power supply PSy receives a signal having the power level for state S1 from the power controller PWRS1y while the digital pulse signal 108 is in state S1, the power supply PSy generates a part of the RF signal 102y having the power level for state S1.

[0078] Similarly, when the digital pulse signal 108 is in state S1, if it is determined that the state of the digital pulse signal 108 is S2, the digital signal processor DSPy sends a control signal to the power controller PWRS2x. When the power controller PWRS2y receives a control signal while the digital pulse signal 108 is in state S2, the power controller PWRS2y accesses the power level for state S2 from the memory device of the power controller PWRS2y, generates a signal including the power level for state S2, and sends that signal to the power supply PSy. When the power supply PSy receives a signal having the power level for state S2 from the power controller PWRS1y while the digital pulse signal 108 is in state S2, the power supply PSy transitions the RF signal 102y from the power level for state S1 to the power level for state S2 and generates a part of the RF signal 102y having the power level for state S2.

[0079] Also, when the digital pulse signal 108 is in state S0, upon identifying that the state of the digital pulse signal 108 is S0, the digital signal processor DSPy transmits a control signal to the power controller PWRS0y. Upon receiving the control signal when the digital pulse signal 108 is in state S0, the power controller PWRS0y accesses the power level for state S0 from the memory device of the power controller PWRS0y, generates a signal including the power level for state S0, and transmits that signal to the power supply PSy. When receiving a signal having the power level for state S0 from the power controller PWRS0y when the digital pulse signal 108 is in state S0, the power supply PSy transitions the RF signal 102y from the power level for state S2 to the power level for state S0, and generates a part of the RF signal 102y having the power level for state S0.

[0080] The RF signal 102x is supplied from the power supply PSx through the output O1x and the RF cable 116x to the input I2x of the impedance matching network IMN. Also, the RF signal 102y is supplied from the power supply Psy through the output O1y and the RF cable 116y to the input I2y of the impedance matching network IMN. The impedance matching network IMN receives the RF signal 102x at the input I2x. Then, as the RF signal 102x is transferred through the branch circuit coupled to the input I2x in the impedance matching network IMN, the impedance of the RF signal RF102x is corrected by the branch circuit, and a first corrected RF signal is output. Similarly, the impedance matching network IMN receives the RF signal 102y at the input I2y. Then, as the RF signal 102y is transferred through the branch circuit coupled to the input I2y in the impedance matching network IMN, the impedance of the RF signal RF102y is corrected by the branch circuit, and a second corrected RF signal is output. The impedances of the RF signals 102x and 102y are corrected to match the impedance of the load coupled to the output O2 and the impedance of the sources coupled to the inputs I2x and I2y. The load coupled to the output O2 is, for example, the RF transmission line 122 and the plasma chamber 106. The sources coupled to the inputs I2x and I2y are, for example, the RF cables 116x and 116y and the RF generators RFGx and RFGy. The branch circuit coupled to the input I2x is connected to the branch circuit coupled to the input I2y at the output O2, and the first and second corrected RF signals are integrated, and an integrated corrected RF signal 124 is output at the output O2.

[0081] The integrated correction RF signal 124 is transmitted from the output O2 of the impedance matching network IMN through the RF transmission line 122 to the lower electrode of the substrate support 104. Further, one or more process gases (such as a fluorine-containing gas, an oxygen-containing gas, or a combination thereof) are supplied to the gap between the upper electrode 118 and the substrate support 104 in the plasma chamber 106. When the integrated correction RF signal 124 and one or more process gases are simultaneously supplied to the plasma chamber 106, plasma is ignited or maintained in the gap to process the substrate S. Examples of the substrate S include a semiconductor wafer formed on a substrate layer and a substrate stack formed on a substrate layer. Examples of the processing of the substrate S include depositing one or more materials (such as an oxide layer, a nitride layer, a silicon nitride layer, a mask layer, or a combination of two or more thereof) on the substrate layer. Other examples of substrate processing include etching of the substrate S, sputtering of the substrate S, or cleaning of the substrate S.

[0082] In one embodiment, the lower electrode of the substrate support 104 is coupled to a ground potential, and the upper electrode 118 is coupled to the output O2 of the impedance matching network IMN.

[0083] In one embodiment, in addition to the RF generators RFGx and RFGy being coupled to the lower electrode of the substrate support 104 through the impedance matching network IMN, one or more RF generators are coupled to the upper electrode 118 through the impedance matching network.

[0084] In one embodiment, the functions or operations described herein as being performed by one or more of digital signal processor DSPx, power controller PWRS1x, power controller PWRS2x, power controller PWRS0x, and automatic frequency tuner AFTSx are performed by a controller or processor of RF generator RFGx. For example, the functions described herein as being performed by power controller PWRS1x, power controller PWRS2x, power controller PWRS0x, and automatic frequency tuner AFTx are performed by digital signal processor DSPx.

[0085] Similarly, in one embodiment, the functions or operations described herein as being performed by one or more of digital signal processor DSPy, power controller PWRS1x, power controller PWRS2y, power controller PWRS0y, and automatic frequency tuner AFTSy are performed by a controller or processor of RF generator RFGy. For example, the functions described herein as being performed by power controller PWRS1y, power controller PWRS2y, power controller PWRS0y, and automatic frequency tuner AFTy are performed by digital signal processor DSPy.

[0086] In one embodiment, the functions or operations described herein as being performed by one or more of digital signal processor DSPx, power controller PWRS1x, power controller PWRS2x, power controller PWRS0x, automatic frequency tuner AFTSx, digital signal processor DSPy, power controller PWRS1y, power controller PWRS2y, power controller PWRS0y, and automatic frequency tuner AFTSy are performed by processor 112.

[0087] In one embodiment, the clock signal is generated by a clock source instead of processor 112.

[0088] Figure 2A is a diagram showing an embodiment of graph 202 of clock signal 204 which is the above-described clock signal. The clock signal 204 is generated by the processor 112. In graph 202, the logical level is plotted on the y-axis and time t is plotted on the x-axis. The y-axis of graph 202 includes logical level 0 and logical level 1. The x-axis of graph 202 includes a plurality of times t0, t1, t2, t3, t4, t5.

[0089] The time interval between any two consecutive times on the x-axis of graph 202 is the same. For example, the time interval between time t0 and t1 is equal to the time interval between time t1 and t2, and the time interval between time t1 and t2 is equal to the time interval between time t2 and t3. The time interval between time t3 and t4 is equal to the time interval between time t2 and t3, and the time interval between time t4 and t5 is equal to the time interval between time t3 and t4. Time t1 is consecutive to time t0. Similarly, time t2 is consecutive to time t1, time t3 is consecutive to time t2, time t4 is consecutive to time t3, and time t5 is consecutive to time t4.

[0090] The clock signal 204 transitions periodically between logical level 0 and 1. For example, in the first half of cycle 1 of the clock signal 204, the clock signal 204 is at logical level 1. At time t1, the clock signal 204 transitions from logical level 1 to logical level 0. In the second half of cycle 1 of the clock signal 204, the clock signal 204 is at logical level 0. At time t2, the clock signal 204 transitions from logical level 0 to logical level 1. In the first half of cycle 2 of the clock signal 204, the clock signal 204 is at logical level 1. At time t3, the clock signal 204 transitions from logical level 1 to logical level 0. In the second half of cycle 2 of the clock signal, the clock signal is at logical level 0. At time t4, the clock signal 204 transitions from logical level 0 to logical level 1.

[0091] Cycle 2 of the clock signal 204 is consecutive to cycle 1 of the clock signal 204. For example, there are no other clock cycles between cycle 1 and cycle 2 of the clock signal 204. Cycle 1 occurs from time t0 to time t2, and cycle 2 occurs from time t2 to time t4.

[0092] FIG. 2B shows an embodiment of a graph 206 for explaining an embodiment of the digital pulse signal 208. The digital pulse signal 208 is an example of the digital pulse signal 108 in FIG. 1. In the graph 206, the logical level of the digital pulse signal 208 is plotted on the y-axis, and time t is plotted on the x-axis. The y-axis of the graph 206 includes logical levels 0, 1, and 2. The x-axis of the graph 206 includes time t0, time t0a, time t0b, time t1, time t2, time t2a, time t2b, time t3, and time t4. Time t0a occurs between time t0 and time t0b, and time t0b occurs between time t0a and time t1. Further, time t2a occurs between time t2 and time t2b, and time t2b occurs between time t2a and time t3.

[0093] The digital pulse signal 208 periodically transitions among states S1, S2, and S0. For example, the digital pulse signal 208 has a state S1 defined by a logical level 0 from time t0 to time t0a. Illustratively, when the digital pulse signal 208 is in state S1, the digital pulse signal 208 is at logical level 0. The digital pulse signal 208 transitions from logical level 0 to logical level 1 at time t0a. The state S2 of the digital pulse signal 208 is defined by a logical level 1. Illustratively, when the digital pulse signal 208 is in state S2, the digital pulse signal 208 is at logical level 1.

[0094] The digital pulse signal 208 is in state S2 from time t0a to time t0b. At time t0b, the digital pulse signal 208 transitions from state S2 to state S0 defined by logic level 2. By way of example, when the digital pulse signal 208 is in state S0, the digital pulse signal 208 is at logic level 2. The digital pulse signal 208 is in state S0 from time t0b to time t2. At time t2, the digital pulse signal 208 transitions from state S0 back to state S1.

[0095] The digital pulse signal 208 is in state S1 from time t2 to time t2a. At time t2a, the digital pulse signal 208 transitions from state S1 to state S2. The digital pulse signal 208 is in state S2 from time t2a to time t2b. At time t2b, the digital pulse signal 208 transitions from state S2 to state S0. The digital pulse signal 208 is in state S0 from time t2b to time t4. At time t4, the digital pulse signal 208 transitions from state S0 back to state S1.

[0096] Note that the states S1, S2, and S0 of the digital pulse signal 208 each occur in a plurality of instances. For example, the first instance of the state S1 of the digital pulse signal 208 occurs between times t0 and t0a, and the second instance of the state S1 of the digital pulse signal 208 occurs between times t2 and t2a. As another example, the first instance of the state S2 of the digital pulse signal 208 occurs between times t0a and t0b, and the second instance of the state S2 of the digital pulse signal 208 occurs between times t2a and t2b. As yet another example, the first instance of the state S0 of the digital pulse signal 208 occurs between times t0b and t2, and the second instance of the state S0 of the digital pulse signal 208 occurs between times t2a and t4. As another example, the first instance of the state S2 of the digital pulse signal 208 is consecutive to the first instance of the state S1 of the digital pulse signal 208, and the first instance of the state S0 of the digital pulse signal 208 is consecutive to the first instance of the state S2 of the digital pulse signal 208. The second instance of the state S1 of the digital pulse signal 208 is consecutive to the first instance of the state S0 of the digital pulse signal 208. Also, the second instance of the state S2 of the digital pulse signal 208 is consecutive to the second instance of the state S1 of the digital pulse signal 208, and the second instance of the state S0 of the digital pulse signal 208 is consecutive to the second instance of the state S2 of the digital pulse signal 208.

[0097] FIG. 2C shows an embodiment of a graph 210 for explaining an embodiment of an RF signal 212 generated by an RF generator RFGx (FIG. 1) and an embodiment of an RF signal 214 generated by an RF generator RFGy (FIG. 1). The RF signal 212 is an example of the RF signal 102x (FIG. 1), and the RF signal 214 is an example of the RF signal 102y (FIG. 1).

[0098] RF signals 212 and 214 are synchronized with the digital pulse signal 208. For example, each of RF signals 212 and 214 starts a transition from state S1 to state S2 at time t0a when the digital pulse signal 208 transitions from state S1 to state S2. As another example, each of RF signals 212 and 214 starts a transition from state S2 to state S0 at time t0b when the digital pulse signal 208 transitions from state S2 to state S0. As yet another example, each of RF signals 212 and 214 starts a transition from state S0 to state S1 at time t2 when the digital pulse signal 208 transitions from state S0 to state S1.

[0099] Graph 210 plots the power levels of RF signals 212 and 214. For example, the y-axis of graph 210 includes power levels P0, P1, P2, P3, P4. Power level P1 is greater than power level P0. Also, power level P2 is greater than power level P1, and power level P3 is greater than power level P2. Power level P4 is greater than power level P3.

[0100] The power levels used herein are the envelopes of the RF signals (such as the peak-to-peak amplitude). For example, power levels P4, P2, P0 are the envelopes of RF signal 102x, and power levels P1, P3, P0 are the envelopes of RF signal 102y. As another example, the power level includes one or more peak-to-peak power values within a predetermined range from the power level (such as greater than or less than the value of the power level). As yet another example, the power level is a statistical value (such as an average value or a median value) of all the peak-to-peak power values of the power level. As another example, the power level is the maximum value of all the peak-to-peak power values of the power level. As yet another example, the power level is the minimum value of all the peak-to-peak power values of the power level.

[0101] Also, the first power level is different from the second power level. For example, one or more power values of power level P0 do not include one or more power values of power level P1. Also, one or more power values of power level P2 do not include one or more power values of each of power levels P0 and P1.

[0102] Also, in graph 210, time t is plotted on the x-axis. For example, the x-axis of graph 210 includes times t0, t0a, t0b, t1, t2, t2a, t2b, t3, t4.

[0103] RF signal 212 periodically transitions among states S1, S2, and S0 of RF signal 212 in the manner described below. Similarly, RF signal 214 periodically transitions among states S1, S2, and S0 of RF signal 214 in the manner described below.

[0104] State S1 of RF signal 212 is defined by power level P4. For example, when digital pulse signal 208 or RF signal 212 is in state S1, RF signal 212 is at power level P4.

[0105] RF signal 212 transitions from state S1 to state S2 within the time window starting from time t0a. State S2 of RF signal 212 is defined by power level P2. For example, when digital pulse signal 208 or RF signal 212 is in state S2, RF signal 212 is at power level P2.

[0106] Note that the RF signals described in this specification do not instantaneously transition from one state to the next consecutive state. For example, the transition of RF signal 212 from state S1 to state S2 does not occur instantaneously. By way of illustration, the transition of RF signal 212 from state S1 to state S2 occurs within a time window. As another example, the time window for a transition from a certain time, as used in this specification, is the period that occurs during the state after that time. By way of illustration, the time window starting from time t0a is the period that occurs while digital pulse signal 208 is in state S2 after time t0a. The period after time t0a is the period that occurs while digital pulse signal 208 is in state S2 from time t0a to the time between t0a and t0b.

[0107] The RF signal 212 transitions from state S2 to state S0 within the time window starting from time t0b. The state S0 of the RF signal 212 is defined by the power level P0. For example, when the digital pulse signal 208 or the RF signal 212 is in state S0, the RF signal 212 has the power level P0.

[0108] The RF signal 212 transitions from state S0 to state S1 within the time window starting from time t2. The RF signal 212 transitions from state S1 to state S2 within the time window starting from time t2a, and transitions from state S2 to state S0 within the time window starting from time t2b.

[0109] Similarly, when the digital pulse signal 208 is in state S1, the RF signal 214 has the power level P1. The state S1 of the RF signal 214 is defined by the power level P1. For example, when the digital pulse signal 208 or the RF signal 214 is in state S1, the RF signal 214 has the power level P1.

[0110] The RF signal 214 transitions from state S1 to state S2 within the time window starting from time t0a. The state S2 of the RF signal 214 is defined by the power level P3. For example, when the digital pulse signal 208 or the RF signal 214 is in state S2, the RF signal 214 has the power level P3.

[0111] The RF signal 214 transitions from state S2 to state S0 within the time window starting from time t0b. The state S0 of the RF signal 214 is defined by the power level P0. For example, when the digital pulse signal 208 or the RF signal 214 is in state S0, the RF signal 214 has the power level P0.

[0112] The RF signal 214 transitions from state S0 to state S1 within the time window starting from time t2. The RF signal 214 transitions from state S1 to state S2 within the time window starting from time t2a, and transitions from state S2 to state S0 within the time window starting from time t2b.

[0113] The state S1 of the RF signal 212 between time t0 and t0a is the first instance of the state S1 of the RF signal 212, and the state S1 of the RF signal 212 between time t2 and t2a is the second instance of the state S1 of the RF signal 212. Similarly, the state S2 of the RF signal 212 between time t0a and t0b is the first instance of the state S2 of the RF signal 212, and the state S2 of the RF signal 212 between time t2a and t2b is the second instance of the state S2 of the RF signal 212. Also, the state S0 of the RF signal 212 between time t0b and t2 is the first instance of the state S0 of the RF signal 212, and the state S0 of the RF signal 212 between time t2b and t4 is the second instance of the state S0 of the RF signal 212.

[0114] Similarly, the state S1 of the RF signal 214 between time t0 and t0a is the first instance of the state S1 of the RF signal 214, and the state S1 of the RF signal 214 between time t2 and t2a is the second instance of the state S1 of the RF signal 214. Similarly, the state S2 of the RF signal 214 between time t0a and t0b is the first instance of the state S2 of the RF signal 214, and the state S2 of the RF signal 214 between time t2a and t2b is the second instance of the state S2 of the RF signal 214. Also, the state S0 of the RF signal 214 between time t0b and t2 is the first instance of the state S0 of the RF signal 214, and the state S0 of the RF signal 214 between time t2b and t4 is the second instance of the state S0 of the RF signal 214.

[0115] FIG. 2D shows an embodiment of a graph 215 for explaining an embodiment of an RF signal 216 generated by an RF generator RFGx (FIG. 1) and an embodiment of an RF signal 218 generated by an RF generator RFGy (FIG. 1). The RF signal 216 is an example of the RF signal 102x (FIG. 1), and the RF signal 218 is an example of the RF signal 102y (FIG. 1).

[0116] Graph 215 plots the power levels of RF signals 216 and 218. Also, graph 215 plots time t on the x-axis. For example, the x-axis of graph 215 includes times t0, t2, t2, t3, t4. Note that the duty cycles of states S1 - S3 of RF signals 216 and 218 are different from the duty cycles of states S1 - S3 illustrated in FIG. 2C. For example, the duty cycle of state S1 of RF signals 216 and 218 is 25%, the duty cycle of state S2 of RF signals 216 and 218 is 40%, and the duty cycle of state S3 of RF signals 216 and 218 is 35%.

[0117] FIG. 3A shows an embodiment of a graph 302 for explaining an enlarged portion of an RF signal 212. Graph 302 plots the power level of RF signal 212 against time t. RF signal 212 transitions from power level P4 to power level P2 within a time window starting from t0a. For example, RF signal 212 transitions from power level P4 to power level P2 during the period from t0a to t0a1. Time t0a1 occurs when RF signal 212 or digital pulse signal 208 (FIG. 2B) is in state S2 and occurs between t0a and t0b. Similarly, RF signal 212 transitions from power level P2 to power level P0 within a time window starting from t0b.

[0118] FIG. 3B shows an embodiment of a graph 304 for explaining an enlarged portion of an RF signal 214. Graph 304 plots the power level of RF signal 214 against time t. RF signal 214 transitions from power level P1 to power level P3 within a time window starting from t0a. For example, RF signal 214 transitions from power level P1 to power level P3 during the period from t0a to t0a2. Time t0a2 occurs when RF signal 214 or digital pulse signal 208 (FIG. 2B) is in state S2 and occurs between t0a and t0b. Similarly, RF signal 214 transitions from power level P3 to power level P0 within a time window starting from t0b.

[0119] FIG. 4A is a diagram showing an embodiment of graph 202 of clock signal 204.

[0120] FIG. 4B is a diagram showing an embodiment of graph 402 for explaining an embodiment of digital pulse signal 404. Digital pulse signal 404 is an example of digital pulse signal 108 in FIG. 1. In graph 402, the logical level of digital pulse signal 404 is plotted on the y-axis and time t is plotted on the x-axis. The y-axis of graph 402 includes logical levels 0, 1, and 2. The x-axis of graph 402 includes time t0, time t0a, time t1, time t1a, time t2, time t2a, time t3, time t3a, and time t4. Time t1a occurs between time t1 and time t2, and time t3a occurs between time t3 and time t4.

[0121] Digital pulse signal 404 periodically transitions between states S1, S0, and S2. For example, digital pulse signal 404 has state S1 defined by logical level 0 from time t0 to time t0a. Illustratively, when in state S1, digital pulse signal 208 is at logical level 0. Digital pulse signal 404 transitions from logical level 0 to logical level 2 at time t0a. State S0 of digital pulse signal 404 is defined by logical level 2. Illustratively, when in state S0, digital pulse signal 404 is at logical level 2.

[0122] Digital pulse signal 404 is in state S0 from time t0a to time t1a. At time t1a, digital pulse signal 404 transitions from state S0 to state S2 defined by logical level 1. Illustratively, when in state S2, digital pulse signal 404 is at logical level 1.

[0123] At time t2, the digital pulse signal 404 transitions from state S2 back to state S1. The digital pulse signal 404 is in state S1 from time t2 to time t2a. The digital pulse signal 404 transitions from state S1 to state S0 at time t2a. The digital pulse signal 404 is in state S0 from time t2a to time t3a. At time t3a, the digital pulse signal 404 transitions from state S0 to state S2. The digital pulse signal 404 is in state S2 from time t3a to time t4. At time t4, the digital pulse signal 404 transitions from state S2 back to state S1.

[0124] Note that the states S1, S0, and S2 of the digital pulse signal 404 occur in multiple instances. For example, the first instance of state S1 of the digital pulse signal 404 occurs between times t0 and t0a, and the second instance of state S1 of the digital pulse signal 404 occurs between times t2 and t2a. As another example, the first instance of state S0 of the digital pulse signal 404 occurs between times t0a and t1a, and the second instance of state S0 of the digital pulse signal 404 occurs between times t2a and t3a. As yet another example, the first instance of state S2 of the digital pulse signal 404 occurs between times t1a and t2, and the second instance of state S2 of the digital pulse signal 404 occurs between times t3a and t4. As another example, the first instance of state S0 is consecutive with the first instance of state S1 of the digital pulse signal 404, and the first instance of state S2 of the digital pulse signal 404 is consecutive with the first instance of state S0. The second instance of state S1 of the digital pulse signal 404 is consecutive with the first instance of state S2 of the digital pulse signal 404. Also, the second instance of state S0 of the digital pulse signal 404 is consecutive with the second instance of state S1 of the digital pulse signal 404, and the second instance of state S2 of the digital pulse signal 404 is consecutive with the second instance of state S0 of the digital pulse signal 404.

[0125] FIG. 4C shows an embodiment of a graph 406 for explaining an embodiment of an RF signal 408 generated by an RF generator RFGx (FIG. 1) and an embodiment of an RF signal 410 generated by an RF generator RFGy (FIG. 1). The RF signal 408 is an example of the RF signal 102x (FIG. 1), and the RF signal 410 is an example of the RF signal 102y (FIG. 1).

[0126] The RF signals 408 and 410 are synchronized with the digital pulse signal 404. For example, each of the RF signals 408 and 410 starts a transition from state S1 to state S0 at the time when the digital pulse signal 404 transitions from state S1 to state S0. As another example, each of the RF signals 408 and 410 starts a transition from state S0 to state S2 at the time when the digital pulse signal 404 transitions from state S0 to state S2. As yet another example, each of the RF signals 408 and 410 starts a transition from state S2 to state S1 at the time when the digital pulse signal 404 transitions from state S2 to state S1.

[0127] The graph 406 plots the power levels of the RF signals 408 and 410. For example, the y-axis of the graph 406 includes power levels P0, P1, P2, P3, P4. Also, the graph 406 plots time t on the x-axis. For example, the x-axis of the graph 406 includes times t0, t0a, t1, t1a, t2, t2a, t3, t3a, t4.

[0128] The RF signal 408 periodically transitions between states S1, S0, and S2 of the RF signal 408 in the manner described below. Similarly, the RF signal 410 periodically transitions between states S1, S0, and S2 of the RF signal 410 in the manner described below.

[0129] The state S1 of the RF signal 408 is defined by the power level P4. For example, when the digital pulse signal 404 or the RF signal 408 is in state S1, the RF signal 408 is at the power level P4.

[0130] The RF signal 408 transitions from state S1 to state S0 within the time window starting from time t0a. The state S0 of the RF signal 408 is defined by the power level P0. For example, when the digital pulse signal 404 or the RF signal 408 is in state S0, the RF signal 408 has the power level P0.

[0131] The RF signal 408 transitions from state S0 to state S2 within the time window starting from time t1a. The state S2 of the RF signal 408 is defined by the power level P2. For example, when the digital pulse signal 404 or the RF signal 408 is in state S2, the RF signal 408 has the power level P2.

[0132] The RF signal 408 transitions from state S2 to state S1 within the time window starting from time t2. The RF signal 408 transitions from state S1 to state S0 within the time window starting from time t2a, and transitions from state S0 to state S2 within the time window starting from time t3a.

[0133] Similarly, when the digital pulse signal 404 is in state S1, the RF signal 410 has the power level P1. The state S1 of the RF signal 410 is defined by the power level P1. For example, when the digital pulse signal 404 or the RF signal 410 is in state S1, the RF signal 410 has the power level P1.

[0134] The RF signal 410 transitions from state S1 to state S0 within the time window starting from time t0a. The state S0 of the RF signal 410 is defined by the power level P0. For example, when the digital pulse signal 404 or the RF signal 410 is in state S0, the RF signal 410 has the power level P0.

[0135] The RF signal 410 transitions from state S0 to state S2 within the time window starting from time t1a. The state S2 of the RF signal 410 is defined by the power level P3. For example, when the digital pulse signal 404 or the RF signal 410 is in state S2, the RF signal 410 has the power level P3.

[0136] The RF signal 410 transitions from state S2 to state S1 within the time window starting from time t2. The RF signal 410 transitions from state S1 to state S0 within the time window starting from time t2a, and transitions from state S0 to state S2 within the time window starting from time t3a.

[0137] The state S1 of the RF signal 408 between time t0 and t0a is the first instance of the state S1 of the RF signal 408, and the state S1 of the RF signal 408 between time t2 and t2a is the second instance of the state S1 of the RF signal 408. Similarly, the state S0 of the RF signal 408 between time t0a and t1a is the first instance of the state S0 of the RF signal 408, and the state S0 of the RF signal 408 between time t2a and t3a is the second instance of the state S0 of the RF signal 408. Also, the state S2 of the RF signal 408 between time t1a and t2 is the first instance of the state S2 of the RF signal 408, and the state S2 of the RF signal 408 between time t3a and t4 is the second instance of the state S2 of the RF signal 408.

[0138] Similarly, the state S1 of the RF signal 410 between time t0 and t0a is the first instance of the state S1 of the RF signal 410, and the state S1 of the RF signal 410 between time t2 and t2a is the second instance of the state S1 of the RF signal 410. Similarly, the state S0 of the RF signal 410 between time t0a and t1a is the first instance of the state S0 of the RF signal 410, and the state S0 of the RF signal 410 between time t2a and t3a is the second instance of the state S0 of the RF signal 410. Also, the state S2 of the RF signal 410 between time t1a and t2 is the first instance of the state S2 of the RF signal 410, and the state S2 of the RF signal 410 between time t3a and t4 is the second instance of the state S2 of the RF signal 410.

[0139] FIG. 4D is a diagram showing an embodiment of graph 411 for explaining an embodiment of RF signal 412 generated by RF generator RFGx (FIG. 1) and an embodiment of RF signal 414 generated by RF generator RFGy (FIG. 1). RF signal 414 is an example of RF signal 102x (FIG. 1), and RF signal 416 is an example of RF signal 102y (FIG. 1).

[0140] Graph 411 plots the power levels of RF signals 414 and 416. Also, graph 411 plots time t on the x-axis. For example, the x-axis of graph 411 includes times t0, t2, t2, t3, t4. Note that the duty cycles of states S1 to S3 of RF signals 414 and 416 are different from the duty cycles of states S1 to S3 illustrated in FIG. 4C. For example, the duty cycle of state S1 of RF signals 414 and 416 is 25%, the duty cycle of state S2 of RF signals 414 and 416 is 40%, and the duty cycle of state S3 of RF signals 414 and 416 is 35%.

[0141] FIG. 5A is a diagram showing an embodiment of graph 502 for explaining an enlarged part of RF signal 408. Graph 502 plots the power level of RF signal 408 against time t. RF signal 408 transitions from power level P4 to power level P0 within a time window starting from t0a. For example, RF signal 408 transitions from power level P4 to power level P0 during the period from t0a to t0a1. Time t0a1 occurs when RF signal 408 and digital pulse signal 404 (FIG. 4B) are in state S0 and occurs between t0a and t1a. Similarly, RF signal 408 transitions from power level P0 to power level P2 within a time window starting from t1a.

[0142] FIG. 5B is a diagram showing an embodiment of a graph 504 for explaining an enlarged portion of an RF signal 410. The graph 504 plots the power level of the RF signal 410 against time t. The RF signal 410 transitions from a power level P1 to a power level P0 within a time window starting from time t0a. For example, the RF signal 410 transitions from the power level P1 to the power level P0 during the period from time t0a to time t0a2. The time t0a2 occurs when the RF signal 410 and the digital pulse signal 404 (FIG. 4B) are in the state S0 and occurs between times t0a and t1a. Similarly, the RF signal 214 transitions from the power level P0 to the power level P3 within a time window starting from time t1a.

[0143] FIG. 6 is a diagram showing an embodiment of a table 600 for explaining the duty cycles associated with the states S1, S2, S0, and the power levels in the states S1, S2, S0. As an example, the duty cycle of the state S1 of the RF signal 102x (FIG. 1) or the digital pulse signal 108 (FIG. 1) is in the range of 3% to 25% (including the boundaries) of the cycle of the clock signal 204 (FIG. 2A). Illustratively, the duty cycle of the state S1 of the RF signal 102x or the digital pulse signal 108 is in the range of 3% to 5% (including the boundaries) of the cycle of the clock signal 204. As another example, the duty cycle of the state S1 of the RF signal 102y (FIG. 1) or the digital pulse signal 108 is in the range of 3% to 25% (including the boundaries) of the cycle of the clock signal 204 (FIG. 2A). Illustratively, the duty cycle of the state S1 of the RF signal 102y or the digital pulse signal 108 is in the range of 3% to 5% (including the boundaries) of the cycle of the clock signal 204.

[0144] As yet another example, the duty cycle of state S2 of the RF signal 102x or the digital pulse signal 108 is in the range of 3% to 50% (including the boundaries) of the cycle of the clock signal 204. By way of illustration, the duty cycle of state S1 of the RF signal 102x or the digital pulse signal 108 is in the range of 3% to 5% (including the boundaries) of the cycle of the clock signal 204. As another example, the duty cycle of state S2 of the RF signal 102y or the digital pulse signal 108 is in the range of 3% to 50% (including the boundaries) of the cycle of the clock signal 204. By way of illustration, the duty cycle of state S2 of the RF signal 102y or the digital pulse signal 108 is in the range of 3% to 5% (including the boundaries) of the cycle of the clock signal 204.

[0145] As yet another example, the duty cycle of state S0 of the RF signal 102x or the digital pulse signal 108 is in the range of 25% to 94% (including the boundaries) of the cycle of the clock signal 204. As another example, the duty cycle of state S2 of the RF signal 102y or the digital pulse signal 108 is in the range of 25% to 94% (including the boundaries) of the cycle of the clock signal 204.

[0146] As another example, in state S1, the ratio of the power level of RF signal 102x to the power level of RF signal 102y is in the range of 6 to 10 (including the boundaries). For illustration, the power level of RF signal 102x is 10 kilowatts (kW), and the power level of RF signal 102y is 1 kW. Note that the duty cycle of state S1 of RF signals 102x and 102y, and the power level ratio between RF signals 102x and 102y in state S1 enhance the mask selection ratio, which will be further described later. As yet another example, in state S2, the ratio of the power level of RF signal 102x to the power level of RF signal 102y is in the range of 0.2 to 1 (including the boundaries). As another example, in state S2, the ratio of the power level of RF signal 102x to the power level of RF signal 102y is in the range of 0.2 to less than 1 (including the boundaries). Examples of ratios less than 1 are 0.4, 0.45, 0.5, 0.8, or 0.9. For illustration, in state S2, the power level of RF signal 102x is 2 kW, and the power level of RF signal 102y is 5 kW. As another example, in state S2, the power level of RF signal 102x is 20% to 100% of the power level of RF signal 102y. As yet another example, when in state S2, the power level of RF signal 102x is 20% to less than 100% of the power level of RF signal 102y. As another example, when in state S2, the power level of RF signal 102x is not approximately zero, and the power level of RF signal 102y is not approximately zero. Further for illustration, the power level of RF signal 102x in state S2 is not in the range of 0 to 300 watts, and the power level of RF signal 102y in state S2 is not in the range of 0 to 300 watts. Note that the duty cycle of state S2 of RF signals 102x and 102y, and the power level ratio between RF signals 102x and 102y in state S2 enhance the warpage passivation, which will be further described later. As another example, in state S0, the power level of RF signal 102x is in the range of 0 to 300 watts (including the boundaries), and the power level of RF signal 102y is in the range of 0 to 300 watts (including the boundaries).

[0147] Note that when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are approximately equal. For example, when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are within a predetermined range from each other. By way of illustration, the power level of the RF signal 102x when the RF signal 102x is in state S0 is in the range of 0 to 300 watts, and the power level of the RF signal 102y when the RF signal 102y is in state S0 is in the range of 0 to 300 watts. As another example, when the RF signals 102x and 102y are in state S0, the power levels of the RF signals 102x and 102y are zero.

[0148] Furthermore, the sum or total of the duty cycles of the states S1 to S3 of the RF signal 102x is equal to 100 percent of the clock cycles of the clock signal 204. For example, the first instance of each of the states S1, S2, S0 of the RF signals 102x and 102y occupies cycle 1 (FIG. 2A) of the clock signal 204, and the second instance of each of the states S1, S2, S0 of the RF signals 102x and 102y occupies cycle 2 (FIG. 2A) of the clock signal 204.

[0149] In one embodiment, the duty cycle of a certain state of an RF signal is the period during which the RF signal has a unique power level. For example, the duty cycle of state S1 of RF signal 212 is the period from time t0 to t0a during which RF signal 212 has power level P4. As another example, the duty cycle of state S2 of RF signal 212 is the period from time t0a to t0b during which RF signal 212 has power level P2. As yet another example, the duty cycle of state S0 of RF signal 212 is the period from time t0b to t2 during which RF signal 212 has power level P0. As another example, the duty cycle of state S1 of RF signal 214 is the period from time t0 to t0a during which RF signal 214 has power level P1. As yet another example, the duty cycle of state S2 of RF signal 214 is the period from time t0a to t0b during which RF signal 214 has power level P3. As yet another example, the duty cycle of state S0 of RF signal 214 is the period from time t0b to t2 during which RF signal 214 has power level P0.

[0150] FIG. 7A is a perspective view of one embodiment of a substrate stack 700. The substrate stack 700 is an example of a substrate S before being processed in the plasma chamber 106 (FIG. 1). The substrate stack 700 includes a substrate layer 714 formed of silicon. The substrate stack 700 further includes a stop layer 712 laminated on the substrate layer 714. An example of the stop layer 712 is an etch stop layer manufactured from a dielectric such as an oxide or a nitride. An oxide layer 710 is deposited on the stop layer 712. Further, a silicon nitride (SiN) layer 708 is laminated on the oxide layer 710, an oxide layer 706 is deposited on the silicon nitride layer 708, another silicon nitride layer 704 is deposited on the oxide layer 706, and a mask layer 702 is deposited on the silicon nitride layer 704. The mask layer 702 is a photolithography mask that is an opaque plate or film.

[0151] In one embodiment, a nitride layer is used instead of the oxide layer 706. Similarly, in one embodiment, a nitride layer is used instead of the oxide layer 710.

[0152] FIG. 7B shows an embodiment of a substrate stack 720 for explaining the balance between the passivation layer 722 deposited on the feature 702B of the mask layer 702 (FIG. 7A) and the passivation layer 724 deposited on the feature 704B of the silicon nitride layer 704 (FIG. 7A). The substrate stack 720 includes the feature 702A of the mask layer 702, the feature 702B, the feature 704A of the silicon nitride layer 704, the feature 704B, the features 706A and 706B of the oxide layer 706 (FIG. 7A), the silicon nitride layer 708, and the oxide layer 710. The remaining layers 712 and 714 (FIG. 7A) of the substrate stack 720 are not shown in FIG. 7B.

[0153] The substrate stack 720 is manufactured by etching the substrate stack 700 of FIG. 7A in the plasma chamber 106 (FIG. 1). The substrate stack 720 is an example of the substrate S (FIG. 1) after partially etching the substrate stack 700. By supplying the integrated corrected RF signal 124 (FIG. 1) generated based on the RF signals 102x and 102y (FIG. 1) to the plasma chamber 106, the substrate stack 700 is etched to achieve the balance between the passivation layer 722 and the passivation layer 724. For example, the balance between the passivation layer 722 and the passivation layer 724 is achieved by depositing the passivation layers 722 and 724 in a substantially equal manner so as to cover the features of the mask layer 702 and the silicon nitride layer 704, respectively. Illustratively, the width of the passivation layer 722 is substantially equal to the width of the passivation layer 724.

[0154] Warpage is controlled by substantially equal passivation by the passivation layer 724. For example, substantially equal passivation by the passivation layer 724 prevents warpage from forming on the sidewalls of the features of the silicon nitride layer 704. As an example, a passivation layer is a layer deposited over or around another layer when a modified RF signal 124 is applied to the substrate S. Illustratively, the passivation layers 722 and 724 include a combination of materials (such as silicon nitride and oxide) that are part of the substrate stack 720 and a combination of materials of one or more process gases.

[0155] In the case of two-state pulsing, the RF signal periodically switches between a first state and a second state during one clock cycle of the clock signal. In the first state of two-state pulsing, the mask selection ratio is high and the passivation level of the feature 702B is high, while the passivation of the feature 704B is negligible or minimal. Also, in the first state, while the passivation level of the feature 702B is high, the passivation of the feature 704B is negligible or minimal, causing warpage in the feature 704B. This warpage is undesirable. Further, in the second state of two-state pulsing, the mask selection ratio is lower compared to the first state, the passivation level of the feature 704B is high, while the passivation of the feature 702B is minimal or negligible. Thus, in two-state pulsing, the balance between the passivation of the feature 702B and the passivation of the feature 704B is not achieved, resulting in warpage. This lack of balance occurs because the amount of passivation of the feature 702B is relatively more compared to the feature 704B in the first state and the amount of passivation of the feature 704B is relatively more compared to the feature 704A in the second state. By pulsing the RF signals 102x and 102y in the manner described with reference to FIGS. 2A-2C or FIGS. 4A-4C, the balance of passivation between the features 702B and 704B is achieved and warpage is reduced or eliminated.

[0156] Furthermore, the pulsing of RF signals 102x and 102y described with reference to FIGS. 2A-2C or FIGS. 4A-4C increases the mask selectivity as compared to binary pulsing. The mask selectivity is, for example, the ratio of the etching rate of any of the layers 704-710 of the substrate stack 700 (FIG. 7A) to the etching rate of the etching of the mask layer 702. The higher the mask selectivity, the faster the etching of the substrate stack 700 (FIG. 7A), and the lower the mask selectivity, the slower the etching of the substrate stack 700.

[0157] Pulsing the RF signals 102x and 102y as described with reference to FIGS. 2A-2C or FIGS. 4A-4C facilitates achieving a balance between mask selectivity and warp control. Warp control is achieved by passivating the sidewalls (such as sidewall 734) of the features of the silicon nitride layer 704. For example, the amount of passivation of the mask layer 702 obtained by pulsing the RF signals 102x and 102y in the manner described with reference to FIGS. 2A-2C or FIGS. 4A-4C is less than the amount of passivation obtained by binary pulsing, thereby increasing the mask selectivity. Furthermore, increasing the amount of passivation of the sidewalls of the features formed by etching the silicon nitride layer 704 as compared to the amount of passivation of the sidewalls by the application of binary pulses is achieved by using the integrated correction RF signal 124 (FIG. 1). By increasing the amount of passivation of the sidewalls of the features formed by etching the silicon nitride layer 704, the warp in the sidewalls of the features formed by etching the silicon nitride layer 704 is reduced or eliminated, and by reducing or eliminating the warp, the mask selectivity increases.

[0158] Pulsing the RF signals 102x and 102y facilitates simultaneously achieving warp control and mask selectivity. By managing the pulsing of the RF signals 102x and 102y, an optimal balance can be achieved that realizes both warp control and mask selectivity while minimizing any trade-offs or compromises associated with binary pulsing.

[0159] FIG. 7C is an enlarged view of a portion 730 of the substrate stack 720 (FIG. 7B). The portion 730 includes a feature 702B of the mask layer 702 (FIG. 7A), a feature 704B of the silicon nitride layer 704 (FIG. 7A), and a feature 706B of the oxide layer 706 (FIG. 7A). Also shown in FIG. 7C as a dashed line is a warp 732. The warp 732 is formed on the sidewall 734 of the feature 704B. The sidewall 734 of the feature 704B faces the sidewall 726 (FIG. 7B) of the feature 704A, and a gap is formed between the sidewalls 726 and 734 when the substrate stack 700 (FIG. 7A) is etched. Note that the warp 732 is formed when a two-state pulse is applied to the substrate S. However, when the pulses of the RF signals 102x and 102y described with reference to FIGS. 2A-2C or FIGS. 4A-4C are applied to the substrate S via the integrated modified RF signal 124 (FIG. 1), the warp 732 is reduced or not formed. When the passivation balance of the features 702B and 704B is achieved by the pulsing of the RF signals 102x and 102y described with reference to FIGS. 2A-2C or FIGS. 4A-4C, the warp 732 is reduced or not formed.

[0160] Warp control is achieved when the warp 732 is reduced or not formed so as to achieve or maintain a predetermined limit dimension. For example, a predetermined critical dimension (CD), which is the predetermined width between the sidewall 734 in the feature 704B of the silicon nitride layer 704 and a sidewall similar to the sidewall 734 in the feature 704A, is achieved by effective warp control. The predetermined width is smaller than the width (such as a horizontal distance) between the warp 732 and a warp similar to this warp formed within the sidewall of the feature 704A.

[0161] FIG. 7D is a diagram showing an embodiment of a substrate stack 740 after processing the substrate stack 700 (FIG. 7A) by applying the method described with reference to FIGS. 2A-2C or FIGS. 4A-4C. The substrate stack 740 is an example of the substrate stack S after applying the pulses of the RF signals 102x and 102y described with reference to FIGS. 2A-2C or FIGS. 4A-4C to the substrate stack 700.

[0162] The substrate stack 740 includes features of the mask layer 702 (FIG. 7A), features of the silicon nitride layer 704 (FIG. 7A), features of the oxide layer 706 (FIG. 7A), features of the silicon nitride layer 708 (FIG. 7A), features of the oxide layer 710 (FIG. 7A), and features of the stop layer 712 (FIG. 7A). A passivation layer 742 including a plurality of passivation portions such as the passivation layer 722 (FIG. 7C) and the passivation layer 724 (FIG. 7C) is deposited over the features 702B, 704B, 706B, the feature 708B of the silicon nitride layer 708, the feature 710B of the oxide layer 710, and the feature 712B of the stop layer 712. The passivation layer 742 is deposited when the integrated modified RF signal 124 generated based on the RF signals 102x and 102y described with reference to FIGS. 2A-2C or FIGS. 4A-4C is applied to the substrate stack 700.

[0163] FIG. 8 is a schematic flowchart of an embodiment. A stack is prepared (step 804). FIG. 9A is a schematic cross-sectional view of a stack 904 processed according to an embodiment. The stack 904 includes a substrate 908. One or more intermediate layers 912, such as an etch stop layer, may be provided above the substrate 908. A first silicon oxide (SiO2) layer 916 is provided above the one or more intermediate layers 912. A first silicon nitride (SiN) layer 920 is provided above the first SiO2 layer 916. A second SiO2 layer 924 is provided above the first SiN layer 920. A second SiN layer 928 is provided above the second SiO2 layer 924. A patterned mask 932 is provided above the second SiN layer 928. In various embodiments, one or more layers may be provided between the patterned mask 932 and the second SiN layer 928. In various embodiments, it may further have alternately stacked SiN layers and SiO2 layers. In other embodiments, it may have layers of other materials. In various embodiments, the stack 904 has a silicon-containing layer. In this embodiment, the patterned mask 932 is a hard mask such as polysilicon.

[0164] The stack 904 may be disposed in a plasma chamber 106. An etching gas is flowed into the plasma chamber 106 (step 808). In this embodiment, the etching gas includes a metal fluoride or a tungsten-containing passivation agent and an etching component. In this embodiment, the metal fluoride or the tungsten-containing passivation agent is tungsten hexafluoride (WF6). In this embodiment, the etching component includes oxygen (O2) and a fluorocarbon (such as hexafluorobutadiene (C4F6) and / or octafluorocyclobutane (C4F8)).

[0165] Execute a multi-state pulsing method to plasma-etch the etching gas, thereby etching the stack 904. In this embodiment, the multi-state pulsing method includes generating a primary RF signal in a first frequency range and generating a secondary RF signal in a second frequency range. Here, the first frequency range is smaller than the second frequency range. The primary RF signal and the secondary RF signal are pulsed among at least three states including a first state, a second state, and a third state. As an example, the frequency of the primary RF signal is 400 kHz, and the frequency of the secondary RF signal is 60 MHz. The first state has a duty cycle of 3% to 20%, the power level of the primary RF signal is 17 kW to 30 kW, and the power level of the secondary RF signal is more than 5 kW. As a more specific example, the first state has a duty cycle of 3% to 5%, and the power level of the primary RF signal is 29 kW. The second state has a duty cycle of 3% to 40%, the power level of the primary RF signal is more than 8 kW, and the power level of the secondary RF signal is more than 3 kW. As a more specific example, the second state has a duty cycle of 3% to 5%, the power level of the primary RF signal is 13 kW, and the power level of the secondary RF signal is 5 kW. The third state has a duty cycle of 40% to 94%, the power level of the primary RF signal is less than 2 kW, and the power level of the secondary RF signal is 1 kW. As a specific example, the third state has a duty cycle of 90% to 94%, the power level of the primary RF signal is 0 kW, and the power level of the secondary RF signal is 0 kW. In one embodiment, the ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and the ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1.

[0166] FIG. 9B is a schematic cross-sectional view of the stack 904 after the etching is completed. By flowing the etching gas (step 808) and performing the above-described etching process in the multi-state pulsing mode, the feature 940 is etched in the stack 904. In this embodiment, the feature 940 is a contact hole. In this embodiment, it is possible to selectively etch the first and second silicon oxide layers 916 and 924 and the first and second silicon nitride layers 920 and 928 by a single etching recipe. When a metal fluoride or tungsten-containing passivation agent is not used, warping indicated by the dotted line 948 may occur. When a metal fluoride or tungsten-containing passivation agent is added alone, necking indicated by the dotted line 944 may occur. By combining a metal fluoride or tungsten-containing passivation agent with the multi-state pulsing mode, it is possible to tune to prevent necking and warping while achieving a high etching selectivity. The multi-state pulsing mode of this embodiment having three power levels is considered to obtain an ion flux and a bias energy capable of preventing necking while using a metal fluoride or tungsten-containing passivation agent. In this embodiment, the etching selectivity for etching the dielectric stack with respect to the polysilicon mask is at least 2:1. More specifically, the etching selectivity for etching the dielectric stack with respect to the polysilicon mask is 2:1 to 3:1.

[0167] In another embodiment, the power level of the primary RF signal in the second state is less than 80% of the power level of the primary RF signal in the first state. The power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state. The power level of the secondary RF signal in the third state is less than 20% of the power level of the secondary RF signal in the second state. The first state has a duty cycle of 3% to 25%. The second state has a duty cycle of 3% to 50%. The third state has a duty cycle of 25% to 94%. In some embodiments, the duty cycle of the first state is smaller than the duty cycle of the third state. The duty cycle of the second state is smaller than the duty cycle of the third state.

[0168] In various embodiments, the first frequency range may be a frequency range of 80 kHz to 14 MHz. Using the first frequency range, a bias for ion bombardment is formed. The second frequency range may be a frequency range of 15 MHz to 120 MHz. Using the second frequency range, plasma is excited. Also, using the second frequency range, the plasma density, ion flux, and degree of dissociation of the plasma may be controlled. In various embodiments, the metal fluoride or tungsten-containing passivation agent is tungsten fluoride. Tungsten fluoride may include tungsten hexafluoride, tungsten pentachloride fluoride (WClF5), and tungsten dichloride tetrafluoride (WCl2F4). In other embodiments, another tungsten-containing passivation agent is tungsten fluoride WF x Cl y (x + y = 4, 5, 6) or WO x F y (2x + y = 4, 5, 6). For example, the tungsten-containing passivation agent may be WO2F2, WOF4, or WCl2F4.

[0169] In various embodiments, the stack has at least one silicon oxide layer. The stack includes a layer mainly composed of silicon. In various embodiments, the mask is a hard mask such as polysilicon. In other embodiments, the stack alternately includes a silicon oxide layer and a silicon nitride layer. In various embodiments, high aspect ratio (HAR) features having a height / width ratio greater than 20:1 are provided.

[0170] In various embodiments, for the etching gas, the ratio of the tungsten-containing passivation agent to the total etching gas flow rate is 1:10 to 1:100 in terms of the number of moles.

[0171] Figure 10 is a schematic diagram of an etching reactor that can be used in one embodiment. In one or more embodiments, the plasma processing system 1000 includes a gas distribution plate 1006 that provides a gas inlet and an electrostatic chuck (ESC) 1008 within a plasma processing chamber 1049 surrounded by a chamber wall 1052. Within the plasma processing chamber 1049, a stack 1018 is disposed above or over the ESC 1008. The ESC 1008 may be supplied with a bias from an ESC source 1048. A primary RF signal from the ESC source 1048 supplies the bias at the ESC 1008. An etching gas source 1010 is connected to the plasma processing chamber 1049 via the gas distribution plate 1006. In this embodiment, the etching gas source 1010 may include a polymer passivation agent source 1012, an etching component gas source 1017, and a WF6 (or tungsten-containing passivation agent) source 1016. An ESC temperature controller 1050 is connected to a cooler 1014. In this embodiment, the cooler 1014 supplies a coolant to a flow path 1005 within or near the ESC 1008. A radio frequency (RF) source 1030 supplies RF power to a lower electrode and / or an upper electrode (in this embodiment, the ESC 1008 and the gas distribution plate 1006). In this embodiment, a secondary RF signal may be supplied by the RF source 1030. The secondary RF signal may be used to supply energy to form a plasma. In an exemplary embodiment, the RF source 1030 and the ESC source 1048 are configured by power supplies of 400 kHz, 60 MHz, and 2 MHz, 27 MHz in any configuration. The RF source 1030 and the ESC source 1048 may include the RF generators RFGx, RFGy, and the impedance matching network IMN shown in FIG. 1. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, multiple generators may be provided within separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other configurations of RF sources and electrodes may be used.Controller 1035 is controllably connected to RF source 1030, ESC source 1048, exhaust pump 1020, and etching gas source 1010. An example of such an etching chamber is the improved Exelan Flex manufactured by Lam Research Corporation (Fremont, California). TM An etching system is included. The process chamber can be a capacitively coupled plasma (CCP) reactor or an inductively coupled plasma (ICP) reactor. In other embodiments, other types of plasma processing chambers, such as dielectric and conductive etching chambers or deposition chambers, may be used.

[0172] In other embodiments, chambers of multiple different dimensions may be provided. These chambers may use different relative powers. For example, larger chambers may use RF power equal to or greater than 120 kW. In other embodiments, other conditions may be added. Thus, a fourth or fifth condition may exist.

[0173] The embodiments described herein may be implemented by various computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable household appliances, minicomputers, mainframe computers, and the like. The embodiments described herein may also be implemented in a distributed computing environment where tasks are performed by remote processing hardware units linked via a computer network.

[0174] In some embodiments, the controller is part of a system, and the system may be part of the examples described above. The system includes a semiconductor processing apparatus that includes one or more processing tools, one or more chambers, one or more processing platforms, and / or certain processing components (such as a wafer pedestal or a gas flow system). The system is integrated with electronics for controlling the operation of the system before, during, and after processing a semiconductor wafer or substrate. The electronics, also referred to as a "controller", may control various components or sub-parts of the system. The controller is programmed to control any of the processes disclosed herein, depending on the processing requirements and / or the type of system. The processes include the supply of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, RF generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid supply setting, position and motion setting, loading and unloading of wafers to and from the tool, and loading and unloading of wafers to and from other transfer tools and / or load locks connected or coordinated with the system.

[0175] In various embodiments, the controller is broadly defined as electronics having various integrated circuits, logic, memory, and / or software, and performs functions such as receiving commands, sending commands, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits include a chip as firmware for storing program instructions, a DSP, a chip defined as an ASIC, a PLD, one or more microprocessors, or a microcontroller for executing program instructions (e.g., software). The program instructions are commands communicated to the controller as various individual settings (or program files) that define the operating parameters for performing a process on or for a semiconductor wafer. In some embodiments, the operating parameters are part of a recipe defined by a process engineer to achieve one or more processing steps in the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0176] In some embodiments, the controller is part of a computer or coupled to a computer. Here, the computer may be integrated with the system, coupled to the system, network-connected to the system in other forms, or a combination thereof. For example, the controller may exist "in the cloud" or in all or part of a factory host computer system. This enables remote access to wafer processing. The computer enables remote access to the system to monitor the progress of the manufacturing process, investigate the past manufacturing process history, or investigate trends or performance metrics from multiple manufacturing processes, and change the parameters of the current process, set the processing steps following the current process, or start a new process.

[0177] In some embodiments, a process recipe is provided to the system from a remote computer (e.g., a server) via a computer network. Here, the network includes a local network or the Internet. The remote computer includes a user interface that enables input of parameters and / or settings and programming. These parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions as settings for processing the wafer. It should be understood that these settings are specific to the type of process to be performed on the wafer and the type of tools that the controller will cooperate with or control. Thus, as described above, the controller is distributed, such as by comprising one or more individual controllers. These individual controllers are networked and operate towards a common purpose, such as the achievement of the processes described herein. An example of a distributed controller for such a purpose is one or more integrated circuits mounted in a chamber that communicate with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer). These integrated circuits cooperate to control the process in the chamber.

[0178] In various embodiments, the plasma system described herein includes, by way of non-limiting example, a plasma etching chamber, a deposition chamber, a spin rinse chamber, a metal plating chamber, a cleaning chamber, a bevel edge etching chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that may be associated with or used in the manufacture and / or production of semiconductor wafers.

[0179] Furthermore, the above operations have been described with reference to a parallel plate plasma chamber (e.g., a capacitively coupled plasma chamber, etc.), but in some embodiments, the above operations are also applicable to other types of plasma chambers. Other types of plasma chambers include, for example, an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, a plasma chamber including a conductor tool and a dielectric tool, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an RF generator of X MHz, an RF generator of Y MHz, and an RF generator of Z MHz are coupled to an inductor in the ICP plasma chamber.

[0180] As described above, depending on the process steps executed by the tool, the controller communicates with one or more of other tool circuits or tool modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools installed throughout the factory, the main computer, another controller, or tools used in material transport for wafer container transfer to tool positions and / or load ports in a semiconductor manufacturing factory.

[0181] It should be understood that, with the above embodiments in mind, some embodiments employ various computer-implemented operations using data stored in a computer system. These computer-implemented operations manipulate physical quantities.

[0182] Some embodiments also relate to hardware units or devices for performing these operations. The device is specially configured for a dedicated computer. When defined as a dedicated computer, the computer is operable for a specific purpose while not performing other processes, program executions, or routines not included in the specific purpose.

[0183] In some embodiments, the operations described herein are performed by a selectively activated computer, constituted by one or more computer programs stored in a computer memory, or obtained via a computer network. When data is obtained via a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0184] One or more embodiments described herein may be manufactured as computer-readable code recorded on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit that stores data (e.g., a memory device, etc.). The data is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD recordable (CD-R), CD rewritable (CD-RW), magnetic tape, as well as other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes tangible computer-readable media distributed on a network-coupled computer system such that the computer-readable code is stored and executed distributively.

[0185] Note that although some of the above method steps are shown in a particular order, in various embodiments, other housekeeping steps may be performed between these method steps, these method steps may be adjusted so as to be performed at slightly different timings, these method steps may be distributed in a system that allows these method steps to be performed at various intervals, or these method steps may be performed in an order different from the above.

[0186] Furthermore, it should be noted that in one embodiment, one or more features of any of the above embodiments may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in the present disclosure.

[0187] Although the above embodiments have been described in some detail for the purpose of providing a clear understanding, it is obvious that some changes and modifications can be made within the scope of the appended claims. Therefore, this embodiment should be considered as illustrative only and not as limiting the present disclosure, and the embodiments are not limited to the details described herein and may be modified within the scope of the appended claims and their equivalents.

Claims

1. A multi-state pulsing method for achieving a balance between warp control and mask selection ratio, comprising: generating a primary radio frequency (RF) signal pulsed among three states including a first state, a second state, and a third state; generating a secondary RF signal pulsed among the three states; in the first state, the power level of the primary RF signal is greater than the power level of the secondary RF signal; in the second state, the power level of the secondary RF signal is greater than the power level of the primary RF signal; in the third state, the power levels of the primary RF signal and the secondary RF signal are substantially equal; a method.

2. The method according to claim 1, wherein: the duty cycle of the first state is smaller than the duty cycle of the third state, and the duty cycle of the second state is smaller than the duty cycle of the third state; a method.

3. The method according to claim 2, wherein: the duty cycle of the first state ranges from 3 percent to 25 percent of the clock cycle of a clock signal; a method.

4. The method according to claim 3, wherein: the duty cycle of the second state ranges from 3 percent to 50 percent of the clock cycle of the clock signal; a method.

5. The method according to claim 4, wherein: the duty cycle of the third state ranges from 25 percent to 94 percent of the clock cycle of the clock signal, and the sum of the duty cycles of the first, second, and third states is equal to 100 percent of the clock cycle; a method.

6. The method according to claim 2, wherein: the fact that the power level of the primary RF signal is greater in the first state, the fact that the power level of the secondary RF signal is greater in the second state, the fact that the duty cycle of the first state is smaller, and the fact that the duty cycle of the second state is smaller facilitate achieving a balance between warp control and mask selection ratio; a method.

7. The method according to claim 1, further comprising: supplying the primary RF signal to an impedance matching network coupled to an electrode of a plasma chamber; further comprising supplying the secondary RF signal to the impedance matching network Method **Claim 8** The method according to claim 1, wherein the power level of the primary RF signal in the first state is at least 6 times, and at most 10 times greater than the power level of the secondary RF signal in the first state Method **Claim 9** The method according to claim 1, wherein the power level of the primary RF signal in the second state is at least 20 percent and less than 100 percent of the power level of the secondary RF signal in the second state Method **Claim 10** The method according to claim 1, wherein the power levels of the primary RF signal and the secondary RF signal in the third state are zero Method **Claim 11** The method according to claim 1, wherein the primary RF signal is pulsed from the power level of the first state to the power level of the second state, pulsed from the power level of the second state to the power level of the third state, and pulsed from the power level of the third state to the power level of the first state Method **Claim 12** The method according to claim 1, wherein the primary RF signal is pulsed among the three power levels in synchronization with the three states of the digital pulse signal Method **Claim 13** A method for etching a stack under a mask in a plasma processing chamber, comprising flowing an etching gas containing a metal fluoride or tungsten-containing passivation agent and an etching component into the plasma processing chamber plasmaizing the etching gas, wherein the plasmaizing comprises generating a primary radio frequency (RF) signal pulsed among at least three states including a first state, a second state, and a third state in a first frequency range generating a secondary RF signal pulsed among the at least three states in a second frequency range, wherein the first frequency range is smaller than the second frequency range wherein the power level of the primary RF signal in the second state is less than 80% of the power level of the primary RF signal in the first state wherein the power level of the primary RF signal in the third state is less than 20% of the power level of the primary RF signal in the second state The power level of the secondary RF signal in the third state is less than 20% of the power level of the secondary RF signal in the second state. Method. **Claim 14** The method according to claim 13, wherein the duty cycle of the first state is smaller than the duty cycle of the third state, and the duty cycle of the second state is smaller than the duty cycle of the third state. Method. **Claim 15** The method according to claim 13, wherein the duty cycle of the first state ranges from 3% to 25% of the clock cycle of the clock signal. Method. **Claim 16** The method according to claim 15, wherein the duty cycle of the second state ranges from 3% to 50% of the clock cycle of the clock signal. Method. **Claim 17** The method according to claim 16, wherein the duty cycle of the third state ranges from 25% to 94% of the clock cycle of the clock signal, and the sum of the duty cycles of the first, second, and third states is equal to 100% of the clock cycle. Method. **Claim 18** The method according to claim 13, wherein the first frequency range is from 80 kHz to 14 MHz (including the boundaries), and the second frequency range is from 15 MHz to 120 MHz (including the boundaries). Method. **Claim 19** The method according to claim 13, wherein the metal fluoride or tungsten-containing passivation agent is tungsten fluoride. Method. **Claim 20** The method according to claim 13, wherein the metal fluoride or tungsten-containing passivation agent is tungsten hexafluoride. Method. **Claim 21** The method according to claim 13, wherein the stack contains silicon. Method. **Claim 22** The method according to claim 21, wherein the mask is a hard mask. Method. **Claim 23** The method according to claim 22, wherein the hard mask contains polysilicon. Method. **Claim 24** The method according to claim 23, wherein the stack contains at least one silicon oxide-containing layer. Method. **Claim 25** The method according to claim 13, The ratio of the power level of the primary RF signal in the first state to the power level of the secondary RF signal in the first state is greater than 1, and the ratio of the power level of the primary RF signal in the second state to the power level of the secondary RF signal in the second state is less than 1. Method. **Claim 26** The method according to claim 13, wherein the multi-state pulsing scheme is adjusted to minimize necking and warping using the metal fluoride or tungsten-containing passivation agent. Method.

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