Low power cryo-CMOS circuit with non-volatile threshold voltage offset compensation

Abstract

To provide systems and methods relating to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation.SOLUTION: A system includes a plurality of devices configured to operate in a cryogenic environment, and a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic coupled to each of the plurality of devices. The control logic is configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage, the second value representing a lower variation among threshold voltages of the plurality of devices.SELECTED DRAWING: Figure 6

Description

Background Art

[0001] Semiconductor-based integrated circuits used in electronic devices, such as digital processors, include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. A further approach to the use of processors and related components based on CMOS technology is the use of superconducting logic-based devices. Superconducting logic-based devices can also be used to process quantum information, such as qubits.

Summary of the Invention

[0002] In one aspect, the present disclosure relates to a system including a plurality of devices configured to operate in a cryogenic environment, wherein a first distribution of threshold voltages of the plurality of devices has a first value indicating a measure of the spread of the threshold voltages. The system can further include control logic coupled to each of the plurality of devices, the control logic being configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value that is a measure of the spread of the threshold voltages, the second value representing a lower variation among the threshold voltages of the plurality of devices.

[0003] In another aspect, the present disclosure relates to a method in a system having a plurality of devices with associated threshold voltages. The method can include determining a variation among the threshold voltages of the plurality of devices while operating an integrated circuit in a cryogenic environment, each of the plurality of devices having a floating gate. The method can further include changing the threshold voltage of at least a subset of the plurality of devices such that the variation among the threshold voltages of the plurality of devices is reduced, by (1) injecting charge into each respective floating gate, or (2) removing charge from each respective floating gate.

[0004] In yet another aspect, the present disclosure relates to a system including a first integrated circuit having a quantum device including a plurality of quantum bit gates, the quantum device being configured to operate at cryogenic temperatures. The system can further include a second integrated circuit configured to operate at the cryogenic temperatures, with the first integrated circuit coupled to the second integrated circuit. The second integrated circuit can include a plurality of devices having a first distribution of threshold voltages having a first value indicative of a measure of the spread of the threshold voltages. The second integrated circuit can further include control logic coupled to each of the plurality of devices, the control logic being configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicative of a measure of the spread of the threshold voltages, the second value representing a lower variation among the threshold voltages of the plurality of devices.

[0005] This summary is provided to introduce in a simplified form a selection of concepts that are further described in detail in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Brief Description of the Drawings

[0006] The present disclosure is not limited to the accompanying drawings, which are presented by way of example and in which like elements are designated by like reference numerals. The elements in the figures are shown simply and clearly, and are not necessarily drawn to scale.

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[0007] Modern computing technology is mainly limited by the power dissipated and heat generated by calculations using complementary metal-oxide-semiconductor (CMOS) field-effect transistors. The power (P) consumed by a transistor has a static (leakage) component and a dynamic component (P = CV 2 f) associated with charging and discharging the device and interconnect capacitance C, where V is the voltage and f is the clock frequency. Many processors and memory subsystems limit the clock rate to keep power consumption at a manageable level.

[0008] In data center applications, one possible approach to addressing power consumption is to cool the transistors, thereby first reducing their static leakage (by freezing thermally activated transport in the mobile carrier and subthreshold regions), and further by taking advantage of the increased carrier mobility resulting from the suppression of electron-photon scattering when the temperature decreases. The increased mobility sharpens the transition between the on and off states of the transistor, leading to a narrower supply voltage required to cover the device operating range. Cryogenic operation provides further reduction in dynamic power by reducing the supply needs to suppress the subthreshold swing, i.e., the thermally activated transport that remains even when the transistor is biased below the threshold.

[0009] However, cryogenic computing brings in at least two challenges. First, as the temperature is lowered, the threshold voltage V TH increases, requiring an even higher supply voltage V DD for compensation. This increase in the threshold voltage V TH can be compensated to some extent by adjusting the dopant concentration and dielectric thickness during manufacturing in the foundry. However, such transistors do not function well at ambient temperatures, which are not cryogenic temperatures. Second, and far more restrictively, the variation in the threshold voltage V TH between transistors means that the supply voltage can only be lowered to the extent tolerated by the variation in the threshold voltage V TH . That is, a sufficient voltage swing is required to ensure that all transistors can be switched from a fully off state to a fully on state. Cryogenic cooling increases carrier mobility by suppressing photon scattering, but atomic-scale disorder also leads to scattering and the generation of offset charges that cause a large variation in the threshold voltage V TH across the die. Furthermore, as the temperature is lowered and the device feature size is reduced, the threshold voltage variation increases. What these limitations mean is that in many situations, cryogenically cooling a CMOS device is generally not a viable approach for net power savings, considering the power cost to produce the cooling. However, if the offset charge problem can be addressed such that the threshold voltage V TH distribution can be made narrower, the increased mobility and transconductance at low temperatures can lead to significant power savings.

[0010] Certain examples of the present disclosure attempt to address variations in the threshold voltage of a transistor by actively compensating for offset charge at cryogenic temperatures. For this purpose, various mechanisms may be used, including Fowler-Nordheim tunneling (FNT) and hot carrier injection (HCI). An example FNT process may include tunneling charge through a thin dielectric by application of a large voltage bias (e.g., several volts). An electric field may also be added to the gate capacitance by creating carriers having energy beyond the dielectric bandgap, effectively enabling over-barrier transport. These hot carrier states can be created using a large electric field within the FET channel and injecting carriers into the gate capacitance at energies far beyond the Fermi level (at deep overdrive limits). Both the through-barrier (FNT) process and the over-barrier (HCI) process can be used to non-volatilely modify the charge on a floating gate capacitor. Thus, in such examples, the charge state remains without an external power source after the charge has been imparted or removed.

[0011] FIG. 1 shows a device 100 with threshold voltage offset compensation according to an example. The device 100 can be formed on a substrate 102. The device 100 can further include a p-type region 104, an n-type region 106, and another n-type region 108. In this example, the device 100 is formed to function as an NPN transistor. However, the device 100 can be any other type of transistor (e.g., PNP transistor), thyristor, thermistor, or any other semiconductor switch or device that operates in a similar manner to a transistor. Further, the device 100 can be a metal-oxide-semiconductor field-effect transistor (MOSFET), fin field-effect transistor (FinFET), insulated-gate field-effect transistor (IGFET), or any other type of transistor. Also, the device 100 can be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is later separated into dies packaged in the form of an integrated circuit package. The semiconductor processing steps can include the use of techniques such as plasma vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Features including sources, drains, and gates can be formed using such techniques or other suitable semiconductor manufacturing techniques.

[0012] Continuing to refer to FIG. 1, stack 120 can be formed. Stack 120 can include a control gate 122 and a floating gate 124. Stack 120 can further include a control dielectric layer 126 that can be formed between control gate 122 and floating gate 124. Stack 120 can further include a tunnel dielectric layer 128 that can be formed between floating gate 124 and the top surface of channel 110. Control gate 122 can be formed using polysilicon, metal, metal alloy, or other suitable material. Floating gate 124 can function as a layer configured to store a controllable amount of charge. Materials such as, for example, silicon nitride, polysilicon, silicon, or germanium can be used. In a particular example, nanocrystals may be used to store charge. Control dielectric layer 126 can be formed using any suitable dielectric material. In one example, control dielectric layer 126 can be formed as an oxide / nitride / oxide (ONO) stack. Tunnel dielectric layer 128 can also be formed using any suitable dielectric material, such as, for example, silicon dioxide or silicon nitride. A high-k dielectric stack can also be used. The dimensions of these various layers and regions are not drawn to scale, and in one example, tunnel dielectric layer 128 can be configured to be thin enough such that stored electrons or holes can pass through tunnel dielectric layer 128 under the application of appropriate voltages to the various terminals of device 100. Although not shown in FIG. 1, sidewalls can be formed adjacent to each side of stack 120. FIG. 1 shows a specific number and specific types of layers formed as part of stack 120, but stack 120 can further include additional layers or fewer layers, as needed.

[0013] Still referring to FIG. 1, device 100 can have several terminals that can be coupled to receive different voltages. As an example, device 100 can have a source voltage (V SA terminal for receiving (2) a drain voltage (V D ) coupled to the drain of device 100 (e.g., n-type region 108), (3) a gate voltage (V G ) coupled to the control gate of device 100 (e.g., control gate 122), and (4) a trimming voltage (V TRIM ) coupled to the control gate of device 100 (e.g., control gate 122). In this example, the trimming voltage (V TRIM ) can be supplied via an external circuit and can be used initially to adjust the offset charge. The trimming voltage (V TRIM ) can be used to add or subtract charge to the gate capacitance via FNT and / or HCI. In one example, this additional connection can be placed in a separate routing layer and connected to the transistor via vias or other routing structures formed within the substrate associated with device 100.

[0014] Regarding the operation of device 100, an appropriate voltage coupled via the terminals of device 100 can be used to inject charge into or remove charge stored in floating gate 124. As an example, in a first phase, a high trimming voltage (V TRIM) (e.g., several volts) is applied to control gate 122 while at the same time a high drain voltage (V D ) can be applied to the drain region of device 100. As a result, electrons can be injected into floating gate 124 during the first phase. In a second phase, holes formed in other parts of device 100 can be removed. As an example, a specific voltage (lower than the trimming voltage applied during the first phase) is applied to control gate 122 while at the same time a negative drain voltage (V D) can be applied to the drain region of device 100. As a result, during the second phase, holes formed in a specific region of device 100 can be removed. The second phase may only be required if device 100 is formed as a semiconductor-on-insulator (SOI) device. This is because when device 100 is formed as a bulk device, holes can be removed through the well electrode.

[0015] Trimming voltage (V TRIM ) To suppress the capacitance effect of the routing structure for routing, such a structure can be disconnected from device 100 after the trimming operation. Further, the control circuit used for the trimming operation can also be permanently disconnected from device 100. As an example, after the trimming operation is completed, an e-fuse or other such technology can be used to burn off the connection for receiving the trimming voltage (V TRIM ).

[0016] FIG. 2 shows a device 200 with threshold voltage offset compensation according to an example. Similar to device 100, device 200 may be formed on a substrate 202. Device 200 may further include a p-type region 204, an n-type region 206, and another n-type region 208. In this example, device 200 is formed to function as an NPN transistor. However, device 200 may be any other type of transistor (e.g., PNP transistor), thyristor, thermistor, or any other semiconductor switch or device that operates in a similar manner to a transistor. Further, device 200 may be a metal oxide semiconductor field effect transistor (MOSFET), fin field effect transistor (FinFET), insulated gate field effect transistor (IGFET), or any other type of transistor. Also, device 200 may be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is later separated into dies that are packaged in the form of an integrated circuit package. The semiconductor processing steps may include the use of techniques such as, for example, plasma vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Using such techniques or other suitable semiconductor manufacturing techniques, features including sources, drains, and gates may be formed.

[0017] Continuing to refer to FIG. 2, stack 220 can be formed. Stack 220 can include a control gate 222 and a floating gate 224. Stack 220 can further include a control dielectric layer 226 that can be formed between control gate 222 and floating gate 224. Stack 220 can further include a tunnel dielectric layer 228 that can be formed between floating gate 224 and the top surface of channel 210. Control gate 222 can be formed using polysilicon, metal, metal alloy, or other suitable material. Floating gate 224 can function as a layer configured to store a controllable amount of charge. Materials such as, for example, silicon nitride, polysilicon, silicon, or germanium can be used. In a particular example, nanocrystals may be used to store charge. Control dielectric layer 226 can be formed using any suitable dielectric material. In one example, control dielectric layer 226 can be formed as an oxide / nitride / oxide (ONO) stack. Tunnel dielectric layer 228 can also be formed using any suitable dielectric material, such as, for example, silicon dioxide or silicon nitride. A high-k dielectric stack can also be used. The dimensions of these various layers and regions are not drawn to scale, and in one example, tunnel dielectric layer 228 can be configured to be thin enough such that stored electrons or holes can pass through tunnel dielectric layer 228 under the application of appropriate voltages to the various terminals of device 200. Although not shown in FIG. 2, sidewalls can be formed adjacent to each side of stack 220. FIG. 2 shows a particular number and particular types of layers formed as part of stack 220, but stack 220 can further include additional layers or fewer layers, as needed.

[0018] Still referring to FIG. 2, device 200 can have several terminals that can be coupled to receive different voltages. As an example, device 200 can have a source voltage (V SA terminal for receiving (2) a drain voltage (V D ) coupled to the drain of device 200 (e.g., n-type region 208), and (3) a gate voltage (V G ) coupled to the control gate of device 200 (e.g., control gate 122). In this example, control gate 222 is used to first set the charge via tunneling at a high voltage and then the same gate is used for standard transistor gating at a lower voltage.

[0019] Regarding the operation of device 200, an appropriate voltage coupled via the terminals of device 200 may be used to inject charge into floating gate 224 or remove the charge stored therein. As an example, in a first phase, a high voltage (e.g., several volts) is applied to control gate 222 while at the same time a high drain voltage (V D ) is applied to the drain region of device 200. As a result, electrons may be injected into floating gate 224 during the first phase. In a second phase, holes formed in other parts of device 200 may be removed. As an example, a particular voltage (lower than the voltage applied to the control gate during the first phase) is applied to control gate 222 while at the same time a negative drain voltage (V D ) is applied to the drain region of device 200. As a result, holes formed in a particular region of device 200 may be removed during the second phase. The second phase may only be required if device 200 is formed as a semiconductor-on-insulator (SOI) device. This is because if device 200 is formed as a bulk device, holes can be removed through the well electrode.

[0020] FIG. 3 shows a device 300 with threshold voltage offset compensation according to an example. The device 300 can be formed on a substrate 302. The device 300 can further include a p-type region 304, an n-type region 306, and another n-type region 308. In this example, the device 300 is formed to function as an NPN transistor. However, the device 300 can be any other type of transistor (e.g., PNP transistor), thyristor, thermistor, or any other semiconductor switch or device that operates in a similar manner to a transistor. Further, the device 300 can be a metal oxide semiconductor field effect transistor (MOSFET), fin field effect transistor (FinFET), insulated gate field effect transistor (IGFET), or any other type of transistor. Also, the device 300 can be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is later separated into dies that are packaged in the form of an integrated circuit package. The semiconductor processing steps can include the use of techniques such as, for example, plasma vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Features including sources, drains, and gates can be formed using such techniques or other suitable semiconductor manufacturing techniques.

[0021] Continuing to refer to FIG. 3, stack 320 can be formed. Stack 320 can include a control gate 322 and a floating gate 324. Stack 320 can further include a control dielectric layer 326 that can be formed between control gate 322 and floating gate 324. Stack 320 can further include a tunnel dielectric layer 328 that can be formed between floating gate 324 and the top surface of channel 310. Sidewalls 332 and 334 can be formed adjacent to the sidewalls of stack 320. Further, a second, split control gate 330 can be formed. Control gate 322 and split control gate 330 can be formed using polysilicon, metal, metal alloy, or other suitable materials. Floating gate 324 can function as a layer configured to store a controllable amount of charge. Materials such as, for example, silicon nitride, polysilicon, silicon, or germanium can be used. In a particular example, nanocrystals may be used to store charge. Control dielectric layer 326 can be formed using any suitable dielectric material. In one example, control dielectric layer 326 can be formed as an oxide / nitride / oxide (ONO) stack. Tunnel dielectric layer 328 can also be formed using any suitable dielectric material, such as, for example, silicon dioxide or silicon nitride. A high-k dielectric stack can also be used. The dimensions of these various layers and regions are not drawn to scale, and in one example, tunnel dielectric layer 328 can be configured to be thin enough such that stored electrons or holes can pass through tunnel dielectric layer 328 under the application of appropriate voltages to the various terminals of device 300. FIG. 3 shows a specific number and type of layers formed as part of stack 320, but stack 320 can further include additional layers or fewer layers as needed.

[0022] Still referring to FIG. 3, device 300 can have several terminals that can be coupled to receive different voltages. As an example, device 300 can have a source voltage (V coupled to the source of device 300 (e.g., n-type region 306). SA terminal for receiving (2) a drain voltage (V coupled to the drain of device 300 (e.g., n-type region 308) D A terminal for receiving (3) a gate voltage (V coupled to the first control gate of device 300 (e.g., control gate 322) G A terminal for receiving (4) a trimming voltage (V coupled to the second control gate of device 300 (e.g., control gate 330) TRIM It may include a terminal for receiving. In this example, the trimming voltage (V TRIM ) can be supplied via an external circuit and can be used to first adjust the offset charge. The trimming voltage (V TRIM ) can be used to add or subtract charge to the gate capacitance via FNT and / or HCI. In this example, using control gate 330, first charge is set via tunneling at a high voltage, and then control gate 322 is used for standard transistor gating at a lower voltage.

[0023] Regarding the operation of device 300, an appropriate voltage coupled via the terminals of device 300 can be used to inject charge into the floating gate 324 or remove the charge stored therein. As an example, in the first phase, a high trimming voltage (V TRIM) (e.g., several volts) is applied to control gate 330, and at the same time a high drain voltage (V D ) can be applied to the drain region of device 300. As a result, electrons can be injected into the floating gate 324 during the first phase. In the second phase, holes formed in other parts of device 300 can be removed. As an example, a specific voltage (lower than the trimming voltage applied during the first phase) is applied to control gate 330, and at the same time a negative drain voltage (V D) can be applied to the drain region of device 300. As a result, during the second phase, holes formed in a specific region of device 300 can be removed. The second phase may only be required if device 300 is formed as a semiconductor-on-insulator (SOI) device. This is because when device 300 is formed as a bulk device, holes can be removed through the well electrode.

[0024] FIG. 4 shows a system 400 having control logic 450 related to threshold voltage offset compensation, according to an example. System 400 may include one or more of a processor, memory, CPU, GPU, FPGA, or any other type of device used in an information processing system. In this example, system 400 can include one or more integrated circuits, each of which can be packaged as a single integrated circuit. At least a subset of the integrated circuits included in system 400 can have any of the types of devices described with respect to FIGS. 1, 2, and 3. System 400 may include (one or more) processing cores 410, volatile memory 420, non-volatile memory 430, other blocks 440, and control logic 450.

[0025] Continuing to refer to FIG. 4, control logic 450 may include components configured to control threshold voltage offset compensation. In this example, control logic 450 may include a finite state machine (FSM) 452, a control & status register 454, and a charge pump 456. The FSM 452 may be configured to be able to control the charge pump 456 via a bus 455. The control & status register 454 may include registers that can be written to and read by the FSM 452. As an example, the control register may include a field that defines information regarding the type of (one or more) voltage waveforms generated by the charge pump 456. Thus, the charge pump 456 may be configured to generate a voltage waveform under the control of the FSM 452. Further, the charge pump 456 may be configured to generate multiple voltage waveforms simultaneously such that appropriate voltages can be coupled to various terminals associated with device 100, device 200, or device 300. Although FIG. 4 shows the system 400 as including a particular number of components, the system 400 may include additional components or fewer components. Also, instead of the FSM 452, instructions programmed in a non-volatile memory such as, for example, a NOR flash memory may be used to control the charge pump 456.

[0026] The circuits constructed from these devices can operate not only in a standard mode (without offset trimming), but also in a low-power mode where the supply voltage is reduced after a trimming procedure. This procedure may involve measuring the threshold voltage of a transistor and adding or removing charge to the floating gate capacitance to adjust the threshold voltage to some predetermined value. The control logic 450 can be used to perform this trimming procedure. In this example, all transistors within the circuit undergo this calibration, but the process need only be performed after the first cooling of the chip to cryogenic temperatures. At a sufficiently low temperature, the calibrated charge on the floating gate can remain indefinitely. The calibration process can be performed as fast as possible for convenience, but can also accommodate serial low clock rate execution if power consumption must be minimized.

[0027] Referring still to FIG. 4, only a subset of the components of the system 400 may include devices with threshold voltage offset compensation. Also, the volatile memory 420 may have devices with threshold voltages designed differently from those of the devices included in the non-volatile memory 430. Thus, different components may have different threshold voltage offset compensations whether they are on the same substrate or on different substrates.

[0028] FIG. 5 shows histograms 510 and 550 that illustrate the distribution of threshold voltages of a device (e.g., any one of device 100, device 200, or device 300) before and after offset compensation. In this example, the vertical axis of each of histograms 510 and 550 indicates the number of devices for which threshold voltage offset compensation is to be performed. In one example, the number of devices can correspond to all of the transistors on one integrated circuit. Alternatively, the number of devices may correspond to a portion of the integrated circuit. By actively adjusting the threshold voltages of the transistors, substantially all of the transistors within the circuit are made to have threshold voltages that are nearly the same. If the distribution of the threshold voltages can be narrowed, the power supply voltage can be lowered, reducing the dynamic power consumption by an order of two. In one example, the first distribution of the threshold voltages of the devices can have a first value that indicates a measure of the spread of the threshold voltages. Using the control logic 450 of FIG. 4, the threshold voltage of each of the devices can be changed such that the first distribution is changed to a second distribution having a second value of the measure of the spread of the threshold voltages, where the second value represents less variation among the threshold voltages of the devices. The measure of the spread can be selected from among variance, standard deviation, or range.

[0029] FIG. 6 shows a flowchart 600 of a method according to an example. Step 610 can include determining the variation between the threshold voltages of a plurality of devices while operating an integrated circuit in a cryogenic environment, where each of the plurality of devices has a floating gate. The first part of this process can involve measuring the transistor threshold voltage for each of the devices. Control logic 450 can be used to measure the threshold voltage. By performing these measurements, a measure of the spread of the distribution of the threshold voltages for the plurality of devices can be determined. The measure of spread can be selected from variance, standard deviation, or range. In one example, instead of measuring the threshold voltage of each device, something that substitutes for the variation in threshold voltage can be used. As an example, control logic 450 can be configured to measure the error rate associated with the signals processed by the devices. By performing error rate analysis across a number of circuits, a correlation between the variation in threshold voltage and the error rate can be established. Thus, the error rate can be used instead as part of the step of determining the variation between the threshold voltages.

[0030] Step 620 can include changing the threshold voltages of at least a subset of the plurality of devices so that the variation between the threshold voltages of the plurality of devices is reduced, by (1) injecting charge into each respective floating gate, or (2) removing charge from each respective floating gate. Depending on the device type (e.g., device 100, device 200, or device 300), the corresponding process described above can be used. To adjust the threshold voltage to some predetermined value, control logic 450 can be used to add charge to or remove charge from the floating gate capacitance. In this example, all transistors in the circuit receive this calibration, but the process need only be done after the first cooling of the chip to cryogenic temperature. As explained above, advantageously, a smaller variation between the threshold voltages of the transistors can make it possible to lower the power supply voltage. This, in turn, can reduce the dynamic power consumption by the circuit by an order of two.

[0031] In certain examples, the devices described herein may be included in a low-power cryogenic CMOS interface for controlling quantum bit gates. Controlling a quantum device ideally requires generating a very large number of static and dynamic voltage signals in close proximity to the quantum device and at cryogenic temperatures. As used in this disclosure, the term "(one or more) cryogenic temperatures" means any temperature below 300 Kelvin. Given that the cryogenic environment strongly constrains the power consumption of active electronics, this is a major challenge. Additionally, it is necessary to couple a large number of voltage signals to the quantum bit gates within a quantum computing device. This is because potentially thousands of wires need to be connected to the voltage sources for driving the quantum bit gates within a quantum computing device. Also, qubits have conventionally been controlled by room-temperature pulse generators that must generate large signals that are attenuated within a cryostat. The power required to overcome this attenuation, and furthermore the power required to drive the cable impedance, are obstacles to scaling quantum computers.

[0032] The specific examples described in this disclosure relate to cryogenic control circuits and architectures for quantum computing devices. The control architecture includes an integrated circuit control chip that includes cryogenic control circuits closely integrated with a qubit plane. As an example, the control chip can be wire-bonded or flip-chip implemented onto the qubit plane. Also, the control chip accumulates charge on capacitors (including interconnect capacitances) to generate voltage biases. A single digital-to-analog converter can be used to set the charge on each capacitor, which remains over long periods at cryogenic temperatures due to the very low leakage paths at these temperatures. Charge refresh can be performed periodically on a time scale commensurate with qubit operation. The challenges associated with heat generated from decay are addressed by disposing a "charge shuffle" circuit that moves charge between capacitors to generate voltage pulses. The capacitance is reduced as much as possible by the close integration between the cryogenic CMOS control chip and the qubit plane. This close integration is, for example, by means of a chip stack packaging technique, which can dramatically reduce the capacitance and thereby affect the power consumption.

[0033] The qubit plane can include topological computing gates that can operate at about 20 millikelvin (~20 mK). A quantum computing device can process quantum information, such as qubits. Qubits can be implemented using various physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. The quantum state can be encoded as the orientation of a spin, the spin as part of a qubit, charge, energy, another aspect of the excitation stage, or the topological phase of a superconducting material. Examples of qubits can operate based on either a low-frequency DC signal (e.g., a bias current) or a high-frequency radio frequency signal (e.g., a 10 GHz signal) or a combination of both. In certain examples, microwave signals can be used to control superconducting devices, including, for example, the state of a qubit (qubit). Certain implementations of gates for qubits (qubits) can require high-frequency microwave signals.

[0034] FIG. 7 shows a system 700 for controlling qubits, according to an example. In this example, system 700 can include multiple stages, each of which can be configured to operate at a different temperature. Thus, system 700 can include stages 710, 730, and 750. Stage 710 can include components configured to operate at cryogenic temperatures (e.g., 300 Kelvin or less). Stage 730 can include components configured to operate at temperatures between 300 Kelvin and 4 Kelvin. Stage 750 can include components configured to operate at or near 20 millikelvin (mK). Stage 710 can include a microcontroller 712 (or microprocessor), a digital-to-analog converter (DAC) 714, a signal generator 716, and a measurement device 718. Microcontroller 712 can generate control signals configured to control qubits and other aspects of system 700. DAC 714 can receive digital control signals from microcontroller 712 (or other components) and convert them into analog form. And, if necessary, these analog signals can be transmitted to other stages. Signal generator 716 can include, if necessary, a microwave signal generator and other clock signal generators. Measurement device 718 can include instruments such as, for example, a spectrum analyzer. In one example, each of microcontroller 712 (or microprocessor), digital-to-analog converter (DAC) 714, signal generator 716, and measurement device 718 can include the aforementioned devices, making it possible to reduce the power consumed by such components.

[0035] Continuing to refer to FIG. 7, stage 730 may include components configured to interconnect stage 710 with stage 750 in a manner that allows for an efficient connection between components at room temperature and components at 20 millikelvin (mK). Thus, in this example, stage 730 may include component 732, interconnect 734, interconnect 736, and interconnect 738. In one example, component 732 may be implemented as a (one or more) high electron mobility transistor (HEMT) low noise amplifier. Interconnects 734, 736, and 738 may be implemented as cables having conductors such as niobium and copper, for example. These conductors may be insulated within the interconnects using a suitable dielectric material such as polyimide, for example.

[0036] Still referring to FIG. 7, stage 750 may include coupler 752, readout multiplexer 754, fast control multiplexer 756, and qubit 760. Coupler 752 may couple a signal from a signal generator (e.g., signal generator 716) to readout multiplexer 754. Coupler 752 may also direct a reflected signal towards component 732. Readout multiplexer 754 and fast control multiplexer 756 may be implemented on a single control chip (sometimes referred to as a cryogenic control CMOS chip). In one example, readout multiplexer 754 may be implemented using a superconducting material such as niobium on an inert substrate such as sapphire, for example. The readout multiplexer 754 chip may include a plurality of inductive elements, capacitive elements, and resistive elements sized to form a (one or more) bank of resonators. At cryogenic temperatures, the resonator circuit exhibits superconductivity and produces resonators with high Q values. This may provide an efficient low-loss frequency multiplexing mechanism. In one example, a cryogenic CMOS control chip (e.g., an ASIC manufactured using semiconductor technology such as CMOS) may be mounted on the same substrate as the qubit (e.g., qubit 760) and configured to operate at the same cryogenic temperature as the qubit (e.g., 20 mK).

[0037] FIG. 8 shows a common substrate 800 including a cryogenic CMOS control chip 810, a qubit chip 850, and a resonator chip 880, according to an example. The cryogenic CMOS control chip 810 can be coupled to contact pads (e.g., contact pads 822 and 824) via wire bonds (e.g., wire bonds 812 and 814). The cryogenic CMOS control chip 810 can further be coupled to contact pads (e.g., contact pads 826 and 828) via wire bonds (e.g., wire bonds 816 and 818). The cryogenic CMOS control chip 810 can further be coupled to other contacts (e.g., contacts 834 and 836) via wire bonds (e.g., wire bonds 830 and 832). The qubit chip 850 can be coupled to contact pads (e.g., contact pads 856 and 858) via wire bonds (e.g., wire bonds 852 and 854). The qubit chip 850 can be coupled to the resonator chip 880 via wire bonds (e.g., wire bonds 860 and 862). The resonator chip 880 can be coupled to contacts (e.g., contacts 890 and 892) via wire bonds (e.g., wire bonds 882 and 884). This example shows a dense integration between the control chip and the qubits via wire bonds, but other techniques can also be used. As an example, the control chip may be flip-chip bonded to a substrate with qubits. Alternatively, a package-on-package, system-in-package, or other multi-chip assembly can also be used.

[0038] While the above description refers to quantum devices, the systems described herein can be implemented to support any service or application that can be provided via a combination of computing, networking, and storage resources, such as via a data center or other infrastructure for delivering services or applications. The described aspects can also be implemented in a cloud computing environment. Cloud computing can refer to a model that enables on-demand network access to a shared pool of configurable computing resources. For example, by deploying cloud computing in the market, ubiquitous and convenient on-demand access to a shared pool of configurable computing resources can be provided. The cloud computing model can be composed of various characteristics, such as on-demand self-service, broad network access, resource pooling, rapid elasticity, and measured service. The cloud computing model can be used to expose various service models, such as hardware as a service (“HaaS”), software as a service (“SaaS”), platform as a service (“PaaS”), and infrastructure as a service (“IaaS”). The cloud computing model can also be deployed using different deployment models, such as private cloud, community cloud, public cloud, and hybrid cloud.

[0039] In summary, in one aspect, the present disclosure relates to a system including a plurality of devices configured to operate in a cryogenic environment, wherein a first distribution of threshold voltages of the plurality of devices has a first value indicating a measure of the spread of the threshold voltages. The system can further include control logic coupled to each of the plurality of devices, the control logic being configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicating a measure of the spread of the threshold voltages, the second value representing a lower variation among the threshold voltages of the plurality of devices.

[0040] The measure of the spread can be selected from among variance, standard deviation, or range. Each of the plurality of devices can have a floating gate. The system can include a charge pump, each of the plurality of devices having a terminal for receiving a trimming voltage via the charge pump, and the control logic being further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into the floating gate or removing charge from the floating gate.

[0041] The system can include a charge pump, each of the plurality of devices having a gate terminal for receiving a voltage via the charge pump, and the control logic being further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into the floating gate or removing charge from the floating gate.

[0042] The system can include a charge pump, each of the plurality of devices having a terminal coupled to a split gate for receiving a trimming voltage via the charge pump, and the control logic being further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into the floating gate or removing charge from the floating gate. The control logic can be further configured to determine the threshold voltage of each of the plurality of devices.

[0043] In another aspect, the present disclosure relates to a method in a system having a plurality of devices with associated threshold voltages. The method can include determining a variation between the threshold voltages of the plurality of devices while operating an integrated circuit in a cryogenic environment, where each of the plurality of devices has a floating gate. The method can further include changing the threshold voltages of at least a subset of the plurality of devices so that the variation between the threshold voltages of the plurality of devices is reduced, by (1) injecting charge into each respective floating gate, or (2) removing charge from each respective floating gate.

[0044] Determining the variation can include determining a measure of spread selected from among variance, standard deviation, or range. Determining the variation between the threshold voltages can include determining an error rate associated with an operation associated with the integrated circuit. Determining the variation between the threshold voltages can include determining the threshold voltage of each of the plurality of devices.

[0045] Changing the threshold voltage of each of the plurality of devices can include applying a voltage through a terminal for receiving a trimming voltage. Changing the threshold voltage of each of the plurality of devices can include applying a voltage through a gate terminal.

[0046] In yet another aspect, the present disclosure relates to a system including a first integrated circuit having a quantum device including a plurality of quantum bit gates, the quantum device being configured to operate at cryogenic temperatures. The system can further include a second integrated circuit configured to operate at the cryogenic temperatures, with the first integrated circuit coupled to the second integrated circuit. The second integrated circuit can include a plurality of devices, a first distribution of threshold voltages of the plurality of devices having a first value indicative of a measure of the spread of the threshold voltages. The second integrated circuit can further include control logic coupled to each of the plurality of devices, the control logic being configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of the spread of the threshold voltages, the second value representing a lower variation among the threshold voltages of the plurality of devices.

[0047] The measure of the spread can be selected from among variance, standard deviation, or range. Each of the plurality of devices can have a floating gate. The system can include a charge pump, each of the plurality of devices having a terminal for receiving a trimming voltage via the charge pump, and the control logic being further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate.

[0048] The system can include a charge pump, each of the plurality of devices having a gate terminal for receiving a voltage via the charge pump, and the control logic being further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate.

[0049] The system can include a charge pump, each of the plurality of devices having a terminal coupled to a split gate for receiving a trimming voltage via the charge pump, and the control logic is further configured to change the threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from a floating gate. The control logic can further be configured to determine the threshold voltage of each of the plurality of devices.

[0050] It should be understood that the methods, modules, and components shown herein are merely exemplary. For example, without limitation, exemplary types of superconducting devices can include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), and the like.

[0051] Also, in an abstract but still clear sense, any configuration of components for achieving the same function is effectively "associated" so that the desired function is achieved. Thus, two components combined here to achieve a particular function can be seen as "associated" with each other so that the desired function is achieved, regardless of the architecture or intermediate components. Similarly, two components so associated can be seen as "operationally connected" or "coupled" to each other to achieve the desired function.

[0052] Also, as will be recognized by those skilled in the art, the boundaries between the functions of the above-described processes are merely exemplary. The functions of multiple processes can be combined into one process, and / or the functions of one process can be distributed to further processes. Also, alternative embodiments can include multiple instances of a particular process, and the order of the processes can be changed in various other embodiments.

[0053] Although specific examples are provided herein, various changes and modifications can be made without departing from the scope of the disclosure as set forth in the following claims. Accordingly, the specification and drawings are to be considered in an illustrative rather than a limiting sense, and it is intended that all such changes be included within the scope of the disclosure. Benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as critical, required, or essential features or elements of any or all claims.

[0054] Also, the term "a" or "an" as used herein is defined as one or more. Also, the use of introductory phrases such as "at least one" or "one or more" in the claims should not be construed to limit a particular claim that introduces another claim element by the indefinite article "a" or "an" to an invention that includes only one such element, even if the same claim includes an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an". The same is true for the use of definite articles.

[0055] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish between elements described by such terms. Accordingly, these terms are not necessarily intended to indicate a temporal or other ranking of such elements.

Claims

1. A system for interfacing with a quantum bit gate, comprising: a first plurality of devices configured to operate in a cryogenic environment; a second plurality of devices different from the first plurality of devices and configured to operate in the cryogenic environment; control logic coupled to each of the first plurality of devices and the second plurality of devices, the control logic being configured to change a threshold voltage of each of the first plurality of devices and the second plurality of devices such that a first threshold voltage of each of the first plurality of devices is different from a second threshold voltage of each of the second plurality of devices; A system having the above.

2. The system according to claim 1, wherein each of the first plurality of devices has a volatile memory device, and each of the second plurality of devices has a non-volatile memory device.

3. The system according to claim 1, wherein each of the first plurality of devices and the second plurality of devices has a floating gate.

4. The system further includes a charge pump, each of the first plurality of devices and the second plurality of devices having a respective terminal for receiving a trimming voltage via the charge pump, and the control logic is further configured to change a threshold voltage of each of the first plurality of devices and the second plurality of devices by either injecting charge into or removing charge from the floating gate. The system according to claim 3.

5. The system further includes a charge pump, each of the first plurality of devices and the second plurality of devices having a respective gate terminal for receiving a voltage via the charge pump, and the control logic is further configured to change a threshold voltage of each of the first plurality of devices and the second plurality of devices by either injecting charge into or removing charge from the floating gate. The system according to claim 3.

6. The system further includes a charge pump, each of the first plurality of devices and the second plurality of devices having a terminal coupled to a respective split gate for receiving a trimming voltage via the charge pump, the control logic further configured to change a threshold voltage of each of the first plurality of devices and the second plurality of devices by either injecting charge into or removing charge from the floating gate, the system of claim 3.

7. The system of claim 3, wherein the control logic is further configured to determine a threshold voltage of each of the first plurality of devices and the second plurality of devices.

8. A method in a system having a first plurality of devices and a second plurality of devices different from the first plurality of devices, comprising: determining a first variation between first threshold voltages of the first plurality of devices while operating an integrated circuit in a cryogenic environment, each of the first plurality of devices having a floating gate; determining a second variation between second threshold voltages of the second plurality of devices while operating the integrated circuit in the cryogenic environment, each of the second plurality of devices having a floating gate; changing a first threshold voltage of at least a subset of the first plurality of devices to reduce the variation between the first threshold voltages of the first plurality of devices by (1) injecting charge into respective floating gates or (2) removing charge from respective floating gates; changing a second threshold voltage of at least a subset of the second plurality of devices to reduce the variation between the second threshold voltages of the second plurality of devices by (1) injecting charge into respective floating gates or (2) removing charge from respective floating gates; A method having the above steps.

9. The method of claim 8, wherein determining the first variation and determining the second variation comprises determining a measure of spread selected from among variance, standard deviation, or range.

10. Determining the first variation between the first threshold voltages and determining the second variation between the second threshold voltages comprises determining an error rate associated with an operation associated with the integrated circuit, the method of claim 8.

11. Determining the first variation between the first threshold voltages comprises determining the threshold voltage of each of the first plurality of devices, and determining the second variation between the second threshold voltages comprises determining the threshold voltage of each of the second plurality of devices, the method of claim 8.

12. Changing the first threshold voltage of at least the subset of the first plurality of devices comprises applying a voltage via respective first terminals for receiving a trimming voltage, and changing the second threshold voltage of at least the subset of the second plurality of devices comprises applying a voltage via respective second terminals for receiving a trimming voltage, the method of claim 8.

13. Changing the first threshold voltage of the subset of the first plurality of devices comprises applying a voltage via respective first gate terminals, and changing the second threshold voltage of the subset of the second plurality of devices comprises applying a voltage via respective second gate terminals, the method of claim 8.

14. A first integrated circuit having a quantum device including a plurality of quantum bit gates, the quantum device being configured to operate at cryogenic temperatures, a first integrated circuit; A second integrated circuit configured to operate at the cryogenic temperature, the first integrated circuit being coupled to the second integrated circuit, the second integrated circuit comprising: A first plurality of devices; A second plurality of devices different from the first plurality of devices; and Control logic coupled to each of the first plurality of devices and the second plurality of devices, the control logic being configured to change the threshold voltage of each of the first plurality of devices and the second plurality of devices such that the first threshold voltage of each of the first plurality of devices is different from the second threshold voltage of each of the second plurality of devices; A second integrated circuit having; A system having.

15. The system according to claim 14, wherein each of the first plurality of devices has a volatile memory device, and each of the second plurality of devices has a non-volatile memory device.

16. The system according to claim 15, wherein each of the first plurality of devices and each of the second plurality of devices have a floating gate.

17. The system further includes a charge pump, each of the first plurality of devices and each of the second plurality of devices having respective terminals for receiving a trimming voltage via the charge pump, and the control logic further being configured to change a threshold voltage of each of the first plurality of devices and each of the second plurality of devices by either injecting charge into or removing charge from the floating gate. The system according to claim 16.

18. The system further includes a charge pump, each of the first plurality of devices and each of the second plurality of devices having respective gate terminals for receiving a voltage via the charge pump, and the control logic further being configured to change a threshold voltage of each of the first plurality of devices and each of the second plurality of devices by either injecting charge into or removing charge from the floating gate. The system according to claim 16.

19. The system further includes a charge pump, each of the first plurality of devices and each of the second plurality of devices having respective terminals coupled to respective split gates for receiving a trimming voltage via the charge pump, and the control logic further being configured to change a threshold voltage of each of the first plurality of devices and each of the second plurality of devices by either injecting charge into or removing charge from the floating gate. The system according to claim 16.

20. The system according to claim 16, wherein the control logic is further configured to determine a threshold voltage of each of the first plurality of devices and each of the second plurality of devices.

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